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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
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commit
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485 changed files with 108790 additions and 107581 deletions
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@ -28,20 +28,20 @@
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/*-----------------------------------------------------------
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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/*
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*/
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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volatile uint32_t ulCriticalNesting = 9999UL;
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@ -57,40 +57,40 @@ void vPortISRStartFirstTask( void );
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void vPortISRStartFirstTask( void )
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{
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/* Simply start the scheduler. This is included here as it can only be
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called from ARM mode. */
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asm volatile ( \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"LDR LR, [R0] \n\t" \
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\
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/* The critical nesting depth is the first item on the stack. */ \
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/* Load it into the ulCriticalNesting variable. */ \
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDMFD LR!, {R1} \n\t" \
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"STR R1, [R0] \n\t" \
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\
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/* Get the SPSR from the stack. */ \
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"LDMFD LR!, {R0} \n\t" \
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"MSR SPSR, R0 \n\t" \
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\
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/* Restore all system mode registers for the task. */ \
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"LDMFD LR, {R0-R14}^ \n\t" \
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"NOP \n\t" \
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\
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/* Restore the return address. */ \
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"LDR LR, [LR, #+60] \n\t" \
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\
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/* And return - correcting the offset in the LR to obtain the */ \
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/* correct address. */ \
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"SUBS PC, LR, #4 \n\t" \
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);
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* called from ARM mode. */
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asm volatile ( \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"LDR LR, [R0] \n\t" \
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\
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/* The critical nesting depth is the first item on the stack. */ \
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/* Load it into the ulCriticalNesting variable. */ \
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDMFD LR!, {R1} \n\t" \
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"STR R1, [R0] \n\t" \
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\
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/* Get the SPSR from the stack. */ \
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"LDMFD LR!, {R0} \n\t" \
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"MSR SPSR, R0 \n\t" \
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\
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/* Restore all system mode registers for the task. */ \
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"LDMFD LR, {R0-R14}^ \n\t" \
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"NOP \n\t" \
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\
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/* Restore the return address. */ \
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"LDR LR, [LR, #+60] \n\t" \
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\
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/* And return - correcting the offset in the LR to obtain the */ \
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/* correct address. */ \
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"SUBS PC, LR, #4 \n\t" \
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);
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}
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/*-----------------------------------------------------------*/
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void vPortTickISR( void )
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{
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/* Increment the RTOS tick count, then look for the highest priority
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task that is ready to run. */
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* task that is ready to run. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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vTaskSwitchContext();
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@ -110,29 +110,29 @@ void vPortTickISR( void )
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*/
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#ifdef THUMB_INTERWORK
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void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
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void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
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void vPortDisableInterruptsFromThumb( void )
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{
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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void vPortEnableInterruptsFromThumb( void )
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{
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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#endif /* THUMB_INTERWORK */
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@ -142,15 +142,15 @@ void vPortEnterCritical( void )
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{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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/* Now that interrupts are disabled, ulCriticalNesting can be accessed
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* directly. Increment ulCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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@ -163,16 +163,16 @@ void vPortExitCritical( void )
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ulCriticalNesting--;
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/* If the nesting level has reached zero then interrupts should be
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re-enabled. */
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* re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable interrupts as per portEXIT_CRITICAL(). */
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asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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}
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}
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}
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