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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
d6bccb1f4c
commit
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485 changed files with 108790 additions and 107581 deletions
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@ -46,127 +46,127 @@
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#if ( configENABLE_MPU == 1 )
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" program_mpu_first_task: \n"
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" ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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" str r2, [r1] \n" /* Disable MPU. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
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" movs r3, #5 \n" /* r3 = 5. */
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" str r3, [r1] \n" /* Program RNR = 5. */
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" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
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" movs r3, #6 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 6. */
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" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
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" movs r3, #7 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 7. */
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" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
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" \n"
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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" str r2, [r1] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" restore_context_first_task: \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
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" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
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" \n"
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" restore_special_regs_first_task: \n"
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" subs r1, #16 \n"
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" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
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" subs r1, #16 \n"
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" msr psp, r2 \n"
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" msr psplim, r3 \n"
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" msr control, r4 \n"
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" mov lr, r5 \n"
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" \n"
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" restore_general_regs_first_task: \n"
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" subs r1, #32 \n"
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" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
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" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
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" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
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" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
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" subs r1, #48 \n"
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" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
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" mov r8, r4 \n" /* r8 = r4. */
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" mov r9, r5 \n" /* r9 = r5. */
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" mov r10, r6 \n" /* r10 = r6. */
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" mov r11, r7 \n" /* r11 = r7. */
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" subs r1, #32 \n"
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" ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
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" subs r1, #16 \n"
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" \n"
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" restore_context_done_first_task: \n"
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" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
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" bx lr \n"
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" \n"
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" .align 4 \n"
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" pxCurrentTCBConst2: .word pxCurrentTCB \n"
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" xMPUCTRLConst2: .word 0xe000ed94 \n"
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" xMAIR0Const2: .word 0xe000edc0 \n"
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" xRNRConst2: .word 0xe000ed98 \n"
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" xRBARConst2: .word 0xe000ed9c \n"
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);
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}
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" program_mpu_first_task: \n"
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" ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
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" \n"
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" dmb \n" /* Complete outstanding transfers before disabling MPU. */
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
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" str r2, [r1] \n" /* Disable MPU. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
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" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r1, [r2] \n" /* Program MAIR0. */
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" \n"
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" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
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" ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
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" \n"
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" movs r3, #4 \n" /* r3 = 4. */
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" str r3, [r1] \n" /* Program RNR = 4. */
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" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
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" movs r3, #5 \n" /* r3 = 5. */
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" str r3, [r1] \n" /* Program RNR = 5. */
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" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
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" movs r3, #6 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 6. */
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" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
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" movs r3, #7 \n" /* r3 = 6. */
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" str r3, [r1] \n" /* Program RNR = 7. */
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" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
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" ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
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" \n"
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" ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
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" movs r3, #1 \n" /* r3 = 1. */
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" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
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" str r2, [r1] \n" /* Enable MPU. */
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" dsb \n" /* Force memory writes before continuing. */
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" \n"
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" restore_context_first_task: \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
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" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
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" \n"
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" restore_special_regs_first_task: \n"
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" subs r1, #16 \n"
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" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
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" subs r1, #16 \n"
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" msr psp, r2 \n"
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" msr psplim, r3 \n"
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" msr control, r4 \n"
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" mov lr, r5 \n"
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" \n"
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" restore_general_regs_first_task: \n"
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" subs r1, #32 \n"
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" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
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" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
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" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
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" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
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" subs r1, #48 \n"
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" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
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" mov r8, r4 \n" /* r8 = r4. */
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" mov r9, r5 \n" /* r9 = r5. */
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" mov r10, r6 \n" /* r10 = r6. */
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" mov r11, r7 \n" /* r11 = r7. */
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" subs r1, #32 \n"
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" ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
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" subs r1, #16 \n"
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" \n"
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" restore_context_done_first_task: \n"
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" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
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" bx lr \n"
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" \n"
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" .align 4 \n"
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" pxCurrentTCBConst2: .word pxCurrentTCB \n"
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" xMPUCTRLConst2: .word 0xe000ed94 \n"
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" xMAIR0Const2: .word 0xe000edc0 \n"
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" xRNRConst2: .word 0xe000ed98 \n"
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" xRBARConst2: .word 0xe000ed9c \n"
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);
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}
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#else /* configENABLE_MPU */
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
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" ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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" ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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" msr psplim, r1 \n"/* Set this task's PSPLIM value. */
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" movs r1, #2 \n"/* r1 = 2. */
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" msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" bx r2 \n"/* Finally, branch to EXC_RETURN. */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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);
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}
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void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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" ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
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" movs r1, #2 \n" /* r1 = 2. */
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" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n" /* Discard everything up to r0. */
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" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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" isb \n"
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" bx r2 \n" /* Finally, branch to EXC_RETURN. */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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);
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}
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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@ -177,15 +177,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" movs r1, #1 \n"/* r1 = 1. */
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" tst r0, r1 \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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" beq running_privileged \n"/* If the result of previous AND operation was 0, branch. */
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" movs r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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" bx lr \n"/* Return. */
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" mrs r0, control \n" /* r0 = CONTROL. */
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" movs r1, #1 \n" /* r1 = 1. */
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" tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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" beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
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" movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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" bx lr \n" /* Return. */
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" running_privileged: \n"
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" movs r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n"/* Return. */
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" movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n" /* Return. */
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" \n"
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" .align 4 \n"
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::: "r0", "r1", "memory"
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@ -199,11 +199,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* Read the CONTROL register. */
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" movs r1, #1 \n"/* r1 = 1. */
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" bics r0, r1 \n"/* Clear the bit 0. */
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" msr control, r0 \n"/* Write back the new CONTROL value. */
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" bx lr \n"/* Return to the caller. */
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" mrs r0, control \n" /* Read the CONTROL register. */
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" movs r1, #1 \n" /* r1 = 1. */
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" bics r0, r1 \n" /* Clear the bit 0. */
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" msr control, r0 \n" /* Write back the new CONTROL value. */
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" bx lr \n" /* Return to the caller. */
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::: "r0", "r1", "memory"
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);
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}
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@ -215,11 +215,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" movs r1, #1 \n"/* r1 = 1. */
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" orrs r0, r1 \n"/* r0 = r0 | r1. */
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" msr control, r0 \n"/* CONTROL = r0. */
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" bx lr \n"/* Return to the caller. */
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" mrs r0, control \n" /* r0 = CONTROL. */
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" movs r1, #1 \n" /* r1 = 1. */
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" orrs r0, r1 \n" /* r0 = r0 | r1. */
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" msr control, r0 \n" /* CONTROL = r0. */
|
||||
" bx lr \n" /* Return to the caller. */
|
||||
::: "r0", "r1", "memory"
|
||||
);
|
||||
}
|
||||
|
|
@ -231,14 +231,14 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
|
||||
" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
|
||||
" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
|
||||
" msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
|
||||
" cpsie i \n"/* Globally enable interrupts. */
|
||||
" ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
|
||||
" ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
|
||||
" ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
|
||||
" msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
|
||||
" cpsie i \n" /* Globally enable interrupts. */
|
||||
" dsb \n"
|
||||
" isb \n"
|
||||
" svc %0 \n"/* System call to start the first task. */
|
||||
" svc %0 \n" /* System call to start the first task. */
|
||||
" nop \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
|
|
@ -277,254 +277,254 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
|
|||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
|
||||
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
|
||||
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
|
||||
" mrs r2, psp \n" /* r2 = PSP. */
|
||||
" \n"
|
||||
" save_general_regs: \n"
|
||||
" stmia r1!, {r4-r7} \n" /* Store r4-r7. */
|
||||
" mov r4, r8 \n" /* r4 = r8. */
|
||||
" mov r5, r9 \n" /* r5 = r9. */
|
||||
" mov r6, r10 \n" /* r6 = r10. */
|
||||
" mov r7, r11 \n" /* r7 = r11. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store r8-r11. */
|
||||
" ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
|
||||
" ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
|
||||
" \n"
|
||||
" save_special_regs: \n"
|
||||
" mrs r2, psp \n" /* r2 = PSP. */
|
||||
" mrs r3, psplim \n" /* r3 = PSPLIM. */
|
||||
" mrs r4, control \n" /* r4 = CONTROL. */
|
||||
" mov r5, lr \n" /* r5 = LR. */
|
||||
" stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
|
||||
" str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
|
||||
" \n"
|
||||
" select_next_task: \n"
|
||||
" cpsid i \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" cpsie i \n"
|
||||
" \n"
|
||||
" program_mpu: \n"
|
||||
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
|
||||
" \n"
|
||||
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
|
||||
" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
|
||||
" movs r3, #1 \n" /* r3 = 1. */
|
||||
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
|
||||
" str r2, [r1] \n" /* Disable MPU. */
|
||||
" \n"
|
||||
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
|
||||
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
|
||||
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
|
||||
" str r1, [r2] \n" /* Program MAIR0. */
|
||||
" \n"
|
||||
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
|
||||
" ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
|
||||
" \n"
|
||||
" movs r3, #4 \n" /* r3 = 4. */
|
||||
" str r3, [r1] \n" /* Program RNR = 4. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
|
||||
" movs r3, #5 \n" /* r3 = 5. */
|
||||
" str r3, [r1] \n" /* Program RNR = 5. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
|
||||
" movs r3, #6 \n" /* r3 = 6. */
|
||||
" str r3, [r1] \n" /* Program RNR = 6. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
|
||||
" movs r3, #7 \n" /* r3 = 6. */
|
||||
" str r3, [r1] \n" /* Program RNR = 7. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
|
||||
" \n"
|
||||
" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
|
||||
" movs r3, #1 \n" /* r3 = 1. */
|
||||
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
|
||||
" str r2, [r1] \n" /* Enable MPU. */
|
||||
" dsb \n" /* Force memory writes before continuing. */
|
||||
" \n"
|
||||
" restore_context: \n"
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
|
||||
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
|
||||
" \n"
|
||||
" restore_special_regs: \n"
|
||||
" subs r1, #16 \n"
|
||||
" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
|
||||
" subs r1, #16 \n"
|
||||
" msr psp, r2 \n"
|
||||
" msr psplim, r3 \n"
|
||||
" msr control, r4 \n"
|
||||
" mov lr, r5 \n"
|
||||
" \n"
|
||||
" restore_general_regs: \n"
|
||||
" subs r1, #32 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
|
||||
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
|
||||
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
|
||||
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
|
||||
" subs r1, #48 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
|
||||
" mov r8, r4 \n" /* r8 = r4. */
|
||||
" mov r9, r5 \n" /* r9 = r5. */
|
||||
" mov r10, r6 \n" /* r10 = r6. */
|
||||
" mov r11, r7 \n" /* r11 = r7. */
|
||||
" subs r1, #32 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
|
||||
" subs r1, #16 \n"
|
||||
" \n"
|
||||
" restore_context_done: \n"
|
||||
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
|
||||
" bx lr \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
" pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
" xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
" xMAIR0Const: .word 0xe000edc0 \n"
|
||||
" xRNRConst: .word 0xe000ed98 \n"
|
||||
" xRBARConst: .word 0xe000ed9c \n"
|
||||
);
|
||||
}
|
||||
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
|
||||
" ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
|
||||
" mrs r2, psp \n" /* r2 = PSP. */
|
||||
" \n"
|
||||
" save_general_regs: \n"
|
||||
" stmia r1!, {r4-r7} \n" /* Store r4-r7. */
|
||||
" mov r4, r8 \n" /* r4 = r8. */
|
||||
" mov r5, r9 \n" /* r5 = r9. */
|
||||
" mov r6, r10 \n" /* r6 = r10. */
|
||||
" mov r7, r11 \n" /* r7 = r11. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store r8-r11. */
|
||||
" ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
|
||||
" ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
|
||||
" stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
|
||||
" \n"
|
||||
" save_special_regs: \n"
|
||||
" mrs r2, psp \n" /* r2 = PSP. */
|
||||
" mrs r3, psplim \n" /* r3 = PSPLIM. */
|
||||
" mrs r4, control \n" /* r4 = CONTROL. */
|
||||
" mov r5, lr \n" /* r5 = LR. */
|
||||
" stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
|
||||
" str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
|
||||
" \n"
|
||||
" select_next_task: \n"
|
||||
" cpsid i \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" cpsie i \n"
|
||||
" \n"
|
||||
" program_mpu: \n"
|
||||
" ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
|
||||
" \n"
|
||||
" dmb \n" /* Complete outstanding transfers before disabling MPU. */
|
||||
" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
|
||||
" movs r3, #1 \n" /* r3 = 1. */
|
||||
" bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
|
||||
" str r2, [r1] \n" /* Disable MPU. */
|
||||
" \n"
|
||||
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
|
||||
" ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
|
||||
" ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
|
||||
" str r1, [r2] \n" /* Program MAIR0. */
|
||||
" \n"
|
||||
" adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
|
||||
" ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
|
||||
" \n"
|
||||
" movs r3, #4 \n" /* r3 = 4. */
|
||||
" str r3, [r1] \n" /* Program RNR = 4. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
|
||||
" movs r3, #5 \n" /* r3 = 5. */
|
||||
" str r3, [r1] \n" /* Program RNR = 5. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
|
||||
" movs r3, #6 \n" /* r3 = 6. */
|
||||
" str r3, [r1] \n" /* Program RNR = 6. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
|
||||
" movs r3, #7 \n" /* r3 = 6. */
|
||||
" str r3, [r1] \n" /* Program RNR = 7. */
|
||||
" ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
|
||||
" ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
|
||||
" \n"
|
||||
" ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
|
||||
" movs r3, #1 \n" /* r3 = 1. */
|
||||
" orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
|
||||
" str r2, [r1] \n" /* Enable MPU. */
|
||||
" dsb \n" /* Force memory writes before continuing. */
|
||||
" \n"
|
||||
" restore_context: \n"
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
|
||||
" ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
|
||||
" \n"
|
||||
" restore_special_regs: \n"
|
||||
" subs r1, #16 \n"
|
||||
" ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
|
||||
" subs r1, #16 \n"
|
||||
" msr psp, r2 \n"
|
||||
" msr psplim, r3 \n"
|
||||
" msr control, r4 \n"
|
||||
" mov lr, r5 \n"
|
||||
" \n"
|
||||
" restore_general_regs: \n"
|
||||
" subs r1, #32 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
|
||||
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
|
||||
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
|
||||
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
|
||||
" subs r1, #48 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
|
||||
" mov r8, r4 \n" /* r8 = r4. */
|
||||
" mov r9, r5 \n" /* r9 = r5. */
|
||||
" mov r10, r6 \n" /* r10 = r6. */
|
||||
" mov r11, r7 \n" /* r11 = r7. */
|
||||
" subs r1, #32 \n"
|
||||
" ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
|
||||
" subs r1, #16 \n"
|
||||
" \n"
|
||||
" restore_context_done: \n"
|
||||
" str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
|
||||
" bx lr \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
" pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
" xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
" xMAIR0Const: .word 0xe000edc0 \n"
|
||||
" xRNRConst: .word 0xe000ed98 \n"
|
||||
" xRBARConst: .word 0xe000ed9c \n"
|
||||
);
|
||||
}
|
||||
|
||||
#else /* configENABLE_MPU */
|
||||
|
||||
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" mrs r0, psp \n"/* Read PSP in r0. */
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" subs r0, r0, #40 \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
|
||||
" str r0, [r1] \n"/* Save the new top of stack in TCB. */
|
||||
" mrs r2, psplim \n"/* r2 = PSPLIM. */
|
||||
" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
|
||||
" stmia r0!, {r2-r7} \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
|
||||
" mov r4, r8 \n"/* r4 = r8. */
|
||||
" mov r5, r9 \n"/* r5 = r9. */
|
||||
" mov r6, r10 \n"/* r6 = r10. */
|
||||
" mov r7, r11 \n"/* r7 = r11. */
|
||||
" stmia r0!, {r4-r7} \n"/* Store the high registers that are not saved automatically. */
|
||||
" \n"
|
||||
" cpsid i \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" cpsie i \n"
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
|
||||
" \n"
|
||||
" adds r0, r0, #24 \n"/* Move to the high registers. */
|
||||
" ldmia r0!, {r4-r7} \n"/* Restore the high registers that are not automatically restored. */
|
||||
" mov r8, r4 \n"/* r8 = r4. */
|
||||
" mov r9, r5 \n"/* r9 = r5. */
|
||||
" mov r10, r6 \n"/* r10 = r6. */
|
||||
" mov r11, r7 \n"/* r11 = r7. */
|
||||
" msr psp, r0 \n"/* Remember the new top of stack for the task. */
|
||||
" subs r0, r0, #40 \n"/* Move to the starting of the saved context. */
|
||||
" ldmia r0!, {r2-r7} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
|
||||
" msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" bx r3 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
);
|
||||
}
|
||||
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" mrs r0, psp \n" /* Read PSP in r0. */
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
|
||||
" subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
|
||||
" str r0, [r1] \n" /* Save the new top of stack in TCB. */
|
||||
" mrs r2, psplim \n" /* r2 = PSPLIM. */
|
||||
" mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
|
||||
" stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
|
||||
" mov r4, r8 \n" /* r4 = r8. */
|
||||
" mov r5, r9 \n" /* r5 = r9. */
|
||||
" mov r6, r10 \n" /* r6 = r10. */
|
||||
" mov r7, r11 \n" /* r7 = r11. */
|
||||
" stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
|
||||
" \n"
|
||||
" cpsid i \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" cpsie i \n"
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n" /* Read pxCurrentTCB. */
|
||||
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
|
||||
" \n"
|
||||
" adds r0, r0, #24 \n" /* Move to the high registers. */
|
||||
" ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
|
||||
" mov r8, r4 \n" /* r8 = r4. */
|
||||
" mov r9, r5 \n" /* r9 = r5. */
|
||||
" mov r10, r6 \n" /* r10 = r6. */
|
||||
" mov r11, r7 \n" /* r11 = r7. */
|
||||
" msr psp, r0 \n" /* Remember the new top of stack for the task. */
|
||||
" subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
|
||||
" ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
|
||||
" msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
|
||||
" bx r3 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* configENABLE_MPU */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
|
||||
|
||||
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
".syntax unified \n"
|
||||
".extern vPortSVCHandler_C \n"
|
||||
".extern vSystemCallEnter \n"
|
||||
".extern vSystemCallEnter_1 \n"
|
||||
".extern vSystemCallExit \n"
|
||||
" \n"
|
||||
"movs r0, #4 \n"
|
||||
"mov r1, lr \n"
|
||||
"tst r0, r1 \n"
|
||||
"beq stack_on_msp \n"
|
||||
"stack_on_psp: \n"
|
||||
" mrs r0, psp \n"
|
||||
" b route_svc \n"
|
||||
"stack_on_msp: \n"
|
||||
" mrs r0, msp \n"
|
||||
" b route_svc \n"
|
||||
" \n"
|
||||
"route_svc: \n"
|
||||
" ldr r2, [r0, #24] \n"
|
||||
" subs r2, #2 \n"
|
||||
" ldrb r3, [r2, #0] \n"
|
||||
" cmp r3, %0 \n"
|
||||
" beq system_call_enter \n"
|
||||
" cmp r3, %1 \n"
|
||||
" beq system_call_enter_1 \n"
|
||||
" cmp r3, %2 \n"
|
||||
" beq system_call_exit \n"
|
||||
" b vPortSVCHandler_C \n"
|
||||
" \n"
|
||||
"system_call_enter: \n"
|
||||
" b vSystemCallEnter \n"
|
||||
"system_call_enter_1: \n"
|
||||
" b vSystemCallEnter_1 \n"
|
||||
"system_call_exit: \n"
|
||||
" b vSystemCallExit \n"
|
||||
" \n"
|
||||
: /* No outputs. */
|
||||
:"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
|
||||
: "r0", "r1", "r2", "r3", "memory"
|
||||
);
|
||||
}
|
||||
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
".syntax unified \n"
|
||||
".extern vPortSVCHandler_C \n"
|
||||
".extern vSystemCallEnter \n"
|
||||
".extern vSystemCallEnter_1 \n"
|
||||
".extern vSystemCallExit \n"
|
||||
" \n"
|
||||
"movs r0, #4 \n"
|
||||
"mov r1, lr \n"
|
||||
"tst r0, r1 \n"
|
||||
"beq stack_on_msp \n"
|
||||
"stack_on_psp: \n"
|
||||
" mrs r0, psp \n"
|
||||
" b route_svc \n"
|
||||
"stack_on_msp: \n"
|
||||
" mrs r0, msp \n"
|
||||
" b route_svc \n"
|
||||
" \n"
|
||||
"route_svc: \n"
|
||||
" ldr r2, [r0, #24] \n"
|
||||
" subs r2, #2 \n"
|
||||
" ldrb r3, [r2, #0] \n"
|
||||
" cmp r3, %0 \n"
|
||||
" beq system_call_enter \n"
|
||||
" cmp r3, %1 \n"
|
||||
" beq system_call_enter_1 \n"
|
||||
" cmp r3, %2 \n"
|
||||
" beq system_call_exit \n"
|
||||
" b vPortSVCHandler_C \n"
|
||||
" \n"
|
||||
"system_call_enter: \n"
|
||||
" b vSystemCallEnter \n"
|
||||
"system_call_enter_1: \n"
|
||||
" b vSystemCallEnter_1 \n"
|
||||
"system_call_exit: \n"
|
||||
" b vSystemCallExit \n"
|
||||
" \n"
|
||||
: /* No outputs. */
|
||||
: "i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
|
||||
: "r0", "r1", "r2", "r3", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
||||
|
||||
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" movs r0, #4 \n"
|
||||
" mov r1, lr \n"
|
||||
" tst r0, r1 \n"
|
||||
" beq stacking_used_msp \n"
|
||||
" mrs r0, psp \n"
|
||||
" ldr r2, svchandler_address_const \n"
|
||||
" bx r2 \n"
|
||||
" stacking_used_msp: \n"
|
||||
" mrs r0, msp \n"
|
||||
" ldr r2, svchandler_address_const \n"
|
||||
" bx r2 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"svchandler_address_const: .word vPortSVCHandler_C \n"
|
||||
);
|
||||
}
|
||||
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
||||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" movs r0, #4 \n"
|
||||
" mov r1, lr \n"
|
||||
" tst r0, r1 \n"
|
||||
" beq stacking_used_msp \n"
|
||||
" mrs r0, psp \n"
|
||||
" ldr r2, svchandler_address_const \n"
|
||||
" bx r2 \n"
|
||||
" stacking_used_msp: \n"
|
||||
" mrs r0, msp \n"
|
||||
" ldr r2, svchandler_address_const \n"
|
||||
" bx r2 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"svchandler_address_const: .word vPortSVCHandler_C \n"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -48,9 +48,9 @@
|
|||
/**
|
||||
* Architecture specifics.
|
||||
*/
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* ARMv8-M common port configurations. */
|
||||
|
|
|
|||
|
|
@ -81,8 +81,8 @@ typedef unsigned long UBaseType_t;
|
|||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#else
|
||||
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
|
||||
|
|
@ -117,7 +117,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
|
|||
extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
|
||||
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
|
||||
extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
|
||||
extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
|
||||
|
|
@ -188,13 +188,13 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
|
||||
/**
|
||||
* @brief Settings to define an MPU region.
|
||||
*/
|
||||
/**
|
||||
* @brief Settings to define an MPU region.
|
||||
*/
|
||||
typedef struct MPURegionSettings
|
||||
{
|
||||
uint32_t ulRBAR; /**< RBAR for the region. */
|
||||
uint32_t ulRLAR; /**< RLAR for the region. */
|
||||
uint32_t ulRBAR; /**< RBAR for the region. */
|
||||
uint32_t ulRLAR; /**< RLAR for the region. */
|
||||
} MPURegionSettings_t;
|
||||
|
||||
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
|
||||
|
|
@ -203,9 +203,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
#error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System call stack.
|
||||
*/
|
||||
/**
|
||||
* @brief System call stack.
|
||||
*/
|
||||
typedef struct SYSTEM_CALL_STACK_INFO
|
||||
{
|
||||
uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
|
||||
|
|
@ -218,74 +218,74 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
|
||||
#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
|
||||
|
||||
/**
|
||||
* @brief MPU settings as stored in the TCB.
|
||||
*/
|
||||
/**
|
||||
* @brief MPU settings as stored in the TCB.
|
||||
*/
|
||||
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
||||
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
|
||||
/*
|
||||
* +-----------+---------------+----------+-----------------+------------------------------+-----+
|
||||
* | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
|
||||
* | | | | PC, xPSR | CONTROL, EXC_RETURN | |
|
||||
* +-----------+---------------+----------+-----------------+------------------------------+-----+
|
||||
*
|
||||
* <-----------><--------------><---------><----------------><-----------------------------><---->
|
||||
* 16 16 8 8 5 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 54
|
||||
/*
|
||||
* +-----------+---------------+----------+-----------------+------------------------------+-----+
|
||||
* | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
|
||||
* | | | | PC, xPSR | CONTROL, EXC_RETURN | |
|
||||
* +-----------+---------------+----------+-----------------+------------------------------+-----+
|
||||
*
|
||||
* <-----------><--------------><---------><----------------><-----------------------------><---->
|
||||
* 16 16 8 8 5 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 54
|
||||
|
||||
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
|
||||
|
||||
/*
|
||||
* +-----------+---------------+----------+-----------------+----------------------+-----+
|
||||
* | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
|
||||
* | | | | PC, xPSR | EXC_RETURN | |
|
||||
* +-----------+---------------+----------+-----------------+----------------------+-----+
|
||||
*
|
||||
* <-----------><--------------><---------><----------------><---------------------><---->
|
||||
* 16 16 8 8 4 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 53
|
||||
/*
|
||||
* +-----------+---------------+----------+-----------------+----------------------+-----+
|
||||
* | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
|
||||
* | | | | PC, xPSR | EXC_RETURN | |
|
||||
* +-----------+---------------+----------+-----------------+----------------------+-----+
|
||||
*
|
||||
* <-----------><--------------><---------><----------------><---------------------><---->
|
||||
* 16 16 8 8 4 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 53
|
||||
|
||||
#endif /* #if( configENABLE_TRUSTZONE == 1 ) */
|
||||
|
||||
#else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
|
||||
|
||||
#if( configENABLE_TRUSTZONE == 1 )
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
|
||||
/*
|
||||
* +----------+-----------------+------------------------------+-----+
|
||||
* | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
|
||||
* | | PC, xPSR | CONTROL, EXC_RETURN | |
|
||||
* +----------+-----------------+------------------------------+-----+
|
||||
*
|
||||
* <---------><----------------><------------------------------><---->
|
||||
* 8 8 5 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 22
|
||||
/*
|
||||
* +----------+-----------------+------------------------------+-----+
|
||||
* | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | |
|
||||
* | | PC, xPSR | CONTROL, EXC_RETURN | |
|
||||
* +----------+-----------------+------------------------------+-----+
|
||||
*
|
||||
* <---------><----------------><------------------------------><---->
|
||||
* 8 8 5 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 22
|
||||
|
||||
#else /* #if( configENABLE_TRUSTZONE == 1 ) */
|
||||
|
||||
/*
|
||||
* +----------+-----------------+----------------------+-----+
|
||||
* | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
|
||||
* | | PC, xPSR | EXC_RETURN | |
|
||||
* +----------+-----------------+----------------------+-----+
|
||||
*
|
||||
* <---------><----------------><----------------------><---->
|
||||
* 8 8 4 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 21
|
||||
/*
|
||||
* +----------+-----------------+----------------------+-----+
|
||||
* | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | |
|
||||
* | | PC, xPSR | EXC_RETURN | |
|
||||
* +----------+-----------------+----------------------+-----+
|
||||
*
|
||||
* <---------><----------------><----------------------><---->
|
||||
* 8 8 4 1
|
||||
*/
|
||||
#define MAX_CONTEXT_SIZE 21
|
||||
|
||||
#endif /* #if( configENABLE_TRUSTZONE == 1 ) */
|
||||
|
||||
#endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
|
||||
|
||||
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
|
||||
#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
|
||||
#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
|
||||
/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
|
||||
#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
|
||||
#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
|
||||
|
||||
typedef struct MPU_SETTINGS
|
||||
{
|
||||
|
|
@ -364,49 +364,49 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
|
||||
#if ( configENABLE_TRUSTZONE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Allocate a secure context for the task.
|
||||
*
|
||||
* Tasks are not created with a secure context. Any task that is going to call
|
||||
* secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
|
||||
* secure context before it calls any secure function.
|
||||
*
|
||||
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
|
||||
*/
|
||||
/**
|
||||
* @brief Allocate a secure context for the task.
|
||||
*
|
||||
* Tasks are not created with a secure context. Any task that is going to call
|
||||
* secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
|
||||
* secure context before it calls any secure function.
|
||||
*
|
||||
* @param[in] ulSecureStackSize The size of the secure stack to be allocated.
|
||||
*/
|
||||
#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
|
||||
|
||||
/**
|
||||
* @brief Called when a task is deleted to delete the task's secure context,
|
||||
* if it has one.
|
||||
*
|
||||
* @param[in] pxTCB The TCB of the task being deleted.
|
||||
*/
|
||||
/**
|
||||
* @brief Called when a task is deleted to delete the task's secure context,
|
||||
* if it has one.
|
||||
*
|
||||
* @param[in] pxTCB The TCB of the task being deleted.
|
||||
*/
|
||||
#define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
|
||||
#endif /* configENABLE_TRUSTZONE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the processor is privileged.
|
||||
*
|
||||
* @return 1 if the processor is already privileged, 0 otherwise.
|
||||
*/
|
||||
/**
|
||||
* @brief Checks whether or not the processor is privileged.
|
||||
*
|
||||
* @return 1 if the processor is already privileged, 0 otherwise.
|
||||
*/
|
||||
#define portIS_PRIVILEGED() xIsPrivileged()
|
||||
|
||||
/**
|
||||
* @brief Raise an SVC request to raise privilege.
|
||||
*
|
||||
* The SVC handler checks that the SVC was raised from a system call and only
|
||||
* then it raises the privilege. If this is called from any other place,
|
||||
* the privilege is not raised.
|
||||
*/
|
||||
/**
|
||||
* @brief Raise an SVC request to raise privilege.
|
||||
*
|
||||
* The SVC handler checks that the SVC was raised from a system call and only
|
||||
* then it raises the privilege. If this is called from any other place,
|
||||
* the privilege is not raised.
|
||||
*/
|
||||
#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
|
||||
|
||||
/**
|
||||
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
|
||||
* register.
|
||||
*/
|
||||
/**
|
||||
* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
|
||||
* register.
|
||||
*/
|
||||
#define portRESET_PRIVILEGE() vResetPrivilege()
|
||||
#else
|
||||
#define portIS_PRIVILEGED()
|
||||
|
|
@ -419,12 +419,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
|
||||
extern BaseType_t xPortIsTaskPrivileged( void );
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the calling task is privileged.
|
||||
*
|
||||
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
|
||||
*/
|
||||
#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
|
||||
/**
|
||||
* @brief Checks whether or not the calling task is privileged.
|
||||
*
|
||||
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
|
||||
*/
|
||||
#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
|
||||
|
||||
#endif /* configENABLE_MPU == 1 */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -439,9 +439,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
* based on whether or not Mainline extension is implemented. */
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#else
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#endif
|
||||
#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
|
|
@ -450,9 +450,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
*/
|
||||
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||
|
||||
/**
|
||||
* @brief Count the number of leading zeros in a 32-bit value.
|
||||
*/
|
||||
/**
|
||||
* @brief Count the number of leading zeros in a 32-bit value.
|
||||
*/
|
||||
static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint32_t ulReturn;
|
||||
|
|
@ -462,7 +462,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
return ulReturn;
|
||||
}
|
||||
|
||||
/* Check the configuration. */
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
|
@ -471,16 +471,16 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
|
|||
#error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Store/clear the ready priorities in a bit map.
|
||||
*/
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/**
|
||||
* @brief Store/clear the ready priorities in a bit map.
|
||||
*/
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/**
|
||||
* @brief Get the priority of the highest-priority task that is ready to execute.
|
||||
*/
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
/**
|
||||
* @brief Get the priority of the highest-priority task that is ready to execute.
|
||||
*/
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue