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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
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485 changed files with 108790 additions and 107581 deletions
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@ -28,45 +28,45 @@
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/*-----------------------------------------------------------
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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/*
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Changes from V2.5.2
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+ The critical section management functions have been changed. These no
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longer modify the stack and are safe to use at all optimisation levels.
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The functions are now also the same for both ARM and THUMB modes.
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Changes from V2.6.0
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+ Removed the 'static' from the definition of vNonPreemptiveTick() to
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allow the demo to link when using the cooperative scheduler.
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Changes from V3.2.4
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+ The assembler statements are now included in a single asm block rather
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than each line having its own asm block.
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*/
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* Changes from V2.5.2
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*
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+ The critical section management functions have been changed. These no
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+ longer modify the stack and are safe to use at all optimisation levels.
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+ The functions are now also the same for both ARM and THUMB modes.
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+
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+ Changes from V2.6.0
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+
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+ Removed the 'static' from the definition of vNonPreemptiveTick() to
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+ allow the demo to link when using the cooperative scheduler.
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+
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+ Changes from V3.2.4
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+
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+ The assembler statements are now included in a single asm block rather
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+ than each line having its own asm block.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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/* Constants required to handle interrupts. */
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#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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volatile uint32_t ulCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/* ISR to handle manual context switches (from a call to taskYIELD()). */
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void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) );
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/*
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* The scheduler can only be started from ARM mode, hence the inclusion of this
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@ -78,7 +78,7 @@ void vPortISRStartFirstTask( void );
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void vPortISRStartFirstTask( void )
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{
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/* Simply start the scheduler. This is included here as it can only be
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called from ARM mode. */
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* called from ARM mode. */
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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@ -94,8 +94,8 @@ void vPortISRStartFirstTask( void )
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void vPortYieldProcessor( void )
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{
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/* Within an IRQ ISR the link register has an offset from the true return
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address, but an SWI ISR does not. Add the offset manually so the same
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ISR return code can be used in both cases. */
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* address, but an SWI ISR does not. Add the offset manually so the same
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* ISR return code can be used in both cases. */
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__asm volatile ( "ADD LR, LR, #4" );
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/* Perform the context switch. First save the context of the current task. */
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@ -112,14 +112,14 @@ void vPortYieldProcessor( void )
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/*
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* The ISR used for the scheduler tick.
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*/
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void vTickISR( void ) __attribute__((naked));
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void vTickISR( void ) __attribute__( ( naked ) );
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void vTickISR( void )
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{
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/* Save the context of the interrupted task. */
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portSAVE_CONTEXT();
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/* Increment the RTOS tick count, then look for the highest priority
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task that is ready to run. */
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* task that is ready to run. */
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__asm volatile
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(
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" bl xTaskIncrementTick \t\n" \
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@ -146,50 +146,50 @@ void vTickISR( void )
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*/
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#ifdef THUMB_INTERWORK
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void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) );
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void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) );
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void vPortDisableInterruptsFromThumb( void )
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{
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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void vPortEnableInterruptsFromThumb( void )
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{
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0} \n\t" /* Pop R0. */
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"BX R14" ); /* Return back to thumb. */
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}
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#endif /* THUMB_INTERWORK */
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/* The code generated by the GCC compiler uses the stack in different ways at
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different optimisation levels. The interrupt flags can therefore not always
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be saved to the stack. Instead the critical section nesting level is stored
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in a variable, which is then saved as part of the stack context. */
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* different optimisation levels. The interrupt flags can therefore not always
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* be saved to the stack. Instead the critical section nesting level is stored
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* in a variable, which is then saved as part of the stack context. */
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void vPortEnterCritical( void )
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{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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/* Now that interrupts are disabled, ulCriticalNesting can be accessed
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* directly. Increment ulCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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@ -201,16 +201,16 @@ void vPortExitCritical( void )
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ulCriticalNesting--;
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/* If the nesting level has reached zero then interrupts should be
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re-enabled. */
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* re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable interrupts as per portEXIT_CRITICAL(). */
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__asm volatile (
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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"STMDB SP!, {R0} \n\t" /* Push R0. */
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"MRS R0, CPSR \n\t" /* Get CPSR. */
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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"MSR CPSR, R0 \n\t" /* Write back modified value. */
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"LDMIA SP!, {R0}" ); /* Pop R0. */
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}
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}
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}
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