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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Update FreeRTOS+ components and demos to use typedef names introduced in FreeRTOS V8.
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4ce4de750a
commit
5e47df8c01
66 changed files with 395 additions and 395 deletions
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@ -71,7 +71,7 @@
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operation will be held in the Blocked state (so other tasks can execute) for
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niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS
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before giving up. */
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#define niTX_BUFFER_FREE_WAIT ( ( portTickType ) 2UL / portTICK_RATE_MS )
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#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS )
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#define niMAX_TX_ATTEMPTS ( 5 )
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/*-----------------------------------------------------------*/
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@ -92,10 +92,10 @@ static xSemaphoreHandle xEMACRxEventSemaphore = NULL;
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceInitialise( void )
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BaseType_t xNetworkInterfaceInitialise( void )
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{
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EMAC_CFG_Type Emac_Config;
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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extern uint8_t ucMACAddress[ 6 ];
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Emac_Config.pbEMAC_Addr = ucMACAddress;
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@ -141,9 +141,9 @@ extern uint8_t ucMACAddress[ 6 ];
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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{
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portBASE_TYPE xReturn = pdFAIL;
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BaseType_t xReturn = pdFAIL;
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int32_t x;
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/* Attempt to obtain access to a Tx descriptor. */
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@ -236,7 +236,7 @@ xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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{
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/* The buffer filled by the DMA is going to be passed into the IP
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stack. Allocate another buffer for the DMA descriptor. */
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pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( portTickType ) 0 );
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pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 );
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if( pxNetworkBuffer != NULL )
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{
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@ -273,7 +273,7 @@ xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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/* Data was received and stored. Send it to the IP task
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for processing. */
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xRxEvent.pvData = ( void * ) pxNetworkBuffer;
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( portTickType ) 0 ) == pdFALSE )
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE )
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{
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/* The buffer could not be sent to the IP task so the
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buffer must be released. */
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@ -81,13 +81,13 @@ static void setEmacAddr( uint8_t abStationAddr[] );
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* all remain interrupts are disabled
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* (Ref. from LPC17xx UM)
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**********************************************************************/
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portBASE_TYPE EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
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BaseType_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
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{
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int32_t id1, id2, regv, phy = 0;
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int32_t phy_linkstatus_reg, phy_linkstatus_mask;
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uint32_t x;
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const uint32_t ulMaxAttempts = 250UL;
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portBASE_TYPE xReturn = pdPASS;
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BaseType_t xReturn = pdPASS;
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/* Enable Ethernet Pins (NGX LPC1830 Xplorer. */
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scu_pinmux(0x2 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7);
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@ -287,9 +287,9 @@ portBASE_TYPE xReturn = pdPASS;
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/*********************************************************************//**
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**********************************************************************/
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portBASE_TYPE EMAC_CheckTransmitIndex( void )
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BaseType_t EMAC_CheckTransmitIndex( void )
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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if( ( Tx_Desc[ TxDescIndex ].Status & OWN_BIT ) == 0 )
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{
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@ -374,9 +374,9 @@ void EMAC_UpdateRxConsumeIndex( void )
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* it means there're available data has been received. They should be read
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* out and released the Receive Data Buffer by updating the RxConsumeIndex value.
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**********************************************************************/
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portBASE_TYPE EMAC_CheckReceiveIndex(void)
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BaseType_t EMAC_CheckReceiveIndex(void)
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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if( ( Rx_Desc[ RxDescIndex ].Status & OWN_BIT ) == 0 )
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{
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@ -215,15 +215,15 @@ typedef struct {
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/* Prototypes */
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portBASE_TYPE EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
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BaseType_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
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int32_t EMAC_UpdatePHYStatus(void);
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uint32_t EMAC_GetReceiveDataSize(void);
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void EMAC_StartTransmitNextBuffer( uint32_t ulLength );
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void EMAC_SetNextPacketToSend( uint8_t * pucBuffer );
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void EMAC_NextPacketToRead( xNetworkBufferDescriptor_t *pxNetworkBuffer );
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void EMAC_UpdateRxConsumeIndex(void);
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portBASE_TYPE EMAC_CheckReceiveIndex(void);
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portBASE_TYPE EMAC_CheckTransmitIndex(void);
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BaseType_t EMAC_CheckReceiveIndex(void);
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BaseType_t EMAC_CheckTransmitIndex(void);
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#ifdef __cplusplus
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}
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@ -78,7 +78,7 @@
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operation will be held in the Blocked state (so other tasks can execute) for
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niTX_BUFFER_FREE_WAIT ticks. It will do this a maximum of niMAX_TX_ATTEMPTS
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before giving up. */
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#define niTX_BUFFER_FREE_WAIT ( ( portTickType ) 2UL / portTICK_RATE_MS )
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#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_RATE_MS )
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#define niMAX_TX_ATTEMPTS ( 5 )
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/*-----------------------------------------------------------*/
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@ -99,9 +99,9 @@ xSemaphoreHandle xEMACRxEventSemaphore = NULL;
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceInitialise( void )
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BaseType_t xNetworkInterfaceInitialise( void )
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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extern uint8_t ucMACAddress[ 6 ];
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xReturn = xEMACInit( ucMACAddress );
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@ -138,9 +138,9 @@ extern uint8_t ucMACAddress[ 6 ];
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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BaseType_t xNetworkInterfaceOutput( xNetworkBufferDescriptor_t * const pxNetworkBuffer )
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{
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portBASE_TYPE xReturn = pdFAIL;
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BaseType_t xReturn = pdFAIL;
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int32_t x;
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/* Attempt to obtain access to a Tx descriptor. */
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@ -203,7 +203,7 @@ xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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{
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/* The buffer filled by the DMA is going to be passed into the IP
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stack. Allocate another buffer for the DMA descriptor. */
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pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( portTickType ) 0 );
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pxNetworkBuffer = pxNetworkBufferGet( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 );
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if( pxNetworkBuffer != NULL )
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{
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@ -240,7 +240,7 @@ xIPStackEvent_t xRxEvent = { eEthernetRxEvent, NULL };
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/* Data was received and stored. Send it to the IP task
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for processing. */
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xRxEvent.pvData = ( void * ) pxNetworkBuffer;
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( portTickType ) 0 ) == pdFALSE )
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if( xQueueSendToBack( xNetworkEventQueue, &xRxEvent, ( TickType_t ) 0 ) == pdFALSE )
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{
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/* The buffer could not be sent to the IP task so the
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buffer must be released. */
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@ -84,9 +84,9 @@ static unsigned int xTxDescriptorIndex = 0;
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/*-----------------------------------------------------------*/
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portBASE_TYPE xEMACInit( uint8_t ucMACAddress[ 6 ] )
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BaseType_t xEMACInit( uint8_t ucMACAddress[ 6 ] )
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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uint32_t ulPHYStatus;
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/* Configure the hardware. */
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@ -151,9 +151,9 @@ uint32_t ulPHYStatus;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xEMACIsTxDescriptorAvailable( void )
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BaseType_t xEMACIsTxDescriptorAvailable( void )
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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if( ( xTxDescriptors[ xTxDescriptorIndex ].CTRLSTAT & RDES_OWN ) == 0 )
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{
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@ -215,9 +215,9 @@ void vEMACReturnRxDescriptor( void )
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xEMACRxDataAvailable( void )
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BaseType_t xEMACRxDataAvailable( void )
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{
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portBASE_TYPE xReturn;
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BaseType_t xReturn;
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if( ( xRXDescriptors[ xRxDescriptorIndex ].STATUS & RDES_OWN ) == 0 )
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{
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@ -46,13 +46,13 @@
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/*
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* Initialise the MAC and PHY.
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*/
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portBASE_TYPE xEMACInit( uint8_t ucMACAddress[ 6 ] );
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BaseType_t xEMACInit( uint8_t ucMACAddress[ 6 ] );
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/*
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* Return pdTRUE if there is a FreeRTOS Tx descriptor. Return pdFALSE if all
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* Tx descriptors are already in use.
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*/
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portBASE_TYPE xEMACIsTxDescriptorAvailable( void );
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BaseType_t xEMACIsTxDescriptorAvailable( void );
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/*
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* Assign a buffer to a Tx descriptor so it is ready to be transmitted, but
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@ -77,7 +77,7 @@ void vEMACReturnRxDescriptor( void );
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* Returns pdTRUE if the next Rx descriptor contains received data. Returns
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* pdFLASE fi the next Rx descriptor is still under the control of the DMA.
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*/
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portBASE_TYPE xEMACRxDataAvailable( void );
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BaseType_t xEMACRxDataAvailable( void );
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void vEMACSwapEmptyBufferForRxedData( xNetworkBufferDescriptor_t *pxNetworkBuffer );
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#endif /* LPC18xx_43xx_EMAC_H */
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