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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Update the Cortex-M3 IAR projects to compile with EWARM 6.20 where necessary.
This commit is contained in:
Richard Barry
parent
d873c2705d
commit
5ddcf3d36a
40 changed files with 3395 additions and 10237 deletions
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@ -619,159 +619,183 @@ static __INLINE void __set_CONTROL(uint32_t control)
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#endif /* __ARMCC_VERSION */
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#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
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/* IAR iccarm specific functions */
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#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
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#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
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#if (__VER__ >= 6020000) // If iccarm version is 6.20.0 or later ----------
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static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
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static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
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#include <cmsis_iar.h>
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static __INLINE void __WFI() { __ASM ("wfi"); }
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static __INLINE void __WFE() { __ASM ("wfe"); }
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static __INLINE void __SEV() { __ASM ("sev"); }
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static __INLINE void __CLREX() { __ASM ("clrex"); }
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#else
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/**
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* @brief Return the Process Stack Pointer
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*
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* @param none
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* @return uint32_t ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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extern uint32_t __get_PSP(void);
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#pragma diag_suppress=Pe940
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#pragma diag_suppress=Pe177
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param uint32_t Process Stack Pointer
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* @return none
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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extern void __set_PSP(uint32_t topOfProcStack);
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#define __enable_irq __enable_interrupt
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#define __disable_irq __disable_interrupt
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#define __NOP __no_operation
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/**
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* @brief Return the Main Stack Pointer
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*
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* @param none
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* @return uint32_t Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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extern uint32_t __get_MSP(void);
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#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param uint32_t Main Stack Pointer
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* @return none
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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extern void __set_MSP(uint32_t topOfMainStack);
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#if (__VER__ < 6010002) // If iccarm version is older than 6.10.2 ----------
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/**
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* @brief Reverse byte order in unsigned short value
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*
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* @param uint16_t value to reverse
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* @return uint32_t reversed value
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*
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* Reverse byte order in unsigned short value
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*/
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extern uint32_t __REV16(uint16_t value);
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static uint32_t __get_APSR(void)
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{
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__ASM("mrs r0, apsr");
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}
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/**
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* @brief Reverse bit order of value
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*
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* @param uint32_t value to reverse
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* @return uint32_t reversed value
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*
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* Reverse bit order of value
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*/
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extern uint32_t __RBIT(uint32_t value);
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static uint32_t __get_xPSR(void)
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{
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__ASM("mrs r0, psr"); // assembler does not know "xpsr"
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}
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/**
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* @brief LDR Exclusive
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*
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* @param uint8_t* address
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* @return uint8_t value of (*address)
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*
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* Exclusive LDR command
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*/
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extern uint8_t __LDREXB(uint8_t *addr);
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#endif // __VER__ < 6010002
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/**
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* @brief LDR Exclusive
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*
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* @param uint16_t* address
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* @return uint16_t value of (*address)
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*
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* Exclusive LDR command
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*/
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extern uint16_t __LDREXH(uint16_t *addr);
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static uint32_t __get_IPSR(void)
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{
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__ASM("mrs r0, ipsr");
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}
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/**
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* @brief LDR Exclusive
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*
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* @param uint32_t* address
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* @return uint32_t value of (*address)
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*
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* Exclusive LDR command
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*/
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extern uint32_t __LDREXW(uint32_t *addr);
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static uint32_t __get_PSR(void)
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{
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__ASM("mrs r0, psr");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint8_t *address
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* @param uint8_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
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static uint32_t __get_PSP(void)
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{
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__ASM("mrs r0, psp");
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}
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static void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM("msr psp, r0");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint16_t *address
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* @param uint16_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
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static uint32_t __get_MSP(void)
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{
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__ASM("mrs r0, msp");
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}
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static void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM("msr msp, r0");
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}
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/**
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* @brief STR Exclusive
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*
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* @param uint32_t *address
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* @param uint32_t value to store
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* @return uint32_t successful / failed
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*
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* Exclusive STR command
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*/
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extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
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static __INLINE void __WFI(void)
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{
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__ASM ("wfi");
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}
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static __INLINE void __WFE(void)
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{
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__ASM ("wfe");
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}
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/* intrinsic void __set_PRIMASK(); */
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/* intrinsic void __get_PRIMASK(); */
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/* intrinsic void __set_FAULTMASK(); */
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/* intrinsic void __get_FAULTMASK(); */
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/* intrinsic uint32_t __REV(uint32_t value); */
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/* intrinsic uint32_t __REVSH(uint32_t value); */
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/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
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/* intrinsic unsigned long __LDREX(unsigned long *); */
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static __INLINE void __SEV(void)
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{
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__ASM ("sev");
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}
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static uint32_t __REV16(uint32_t value)
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{
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__ASM("rev16 r0, r0");
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}
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#endif // __VER__ < 6020000
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#if (__CORTEX_M >= 0x03) // __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h.
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#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------
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static __INLINE void __enable_fault_irq(void)
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{
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__ASM ("cpsie f");
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}
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static __INLINE void __disable_fault_irq(void)
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{
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__ASM ("cpsid f");
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}
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static uint32_t __RBIT(uint32_t value)
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{
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__ASM("rbit r0, r0");
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}
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static uint8_t __LDREXB(volatile uint8_t *addr)
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{
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__ASM("ldrexb r0, [r0]");
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}
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static uint16_t __LDREXH(volatile uint16_t *addr)
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{
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__ASM("ldrexh r0, [r0]");
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}
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static uint32_t __LDREXW(volatile uint32_t *addr)
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{
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__ASM("ldrex r0, [r0]");
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}
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static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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{
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__ASM("strexb r0, r0, [r1]");
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}
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static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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{
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__ASM("strexh r0, r0, [r1]");
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}
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static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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{
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__ASM("strex r0, r0, [r1]");
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}
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static __INLINE void __CLREX(void)
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{
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__ASM ("clrex");
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}
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#else // __VER__ >= 6020000 ---------------------
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#define __LDREXW __LDREX
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#define __STREXW __STREX
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#define __enable_fault_irq __enable_fiq
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#define __disable_fault_irq __disable_fiq
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#endif // __VER__ < 6020000
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04) // __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h.
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#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------
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static uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) // __FPU_PRESENT is defined in the device header file, if present in current device.
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__ASM("vmrs r0, fpscr");
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#else
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return(0);
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#endif
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}
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static void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1) // __FPU_PRESENT is defined in the device header file, if present in current device.
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__ASM("vmsr fpscr, r0");
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#endif
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}
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#endif // __VER__ < 6020000
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#endif /* (__CORTEX_M == 0x04) */
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#pragma diag_default=Pe940
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#pragma diag_default=Pe177
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#endif // __VER__ >= 6020000
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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