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Complete RX64M GCC demo.
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Richard Barry
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23 changed files with 1538 additions and 356 deletions
181
FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c
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FreeRTOS/Demo/RX600_RX64M_RSK_GCC_e2studio/src/IntQueueTimer.c
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/*
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FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to !<<
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>>! distribute a combined work that includes FreeRTOS without being !<<
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>>! obliged to provide the source code for proprietary components !<<
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>>! outside of the FreeRTOS kernel. !<<
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
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mission critical applications that require provable dependability.
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*/
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/*
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* This file contains the non-portable and therefore RX64M specific parts of
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* the IntQueue standard demo task - namely the configuration of the timers
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* that generate the interrupts and the interrupt entry points.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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#define IPR_PERIB_INTB128 128
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#define IPR_PERIB_INTB129 129
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#define IER_PERIB_INTB128 0x10
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#define IER_PERIB_INTB129 0x10
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#define IEN_PERIB_INTB128 IEN0
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#define IEN_PERIB_INTB129 IEN1
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#define IR_PERIB_INTB128 128
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#define IR_PERIB_INTB129 129
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void vIntQTimerISR0( void ) __attribute__ ((interrupt));
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void vIntQTimerISR1( void ) __attribute__ ((interrupt));
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#define tmrTIMER_0_1_FREQUENCY ( 2000UL )
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#define tmrTIMER_2_3_FREQUENCY ( 2001UL )
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void vInitialiseTimerForIntQueueTest( void )
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{
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/* Ensure interrupts do not start until full configuration is complete. */
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portENTER_CRITICAL();
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{
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/* Give write access. */
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SYSTEM.PRCR.WORD = 0xa502;
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/* Cascade two 8bit timer channels to generate the interrupts.
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8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
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utilised for this test. */
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/* Enable the timers. */
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SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
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SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
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/* Enable compare match A interrupt request. */
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Clear the timer on compare match A. */
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TMR0.TCR.BIT.CCLR = 1;
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TMR2.TCR.BIT.CCLR = 1;
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/* Set the compare match value. */
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TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
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/* 16 bit operation ( count from timer 1,2 ). */
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TMR0.TCCR.BIT.CSS = 3;
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TMR2.TCCR.BIT.CSS = 3;
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/* Use PCLK as the input. */
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TMR1.TCCR.BIT.CSS = 1;
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TMR3.TCCR.BIT.CSS = 1;
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/* Divide PCLK by 8. */
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TMR1.TCCR.BIT.CKS = 2;
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TMR3.TCCR.BIT.CKS = 2;
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/* Enable TMR 0, 2 interrupts. */
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TMR0.TCR.BIT.CMIEA = 1;
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TMR2.TCR.BIT.CMIEA = 1;
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/* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set
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priority above the kernel's priority, but below the max syscall
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priority. */
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ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */
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IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
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IEN( PERIB, INTB128 ) = 1;
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/* Ensure that the flag is set to 0, otherwise the interrupt will not be
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accepted. */
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IR( PERIB, INTB128 ) = 0;
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/* Do the same for TMR2, but to vector 129. */
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ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */
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IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
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IEN( PERIB, INTB129 ) = 1;
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IR( PERIB, INTB129 ) = 0;
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}
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portEXIT_CRITICAL();
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}
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/*-----------------------------------------------------------*/
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/* On vector 128. */
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void vIntQTimerISR0( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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portYIELD_FROM_ISR( xFirstTimerHandler() );
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}
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/*-----------------------------------------------------------*/
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/* On vector 129. */
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void vIntQTimerISR1( void )
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{
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/* Enable interrupts to allow interrupt nesting. */
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__asm volatile( "setpsw i" );
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portYIELD_FROM_ISR( xSecondTimerHandler() );
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}
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