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Before changing headers to V6 and changing portLONG, portSHORt and portCHAR to their standard C types.

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This commit is contained in:
Richard Barry 2009-10-05 08:33:08 +00:00
parent 3dfbb349ca
commit 5c64e1fad9
4417 changed files with 1261274 additions and 0 deletions
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89
20091005/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_H__
#define __MCF52221_H__
/********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
#ifdef __cplusplus
extern "C" {
#endif
#pragma define_section system ".system" far_absolute RW
/***
* MCF52221 Derivative Memory map definitions from linker command files:
* __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
* symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __IPSBAR[];
extern __declspec(system) uint8 __RAMBAR[];
extern __declspec(system) uint8 __RAMBAR_SIZE[];
extern __declspec(system) uint8 __FLASHBAR[];
extern __declspec(system) uint8 __FLASHBAR_SIZE[];
#define IPSBAR_ADDRESS (uint32)__IPSBAR
#define RAMBAR_ADDRESS (uint32)__RAMBAR
#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
#include "MCF52221_SCM.h"
#include "MCF52221_DMA.h"
#include "MCF52221_UART.h"
#include "MCF52221_I2C.h"
#include "MCF52221_QSPI.h"
#include "MCF52221_RTC.h"
#include "MCF52221_DTIM.h"
#include "MCF52221_INTC.h"
#include "MCF52221_GPIO.h"
#include "MCF52221_PAD.h"
#include "MCF52221_RCM.h"
#include "MCF52221_CCM.h"
#include "MCF52221_PMM.h"
#include "MCF52221_CLOCK.h"
#include "MCF52221_EPORT.h"
#include "MCF52221_PIT.h"
#include "MCF52221_ADC.h"
#include "MCF52221_GPTA.h"
#include "MCF52221_PWM.h"
#include "MCF52221_USB_OTG.h"
#include "MCF52221_CFM.h"
#ifdef __cplusplus
}
#endif
#endif /* __MCF52221_H__ */

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20091005/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_ADC.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_ADC_H__
#define __MCF52221_ADC_H__
/*********************************************************************
*
* Analog-to-Digital Converter (ADC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000))
#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002))
#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004))
#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006))
#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008))
#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A))
#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C))
#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E))
#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010))
#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012))
#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014))
#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016))
#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018))
#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A))
#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C))
#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E))
#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020))
#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022))
#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024))
#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026))
#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028))
#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A))
#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C))
#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E))
#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030))
#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032))
#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034))
#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036))
#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038))
#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A))
#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C))
#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E))
#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040))
#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042))
#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044))
#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046))
#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048))
#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A))
#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C))
#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E))
#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050))
#define MCF_ADC_POWER (*(vuint16*)(0x40190052))
#define MCF_ADC_CAL (*(vuint16*)(0x40190054))
#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2)))
#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2)))
#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2)))
#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2)))
/* Bit definitions and macros for MCF_ADC_CTRL1 */
#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)
#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)
#define MCF_ADC_CTRL1_HLMTIE (0x100)
#define MCF_ADC_CTRL1_LLMTIE (0x200)
#define MCF_ADC_CTRL1_ZCIE (0x400)
#define MCF_ADC_CTRL1_EOSIE0 (0x800)
#define MCF_ADC_CTRL1_SYNC0 (0x1000)
#define MCF_ADC_CTRL1_START0 (0x2000)
#define MCF_ADC_CTRL1_STOP0 (0x4000)
/* Bit definitions and macros for MCF_ADC_CTRL2 */
#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)
#define MCF_ADC_CTRL2_SIMULT (0x20)
#define MCF_ADC_CTRL2_EOSIE1 (0x800)
#define MCF_ADC_CTRL2_SYNC1 (0x1000)
#define MCF_ADC_CTRL2_START1 (0x2000)
#define MCF_ADC_CTRL2_STOP1 (0x4000)
/* Bit definitions and macros for MCF_ADC_ADZCC */
#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)
#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)
#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)
#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)
#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)
#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)
#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)
#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)
/* Bit definitions and macros for MCF_ADC_ADLST1 */
#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)
#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)
#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)
#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)
/* Bit definitions and macros for MCF_ADC_ADLST2 */
#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)
#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)
#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)
#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)
/* Bit definitions and macros for MCF_ADC_ADSDIS */
#define MCF_ADC_ADSDIS_DS0 (0x1)
#define MCF_ADC_ADSDIS_DS1 (0x2)
#define MCF_ADC_ADSDIS_DS2 (0x4)
#define MCF_ADC_ADSDIS_DS3 (0x8)
#define MCF_ADC_ADSDIS_DS4 (0x10)
#define MCF_ADC_ADSDIS_DS5 (0x20)
#define MCF_ADC_ADSDIS_DS6 (0x40)
#define MCF_ADC_ADSDIS_DS7 (0x80)
/* Bit definitions and macros for MCF_ADC_ADSTAT */
#define MCF_ADC_ADSTAT_RDY0 (0x1)
#define MCF_ADC_ADSTAT_RDY1 (0x2)
#define MCF_ADC_ADSTAT_RDY2 (0x4)
#define MCF_ADC_ADSTAT_RDY3 (0x8)
#define MCF_ADC_ADSTAT_RDY4 (0x10)
#define MCF_ADC_ADSTAT_RDY5 (0x20)
#define MCF_ADC_ADSTAT_RDY6 (0x40)
#define MCF_ADC_ADSTAT_RDY7 (0x80)
#define MCF_ADC_ADSTAT_HLMTI (0x100)
#define MCF_ADC_ADSTAT_LLMTI (0x200)
#define MCF_ADC_ADSTAT_ZCI (0x400)
#define MCF_ADC_ADSTAT_EOSI0 (0x800)
#define MCF_ADC_ADSTAT_EOSI1 (0x1000)
#define MCF_ADC_ADSTAT_CIP1 (0x4000)
#define MCF_ADC_ADSTAT_CIP0 (0x8000)
/* Bit definitions and macros for MCF_ADC_ADLSTAT */
#define MCF_ADC_ADLSTAT_LLS0 (0x1)
#define MCF_ADC_ADLSTAT_LLS1 (0x2)
#define MCF_ADC_ADLSTAT_LLS2 (0x4)
#define MCF_ADC_ADLSTAT_LLS3 (0x8)
#define MCF_ADC_ADLSTAT_LLS4 (0x10)
#define MCF_ADC_ADLSTAT_LLS5 (0x20)
#define MCF_ADC_ADLSTAT_LLS6 (0x40)
#define MCF_ADC_ADLSTAT_LLS7 (0x80)
#define MCF_ADC_ADLSTAT_HLS0 (0x100)
#define MCF_ADC_ADLSTAT_HLS1 (0x200)
#define MCF_ADC_ADLSTAT_HLS2 (0x400)
#define MCF_ADC_ADLSTAT_HLS3 (0x800)
#define MCF_ADC_ADLSTAT_HLS4 (0x1000)
#define MCF_ADC_ADLSTAT_HLS5 (0x2000)
#define MCF_ADC_ADLSTAT_HLS6 (0x4000)
#define MCF_ADC_ADLSTAT_HLS7 (0x8000)
/* Bit definitions and macros for MCF_ADC_ADZCSTAT */
#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)
#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)
#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)
#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)
#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)
#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)
#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)
#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)
/* Bit definitions and macros for MCF_ADC_ADRSLT */
#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)
#define MCF_ADC_ADRSLT_SEXT (0x8000)
/* Bit definitions and macros for MCF_ADC_ADLLMT */
#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)
/* Bit definitions and macros for MCF_ADC_ADHLMT */
#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)
/* Bit definitions and macros for MCF_ADC_ADOFS */
#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)
/* Bit definitions and macros for MCF_ADC_POWER */
#define MCF_ADC_POWER_PD0 (0x1)
#define MCF_ADC_POWER_PD1 (0x2)
#define MCF_ADC_POWER_PD2 (0x4)
#define MCF_ADC_POWER_APD (0x8)
#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)
#define MCF_ADC_POWER_PSTS0 (0x400)
#define MCF_ADC_POWER_PSTS1 (0x800)
#define MCF_ADC_POWER_PSTS2 (0x1000)
#define MCF_ADC_POWER_ASB (0x8000)
/* Bit definitions and macros for MCF_ADC_CAL */
#define MCF_ADC_CAL_SEL_VREFL (0x4000)
#define MCF_ADC_CAL_SEL_VREFH (0x8000)
#endif /* __MCF52221_ADC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CCM_H__
#define __MCF52221_CCM_H__
/*********************************************************************
*
* Chip Configuration Module (CCM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CCM_CCR (*(vuint16*)(0x40110004))
#define MCF_CCM_RCON (*(vuint16*)(0x40110008))
#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))
/* Bit definitions and macros for MCF_CCM_CCR */
#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)
#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)
#define MCF_CCM_CCR_MODE_EZPORT (0x500)
/* Bit definitions and macros for MCF_CCM_RCON */
#define MCF_CCM_RCON_MODE (0x1)
#define MCF_CCM_RCON_RLOAD (0x20)
/* Bit definitions and macros for MCF_CCM_CIR */
#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)
#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)
#endif /* __MCF52221_CCM_H__ */

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20091005/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_CFM.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CFM_H__
#define __MCF52221_CFM_H__
/*********************************************************************
*
* ColdFire Flash Module (CFM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))
#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))
#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))
#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))
#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))
#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))
#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))
#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))
#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))
/* Bit definitions and macros for MCF_CFM_CFMMCR */
#define MCF_CFM_CFMMCR_KEYACC (0x20)
#define MCF_CFM_CFMMCR_CCIE (0x40)
#define MCF_CFM_CFMMCR_CBEIE (0x80)
#define MCF_CFM_CFMMCR_AEIE (0x100)
#define MCF_CFM_CFMMCR_PVIE (0x200)
#define MCF_CFM_CFMMCR_LOCK (0x400)
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
#define MCF_CFM_CFMCLKD_DIVLD (0x80)
/* Bit definitions and macros for MCF_CFM_CFMSEC */
#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
/* Bit definitions and macros for MCF_CFM_CFMPROT */
#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMSACC */
#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMDACC */
#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
#define MCF_CFM_CFMUSTAT_BLANK (0x4)
#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
#define MCF_CFM_CFMUSTAT_CCIF (0x40)
#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
/* Bit definitions and macros for MCF_CFM_CFMCMD */
#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */
#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)
#endif /* __MCF52221_CFM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_CLOCK_H__
#define __MCF52221_CLOCK_H__
/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))
#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))
#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))
#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))
#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))
#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))
#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))
#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))
#define MCF_CLOCK_RTCDR (*(vuint32*)(0x4012000C))
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
#define MCF_CLOCK_SYNCR_PLLEN (0x1)
#define MCF_CLOCK_SYNCR_PLLMODE (0x2)
#define MCF_CLOCK_SYNCR_CLKSRC (0x4)
#define MCF_CLOCK_SYNCR_FWKUP (0x20)
#define MCF_CLOCK_SYNCR_DISCLK (0x40)
#define MCF_CLOCK_SYNCR_LOCEN (0x80)
#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
#define MCF_CLOCK_SYNCR_LOCRE (0x800)
#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
#define MCF_CLOCK_SYNSR_LOCS (0x4)
#define MCF_CLOCK_SYNSR_LOCK (0x8)
#define MCF_CLOCK_SYNSR_LOCKS (0x10)
#define MCF_CLOCK_SYNSR_CRYOSC (0x20)
#define MCF_CLOCK_SYNSR_OCOSC (0x40)
#define MCF_CLOCK_SYNSR_EXTOSC (0x80)
/* Bit definitions and macros for MCF_CLOCK_ROCR */
#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_CLOCK_LPDR */
#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)
/* Bit definitions and macros for MCF_CLOCK_CCHR */
#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)
/* Bit definitions and macros for MCF_CLOCK_CCLR */
#define MCF_CLOCK_CCLR_OSCSEL (0x1)
/* Bit definitions and macros for MCF_CLOCK_OCHR */
#define MCF_CLOCK_OCHR_STBY (0x40)
#define MCF_CLOCK_OCHR_OCOEN (0x80)
/* Bit definitions and macros for MCF_CLOCK_OCLR */
#define MCF_CLOCK_OCLR_RANGE (0x10)
#define MCF_CLOCK_OCLR_LPEN (0x20)
#define MCF_CLOCK_OCLR_REFS (0x40)
#define MCF_CLOCK_OCLR_OSCEN (0x80)
/* Bit definitions and macros for MCF_CLOCK_RTCDR */
#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF52221_CLOCK_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_DMA_H__
#define __MCF52221_DMA_H__
/*********************************************************************
*
* DMA Controller (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))
#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))
#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))
#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))
#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))
#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))
#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))
#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))
#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))
#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))
#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))
#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))
#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))
#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))
#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))
#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))
#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))
#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))
#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))
#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))
#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))
#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))
#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))
#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))
#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))
/* Bit definitions and macros for MCF_DMA_SAR */
#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DAR */
#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DSR */
#define MCF_DMA_DSR_DONE (0x1)
#define MCF_DMA_DSR_BSY (0x2)
#define MCF_DMA_DSR_REQ (0x4)
#define MCF_DMA_DSR_BED (0x10)
#define MCF_DMA_DSR_BES (0x20)
#define MCF_DMA_DSR_CE (0x40)
/* Bit definitions and macros for MCF_DMA_BCR */
#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)
#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_DMA_DCR */
#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)
#define MCF_DMA_DCR_LCH2_CH0 (0)
#define MCF_DMA_DCR_LCH2_CH1 (0x1)
#define MCF_DMA_DCR_LCH2_CH2 (0x2)
#define MCF_DMA_DCR_LCH2_CH3 (0x3)
#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)
#define MCF_DMA_DCR_LCH1_CH0 (0)
#define MCF_DMA_DCR_LCH1_CH1 (0x1)
#define MCF_DMA_DCR_LCH1_CH2 (0x2)
#define MCF_DMA_DCR_LCH1_CH3 (0x3)
#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)
#define MCF_DMA_DCR_D_REQ (0x80)
#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)
#define MCF_DMA_DCR_DMOD_DIS (0)
#define MCF_DMA_DCR_DMOD_16 (0x1)
#define MCF_DMA_DCR_DMOD_32 (0x2)
#define MCF_DMA_DCR_DMOD_64 (0x3)
#define MCF_DMA_DCR_DMOD_128 (0x4)
#define MCF_DMA_DCR_DMOD_256 (0x5)
#define MCF_DMA_DCR_DMOD_512 (0x6)
#define MCF_DMA_DCR_DMOD_1K (0x7)
#define MCF_DMA_DCR_DMOD_2K (0x8)
#define MCF_DMA_DCR_DMOD_4K (0x9)
#define MCF_DMA_DCR_DMOD_8K (0xA)
#define MCF_DMA_DCR_DMOD_16K (0xB)
#define MCF_DMA_DCR_DMOD_32K (0xC)
#define MCF_DMA_DCR_DMOD_64K (0xD)
#define MCF_DMA_DCR_DMOD_128K (0xE)
#define MCF_DMA_DCR_DMOD_256K (0xF)
#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)
#define MCF_DMA_DCR_SMOD_DIS (0)
#define MCF_DMA_DCR_SMOD_16 (0x1)
#define MCF_DMA_DCR_SMOD_32 (0x2)
#define MCF_DMA_DCR_SMOD_64 (0x3)
#define MCF_DMA_DCR_SMOD_128 (0x4)
#define MCF_DMA_DCR_SMOD_256 (0x5)
#define MCF_DMA_DCR_SMOD_512 (0x6)
#define MCF_DMA_DCR_SMOD_1K (0x7)
#define MCF_DMA_DCR_SMOD_2K (0x8)
#define MCF_DMA_DCR_SMOD_4K (0x9)
#define MCF_DMA_DCR_SMOD_8K (0xA)
#define MCF_DMA_DCR_SMOD_16K (0xB)
#define MCF_DMA_DCR_SMOD_32K (0xC)
#define MCF_DMA_DCR_SMOD_64K (0xD)
#define MCF_DMA_DCR_SMOD_128K (0xE)
#define MCF_DMA_DCR_SMOD_256K (0xF)
#define MCF_DMA_DCR_START (0x10000)
#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
#define MCF_DMA_DCR_DSIZE_LONG (0)
#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
#define MCF_DMA_DCR_DSIZE_WORD (0x2)
#define MCF_DMA_DCR_DSIZE_LINE (0x3)
#define MCF_DMA_DCR_DINC (0x80000)
#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
#define MCF_DMA_DCR_SSIZE_LONG (0)
#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
#define MCF_DMA_DCR_SSIZE_WORD (0x2)
#define MCF_DMA_DCR_SSIZE_LINE (0x3)
#define MCF_DMA_DCR_SINC (0x400000)
#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
#define MCF_DMA_DCR_BWC_16K (0x1)
#define MCF_DMA_DCR_BWC_32K (0x2)
#define MCF_DMA_DCR_BWC_64K (0x3)
#define MCF_DMA_DCR_BWC_128K (0x4)
#define MCF_DMA_DCR_BWC_256K (0x5)
#define MCF_DMA_DCR_BWC_512K (0x6)
#define MCF_DMA_DCR_BWC_1024K (0x7)
#define MCF_DMA_DCR_AA (0x10000000)
#define MCF_DMA_DCR_CS (0x20000000)
#define MCF_DMA_DCR_EEXT (0x40000000)
#define MCF_DMA_DCR_INT (0x80000000)
#endif /* __MCF52221_DMA_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_DTIM_H__
#define __MCF52221_DTIM_H__
/*********************************************************************
*
* DMA Timers (DTIM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))
#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))
#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))
#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))
#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))
#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))
#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))
#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))
#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))
#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))
#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))
#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))
#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))
#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))
#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))
#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))
#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))
#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))
#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))
#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))
#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))
#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))
#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))
#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))
#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))
#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))
#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))
#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))
#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))
/* Bit definitions and macros for MCF_DTIM_DTMR */
#define MCF_DTIM_DTMR_RST (0x1)
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
#define MCF_DTIM_DTMR_CLK_STOP (0)
#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
#define MCF_DTIM_DTMR_FRR (0x8)
#define MCF_DTIM_DTMR_ORRI (0x10)
#define MCF_DTIM_DTMR_OM (0x20)
#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
#define MCF_DTIM_DTMR_CE_NONE (0)
#define MCF_DTIM_DTMR_CE_RISE (0x40)
#define MCF_DTIM_DTMR_CE_FALL (0x80)
#define MCF_DTIM_DTMR_CE_ANY (0xC0)
#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
/* Bit definitions and macros for MCF_DTIM_DTXMR */
#define MCF_DTIM_DTXMR_MODE16 (0x1)
#define MCF_DTIM_DTXMR_HALTED (0x40)
#define MCF_DTIM_DTXMR_DMAEN (0x80)
/* Bit definitions and macros for MCF_DTIM_DTER */
#define MCF_DTIM_DTER_CAP (0x1)
#define MCF_DTIM_DTER_REF (0x2)
/* Bit definitions and macros for MCF_DTIM_DTRR */
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCR */
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCN */
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF52221_DTIM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_EPORT_H__
#define __MCF52221_EPORT_H__
/*********************************************************************
*
* Edge Port Module (EPORT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))
#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))
#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))
#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))
#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))
#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (0x1)
#define MCF_EPORT_EPPAR_FALLING (0x2)
#define MCF_EPORT_EPPAR_BOTH (0x3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x2)
#define MCF_EPORT_EPIER_EPIE2 (0x4)
#define MCF_EPORT_EPIER_EPIE3 (0x8)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x2)
#define MCF_EPORT_EPDR_EPD2 (0x4)
#define MCF_EPORT_EPDR_EPD3 (0x8)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x2)
#define MCF_EPORT_EPFR_EPF2 (0x4)
#define MCF_EPORT_EPFR_EPF3 (0x8)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF52221_EPORT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_GPIO_H__
#define __MCF52221_GPIO_H__
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008))
#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020))
#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038))
#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050))
#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068))
#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A))
#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022))
#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A))
#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052))
#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A))
#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B))
#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023))
#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B))
#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053))
#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B))
#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C))
#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024))
#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C))
#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054))
#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C))
#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E))
#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026))
#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E))
#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056))
#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E))
#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F))
#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027))
#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F))
#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057))
#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F))
#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011))
#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029))
#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041))
#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059))
#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071))
#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012))
#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A))
#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042))
#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A))
#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072))
/* Bit definitions and macros for MCF_GPIO_PORTNQ */
#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)
#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)
#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)
#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)
#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)
#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)
#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)
/* Bit definitions and macros for MCF_GPIO_DDRNQ */
#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)
#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)
#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)
#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)
#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)
#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)
#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)
/* Bit definitions and macros for MCF_GPIO_SETNQ */
#define MCF_GPIO_SETNQ_SETNQ1 (0x2)
#define MCF_GPIO_SETNQ_SETNQ2 (0x4)
#define MCF_GPIO_SETNQ_SETNQ3 (0x8)
#define MCF_GPIO_SETNQ_SETNQ4 (0x10)
#define MCF_GPIO_SETNQ_SETNQ5 (0x20)
#define MCF_GPIO_SETNQ_SETNQ6 (0x40)
#define MCF_GPIO_SETNQ_SETNQ7 (0x80)
/* Bit definitions and macros for MCF_GPIO_CLRNQ */
#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)
#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)
#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)
#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)
#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)
#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)
#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PNQPAR */
#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)
#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8)
#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC)
#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10)
#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)
#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)
#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100)
#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)
#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)
#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)
#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)
#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)
#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)
#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)
/* Bit definitions and macros for MCF_GPIO_PORTAN */
#define MCF_GPIO_PORTAN_PORTAN0 (0x1)
#define MCF_GPIO_PORTAN_PORTAN1 (0x2)
#define MCF_GPIO_PORTAN_PORTAN2 (0x4)
#define MCF_GPIO_PORTAN_PORTAN3 (0x8)
#define MCF_GPIO_PORTAN_PORTAN4 (0x10)
#define MCF_GPIO_PORTAN_PORTAN5 (0x20)
#define MCF_GPIO_PORTAN_PORTAN6 (0x40)
#define MCF_GPIO_PORTAN_PORTAN7 (0x80)
/* Bit definitions and macros for MCF_GPIO_DDRAN */
#define MCF_GPIO_DDRAN_DDRAN0 (0x1)
#define MCF_GPIO_DDRAN_DDRAN1 (0x2)
#define MCF_GPIO_DDRAN_DDRAN2 (0x4)
#define MCF_GPIO_DDRAN_DDRAN3 (0x8)
#define MCF_GPIO_DDRAN_DDRAN4 (0x10)
#define MCF_GPIO_DDRAN_DDRAN5 (0x20)
#define MCF_GPIO_DDRAN_DDRAN6 (0x40)
#define MCF_GPIO_DDRAN_DDRAN7 (0x80)
/* Bit definitions and macros for MCF_GPIO_SETAN */
#define MCF_GPIO_SETAN_SETAN0 (0x1)
#define MCF_GPIO_SETAN_SETAN1 (0x2)
#define MCF_GPIO_SETAN_SETAN2 (0x4)
#define MCF_GPIO_SETAN_SETAN3 (0x8)
#define MCF_GPIO_SETAN_SETAN4 (0x10)
#define MCF_GPIO_SETAN_SETAN5 (0x20)
#define MCF_GPIO_SETAN_SETAN6 (0x40)
#define MCF_GPIO_SETAN_SETAN7 (0x80)
/* Bit definitions and macros for MCF_GPIO_CLRAN */
#define MCF_GPIO_CLRAN_CLRAN0 (0x1)
#define MCF_GPIO_CLRAN_CLRAN1 (0x2)
#define MCF_GPIO_CLRAN_CLRAN2 (0x4)
#define MCF_GPIO_CLRAN_CLRAN3 (0x8)
#define MCF_GPIO_CLRAN_CLRAN4 (0x10)
#define MCF_GPIO_CLRAN_CLRAN5 (0x20)
#define MCF_GPIO_CLRAN_CLRAN6 (0x40)
#define MCF_GPIO_CLRAN_CLRAN7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PANPAR */
#define MCF_GPIO_PANPAR_PANPAR0 (0x1)
#define MCF_GPIO_PANPAR_AN0_GPIO (0)
#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)
#define MCF_GPIO_PANPAR_PANPAR1 (0x2)
#define MCF_GPIO_PANPAR_AN1_GPIO (0)
#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)
#define MCF_GPIO_PANPAR_PANPAR2 (0x4)
#define MCF_GPIO_PANPAR_AN2_GPIO (0)
#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)
#define MCF_GPIO_PANPAR_PANPAR3 (0x8)
#define MCF_GPIO_PANPAR_AN3_GPIO (0)
#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)
#define MCF_GPIO_PANPAR_PANPAR4 (0x10)
#define MCF_GPIO_PANPAR_AN4_GPIO (0)
#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)
#define MCF_GPIO_PANPAR_PANPAR5 (0x20)
#define MCF_GPIO_PANPAR_AN5_GPIO (0)
#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)
#define MCF_GPIO_PANPAR_PANPAR6 (0x40)
#define MCF_GPIO_PANPAR_AN6_GPIO (0)
#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)
#define MCF_GPIO_PANPAR_PANPAR7 (0x80)
#define MCF_GPIO_PANPAR_AN7_GPIO (0)
#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PORTAS */
#define MCF_GPIO_PORTAS_PORTAS0 (0x1)
#define MCF_GPIO_PORTAS_PORTAS1 (0x2)
/* Bit definitions and macros for MCF_GPIO_DDRAS */
#define MCF_GPIO_DDRAS_DDRAS0 (0x1)
#define MCF_GPIO_DDRAS_DDRAS1 (0x2)
/* Bit definitions and macros for MCF_GPIO_SETAS */
#define MCF_GPIO_SETAS_SETAS0 (0x1)
#define MCF_GPIO_SETAS_SETAS1 (0x2)
/* Bit definitions and macros for MCF_GPIO_CLRAS */
#define MCF_GPIO_CLRAS_CLRAS0 (0x1)
#define MCF_GPIO_CLRAS_CLRAS1 (0x2)
/* Bit definitions and macros for MCF_GPIO_PASPAR */
#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PASPAR_SCL_GPIO (0)
#define MCF_GPIO_PASPAR_SCL_SCL (0x1)
#define MCF_GPIO_PASPAR_SCL_USB_DMI (0x2)
#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3)
#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PASPAR_SDA_GPIO (0)
#define MCF_GPIO_PASPAR_SDA_SDA (0x4)
#define MCF_GPIO_PASPAR_SDA_USB_DPI (0x8)
#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC)
/* Bit definitions and macros for MCF_GPIO_PORTQS */
#define MCF_GPIO_PORTQS_PORTQS0 (0x1)
#define MCF_GPIO_PORTQS_PORTQS1 (0x2)
#define MCF_GPIO_PORTQS_PORTQS2 (0x4)
#define MCF_GPIO_PORTQS_PORTQS3 (0x8)
#define MCF_GPIO_PORTQS_PORTQS4 (0x10)
#define MCF_GPIO_PORTQS_PORTQS5 (0x20)
#define MCF_GPIO_PORTQS_PORTQS6 (0x40)
/* Bit definitions and macros for MCF_GPIO_DDRQS */
#define MCF_GPIO_DDRQS_DDRQS0 (0x1)
#define MCF_GPIO_DDRQS_DDRQS1 (0x2)
#define MCF_GPIO_DDRQS_DDRQS2 (0x4)
#define MCF_GPIO_DDRQS_DDRQS3 (0x8)
#define MCF_GPIO_DDRQS_DDRQS4 (0x10)
#define MCF_GPIO_DDRQS_DDRQS5 (0x20)
#define MCF_GPIO_DDRQS_DDRQS6 (0x40)
/* Bit definitions and macros for MCF_GPIO_SETQS */
#define MCF_GPIO_SETQS_SETQS0 (0x1)
#define MCF_GPIO_SETQS_SETQS1 (0x2)
#define MCF_GPIO_SETQS_SETQS2 (0x4)
#define MCF_GPIO_SETQS_SETQS3 (0x8)
#define MCF_GPIO_SETQS_SETQS4 (0x10)
#define MCF_GPIO_SETQS_SETQS5 (0x20)
#define MCF_GPIO_SETQS_SETQS6 (0x40)
/* Bit definitions and macros for MCF_GPIO_CLRQS */
#define MCF_GPIO_CLRQS_CLRQS0 (0x1)
#define MCF_GPIO_CLRQS_CLRQS1 (0x2)
#define MCF_GPIO_CLRQS_CLRQS2 (0x4)
#define MCF_GPIO_CLRQS_CLRQS3 (0x8)
#define MCF_GPIO_CLRQS_CLRQS4 (0x10)
#define MCF_GPIO_CLRQS_CLRQS5 (0x20)
#define MCF_GPIO_CLRQS_CLRQS6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PQSPAR */
#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)
#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)
#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)
#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)
#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)
#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20)
#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)
#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)
#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)
#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)
#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100)
#define MCF_GPIO_PQSPAR_QSPI_CS1_USB_PULLUP (0x300)
#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)
#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)
#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PD (0xC00)
#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)
#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)
#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)
#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)
#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PD (0x3000)
/* Bit definitions and macros for MCF_GPIO_PORTTA */
#define MCF_GPIO_PORTTA_PORTTA0 (0x1)
#define MCF_GPIO_PORTTA_PORTTA1 (0x2)
#define MCF_GPIO_PORTTA_PORTTA2 (0x4)
#define MCF_GPIO_PORTTA_PORTTA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_DDRTA */
#define MCF_GPIO_DDRTA_DDRTA0 (0x1)
#define MCF_GPIO_DDRTA_DDRTA1 (0x2)
#define MCF_GPIO_DDRTA_DDRTA2 (0x4)
#define MCF_GPIO_DDRTA_DDRTA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_SETTA */
#define MCF_GPIO_SETTA_SETTA0 (0x1)
#define MCF_GPIO_SETTA_SETTA1 (0x2)
#define MCF_GPIO_SETTA_SETTA2 (0x4)
#define MCF_GPIO_SETTA_SETTA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_CLRTA */
#define MCF_GPIO_CLRTA_CLRTA0 (0x1)
#define MCF_GPIO_CLRTA_CLRTA1 (0x2)
#define MCF_GPIO_CLRTA_CLRTA2 (0x4)
#define MCF_GPIO_CLRTA_CLRTA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PTAPAR */
#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PTAPAR_GPT0_GPIO (0)
#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1)
#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3)
#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PTAPAR_GPT1_GPIO (0)
#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4)
#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC)
#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PTAPAR_GPT2_GPIO (0)
#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10)
#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30)
#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PTAPAR_GPT3_GPIO (0)
#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40)
#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0)
/* Bit definitions and macros for MCF_GPIO_PORTTC */
#define MCF_GPIO_PORTTC_PORTTC0 (0x1)
#define MCF_GPIO_PORTTC_PORTTC1 (0x2)
#define MCF_GPIO_PORTTC_PORTTC2 (0x4)
#define MCF_GPIO_PORTTC_PORTTC3 (0x8)
/* Bit definitions and macros for MCF_GPIO_DDRTC */
#define MCF_GPIO_DDRTC_DDRTC0 (0x1)
#define MCF_GPIO_DDRTC_DDRTC1 (0x2)
#define MCF_GPIO_DDRTC_DDRTC2 (0x4)
#define MCF_GPIO_DDRTC_DDRTC3 (0x8)
/* Bit definitions and macros for MCF_GPIO_SETTC */
#define MCF_GPIO_SETTC_SETTC0 (0x1)
#define MCF_GPIO_SETTC_SETTC1 (0x2)
#define MCF_GPIO_SETTC_SETTC2 (0x4)
#define MCF_GPIO_SETTC_SETTC3 (0x8)
/* Bit definitions and macros for MCF_GPIO_CLRTC */
#define MCF_GPIO_CLRTC_CLRTC0 (0x1)
#define MCF_GPIO_CLRTC_CLRTC1 (0x2)
#define MCF_GPIO_CLRTC_CLRTC2 (0x4)
#define MCF_GPIO_CLRTC_CLRTC3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PTCPAR */
#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)
#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)
#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)
#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)
#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)
#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)
#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)
#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)
#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)
#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)
#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)
#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)
#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)
#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)
#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)
#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)
/* Bit definitions and macros for MCF_GPIO_PORTUA */
#define MCF_GPIO_PORTUA_PORTUA0 (0x1)
#define MCF_GPIO_PORTUA_PORTUA1 (0x2)
#define MCF_GPIO_PORTUA_PORTUA2 (0x4)
#define MCF_GPIO_PORTUA_PORTUA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_DDRUA */
#define MCF_GPIO_DDRUA_DDRUA0 (0x1)
#define MCF_GPIO_DDRUA_DDRUA1 (0x2)
#define MCF_GPIO_DDRUA_DDRUA2 (0x4)
#define MCF_GPIO_DDRUA_DDRUA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_SETUA */
#define MCF_GPIO_SETUA_SETUA0 (0x1)
#define MCF_GPIO_SETUA_SETUA1 (0x2)
#define MCF_GPIO_SETUA_SETUA2 (0x4)
#define MCF_GPIO_SETUA_SETUA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_CLRUA */
#define MCF_GPIO_CLRUA_CLRUA0 (0x1)
#define MCF_GPIO_CLRUA_CLRUA1 (0x2)
#define MCF_GPIO_CLRUA_CLRUA2 (0x4)
#define MCF_GPIO_CLRUA_CLRUA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PUAPAR */
#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)
#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)
#define MCF_GPIO_PUAPAR_UTXD0_USB_SUSPEND (0x3)
#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)
#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)
#define MCF_GPIO_PUAPAR_URXD0_USB_RCV (0xC)
#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)
#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)
#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30)
#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)
#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)
#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0)
/* Bit definitions and macros for MCF_GPIO_PORTUB */
#define MCF_GPIO_PORTUB_PORTUB0 (0x1)
#define MCF_GPIO_PORTUB_PORTUB1 (0x2)
#define MCF_GPIO_PORTUB_PORTUB2 (0x4)
#define MCF_GPIO_PORTUB_PORTUB3 (0x8)
/* Bit definitions and macros for MCF_GPIO_DDRUB */
#define MCF_GPIO_DDRUB_DDRUB0 (0x1)
#define MCF_GPIO_DDRUB_DDRUB1 (0x2)
#define MCF_GPIO_DDRUB_DDRUB2 (0x4)
#define MCF_GPIO_DDRUB_DDRUB3 (0x8)
/* Bit definitions and macros for MCF_GPIO_SETUB */
#define MCF_GPIO_SETUB_SETUB0 (0x1)
#define MCF_GPIO_SETUB_SETUB1 (0x2)
#define MCF_GPIO_SETUB_SETUB2 (0x4)
#define MCF_GPIO_SETUB_SETUB3 (0x8)
/* Bit definitions and macros for MCF_GPIO_CLRUB */
#define MCF_GPIO_CLRUB_CLRUB0 (0x1)
#define MCF_GPIO_CLRUB_CLRUB1 (0x2)
#define MCF_GPIO_CLRUB_CLRUB2 (0x4)
#define MCF_GPIO_CLRUB_CLRUB3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PUBPAR */
#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)
#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)
#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)
#define MCF_GPIO_PUBPAR_UTXD1_USB_SPEED (0x3)
#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)
#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)
#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)
#define MCF_GPIO_PUBPAR_URXD1_USB_OE (0xC)
#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)
#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)
#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)
#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)
#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)
#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)
#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)
#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)
#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)
#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)
#endif /* __MCF52221_GPIO_H__ */

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20091005/Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_GPTA.h Normal file
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_GPTA_H__
#define __MCF52221_GPTA_H__
/*********************************************************************
*
* General Purpose Timer Module (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPTA_GPTIOS (*(vuint8 *)(0x401A0000))
#define MCF_GPTA_GPTCFORC (*(vuint8 *)(0x401A0001))
#define MCF_GPTA_GPTOC3M (*(vuint8 *)(0x401A0002))
#define MCF_GPTA_GPTOC3D (*(vuint8 *)(0x401A0003))
#define MCF_GPTA_GPTCNT (*(vuint16*)(0x401A0004))
#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(0x401A0006))
#define MCF_GPTA_GPTTOV (*(vuint8 *)(0x401A0008))
#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(0x401A0009))
#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(0x401A000B))
#define MCF_GPTA_GPTIE (*(vuint8 *)(0x401A000C))
#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(0x401A000D))
#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(0x401A000E))
#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(0x401A000F))
#define MCF_GPTA_GPTC0 (*(vuint16*)(0x401A0010))
#define MCF_GPTA_GPTC1 (*(vuint16*)(0x401A0012))
#define MCF_GPTA_GPTC2 (*(vuint16*)(0x401A0014))
#define MCF_GPTA_GPTC3 (*(vuint16*)(0x401A0016))
#define MCF_GPTA_GPTPACTL (*(vuint8 *)(0x401A0018))
#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(0x401A0019))
#define MCF_GPTA_GPTPACNT (*(vuint16*)(0x401A001A))
#define MCF_GPTA_GPTPORT (*(vuint8 *)(0x401A001D))
#define MCF_GPTA_GPTDDR (*(vuint8 *)(0x401A001E))
#define MCF_GPTA_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2)))
/* Bit definitions and macros for MCF_GPTA_GPTIOS */
#define MCF_GPTA_GPTIOS_IOS0 (0x1)
#define MCF_GPTA_GPTIOS_IOS1 (0x2)
#define MCF_GPTA_GPTIOS_IOS2 (0x4)
#define MCF_GPTA_GPTIOS_IOS3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTCFORC */
#define MCF_GPTA_GPTCFORC_FOC0 (0x1)
#define MCF_GPTA_GPTCFORC_FOC1 (0x2)
#define MCF_GPTA_GPTCFORC_FOC2 (0x4)
#define MCF_GPTA_GPTCFORC_FOC3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTOC3M */
#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)
#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)
#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)
#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTOC3D */
#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)
#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)
#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)
#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTCNT */
#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */
#define MCF_GPTA_GPTSCR1_TFFCA (0x10)
#define MCF_GPTA_GPTSCR1_GPTEN (0x80)
/* Bit definitions and macros for MCF_GPTA_GPTTOV */
#define MCF_GPTA_GPTTOV_TOV0 (0x1)
#define MCF_GPTA_GPTTOV_TOV1 (0x2)
#define MCF_GPTA_GPTTOV_TOV2 (0x4)
#define MCF_GPTA_GPTTOV_TOV3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */
#define MCF_GPTA_GPTCTL1_OL0 (0x1)
#define MCF_GPTA_GPTCTL1_OM0 (0x2)
#define MCF_GPTA_GPTCTL1_OL1 (0x4)
#define MCF_GPTA_GPTCTL1_OM1 (0x8)
#define MCF_GPTA_GPTCTL1_OL2 (0x10)
#define MCF_GPTA_GPTCTL1_OM2 (0x20)
#define MCF_GPTA_GPTCTL1_OL3 (0x40)
#define MCF_GPTA_GPTCTL1_OM3 (0x80)
#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)
#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)
#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)
#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)
#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)
#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)
#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)
#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)
#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)
#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)
#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)
#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)
#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)
#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)
#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)
#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)
/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */
#define MCF_GPTA_GPTCTL2_EDG0A (0x1)
#define MCF_GPTA_GPTCTL2_EDG0B (0x2)
#define MCF_GPTA_GPTCTL2_EDG1A (0x4)
#define MCF_GPTA_GPTCTL2_EDG1B (0x8)
#define MCF_GPTA_GPTCTL2_EDG2A (0x10)
#define MCF_GPTA_GPTCTL2_EDG2B (0x20)
#define MCF_GPTA_GPTCTL2_EDG3A (0x40)
#define MCF_GPTA_GPTCTL2_EDG3B (0x80)
#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)
#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)
#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)
#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)
#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)
#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)
#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)
#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)
#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)
#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)
#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)
#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)
#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)
#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)
#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)
#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)
/* Bit definitions and macros for MCF_GPTA_GPTIE */
#define MCF_GPTA_GPTIE_CI0 (0x1)
#define MCF_GPTA_GPTIE_CI1 (0x2)
#define MCF_GPTA_GPTIE_CI2 (0x4)
#define MCF_GPTA_GPTIE_CI3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */
#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)
#define MCF_GPTA_GPTSCR2_PR_1 (0)
#define MCF_GPTA_GPTSCR2_PR_2 (0x1)
#define MCF_GPTA_GPTSCR2_PR_4 (0x2)
#define MCF_GPTA_GPTSCR2_PR_8 (0x3)
#define MCF_GPTA_GPTSCR2_PR_16 (0x4)
#define MCF_GPTA_GPTSCR2_PR_32 (0x5)
#define MCF_GPTA_GPTSCR2_PR_64 (0x6)
#define MCF_GPTA_GPTSCR2_PR_128 (0x7)
#define MCF_GPTA_GPTSCR2_TCRE (0x8)
#define MCF_GPTA_GPTSCR2_RDPT (0x10)
#define MCF_GPTA_GPTSCR2_PUPT (0x20)
#define MCF_GPTA_GPTSCR2_TOI (0x80)
/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */
#define MCF_GPTA_GPTFLG1_CF0 (0x1)
#define MCF_GPTA_GPTFLG1_CF1 (0x2)
#define MCF_GPTA_GPTFLG1_CF2 (0x4)
#define MCF_GPTA_GPTFLG1_CF3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */
#define MCF_GPTA_GPTFLG2_TOF (0x80)
/* Bit definitions and macros for MCF_GPTA_GPTC */
#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_GPTA_GPTPACTL */
#define MCF_GPTA_GPTPACTL_PAI (0x1)
#define MCF_GPTA_GPTPACTL_PAOVI (0x2)
#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)
#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)
#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)
#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)
#define MCF_GPTA_GPTPACTL_PEDGE (0x10)
#define MCF_GPTA_GPTPACTL_PAMOD (0x20)
#define MCF_GPTA_GPTPACTL_PAE (0x40)
/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */
#define MCF_GPTA_GPTPAFLG_PAIF (0x1)
#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)
/* Bit definitions and macros for MCF_GPTA_GPTPACNT */
#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_GPTA_GPTPORT */
#define MCF_GPTA_GPTPORT_PORTT0 (0x1)
#define MCF_GPTA_GPTPORT_PORTT1 (0x2)
#define MCF_GPTA_GPTPORT_PORTT2 (0x4)
#define MCF_GPTA_GPTPORT_PORTT3 (0x8)
/* Bit definitions and macros for MCF_GPTA_GPTDDR */
#define MCF_GPTA_GPTDDR_DDRT0 (0x1)
#define MCF_GPTA_GPTDDR_DDRT1 (0x2)
#define MCF_GPTA_GPTDDR_DDRT2 (0x4)
#define MCF_GPTA_GPTDDR_DDRT3 (0x8)
#endif /* __MCF52221_GPTA_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_I2C_H__
#define __MCF52221_I2C_H__
/*********************************************************************
*
* I2C Module (I2C)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_I2C_I2ADR (*(vuint8 *)(0x40000300))
#define MCF_I2C_I2FDR (*(vuint8 *)(0x40000304))
#define MCF_I2C_I2CR (*(vuint8 *)(0x40000308))
#define MCF_I2C_I2SR (*(vuint8 *)(0x4000030C))
#define MCF_I2C_I2DR (*(vuint8 *)(0x40000310))
/* Bit definitions and macros for MCF_I2C_I2ADR */
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x4)
#define MCF_I2C_I2CR_TXAK (0x8)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x1)
#define MCF_I2C_I2SR_IIF (0x2)
#define MCF_I2C_I2SR_SRW (0x4)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2DR */
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
#endif /* __MCF52221_I2C_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_INTC_H__
#define __MCF52221_INTC_H__
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))
#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))
#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))
#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))
#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))
#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))
#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))
#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))
#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))
#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))
#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))
#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))
#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))
#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))
#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))
#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))
#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))
#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))
#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))
#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))
#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))
#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))
#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))
#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))
#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))
#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))
#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))
#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))
#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))
#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))
#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))
#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))
#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))
#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))
#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))
#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))
#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))
#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))
#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))
#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))
#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))
#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))
#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))
#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))
#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))
#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))
#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))
#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))
#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))
#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))
#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))
#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))
#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))
#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))
#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))
#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))
#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))
#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))
#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))
#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))
#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))
#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))
#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))
#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))
#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))
#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))
#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))
#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))
#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))
#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))
#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))
#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))
#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))
#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))
#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))
#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))
#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))
#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))
#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))
#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))
#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x1)
#define MCF_INTC_IPRH_INT33 (0x2)
#define MCF_INTC_IPRH_INT34 (0x4)
#define MCF_INTC_IPRH_INT35 (0x8)
#define MCF_INTC_IPRH_INT36 (0x10)
#define MCF_INTC_IPRH_INT37 (0x20)
#define MCF_INTC_IPRH_INT38 (0x40)
#define MCF_INTC_IPRH_INT39 (0x80)
#define MCF_INTC_IPRH_INT40 (0x100)
#define MCF_INTC_IPRH_INT41 (0x200)
#define MCF_INTC_IPRH_INT42 (0x400)
#define MCF_INTC_IPRH_INT43 (0x800)
#define MCF_INTC_IPRH_INT44 (0x1000)
#define MCF_INTC_IPRH_INT45 (0x2000)
#define MCF_INTC_IPRH_INT46 (0x4000)
#define MCF_INTC_IPRH_INT47 (0x8000)
#define MCF_INTC_IPRH_INT48 (0x10000)
#define MCF_INTC_IPRH_INT49 (0x20000)
#define MCF_INTC_IPRH_INT50 (0x40000)
#define MCF_INTC_IPRH_INT51 (0x80000)
#define MCF_INTC_IPRH_INT52 (0x100000)
#define MCF_INTC_IPRH_INT53 (0x200000)
#define MCF_INTC_IPRH_INT54 (0x400000)
#define MCF_INTC_IPRH_INT55 (0x800000)
#define MCF_INTC_IPRH_INT56 (0x1000000)
#define MCF_INTC_IPRH_INT57 (0x2000000)
#define MCF_INTC_IPRH_INT58 (0x4000000)
#define MCF_INTC_IPRH_INT59 (0x8000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1 (0x2)
#define MCF_INTC_IPRL_INT2 (0x4)
#define MCF_INTC_IPRL_INT3 (0x8)
#define MCF_INTC_IPRL_INT4 (0x10)
#define MCF_INTC_IPRL_INT5 (0x20)
#define MCF_INTC_IPRL_INT6 (0x40)
#define MCF_INTC_IPRL_INT7 (0x80)
#define MCF_INTC_IPRL_INT8 (0x100)
#define MCF_INTC_IPRL_INT9 (0x200)
#define MCF_INTC_IPRL_INT10 (0x400)
#define MCF_INTC_IPRL_INT11 (0x800)
#define MCF_INTC_IPRL_INT12 (0x1000)
#define MCF_INTC_IPRL_INT13 (0x2000)
#define MCF_INTC_IPRL_INT14 (0x4000)
#define MCF_INTC_IPRL_INT15 (0x8000)
#define MCF_INTC_IPRL_INT16 (0x10000)
#define MCF_INTC_IPRL_INT17 (0x20000)
#define MCF_INTC_IPRL_INT18 (0x40000)
#define MCF_INTC_IPRL_INT19 (0x80000)
#define MCF_INTC_IPRL_INT20 (0x100000)
#define MCF_INTC_IPRL_INT21 (0x200000)
#define MCF_INTC_IPRL_INT22 (0x400000)
#define MCF_INTC_IPRL_INT23 (0x800000)
#define MCF_INTC_IPRL_INT24 (0x1000000)
#define MCF_INTC_IPRL_INT25 (0x2000000)
#define MCF_INTC_IPRL_INT26 (0x4000000)
#define MCF_INTC_IPRL_INT27 (0x8000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL (0x1)
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
#endif /* __MCF52221_INTC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PAD_H__
#define __MCF52221_PAD_H__
/*********************************************************************
*
* Common GPIO
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PAD_PSRR (*(vuint32*)(0x40100078))
#define MCF_PAD_PDSR (*(vuint32*)(0x4010007C))
/* Bit definitions and macros for MCF_PAD_PSRR */
#define MCF_PAD_PSRR_PSRR0 (0x1)
#define MCF_PAD_PSRR_PSRR1 (0x2)
#define MCF_PAD_PSRR_PSRR2 (0x4)
#define MCF_PAD_PSRR_PSRR3 (0x8)
#define MCF_PAD_PSRR_PSRR4 (0x10)
#define MCF_PAD_PSRR_PSRR5 (0x20)
#define MCF_PAD_PSRR_PSRR6 (0x40)
#define MCF_PAD_PSRR_PSRR7 (0x80)
#define MCF_PAD_PSRR_PSRR8 (0x100)
#define MCF_PAD_PSRR_PSRR9 (0x200)
#define MCF_PAD_PSRR_PSRR10 (0x400)
#define MCF_PAD_PSRR_PSRR11 (0x800)
#define MCF_PAD_PSRR_PSRR12 (0x1000)
#define MCF_PAD_PSRR_PSRR13 (0x2000)
#define MCF_PAD_PSRR_PSRR14 (0x4000)
#define MCF_PAD_PSRR_PSRR15 (0x8000)
#define MCF_PAD_PSRR_PSRR16 (0x10000)
#define MCF_PAD_PSRR_PSRR17 (0x20000)
#define MCF_PAD_PSRR_PSRR18 (0x40000)
#define MCF_PAD_PSRR_PSRR19 (0x80000)
#define MCF_PAD_PSRR_PSRR20 (0x100000)
#define MCF_PAD_PSRR_PSRR21 (0x200000)
#define MCF_PAD_PSRR_PSRR22 (0x400000)
#define MCF_PAD_PSRR_PSRR23 (0x800000)
#define MCF_PAD_PSRR_PSRR24 (0x1000000)
#define MCF_PAD_PSRR_PSRR25 (0x2000000)
#define MCF_PAD_PSRR_PSRR26 (0x4000000)
#define MCF_PAD_PSRR_PSRR27 (0x8000000)
/* Bit definitions and macros for MCF_PAD_PDSR */
#define MCF_PAD_PDSR_PDSR0 (0x1)
#define MCF_PAD_PDSR_PDSR1 (0x2)
#define MCF_PAD_PDSR_PDSR2 (0x4)
#define MCF_PAD_PDSR_PDSR3 (0x8)
#define MCF_PAD_PDSR_PDSR4 (0x10)
#define MCF_PAD_PDSR_PDSR5 (0x20)
#define MCF_PAD_PDSR_PDSR6 (0x40)
#define MCF_PAD_PDSR_PDSR7 (0x80)
#define MCF_PAD_PDSR_PDSR8 (0x100)
#define MCF_PAD_PDSR_PDSR9 (0x200)
#define MCF_PAD_PDSR_PDSR10 (0x400)
#define MCF_PAD_PDSR_PDSR11 (0x800)
#define MCF_PAD_PDSR_PDSR12 (0x1000)
#define MCF_PAD_PDSR_PDSR13 (0x2000)
#define MCF_PAD_PDSR_PDSR14 (0x4000)
#define MCF_PAD_PDSR_PDSR15 (0x8000)
#define MCF_PAD_PDSR_PDSR16 (0x10000)
#define MCF_PAD_PDSR_PDSR17 (0x20000)
#define MCF_PAD_PDSR_PDSR18 (0x40000)
#define MCF_PAD_PDSR_PDSR19 (0x80000)
#define MCF_PAD_PDSR_PDSR20 (0x100000)
#define MCF_PAD_PDSR_PDSR21 (0x200000)
#define MCF_PAD_PDSR_PDSR22 (0x400000)
#define MCF_PAD_PDSR_PDSR23 (0x800000)
#define MCF_PAD_PDSR_PDSR24 (0x1000000)
#define MCF_PAD_PDSR_PDSR25 (0x2000000)
#define MCF_PAD_PDSR_PDSR26 (0x4000000)
#define MCF_PAD_PDSR_PDSR27 (0x8000000)
#endif /* __MCF52221_PAD_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PIT_H__
#define __MCF52221_PIT_H__
/*********************************************************************
*
* Programmable Interrupt Timer (PIT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))
#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))
#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))
#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))
#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))
#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))
#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))
#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))
#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))
/* Bit definitions and macros for MCF_PIT_PCSR */
#define MCF_PIT_PCSR_EN (0x1)
#define MCF_PIT_PCSR_RLD (0x2)
#define MCF_PIT_PCSR_PIF (0x4)
#define MCF_PIT_PCSR_PIE (0x8)
#define MCF_PIT_PCSR_OVW (0x10)
#define MCF_PIT_PCSR_DBG (0x20)
#define MCF_PIT_PCSR_DOZE (0x40)
#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
/* Bit definitions and macros for MCF_PIT_PMR */
#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_PIT_PCNTR */
#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
#endif /* __MCF52221_PIT_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PMM_H__
#define __MCF52221_PMM_H__
/*********************************************************************
*
* Power Management (PMM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))
#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))
/* Bit definitions and macros for MCF_PMM_LPICR */
#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
#define MCF_PMM_LPICR_ENBSTOP (0x80)
/* Bit definitions and macros for MCF_PMM_LPCR */
#define MCF_PMM_LPCR_STPMD (0x8)
#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
#define MCF_PMM_LPCR_LPMD_RUN (0)
#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
#endif /* __MCF52221_PMM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_PWM_H__
#define __MCF52221_PWM_H__
/*********************************************************************
*
* Pulse Width Modulation (PWM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))
#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))
#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))
#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))
#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))
#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))
#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))
#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))
#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))
#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))
#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))
#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))
#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))
#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))
#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))
#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))
#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))
#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))
#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))
#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))
#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))
#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))
#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))
#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))
#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))
#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))
#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))
#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))
#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))
#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))
#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))
#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))
#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))
#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))
#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))
#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))
/* Bit definitions and macros for MCF_PWM_PWME */
#define MCF_PWM_PWME_PWME0 (0x1)
#define MCF_PWM_PWME_PWME1 (0x2)
#define MCF_PWM_PWME_PWME2 (0x4)
#define MCF_PWM_PWME_PWME3 (0x8)
#define MCF_PWM_PWME_PWME4 (0x10)
#define MCF_PWM_PWME_PWME5 (0x20)
#define MCF_PWM_PWME_PWME6 (0x40)
#define MCF_PWM_PWME_PWME7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMPOL */
#define MCF_PWM_PWMPOL_PPOL0 (0x1)
#define MCF_PWM_PWMPOL_PPOL1 (0x2)
#define MCF_PWM_PWMPOL_PPOL2 (0x4)
#define MCF_PWM_PWMPOL_PPOL3 (0x8)
#define MCF_PWM_PWMPOL_PPOL4 (0x10)
#define MCF_PWM_PWMPOL_PPOL5 (0x20)
#define MCF_PWM_PWMPOL_PPOL6 (0x40)
#define MCF_PWM_PWMPOL_PPOL7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMCLK */
#define MCF_PWM_PWMCLK_PCLK0 (0x1)
#define MCF_PWM_PWMCLK_PCLK1 (0x2)
#define MCF_PWM_PWMCLK_PCLK2 (0x4)
#define MCF_PWM_PWMCLK_PCLK3 (0x8)
#define MCF_PWM_PWMCLK_PCLK4 (0x10)
#define MCF_PWM_PWMCLK_PCLK5 (0x20)
#define MCF_PWM_PWMCLK_PCLK6 (0x40)
#define MCF_PWM_PWMCLK_PCLK7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)
#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_PWM_PWMCAE */
#define MCF_PWM_PWMCAE_CAE0 (0x1)
#define MCF_PWM_PWMCAE_CAE1 (0x2)
#define MCF_PWM_PWMCAE_CAE2 (0x4)
#define MCF_PWM_PWMCAE_CAE3 (0x8)
#define MCF_PWM_PWMCAE_CAE4 (0x10)
#define MCF_PWM_PWMCAE_CAE5 (0x20)
#define MCF_PWM_PWMCAE_CAE6 (0x40)
#define MCF_PWM_PWMCAE_CAE7 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMCTL */
#define MCF_PWM_PWMCTL_PFRZ (0x4)
#define MCF_PWM_PWMCTL_PSWAI (0x8)
#define MCF_PWM_PWMCTL_CON01 (0x10)
#define MCF_PWM_PWMCTL_CON23 (0x20)
#define MCF_PWM_PWMCTL_CON45 (0x40)
#define MCF_PWM_PWMCTL_CON67 (0x80)
/* Bit definitions and macros for MCF_PWM_PWMSCLA */
#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMSCLB */
#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMCNT */
#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMPER */
#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMDTY */
#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_PWM_PWMSDN */
#define MCF_PWM_PWMSDN_SDNEN (0x1)
#define MCF_PWM_PWMSDN_PWM7IL (0x2)
#define MCF_PWM_PWMSDN_PWM7IN (0x4)
#define MCF_PWM_PWMSDN_LVL (0x10)
#define MCF_PWM_PWMSDN_RESTART (0x20)
#define MCF_PWM_PWMSDN_IE (0x40)
#define MCF_PWM_PWMSDN_IF (0x80)
#endif /* __MCF52221_PWM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_QSPI_H__
#define __MCF52221_QSPI_H__
/*********************************************************************
*
* Queued Serial Peripheral Interface (QSPI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))
#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))
#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))
#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))
#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))
#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))
/* Bit definitions and macros for MCF_QSPI_QMR */
#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
#define MCF_QSPI_QMR_CPHA (0x100)
#define MCF_QSPI_QMR_CPOL (0x200)
#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
#define MCF_QSPI_QMR_DOHIE (0x4000)
#define MCF_QSPI_QMR_MSTR (0x8000)
/* Bit definitions and macros for MCF_QSPI_QDLYR */
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
#define MCF_QSPI_QDLYR_SPE (0x8000)
/* Bit definitions and macros for MCF_QSPI_QWR */
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
#define MCF_QSPI_QWR_CSIV (0x1000)
#define MCF_QSPI_QWR_WRTO (0x2000)
#define MCF_QSPI_QWR_WREN (0x4000)
#define MCF_QSPI_QWR_HALT (0x8000)
/* Bit definitions and macros for MCF_QSPI_QIR */
#define MCF_QSPI_QIR_SPIF (0x1)
#define MCF_QSPI_QIR_ABRT (0x4)
#define MCF_QSPI_QIR_WCEF (0x8)
#define MCF_QSPI_QIR_SPIFE (0x100)
#define MCF_QSPI_QIR_ABRTE (0x400)
#define MCF_QSPI_QIR_WCEFE (0x800)
#define MCF_QSPI_QIR_ABRTL (0x1000)
#define MCF_QSPI_QIR_ABRTB (0x4000)
#define MCF_QSPI_QIR_WCEFB (0x8000)
/* Bit definitions and macros for MCF_QSPI_QAR */
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
#define MCF_QSPI_QAR_TRANS (0)
#define MCF_QSPI_QAR_RECV (0x10)
#define MCF_QSPI_QAR_CMD (0x20)
/* Bit definitions and macros for MCF_QSPI_QDR */
#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
#define MCF_QSPI_QDR_CONT (0x8000)
#define MCF_QSPI_QDR_BITSE (0x4000)
#define MCF_QSPI_QDR_DT (0x2000)
#define MCF_QSPI_QDR_DSCK (0x1000)
#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
#endif /* __MCF52221_QSPI_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_RCM_H__
#define __MCF52221_RCM_H__
/*********************************************************************
*
* Reset Controller Module (RCM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))
#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))
/* Bit definitions and macros for MCF_RCM_RCR */
#define MCF_RCM_RCR_LVDE (0x1)
#define MCF_RCM_RCR_LVDRE (0x4)
#define MCF_RCM_RCR_LVDIE (0x8)
#define MCF_RCM_RCR_LVDF (0x10)
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
#define MCF_RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for MCF_RCM_RSR */
#define MCF_RCM_RSR_LOL (0x1)
#define MCF_RCM_RSR_LOC (0x2)
#define MCF_RCM_RSR_EXT (0x4)
#define MCF_RCM_RSR_POR (0x8)
#define MCF_RCM_RSR_SOFT (0x20)
#define MCF_RCM_RSR_LVD (0x40)
#endif /* __MCF52221_RCM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_RTC_H__
#define __MCF52221_RTC_H__
/*********************************************************************
*
* Real-Time Clock (RTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_RTC_HOURMIN (*(vuint32*)(0x400003C0))
#define MCF_RTC_SECONDS (*(vuint32*)(0x400003C4))
#define MCF_RTC_ALRM_HM (*(vuint32*)(0x400003C8))
#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x400003CC))
#define MCF_RTC_RTCCTL (*(vuint32*)(0x400003D0))
#define MCF_RTC_RTCISR (*(vuint32*)(0x400003D4))
#define MCF_RTC_RTCIENR (*(vuint32*)(0x400003D8))
#define MCF_RTC_STPWCH (*(vuint32*)(0x400003DC))
#define MCF_RTC_DAYS (*(vuint32*)(0x400003E0))
#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x400003E4))
/* Bit definitions and macros for MCF_RTC_HOURMIN */
#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)
#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)
/* Bit definitions and macros for MCF_RTC_SECONDS */
#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_ALRM_HM */
#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)
#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)
/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_RTCCTL */
#define MCF_RTC_RTCCTL_SWR (0x1)
#define MCF_RTC_RTCCTL_EN (0x80)
/* Bit definitions and macros for MCF_RTC_RTCISR */
#define MCF_RTC_RTCISR_SW (0x1)
#define MCF_RTC_RTCISR_MIN (0x2)
#define MCF_RTC_RTCISR_ALM (0x4)
#define MCF_RTC_RTCISR_DAY (0x8)
#define MCF_RTC_RTCISR_1HZ (0x10)
#define MCF_RTC_RTCISR_HR (0x20)
/* Bit definitions and macros for MCF_RTC_RTCIENR */
#define MCF_RTC_RTCIENR_SW (0x1)
#define MCF_RTC_RTCIENR_MIN (0x2)
#define MCF_RTC_RTCIENR_ALM (0x4)
#define MCF_RTC_RTCIENR_DAY (0x8)
#define MCF_RTC_RTCIENR_1HZ (0x10)
#define MCF_RTC_RTCIENR_HR (0x20)
/* Bit definitions and macros for MCF_RTC_STPWCH */
#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_RTC_DAYS */
#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)
#endif /* __MCF52221_RTC_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_SCM_H__
#define __MCF52221_SCM_H__
/*********************************************************************
*
* System Control Module (SCM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008))
#define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C))
#define MCF_SCM_CRSR (*(vuint8 *)(0x40000010))
#define MCF_SCM_CWCR (*(vuint8 *)(0x40000011))
#define MCF_SCM_CWSR (*(vuint8 *)(0x40000013))
#define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014))
#define MCF_SCM_PPMRL (*(vuint32*)(0x40000018))
#define MCF_SCM_MPARK (*(vuint32*)(0x4000001C))
#define MCF_SCM_MPR (*(vuint8 *)(0x40000020))
#define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021))
#define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022))
#define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023))
#define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024))
#define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025))
#define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026))
#define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027))
#define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028))
#define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029))
#define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A))
#define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B))
#define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C))
#define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030))
#define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031))
#define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1)))
#define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1)))
/* Other macros */
#define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000))
#define MCF_SCM_IPSBAR_V (0x1)
#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
/* Bit definitions and macros for MCF_SCM_RAMBAR */
#define MCF_SCM_RAMBAR_BDE (0x200)
#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_SCM_PPMRH */
#define MCF_SCM_PPMRH_CDPORTS (0x1)
#define MCF_SCM_PPMRH_CDEPORT (0x2)
#define MCF_SCM_PPMRH_CDPIT0 (0x8)
#define MCF_SCM_PPMRH_CDPIT1 (0x10)
#define MCF_SCM_PPMRH_CDADC (0x80)
#define MCF_SCM_PPMRH_CDGPT (0x100)
#define MCF_SCM_PPMRH_CDPWM (0x200)
#define MCF_SCM_PPMRH_CDFCAN (0x400)
#define MCF_SCM_PPMRH_CDCFM (0x800)
/* Bit definitions and macros for MCF_SCM_CRSR */
#define MCF_SCM_CRSR_EXT (0x80)
/* Bit definitions and macros for MCF_SCM_CWCR */
#define MCF_SCM_CWCR_CWTIF (0x1)
#define MCF_SCM_CWCR_CWTAVAL (0x2)
#define MCF_SCM_CWCR_CWTA (0x4)
#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
#define MCF_SCM_CWCR_CWT_2_9 (0)
#define MCF_SCM_CWCR_CWT_2_11 (0x8)
#define MCF_SCM_CWCR_CWT_2_13 (0x10)
#define MCF_SCM_CWCR_CWT_2_15 (0x18)
#define MCF_SCM_CWCR_CWT_2_19 (0x20)
#define MCF_SCM_CWCR_CWT_2_23 (0x28)
#define MCF_SCM_CWCR_CWT_2_27 (0x30)
#define MCF_SCM_CWCR_CWT_2_31 (0x38)
#define MCF_SCM_CWCR_CWRI (0x40)
#define MCF_SCM_CWCR_CWE (0x80)
/* Bit definitions and macros for MCF_SCM_CWSR */
#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_SCM_DMAREQC */
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
/* Bit definitions and macros for MCF_SCM_PPMRL */
#define MCF_SCM_PPMRL_CDG (0x2)
#define MCF_SCM_PPMRL_CDDMA (0x10)
#define MCF_SCM_PPMRL_CDUART0 (0x20)
#define MCF_SCM_PPMRL_CDUART1 (0x40)
#define MCF_SCM_PPMRL_CDUART2 (0x80)
#define MCF_SCM_PPMRL_CDI2C (0x200)
#define MCF_SCM_PPMRL_CDQSPI (0x400)
#define MCF_SCM_PPMRL_CDTMR0 (0x2000)
#define MCF_SCM_PPMRL_CDTMR1 (0x4000)
#define MCF_SCM_PPMRL_CDTMR2 (0x8000)
#define MCF_SCM_PPMRL_CDTMR3 (0x10000)
#define MCF_SCM_PPMRL_CDINTC0 (0x20000)
/* Bit definitions and macros for MCF_SCM_MPARK */
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
#define MCF_SCM_MPARK_PRKLAST (0x1000)
#define MCF_SCM_MPARK_TIMEOUT (0x2000)
#define MCF_SCM_MPARK_FIXED (0x4000)
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
#define MCF_SCM_MPARK_BCR24BIT (0x1000000)
#define MCF_SCM_MPARK_M2_P_EN (0x2000000)
/* Bit definitions and macros for MCF_SCM_MPR */
#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
/* Bit definitions and macros for MCF_SCM_PPMRS */
#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
#define MCF_SCM_PPMRS_SET_CDG (0x1)
/* Bit definitions and macros for MCF_SCM_PPMRC */
#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
/* Bit definitions and macros for MCF_SCM_IPSBMT */
#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
#define MCF_SCM_IPSBMT_BME (0x8)
/* Bit definitions and macros for MCF_SCM_PACR */
#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
#define MCF_SCM_PACR_LOCK0 (0x8)
#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
#define MCF_SCM_PACR_LOCK1 (0x80)
/* Bit definitions and macros for MCF_SCM_GPACR */
#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
#define MCF_SCM_GPACR_LOCK (0x80)
#endif /* __MCF52221_SCM_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_UART_H__
#define __MCF52221_UART_H__
/*********************************************************************
*
* Universal Asynchronous Receiver Transmitter (UART)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200))
#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200))
#define MCF_UART0_USR (*(vuint8 *)(0x40000204))
#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204))
#define MCF_UART0_UCR (*(vuint8 *)(0x40000208))
#define MCF_UART0_URB (*(vuint8 *)(0x4000020C))
#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C))
#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210))
#define MCF_UART0_UACR (*(vuint8 *)(0x40000210))
#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214))
#define MCF_UART0_UISR (*(vuint8 *)(0x40000214))
#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218))
#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C))
#define MCF_UART0_UIP (*(vuint8 *)(0x40000234))
#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238))
#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C))
#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240))
#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240))
#define MCF_UART1_USR (*(vuint8 *)(0x40000244))
#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244))
#define MCF_UART1_UCR (*(vuint8 *)(0x40000248))
#define MCF_UART1_URB (*(vuint8 *)(0x4000024C))
#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C))
#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250))
#define MCF_UART1_UACR (*(vuint8 *)(0x40000250))
#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254))
#define MCF_UART1_UISR (*(vuint8 *)(0x40000254))
#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258))
#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C))
#define MCF_UART1_UIP (*(vuint8 *)(0x40000274))
#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278))
#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C))
#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280))
#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280))
#define MCF_UART2_USR (*(vuint8 *)(0x40000284))
#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284))
#define MCF_UART2_UCR (*(vuint8 *)(0x40000288))
#define MCF_UART2_URB (*(vuint8 *)(0x4000028C))
#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C))
#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290))
#define MCF_UART2_UACR (*(vuint8 *)(0x40000290))
#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294))
#define MCF_UART2_UISR (*(vuint8 *)(0x40000294))
#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298))
#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C))
#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4))
#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8))
#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC))
#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40)))
#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40)))
#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40)))
#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40)))
#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40)))
#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40)))
#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40)))
/* Bit definitions and macros for MCF_UART_UMR */
#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)
#define MCF_UART_UMR_BC_5 (0)
#define MCF_UART_UMR_BC_6 (0x1)
#define MCF_UART_UMR_BC_7 (0x2)
#define MCF_UART_UMR_BC_8 (0x3)
#define MCF_UART_UMR_PT (0x4)
#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)
#define MCF_UART_UMR_ERR (0x20)
#define MCF_UART_UMR_RXIRQ (0x40)
#define MCF_UART_UMR_RXRTS (0x80)
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
#define MCF_UART_UMR_PM_NONE (0x10)
#define MCF_UART_UMR_PM_FORCE_HI (0xC)
#define MCF_UART_UMR_PM_FORCE_LO (0x8)
#define MCF_UART_UMR_PM_ODD (0x4)
#define MCF_UART_UMR_PM_EVEN (0)
#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)
#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)
#define MCF_UART_UMR_TXCTS (0x10)
#define MCF_UART_UMR_TXRTS (0x20)
#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)
#define MCF_UART_UMR_CM_NORMAL (0)
#define MCF_UART_UMR_CM_ECHO (0x40)
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
/* Bit definitions and macros for MCF_UART_USR */
#define MCF_UART_USR_RXRDY (0x1)
#define MCF_UART_USR_FFULL (0x2)
#define MCF_UART_USR_TXRDY (0x4)
#define MCF_UART_USR_TXEMP (0x8)
#define MCF_UART_USR_OE (0x10)
#define MCF_UART_USR_PE (0x20)
#define MCF_UART_USR_FE (0x40)
#define MCF_UART_USR_RB (0x80)
/* Bit definitions and macros for MCF_UART_UCSR */
#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)
#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)
#define MCF_UART_UCSR_TCS_CTM16 (0xE)
#define MCF_UART_UCSR_TCS_CTM (0xF)
#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
#define MCF_UART_UCSR_RCS_CTM (0xF0)
/* Bit definitions and macros for MCF_UART_UCR */
#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)
#define MCF_UART_UCR_RX_ENABLED (0x1)
#define MCF_UART_UCR_RX_DISABLED (0x2)
#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)
#define MCF_UART_UCR_TX_ENABLED (0x4)
#define MCF_UART_UCR_TX_DISABLED (0x8)
#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)
#define MCF_UART_UCR_NONE (0)
#define MCF_UART_UCR_RESET_MR (0x10)
#define MCF_UART_UCR_RESET_RX (0x20)
#define MCF_UART_UCR_RESET_TX (0x30)
#define MCF_UART_UCR_RESET_ERROR (0x40)
#define MCF_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF_UART_UCR_START_BREAK (0x60)
#define MCF_UART_UCR_STOP_BREAK (0x70)
/* Bit definitions and macros for MCF_UART_URB */
#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_UART_UTB */
#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_UART_UIPCR */
#define MCF_UART_UIPCR_CTS (0x1)
#define MCF_UART_UIPCR_COS (0x10)
/* Bit definitions and macros for MCF_UART_UACR */
#define MCF_UART_UACR_IEC (0x1)
/* Bit definitions and macros for MCF_UART_UIMR */
#define MCF_UART_UIMR_TXRDY (0x1)
#define MCF_UART_UIMR_FFULL_RXRDY (0x2)
#define MCF_UART_UIMR_DB (0x4)
#define MCF_UART_UIMR_COS (0x80)
/* Bit definitions and macros for MCF_UART_UISR */
#define MCF_UART_UISR_TXRDY (0x1)
#define MCF_UART_UISR_FFULL_RXRDY (0x2)
#define MCF_UART_UISR_DB (0x4)
#define MCF_UART_UISR_COS (0x80)
/* Bit definitions and macros for MCF_UART_UBG1 */
#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_UART_UBG2 */
#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_UART_UIP */
#define MCF_UART_UIP_CTS (0x1)
/* Bit definitions and macros for MCF_UART_UOP1 */
#define MCF_UART_UOP1_RTS (0x1)
/* Bit definitions and macros for MCF_UART_UOP0 */
#define MCF_UART_UOP0_RTS (0x1)
#endif /* __MCF52221_UART_H__ */

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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.95
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF52221_USB_OTG_H__
#define __MCF52221_USB_OTG_H__
/*********************************************************************
*
* Universal Serial Bus - OTG Controller (USB_OTG)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_USB_OTG_PER_ID (*(vuint8 *)(0x401C0000))
#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(0x401C0004))
#define MCF_USB_OTG_REV (*(vuint8 *)(0x401C0008))
#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(0x401C000C))
#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(0x401C0010))
#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(0x401C0014))
#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(0x401C0018))
#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(0x401C001C))
#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(0x401C0080))
#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(0x401C0084))
#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(0x401C0088))
#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(0x401C008C))
#define MCF_USB_OTG_STAT (*(vuint8 *)(0x401C0090))
#define MCF_USB_OTG_CTL (*(vuint8 *)(0x401C0094))
#define MCF_USB_OTG_ADDR (*(vuint8 *)(0x401C0098))
#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(0x401C009C))
#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(0x401C00A0))
#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(0x401C00A4))
#define MCF_USB_OTG_TOKEN (*(vuint8 *)(0x401C00A8))
#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(0x401C00AC))
#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(0x401C00B0))
#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(0x401C00B4))
#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(0x401C00C0))
#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(0x401C00C4))
#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(0x401C00C8))
#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(0x401C00CC))
#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(0x401C00D0))
#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(0x401C00D4))
#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(0x401C00D8))
#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(0x401C00DC))
#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(0x401C00E0))
#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(0x401C00E4))
#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(0x401C00E8))
#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(0x401C00EC))
#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(0x401C00F0))
#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(0x401C00F4))
#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(0x401C00F8))
#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(0x401C00FC))
#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(0x401C0100))
#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(0x401C0104))
#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(0x401C0108))
#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(0x401C00C0 + ((x)*0x4)))
/* Other macros */
#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8))
/* Bit definitions and macros for MCF_USB_OTG_PER_ID */
#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */
#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_USB_OTG_REV */
#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */
#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1)
#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3)
/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */
#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1)
#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4)
#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8)
#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20)
#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40)
#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80)
/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */
#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1)
#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4)
#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8)
#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20)
#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40)
#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80)
/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */
#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1)
#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4)
#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8)
#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20)
#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40)
#define MCF_USB_OTG_OTG_STAT_ID (0x80)
/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */
#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1)
#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2)
#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4)
#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8)
#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10)
#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20)
#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80)
/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */
#define MCF_USB_OTG_INT_STAT_USB_RST (0x1)
#define MCF_USB_OTG_INT_STAT_ERROR (0x2)
#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4)
#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8)
#define MCF_USB_OTG_INT_STAT_SLEEP (0x10)
#define MCF_USB_OTG_INT_STAT_RESUME (0x20)
#define MCF_USB_OTG_INT_STAT_ATTACH (0x40)
#define MCF_USB_OTG_INT_STAT_STALL (0x80)
/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */
#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1)
#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2)
#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4)
#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8)
#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10)
#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20)
#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40)
#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80)
/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */
#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1)
#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2)
#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4)
#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8)
#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10)
#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20)
#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80)
/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */
#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1)
#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2)
#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4)
#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8)
#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10)
#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20)
#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80)
/* Bit definitions and macros for MCF_USB_OTG_STAT */
#define MCF_USB_OTG_STAT_ODD (0x4)
#define MCF_USB_OTG_STAT_TX (0x8)
#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4)
/* Bit definitions and macros for MCF_USB_OTG_CTL */
#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1)
#define MCF_USB_OTG_CTL_ODD_RST (0x2)
#define MCF_USB_OTG_CTL_RESUME (0x4)
#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8)
#define MCF_USB_OTG_CTL_RESET (0x10)
#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20)
#define MCF_USB_OTG_CTL_SE0 (0x40)
#define MCF_USB_OTG_CTL_JSTATE (0x80)
/* Bit definitions and macros for MCF_USB_OTG_ADDR */
#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0)
#define MCF_USB_OTG_ADDR_LS_EN (0x80)
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40)
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80)
/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */
#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1)
#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2)
#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4)
#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8)
#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10)
#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20)
#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40)
#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80)
/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */
#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1)
#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2)
#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4)
/* Bit definitions and macros for MCF_USB_OTG_TOKEN */
#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0)
#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4)
#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10)
#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90)
#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0)
/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */
#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1)
#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2)
#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4)
#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8)
#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10)
#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20)
#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40)
#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80)
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40)
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80)
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40)
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80)
/* Bit definitions and macros for MCF_USB_OTG_ENDPT */
#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1)
#define MCF_USB_OTG_ENDPT_EP_STALL (0x2)
#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4)
#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8)
#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10)
#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40)
#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80)
/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */
#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0)
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0)
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1)
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3)
#define MCF_USB_OTG_USB_CTRL_PDE (0x40)
#define MCF_USB_OTG_USB_CTRL_SUSP (0x80)
/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSDIS (0x2)
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSCHG (0x4)
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSE (0x8)
#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10)
#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40)
#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80)
/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */
#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1)
#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2)
#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4)
#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8)
#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSD (0x10)
#endif /* __MCF52221_USB_OTG_H__ */