mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Before changing headers to V6 and changing portLONG, portSHORt and portCHAR to their standard C types.
This commit is contained in:
Richard Barry
parent
3dfbb349ca
commit
5c64e1fad9
4417 changed files with 1261274 additions and 0 deletions
BIN
20091005/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp
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20091005/Demo/ColdFire_MCF52221_CodeWarrior/RTOSDemo.mcp
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@ -0,0 +1,14 @@
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ResetHalt
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; Set VBR to the beginning of what will be SRAM
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; VBR is an absolute CPU register
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writecontrolreg 0x0801 0x20000000
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; Set RAMBAR1 (SRAM)
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writecontrolreg 0x0C05 0x20000021
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; Set FLASHBAR (Flash)
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writecontrolreg 0x0C04 0x00000061
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; Enable PST[3:0] signals
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writemem.b 0x40100074 0x0F
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@ -0,0 +1,31 @@
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// Memory Configuration File
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//
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// Description:
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// A memory configuration file contains commands that define the legally accessible
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// areas of memory for your specific board. Useful for example when the debugger
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// tries to display the content of a "char *" variable, that has not yet been initialized.
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// In this case the debugger may try to read from a bogus address, which could cause a
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// bus error.
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//
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// Board:
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// Freescale M52221DEMO
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//
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// Reference:
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// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
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// All reserved ranges read back 0xBABA...
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reservedchar 0xBA
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address IPSBAR_BASE 0x40000000
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usederivative "MCF52221"
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// Memory Map:
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// ----------------------------------------------------------------------
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range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
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reserved 0x00020000 0x1FFFFFFF
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range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
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reserved 0x20004000 0x40000007
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// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
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reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
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@ -0,0 +1,14 @@
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ResetHalt
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; Set VBR to the beginning of what will be SRAM
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; VBR is an absolute CPU register
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writecontrolreg 0x0801 0x20000000
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; Set RAMBAR1 (SRAM)
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writecontrolreg 0x0C05 0x20000021
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; Set FLASHBAR (Flash)
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writecontrolreg 0x0C04 0x00000061
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; Enable PST[3:0] signals
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writemem.b 0x40100074 0x0F
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@ -0,0 +1,31 @@
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// Memory Configuration File
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//
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// Description:
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// A memory configuration file contains commands that define the legally accessible
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||||
// areas of memory for your specific board. Useful for example when the debugger
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// tries to display the content of a "char *" variable, that has not yet been initialized.
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// In this case the debugger may try to read from a bogus address, which could cause a
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// bus error.
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//
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// Board:
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// Freescale M52221DEMO
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//
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// Reference:
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// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
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// All reserved ranges read back 0xBABA...
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reservedchar 0xBA
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address IPSBAR_BASE 0x40000000
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usederivative "MCF52221"
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// Memory Map:
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// ----------------------------------------------------------------------
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range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
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reserved 0x00020000 0x1FFFFFFF
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range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
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reserved 0x20004000 0x40000007
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// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
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reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
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@ -0,0 +1,14 @@
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ResetHalt
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; Set VBR to the beginning of what will be SRAM
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; VBR is an absolute CPU register
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writecontrolreg 0x0801 0x20000000
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; Set RAMBAR1 (SRAM)
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writecontrolreg 0x0C05 0x20000021
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; Set FLASHBAR (Flash)
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writecontrolreg 0x0C04 0x00000061
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; Enable PST[3:0] signals
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writemem.b 0x40100074 0x0F
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|
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@ -0,0 +1,31 @@
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// Memory Configuration File
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//
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||||
// Description:
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||||
// A memory configuration file contains commands that define the legally accessible
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||||
// areas of memory for your specific board. Useful for example when the debugger
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||||
// tries to display the content of a "char *" variable, that has not yet been initialized.
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// In this case the debugger may try to read from a bogus address, which could cause a
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// bus error.
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//
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// Board:
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// Freescale M52221DEMO
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//
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// Reference:
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// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7
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// All reserved ranges read back 0xBABA...
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reservedchar 0xBA
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address IPSBAR_BASE 0x40000000
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usederivative "MCF52221"
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// Memory Map:
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// ----------------------------------------------------------------------
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range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory
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reserved 0x00020000 0x1FFFFFFF
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range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM
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reserved 0x20004000 0x40000007
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// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers
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reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF
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@ -0,0 +1,48 @@
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<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
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<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">
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<targetconfwindow>
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<usecustomsettings>false</usecustomsettings>
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<targetprocessor>52221</targetprocessor>
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<connection></connection>
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<usetargetinit>true</usetargetinit>
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<targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\M52221DEMO.cfg</targetinitfile>
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<targetmembuffaddr>0x20000000</targetmembuffaddr>
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<targetmembuffsize>0x00004000</targetmembuffsize>
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<enablelogging>true</enablelogging>
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<verifywrites>false</verifywrites>
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</targetconfwindow>
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<flashconfwindow>
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<membaseaddr>0x00000000</membaseaddr>
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<device>CFM_MCF52221</device>
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<organization>4Kx32x1</organization>
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<flashstart>0x00000000</flashstart>
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<flashend>0x0001FFFF</flashend>
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</flashconfwindow>
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<programverifywindow>
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<useselectedfile>false</useselectedfile>
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<projbuildtargetfile>nofile</projbuildtargetfile>
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<fileiotype>Auto Detect</fileiotype>
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<restrictaddrrange>false</restrictaddrrange>
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<restrictaddrrangestart>0x00000000</restrictaddrrangestart>
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<restrictaddrrangeend>0x0001FFFF</restrictaddrrangeend>
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<applyaddroffset>false</applyaddroffset>
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<addroffset>0x00000000</addroffset>
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</programverifywindow>
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<eraseblankcheckwindow>
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<eraseallsectors>true</eraseallsectors>
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<sector/>
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<processsectorsindividually>false</processsectorsindividually>
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</eraseblankcheckwindow>
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<checksumwindow>
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<computechecksumover>FileOnTarg</computechecksumover>
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<addrstart>0x00000000</addrstart>
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<addrsize>0x0000FFFF</addrsize>
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</checksumwindow>
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</fpconfig>
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@ -0,0 +1,89 @@
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/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.95
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF52221_H__
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#define __MCF52221_H__
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/********************************************************************/
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/*
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* The basic data types
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*/
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typedef unsigned char uint8; /* 8 bits */
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typedef unsigned short int uint16; /* 16 bits */
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typedef unsigned long int uint32; /* 32 bits */
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typedef signed char int8; /* 8 bits */
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typedef signed short int int16; /* 16 bits */
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typedef signed long int int32; /* 32 bits */
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typedef volatile uint8 vuint8; /* 8 bits */
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typedef volatile uint16 vuint16; /* 16 bits */
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typedef volatile uint32 vuint32; /* 32 bits */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#pragma define_section system ".system" far_absolute RW
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/***
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* MCF52221 Derivative Memory map definitions from linker command files:
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* __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
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* symbols must be defined in the linker command file.
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*/
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extern __declspec(system) uint8 __IPSBAR[];
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extern __declspec(system) uint8 __RAMBAR[];
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extern __declspec(system) uint8 __RAMBAR_SIZE[];
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extern __declspec(system) uint8 __FLASHBAR[];
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extern __declspec(system) uint8 __FLASHBAR_SIZE[];
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#define IPSBAR_ADDRESS (uint32)__IPSBAR
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#define RAMBAR_ADDRESS (uint32)__RAMBAR
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#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
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#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
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#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
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#include "MCF52221_SCM.h"
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#include "MCF52221_DMA.h"
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#include "MCF52221_UART.h"
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#include "MCF52221_I2C.h"
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#include "MCF52221_QSPI.h"
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#include "MCF52221_RTC.h"
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#include "MCF52221_DTIM.h"
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#include "MCF52221_INTC.h"
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#include "MCF52221_GPIO.h"
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#include "MCF52221_PAD.h"
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#include "MCF52221_RCM.h"
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#include "MCF52221_CCM.h"
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#include "MCF52221_PMM.h"
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#include "MCF52221_CLOCK.h"
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#include "MCF52221_EPORT.h"
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#include "MCF52221_PIT.h"
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#include "MCF52221_ADC.h"
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#include "MCF52221_GPTA.h"
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#include "MCF52221_PWM.h"
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#include "MCF52221_USB_OTG.h"
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#include "MCF52221_CFM.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MCF52221_H__ */
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@ -0,0 +1,201 @@
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/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.95
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF52221_ADC_H__
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#define __MCF52221_ADC_H__
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/*********************************************************************
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*
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* Analog-to-Digital Converter (ADC)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000))
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#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002))
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#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004))
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#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006))
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#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008))
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#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A))
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#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C))
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#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E))
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#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010))
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#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012))
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#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014))
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#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016))
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#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018))
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#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A))
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#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C))
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#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E))
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#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020))
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#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022))
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#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024))
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#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026))
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#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028))
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#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A))
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#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C))
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#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E))
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#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030))
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#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032))
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#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034))
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#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036))
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#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038))
|
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#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A))
|
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#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C))
|
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#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E))
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#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040))
|
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#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042))
|
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#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044))
|
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#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046))
|
||||
#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048))
|
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#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A))
|
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#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C))
|
||||
#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E))
|
||||
#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050))
|
||||
#define MCF_ADC_POWER (*(vuint16*)(0x40190052))
|
||||
#define MCF_ADC_CAL (*(vuint16*)(0x40190054))
|
||||
#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2)))
|
||||
#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2)))
|
||||
#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2)))
|
||||
#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_CTRL1 */
|
||||
#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)
|
||||
#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_ADC_CTRL1_HLMTIE (0x100)
|
||||
#define MCF_ADC_CTRL1_LLMTIE (0x200)
|
||||
#define MCF_ADC_CTRL1_ZCIE (0x400)
|
||||
#define MCF_ADC_CTRL1_EOSIE0 (0x800)
|
||||
#define MCF_ADC_CTRL1_SYNC0 (0x1000)
|
||||
#define MCF_ADC_CTRL1_START0 (0x2000)
|
||||
#define MCF_ADC_CTRL1_STOP0 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_CTRL2 */
|
||||
#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)
|
||||
#define MCF_ADC_CTRL2_SIMULT (0x20)
|
||||
#define MCF_ADC_CTRL2_EOSIE1 (0x800)
|
||||
#define MCF_ADC_CTRL2_SYNC1 (0x1000)
|
||||
#define MCF_ADC_CTRL2_START1 (0x2000)
|
||||
#define MCF_ADC_CTRL2_STOP1 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADZCC */
|
||||
#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)
|
||||
#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADLST1 */
|
||||
#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)
|
||||
#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADLST2 */
|
||||
#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)
|
||||
#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADSDIS */
|
||||
#define MCF_ADC_ADSDIS_DS0 (0x1)
|
||||
#define MCF_ADC_ADSDIS_DS1 (0x2)
|
||||
#define MCF_ADC_ADSDIS_DS2 (0x4)
|
||||
#define MCF_ADC_ADSDIS_DS3 (0x8)
|
||||
#define MCF_ADC_ADSDIS_DS4 (0x10)
|
||||
#define MCF_ADC_ADSDIS_DS5 (0x20)
|
||||
#define MCF_ADC_ADSDIS_DS6 (0x40)
|
||||
#define MCF_ADC_ADSDIS_DS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADSTAT */
|
||||
#define MCF_ADC_ADSTAT_RDY0 (0x1)
|
||||
#define MCF_ADC_ADSTAT_RDY1 (0x2)
|
||||
#define MCF_ADC_ADSTAT_RDY2 (0x4)
|
||||
#define MCF_ADC_ADSTAT_RDY3 (0x8)
|
||||
#define MCF_ADC_ADSTAT_RDY4 (0x10)
|
||||
#define MCF_ADC_ADSTAT_RDY5 (0x20)
|
||||
#define MCF_ADC_ADSTAT_RDY6 (0x40)
|
||||
#define MCF_ADC_ADSTAT_RDY7 (0x80)
|
||||
#define MCF_ADC_ADSTAT_HLMTI (0x100)
|
||||
#define MCF_ADC_ADSTAT_LLMTI (0x200)
|
||||
#define MCF_ADC_ADSTAT_ZCI (0x400)
|
||||
#define MCF_ADC_ADSTAT_EOSI0 (0x800)
|
||||
#define MCF_ADC_ADSTAT_EOSI1 (0x1000)
|
||||
#define MCF_ADC_ADSTAT_CIP1 (0x4000)
|
||||
#define MCF_ADC_ADSTAT_CIP0 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADLSTAT */
|
||||
#define MCF_ADC_ADLSTAT_LLS0 (0x1)
|
||||
#define MCF_ADC_ADLSTAT_LLS1 (0x2)
|
||||
#define MCF_ADC_ADLSTAT_LLS2 (0x4)
|
||||
#define MCF_ADC_ADLSTAT_LLS3 (0x8)
|
||||
#define MCF_ADC_ADLSTAT_LLS4 (0x10)
|
||||
#define MCF_ADC_ADLSTAT_LLS5 (0x20)
|
||||
#define MCF_ADC_ADLSTAT_LLS6 (0x40)
|
||||
#define MCF_ADC_ADLSTAT_LLS7 (0x80)
|
||||
#define MCF_ADC_ADLSTAT_HLS0 (0x100)
|
||||
#define MCF_ADC_ADLSTAT_HLS1 (0x200)
|
||||
#define MCF_ADC_ADLSTAT_HLS2 (0x400)
|
||||
#define MCF_ADC_ADLSTAT_HLS3 (0x800)
|
||||
#define MCF_ADC_ADLSTAT_HLS4 (0x1000)
|
||||
#define MCF_ADC_ADLSTAT_HLS5 (0x2000)
|
||||
#define MCF_ADC_ADLSTAT_HLS6 (0x4000)
|
||||
#define MCF_ADC_ADLSTAT_HLS7 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADZCSTAT */
|
||||
#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)
|
||||
#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADRSLT */
|
||||
#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)
|
||||
#define MCF_ADC_ADRSLT_SEXT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADLLMT */
|
||||
#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADHLMT */
|
||||
#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_ADOFS */
|
||||
#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_POWER */
|
||||
#define MCF_ADC_POWER_PD0 (0x1)
|
||||
#define MCF_ADC_POWER_PD1 (0x2)
|
||||
#define MCF_ADC_POWER_PD2 (0x4)
|
||||
#define MCF_ADC_POWER_APD (0x8)
|
||||
#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)
|
||||
#define MCF_ADC_POWER_PSTS0 (0x400)
|
||||
#define MCF_ADC_POWER_PSTS1 (0x800)
|
||||
#define MCF_ADC_POWER_PSTS2 (0x1000)
|
||||
#define MCF_ADC_POWER_ASB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ADC_CAL */
|
||||
#define MCF_ADC_CAL_SEL_VREFL (0x4000)
|
||||
#define MCF_ADC_CAL_SEL_VREFH (0x8000)
|
||||
|
||||
|
||||
#endif /* __MCF52221_ADC_H__ */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_CCM_H__
|
||||
#define __MCF52221_CCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(0x40110004))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(0x40110008))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)
|
||||
#define MCF_CCM_CCR_MODE_EZPORT (0x500)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x1)
|
||||
#define MCF_CCM_RCON_RLOAD (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)
|
||||
|
||||
|
||||
#endif /* __MCF52221_CCM_H__ */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_CFM_H__
|
||||
#define __MCF52221_CFM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ColdFire Flash Module (CFM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))
|
||||
#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))
|
||||
#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))
|
||||
#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))
|
||||
#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))
|
||||
#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))
|
||||
#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))
|
||||
#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))
|
||||
#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMMCR */
|
||||
#define MCF_CFM_CFMMCR_KEYACC (0x20)
|
||||
#define MCF_CFM_CFMMCR_CCIE (0x40)
|
||||
#define MCF_CFM_CFMMCR_CBEIE (0x80)
|
||||
#define MCF_CFM_CFMMCR_AEIE (0x100)
|
||||
#define MCF_CFM_CFMMCR_PVIE (0x200)
|
||||
#define MCF_CFM_CFMMCR_LOCK (0x400)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
|
||||
#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
|
||||
#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
|
||||
#define MCF_CFM_CFMCLKD_DIVLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSEC */
|
||||
#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
|
||||
#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMPROT */
|
||||
#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSACC */
|
||||
#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMDACC */
|
||||
#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
|
||||
#define MCF_CFM_CFMUSTAT_BLANK (0x4)
|
||||
#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
|
||||
#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
|
||||
#define MCF_CFM_CFMUSTAT_CCIF (0x40)
|
||||
#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCMD */
|
||||
#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
|
||||
#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
|
||||
#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
|
||||
#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */
|
||||
#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_CFM_H__ */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_CLOCK_H__
|
||||
#define __MCF52221_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))
|
||||
#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))
|
||||
#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))
|
||||
#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))
|
||||
#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))
|
||||
#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))
|
||||
#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))
|
||||
#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))
|
||||
#define MCF_CLOCK_RTCDR (*(vuint32*)(0x4012000C))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
|
||||
#define MCF_CLOCK_SYNCR_PLLEN (0x1)
|
||||
#define MCF_CLOCK_SYNCR_PLLMODE (0x2)
|
||||
#define MCF_CLOCK_SYNCR_CLKSRC (0x4)
|
||||
#define MCF_CLOCK_SYNCR_FWKUP (0x20)
|
||||
#define MCF_CLOCK_SYNCR_DISCLK (0x40)
|
||||
#define MCF_CLOCK_SYNCR_LOCEN (0x80)
|
||||
#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_CLOCK_SYNCR_LOCRE (0x800)
|
||||
#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
|
||||
#define MCF_CLOCK_SYNSR_LOCS (0x4)
|
||||
#define MCF_CLOCK_SYNSR_LOCK (0x8)
|
||||
#define MCF_CLOCK_SYNSR_LOCKS (0x10)
|
||||
#define MCF_CLOCK_SYNSR_CRYOSC (0x20)
|
||||
#define MCF_CLOCK_SYNSR_OCOSC (0x40)
|
||||
#define MCF_CLOCK_SYNSR_EXTOSC (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_ROCR */
|
||||
#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_LPDR */
|
||||
#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_CCHR */
|
||||
#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_CCLR */
|
||||
#define MCF_CLOCK_CCLR_OSCSEL (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_OCHR */
|
||||
#define MCF_CLOCK_OCHR_STBY (0x40)
|
||||
#define MCF_CLOCK_OCHR_OCOEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_OCLR */
|
||||
#define MCF_CLOCK_OCLR_RANGE (0x10)
|
||||
#define MCF_CLOCK_OCLR_LPEN (0x20)
|
||||
#define MCF_CLOCK_OCLR_REFS (0x40)
|
||||
#define MCF_CLOCK_OCLR_OSCEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_RTCDR */
|
||||
#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_CLOCK_H__ */
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_DMA_H__
|
||||
#define __MCF52221_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Controller (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))
|
||||
#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))
|
||||
#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))
|
||||
#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))
|
||||
#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))
|
||||
|
||||
#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))
|
||||
#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))
|
||||
#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))
|
||||
#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))
|
||||
#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))
|
||||
|
||||
#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))
|
||||
#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))
|
||||
#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))
|
||||
#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))
|
||||
#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))
|
||||
|
||||
#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))
|
||||
#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))
|
||||
#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))
|
||||
#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))
|
||||
#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))
|
||||
|
||||
#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))
|
||||
#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))
|
||||
#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))
|
||||
#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))
|
||||
#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_SAR */
|
||||
#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DAR */
|
||||
#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DSR */
|
||||
#define MCF_DMA_DSR_DONE (0x1)
|
||||
#define MCF_DMA_DSR_BSY (0x2)
|
||||
#define MCF_DMA_DSR_REQ (0x4)
|
||||
#define MCF_DMA_DSR_BED (0x10)
|
||||
#define MCF_DMA_DSR_BES (0x20)
|
||||
#define MCF_DMA_DSR_CE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_BCR */
|
||||
#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)
|
||||
#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DCR */
|
||||
#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_DCR_LCH2_CH0 (0)
|
||||
#define MCF_DMA_DCR_LCH2_CH1 (0x1)
|
||||
#define MCF_DMA_DCR_LCH2_CH2 (0x2)
|
||||
#define MCF_DMA_DCR_LCH2_CH3 (0x3)
|
||||
#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_DCR_LCH1_CH0 (0)
|
||||
#define MCF_DMA_DCR_LCH1_CH1 (0x1)
|
||||
#define MCF_DMA_DCR_LCH1_CH2 (0x2)
|
||||
#define MCF_DMA_DCR_LCH1_CH3 (0x3)
|
||||
#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_DCR_D_REQ (0x80)
|
||||
#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DMA_DCR_DMOD_DIS (0)
|
||||
#define MCF_DMA_DCR_DMOD_16 (0x1)
|
||||
#define MCF_DMA_DCR_DMOD_32 (0x2)
|
||||
#define MCF_DMA_DCR_DMOD_64 (0x3)
|
||||
#define MCF_DMA_DCR_DMOD_128 (0x4)
|
||||
#define MCF_DMA_DCR_DMOD_256 (0x5)
|
||||
#define MCF_DMA_DCR_DMOD_512 (0x6)
|
||||
#define MCF_DMA_DCR_DMOD_1K (0x7)
|
||||
#define MCF_DMA_DCR_DMOD_2K (0x8)
|
||||
#define MCF_DMA_DCR_DMOD_4K (0x9)
|
||||
#define MCF_DMA_DCR_DMOD_8K (0xA)
|
||||
#define MCF_DMA_DCR_DMOD_16K (0xB)
|
||||
#define MCF_DMA_DCR_DMOD_32K (0xC)
|
||||
#define MCF_DMA_DCR_DMOD_64K (0xD)
|
||||
#define MCF_DMA_DCR_DMOD_128K (0xE)
|
||||
#define MCF_DMA_DCR_DMOD_256K (0xF)
|
||||
#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DMA_DCR_SMOD_DIS (0)
|
||||
#define MCF_DMA_DCR_SMOD_16 (0x1)
|
||||
#define MCF_DMA_DCR_SMOD_32 (0x2)
|
||||
#define MCF_DMA_DCR_SMOD_64 (0x3)
|
||||
#define MCF_DMA_DCR_SMOD_128 (0x4)
|
||||
#define MCF_DMA_DCR_SMOD_256 (0x5)
|
||||
#define MCF_DMA_DCR_SMOD_512 (0x6)
|
||||
#define MCF_DMA_DCR_SMOD_1K (0x7)
|
||||
#define MCF_DMA_DCR_SMOD_2K (0x8)
|
||||
#define MCF_DMA_DCR_SMOD_4K (0x9)
|
||||
#define MCF_DMA_DCR_SMOD_8K (0xA)
|
||||
#define MCF_DMA_DCR_SMOD_16K (0xB)
|
||||
#define MCF_DMA_DCR_SMOD_32K (0xC)
|
||||
#define MCF_DMA_DCR_SMOD_64K (0xD)
|
||||
#define MCF_DMA_DCR_SMOD_128K (0xE)
|
||||
#define MCF_DMA_DCR_SMOD_256K (0xF)
|
||||
#define MCF_DMA_DCR_START (0x10000)
|
||||
#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
|
||||
#define MCF_DMA_DCR_DSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_DSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_DSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_DINC (0x80000)
|
||||
#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_DCR_SSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_SSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_SSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_SINC (0x400000)
|
||||
#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
|
||||
#define MCF_DMA_DCR_BWC_16K (0x1)
|
||||
#define MCF_DMA_DCR_BWC_32K (0x2)
|
||||
#define MCF_DMA_DCR_BWC_64K (0x3)
|
||||
#define MCF_DMA_DCR_BWC_128K (0x4)
|
||||
#define MCF_DMA_DCR_BWC_256K (0x5)
|
||||
#define MCF_DMA_DCR_BWC_512K (0x6)
|
||||
#define MCF_DMA_DCR_BWC_1024K (0x7)
|
||||
#define MCF_DMA_DCR_AA (0x10000000)
|
||||
#define MCF_DMA_DCR_CS (0x20000000)
|
||||
#define MCF_DMA_DCR_EEXT (0x40000000)
|
||||
#define MCF_DMA_DCR_INT (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF52221_DMA_H__ */
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_DTIM_H__
|
||||
#define __MCF52221_DTIM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (DTIM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))
|
||||
#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))
|
||||
#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))
|
||||
#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))
|
||||
#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))
|
||||
#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))
|
||||
|
||||
#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))
|
||||
#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))
|
||||
#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))
|
||||
#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))
|
||||
#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))
|
||||
#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))
|
||||
|
||||
#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))
|
||||
#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))
|
||||
#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))
|
||||
#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))
|
||||
#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))
|
||||
#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))
|
||||
|
||||
#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))
|
||||
#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))
|
||||
#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))
|
||||
#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))
|
||||
#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))
|
||||
#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))
|
||||
|
||||
#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
|
||||
#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))
|
||||
#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))
|
||||
#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))
|
||||
#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))
|
||||
#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTMR */
|
||||
#define MCF_DTIM_DTMR_RST (0x1)
|
||||
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_DTIM_DTMR_CLK_STOP (0)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
|
||||
#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
|
||||
#define MCF_DTIM_DTMR_FRR (0x8)
|
||||
#define MCF_DTIM_DTMR_ORRI (0x10)
|
||||
#define MCF_DTIM_DTMR_OM (0x20)
|
||||
#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DTIM_DTMR_CE_NONE (0)
|
||||
#define MCF_DTIM_DTMR_CE_RISE (0x40)
|
||||
#define MCF_DTIM_DTMR_CE_FALL (0x80)
|
||||
#define MCF_DTIM_DTMR_CE_ANY (0xC0)
|
||||
#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTXMR */
|
||||
#define MCF_DTIM_DTXMR_MODE16 (0x1)
|
||||
#define MCF_DTIM_DTXMR_HALTED (0x40)
|
||||
#define MCF_DTIM_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTER */
|
||||
#define MCF_DTIM_DTER_CAP (0x1)
|
||||
#define MCF_DTIM_DTER_REF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTRR */
|
||||
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCR */
|
||||
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCN */
|
||||
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_DTIM_H__ */
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_EPORT_H__
|
||||
#define __MCF52221_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52221_EPORT_H__ */
|
||||
|
|
@ -0,0 +1,475 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_GPIO_H__
|
||||
#define __MCF52221_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008))
|
||||
#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020))
|
||||
#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038))
|
||||
#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050))
|
||||
#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068))
|
||||
|
||||
#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A))
|
||||
#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022))
|
||||
#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A))
|
||||
#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052))
|
||||
#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A))
|
||||
|
||||
#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B))
|
||||
#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023))
|
||||
#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B))
|
||||
#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053))
|
||||
#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B))
|
||||
|
||||
#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C))
|
||||
#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024))
|
||||
#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C))
|
||||
#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054))
|
||||
#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C))
|
||||
|
||||
#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E))
|
||||
#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026))
|
||||
#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E))
|
||||
#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056))
|
||||
#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E))
|
||||
|
||||
#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F))
|
||||
#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027))
|
||||
#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F))
|
||||
#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057))
|
||||
#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F))
|
||||
|
||||
#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011))
|
||||
#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029))
|
||||
#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041))
|
||||
#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059))
|
||||
#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071))
|
||||
|
||||
#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012))
|
||||
#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A))
|
||||
#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042))
|
||||
#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A))
|
||||
#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTNQ */
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRNQ */
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETNQ */
|
||||
#define MCF_GPIO_SETNQ_SETNQ1 (0x2)
|
||||
#define MCF_GPIO_SETNQ_SETNQ2 (0x4)
|
||||
#define MCF_GPIO_SETNQ_SETNQ3 (0x8)
|
||||
#define MCF_GPIO_SETNQ_SETNQ4 (0x10)
|
||||
#define MCF_GPIO_SETNQ_SETNQ5 (0x20)
|
||||
#define MCF_GPIO_SETNQ_SETNQ6 (0x40)
|
||||
#define MCF_GPIO_SETNQ_SETNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRNQ */
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PNQPAR */
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTAN */
|
||||
#define MCF_GPIO_PORTAN_PORTAN0 (0x1)
|
||||
#define MCF_GPIO_PORTAN_PORTAN1 (0x2)
|
||||
#define MCF_GPIO_PORTAN_PORTAN2 (0x4)
|
||||
#define MCF_GPIO_PORTAN_PORTAN3 (0x8)
|
||||
#define MCF_GPIO_PORTAN_PORTAN4 (0x10)
|
||||
#define MCF_GPIO_PORTAN_PORTAN5 (0x20)
|
||||
#define MCF_GPIO_PORTAN_PORTAN6 (0x40)
|
||||
#define MCF_GPIO_PORTAN_PORTAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRAN */
|
||||
#define MCF_GPIO_DDRAN_DDRAN0 (0x1)
|
||||
#define MCF_GPIO_DDRAN_DDRAN1 (0x2)
|
||||
#define MCF_GPIO_DDRAN_DDRAN2 (0x4)
|
||||
#define MCF_GPIO_DDRAN_DDRAN3 (0x8)
|
||||
#define MCF_GPIO_DDRAN_DDRAN4 (0x10)
|
||||
#define MCF_GPIO_DDRAN_DDRAN5 (0x20)
|
||||
#define MCF_GPIO_DDRAN_DDRAN6 (0x40)
|
||||
#define MCF_GPIO_DDRAN_DDRAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETAN */
|
||||
#define MCF_GPIO_SETAN_SETAN0 (0x1)
|
||||
#define MCF_GPIO_SETAN_SETAN1 (0x2)
|
||||
#define MCF_GPIO_SETAN_SETAN2 (0x4)
|
||||
#define MCF_GPIO_SETAN_SETAN3 (0x8)
|
||||
#define MCF_GPIO_SETAN_SETAN4 (0x10)
|
||||
#define MCF_GPIO_SETAN_SETAN5 (0x20)
|
||||
#define MCF_GPIO_SETAN_SETAN6 (0x40)
|
||||
#define MCF_GPIO_SETAN_SETAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRAN */
|
||||
#define MCF_GPIO_CLRAN_CLRAN0 (0x1)
|
||||
#define MCF_GPIO_CLRAN_CLRAN1 (0x2)
|
||||
#define MCF_GPIO_CLRAN_CLRAN2 (0x4)
|
||||
#define MCF_GPIO_CLRAN_CLRAN3 (0x8)
|
||||
#define MCF_GPIO_CLRAN_CLRAN4 (0x10)
|
||||
#define MCF_GPIO_CLRAN_CLRAN5 (0x20)
|
||||
#define MCF_GPIO_CLRAN_CLRAN6 (0x40)
|
||||
#define MCF_GPIO_CLRAN_CLRAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PANPAR */
|
||||
#define MCF_GPIO_PANPAR_PANPAR0 (0x1)
|
||||
#define MCF_GPIO_PANPAR_AN0_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)
|
||||
#define MCF_GPIO_PANPAR_PANPAR1 (0x2)
|
||||
#define MCF_GPIO_PANPAR_AN1_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)
|
||||
#define MCF_GPIO_PANPAR_PANPAR2 (0x4)
|
||||
#define MCF_GPIO_PANPAR_AN2_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)
|
||||
#define MCF_GPIO_PANPAR_PANPAR3 (0x8)
|
||||
#define MCF_GPIO_PANPAR_AN3_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)
|
||||
#define MCF_GPIO_PANPAR_PANPAR4 (0x10)
|
||||
#define MCF_GPIO_PANPAR_AN4_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)
|
||||
#define MCF_GPIO_PANPAR_PANPAR5 (0x20)
|
||||
#define MCF_GPIO_PANPAR_AN5_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)
|
||||
#define MCF_GPIO_PANPAR_PANPAR6 (0x40)
|
||||
#define MCF_GPIO_PANPAR_AN6_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)
|
||||
#define MCF_GPIO_PANPAR_PANPAR7 (0x80)
|
||||
#define MCF_GPIO_PANPAR_AN7_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTAS */
|
||||
#define MCF_GPIO_PORTAS_PORTAS0 (0x1)
|
||||
#define MCF_GPIO_PORTAS_PORTAS1 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRAS */
|
||||
#define MCF_GPIO_DDRAS_DDRAS0 (0x1)
|
||||
#define MCF_GPIO_DDRAS_DDRAS1 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETAS */
|
||||
#define MCF_GPIO_SETAS_SETAS0 (0x1)
|
||||
#define MCF_GPIO_SETAS_SETAS1 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRAS */
|
||||
#define MCF_GPIO_CLRAS_CLRAS0 (0x1)
|
||||
#define MCF_GPIO_CLRAS_CLRAS1 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PASPAR */
|
||||
#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PASPAR_SCL_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SCL_SCL (0x1)
|
||||
#define MCF_GPIO_PASPAR_SCL_USB_DMI (0x2)
|
||||
#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3)
|
||||
#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PASPAR_SDA_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SDA_SDA (0x4)
|
||||
#define MCF_GPIO_PASPAR_SDA_USB_DPI (0x8)
|
||||
#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTQS */
|
||||
#define MCF_GPIO_PORTQS_PORTQS0 (0x1)
|
||||
#define MCF_GPIO_PORTQS_PORTQS1 (0x2)
|
||||
#define MCF_GPIO_PORTQS_PORTQS2 (0x4)
|
||||
#define MCF_GPIO_PORTQS_PORTQS3 (0x8)
|
||||
#define MCF_GPIO_PORTQS_PORTQS4 (0x10)
|
||||
#define MCF_GPIO_PORTQS_PORTQS5 (0x20)
|
||||
#define MCF_GPIO_PORTQS_PORTQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRQS */
|
||||
#define MCF_GPIO_DDRQS_DDRQS0 (0x1)
|
||||
#define MCF_GPIO_DDRQS_DDRQS1 (0x2)
|
||||
#define MCF_GPIO_DDRQS_DDRQS2 (0x4)
|
||||
#define MCF_GPIO_DDRQS_DDRQS3 (0x8)
|
||||
#define MCF_GPIO_DDRQS_DDRQS4 (0x10)
|
||||
#define MCF_GPIO_DDRQS_DDRQS5 (0x20)
|
||||
#define MCF_GPIO_DDRQS_DDRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETQS */
|
||||
#define MCF_GPIO_SETQS_SETQS0 (0x1)
|
||||
#define MCF_GPIO_SETQS_SETQS1 (0x2)
|
||||
#define MCF_GPIO_SETQS_SETQS2 (0x4)
|
||||
#define MCF_GPIO_SETQS_SETQS3 (0x8)
|
||||
#define MCF_GPIO_SETQS_SETQS4 (0x10)
|
||||
#define MCF_GPIO_SETQS_SETQS5 (0x20)
|
||||
#define MCF_GPIO_SETQS_SETQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRQS */
|
||||
#define MCF_GPIO_CLRQS_CLRQS0 (0x1)
|
||||
#define MCF_GPIO_CLRQS_CLRQS1 (0x2)
|
||||
#define MCF_GPIO_CLRQS_CLRQS2 (0x4)
|
||||
#define MCF_GPIO_CLRQS_CLRQS3 (0x8)
|
||||
#define MCF_GPIO_CLRQS_CLRQS4 (0x10)
|
||||
#define MCF_GPIO_CLRQS_CLRQS5 (0x20)
|
||||
#define MCF_GPIO_CLRQS_CLRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PQSPAR */
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_USB_PULLUP (0x300)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PD (0xC00)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PD (0x3000)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTA */
|
||||
#define MCF_GPIO_PORTTA_PORTTA0 (0x1)
|
||||
#define MCF_GPIO_PORTTA_PORTTA1 (0x2)
|
||||
#define MCF_GPIO_PORTTA_PORTTA2 (0x4)
|
||||
#define MCF_GPIO_PORTTA_PORTTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTA */
|
||||
#define MCF_GPIO_DDRTA_DDRTA0 (0x1)
|
||||
#define MCF_GPIO_DDRTA_DDRTA1 (0x2)
|
||||
#define MCF_GPIO_DDRTA_DDRTA2 (0x4)
|
||||
#define MCF_GPIO_DDRTA_DDRTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTA */
|
||||
#define MCF_GPIO_SETTA_SETTA0 (0x1)
|
||||
#define MCF_GPIO_SETTA_SETTA1 (0x2)
|
||||
#define MCF_GPIO_SETTA_SETTA2 (0x4)
|
||||
#define MCF_GPIO_SETTA_SETTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTA */
|
||||
#define MCF_GPIO_CLRTA_CLRTA0 (0x1)
|
||||
#define MCF_GPIO_CLRTA_CLRTA1 (0x2)
|
||||
#define MCF_GPIO_CLRTA_CLRTA2 (0x4)
|
||||
#define MCF_GPIO_CLRTA_CLRTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PTAPAR */
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTC */
|
||||
#define MCF_GPIO_PORTTC_PORTTC0 (0x1)
|
||||
#define MCF_GPIO_PORTTC_PORTTC1 (0x2)
|
||||
#define MCF_GPIO_PORTTC_PORTTC2 (0x4)
|
||||
#define MCF_GPIO_PORTTC_PORTTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTC */
|
||||
#define MCF_GPIO_DDRTC_DDRTC0 (0x1)
|
||||
#define MCF_GPIO_DDRTC_DDRTC1 (0x2)
|
||||
#define MCF_GPIO_DDRTC_DDRTC2 (0x4)
|
||||
#define MCF_GPIO_DDRTC_DDRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTC */
|
||||
#define MCF_GPIO_SETTC_SETTC0 (0x1)
|
||||
#define MCF_GPIO_SETTC_SETTC1 (0x2)
|
||||
#define MCF_GPIO_SETTC_SETTC2 (0x4)
|
||||
#define MCF_GPIO_SETTC_SETTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTC */
|
||||
#define MCF_GPIO_CLRTC_CLRTC0 (0x1)
|
||||
#define MCF_GPIO_CLRTC_CLRTC1 (0x2)
|
||||
#define MCF_GPIO_CLRTC_CLRTC2 (0x4)
|
||||
#define MCF_GPIO_CLRTC_CLRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PTCPAR */
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUA */
|
||||
#define MCF_GPIO_PORTUA_PORTUA0 (0x1)
|
||||
#define MCF_GPIO_PORTUA_PORTUA1 (0x2)
|
||||
#define MCF_GPIO_PORTUA_PORTUA2 (0x4)
|
||||
#define MCF_GPIO_PORTUA_PORTUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUA */
|
||||
#define MCF_GPIO_DDRUA_DDRUA0 (0x1)
|
||||
#define MCF_GPIO_DDRUA_DDRUA1 (0x2)
|
||||
#define MCF_GPIO_DDRUA_DDRUA2 (0x4)
|
||||
#define MCF_GPIO_DDRUA_DDRUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUA */
|
||||
#define MCF_GPIO_SETUA_SETUA0 (0x1)
|
||||
#define MCF_GPIO_SETUA_SETUA1 (0x2)
|
||||
#define MCF_GPIO_SETUA_SETUA2 (0x4)
|
||||
#define MCF_GPIO_SETUA_SETUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUA */
|
||||
#define MCF_GPIO_CLRUA_CLRUA0 (0x1)
|
||||
#define MCF_GPIO_CLRUA_CLRUA1 (0x2)
|
||||
#define MCF_GPIO_CLRUA_CLRUA2 (0x4)
|
||||
#define MCF_GPIO_CLRUA_CLRUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PUAPAR */
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_USB_SUSPEND (0x3)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_USB_RCV (0xC)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUB */
|
||||
#define MCF_GPIO_PORTUB_PORTUB0 (0x1)
|
||||
#define MCF_GPIO_PORTUB_PORTUB1 (0x2)
|
||||
#define MCF_GPIO_PORTUB_PORTUB2 (0x4)
|
||||
#define MCF_GPIO_PORTUB_PORTUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUB */
|
||||
#define MCF_GPIO_DDRUB_DDRUB0 (0x1)
|
||||
#define MCF_GPIO_DDRUB_DDRUB1 (0x2)
|
||||
#define MCF_GPIO_DDRUB_DDRUB2 (0x4)
|
||||
#define MCF_GPIO_DDRUB_DDRUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUB */
|
||||
#define MCF_GPIO_SETUB_SETUB0 (0x1)
|
||||
#define MCF_GPIO_SETUB_SETUB1 (0x2)
|
||||
#define MCF_GPIO_SETUB_SETUB2 (0x4)
|
||||
#define MCF_GPIO_SETUB_SETUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUB */
|
||||
#define MCF_GPIO_CLRUB_CLRUB0 (0x1)
|
||||
#define MCF_GPIO_CLRUB_CLRUB1 (0x2)
|
||||
#define MCF_GPIO_CLRUB_CLRUB2 (0x4)
|
||||
#define MCF_GPIO_CLRUB_CLRUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PUBPAR */
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_USB_SPEED (0x3)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_USB_OE (0xC)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_GPTA_H__
|
||||
#define __MCF52221_GPTA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timer Module (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPTA_GPTIOS (*(vuint8 *)(0x401A0000))
|
||||
#define MCF_GPTA_GPTCFORC (*(vuint8 *)(0x401A0001))
|
||||
#define MCF_GPTA_GPTOC3M (*(vuint8 *)(0x401A0002))
|
||||
#define MCF_GPTA_GPTOC3D (*(vuint8 *)(0x401A0003))
|
||||
#define MCF_GPTA_GPTCNT (*(vuint16*)(0x401A0004))
|
||||
#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(0x401A0006))
|
||||
#define MCF_GPTA_GPTTOV (*(vuint8 *)(0x401A0008))
|
||||
#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(0x401A0009))
|
||||
#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(0x401A000B))
|
||||
#define MCF_GPTA_GPTIE (*(vuint8 *)(0x401A000C))
|
||||
#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(0x401A000D))
|
||||
#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(0x401A000E))
|
||||
#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(0x401A000F))
|
||||
#define MCF_GPTA_GPTC0 (*(vuint16*)(0x401A0010))
|
||||
#define MCF_GPTA_GPTC1 (*(vuint16*)(0x401A0012))
|
||||
#define MCF_GPTA_GPTC2 (*(vuint16*)(0x401A0014))
|
||||
#define MCF_GPTA_GPTC3 (*(vuint16*)(0x401A0016))
|
||||
#define MCF_GPTA_GPTPACTL (*(vuint8 *)(0x401A0018))
|
||||
#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(0x401A0019))
|
||||
#define MCF_GPTA_GPTPACNT (*(vuint16*)(0x401A001A))
|
||||
#define MCF_GPTA_GPTPORT (*(vuint8 *)(0x401A001D))
|
||||
#define MCF_GPTA_GPTDDR (*(vuint8 *)(0x401A001E))
|
||||
#define MCF_GPTA_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIOS */
|
||||
#define MCF_GPTA_GPTIOS_IOS0 (0x1)
|
||||
#define MCF_GPTA_GPTIOS_IOS1 (0x2)
|
||||
#define MCF_GPTA_GPTIOS_IOS2 (0x4)
|
||||
#define MCF_GPTA_GPTIOS_IOS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCFORC */
|
||||
#define MCF_GPTA_GPTCFORC_FOC0 (0x1)
|
||||
#define MCF_GPTA_GPTCFORC_FOC1 (0x2)
|
||||
#define MCF_GPTA_GPTCFORC_FOC2 (0x4)
|
||||
#define MCF_GPTA_GPTCFORC_FOC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3M */
|
||||
#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3D */
|
||||
#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCNT */
|
||||
#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */
|
||||
#define MCF_GPTA_GPTSCR1_TFFCA (0x10)
|
||||
#define MCF_GPTA_GPTSCR1_GPTEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTTOV */
|
||||
#define MCF_GPTA_GPTTOV_TOV0 (0x1)
|
||||
#define MCF_GPTA_GPTTOV_TOV1 (0x2)
|
||||
#define MCF_GPTA_GPTTOV_TOV2 (0x4)
|
||||
#define MCF_GPTA_GPTTOV_TOV3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */
|
||||
#define MCF_GPTA_GPTCTL1_OL0 (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OM0 (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OL1 (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OM1 (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OL2 (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OM2 (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OL3 (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OM3 (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */
|
||||
#define MCF_GPTA_GPTCTL2_EDG0A (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_EDG0B (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1A (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1B (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2A (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2B (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3A (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3B (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIE */
|
||||
#define MCF_GPTA_GPTIE_CI0 (0x1)
|
||||
#define MCF_GPTA_GPTIE_CI1 (0x2)
|
||||
#define MCF_GPTA_GPTIE_CI2 (0x4)
|
||||
#define MCF_GPTA_GPTIE_CI3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */
|
||||
#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_1 (0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_2 (0x1)
|
||||
#define MCF_GPTA_GPTSCR2_PR_4 (0x2)
|
||||
#define MCF_GPTA_GPTSCR2_PR_8 (0x3)
|
||||
#define MCF_GPTA_GPTSCR2_PR_16 (0x4)
|
||||
#define MCF_GPTA_GPTSCR2_PR_32 (0x5)
|
||||
#define MCF_GPTA_GPTSCR2_PR_64 (0x6)
|
||||
#define MCF_GPTA_GPTSCR2_PR_128 (0x7)
|
||||
#define MCF_GPTA_GPTSCR2_TCRE (0x8)
|
||||
#define MCF_GPTA_GPTSCR2_RDPT (0x10)
|
||||
#define MCF_GPTA_GPTSCR2_PUPT (0x20)
|
||||
#define MCF_GPTA_GPTSCR2_TOI (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */
|
||||
#define MCF_GPTA_GPTFLG1_CF0 (0x1)
|
||||
#define MCF_GPTA_GPTFLG1_CF1 (0x2)
|
||||
#define MCF_GPTA_GPTFLG1_CF2 (0x4)
|
||||
#define MCF_GPTA_GPTFLG1_CF3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */
|
||||
#define MCF_GPTA_GPTFLG2_TOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTC */
|
||||
#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACTL */
|
||||
#define MCF_GPTA_GPTPACTL_PAI (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_PAOVI (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)
|
||||
#define MCF_GPTA_GPTPACTL_PEDGE (0x10)
|
||||
#define MCF_GPTA_GPTPACTL_PAMOD (0x20)
|
||||
#define MCF_GPTA_GPTPACTL_PAE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */
|
||||
#define MCF_GPTA_GPTPAFLG_PAIF (0x1)
|
||||
#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACNT */
|
||||
#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPORT */
|
||||
#define MCF_GPTA_GPTPORT_PORTT0 (0x1)
|
||||
#define MCF_GPTA_GPTPORT_PORTT1 (0x2)
|
||||
#define MCF_GPTA_GPTPORT_PORTT2 (0x4)
|
||||
#define MCF_GPTA_GPTPORT_PORTT3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTDDR */
|
||||
#define MCF_GPTA_GPTDDR_DDRT0 (0x1)
|
||||
#define MCF_GPTA_GPTDDR_DDRT1 (0x2)
|
||||
#define MCF_GPTA_GPTDDR_DDRT2 (0x4)
|
||||
#define MCF_GPTA_GPTDDR_DDRT3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF52221_GPTA_H__ */
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_I2C_H__
|
||||
#define __MCF52221_I2C_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2ADR (*(vuint8 *)(0x40000300))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(0x40000304))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(0x40000308))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(0x4000030C))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(0x40000310))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ADR */
|
||||
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x4)
|
||||
#define MCF_I2C_I2CR_TXAK (0x8)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x1)
|
||||
#define MCF_I2C_I2SR_IIF (0x2)
|
||||
#define MCF_I2C_I2SR_SRW (0x4)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2DR */
|
||||
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_I2C_H__ */
|
||||
|
|
@ -0,0 +1,331 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_INTC_H__
|
||||
#define __MCF52221_INTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller (INTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))
|
||||
#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))
|
||||
#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))
|
||||
#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))
|
||||
#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))
|
||||
#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))
|
||||
#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))
|
||||
#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))
|
||||
#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))
|
||||
#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))
|
||||
#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))
|
||||
#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x1)
|
||||
#define MCF_INTC_IPRH_INT33 (0x2)
|
||||
#define MCF_INTC_IPRH_INT34 (0x4)
|
||||
#define MCF_INTC_IPRH_INT35 (0x8)
|
||||
#define MCF_INTC_IPRH_INT36 (0x10)
|
||||
#define MCF_INTC_IPRH_INT37 (0x20)
|
||||
#define MCF_INTC_IPRH_INT38 (0x40)
|
||||
#define MCF_INTC_IPRH_INT39 (0x80)
|
||||
#define MCF_INTC_IPRH_INT40 (0x100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x1000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x2000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x4000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x8000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x10000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x20000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x40000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x80000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x1000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x2000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x4000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x8000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT1 (0x2)
|
||||
#define MCF_INTC_IPRL_INT2 (0x4)
|
||||
#define MCF_INTC_IPRL_INT3 (0x8)
|
||||
#define MCF_INTC_IPRL_INT4 (0x10)
|
||||
#define MCF_INTC_IPRL_INT5 (0x20)
|
||||
#define MCF_INTC_IPRL_INT6 (0x40)
|
||||
#define MCF_INTC_IPRL_INT7 (0x80)
|
||||
#define MCF_INTC_IPRL_INT8 (0x100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x1000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x2000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x4000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x8000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x10000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x20000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x40000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x80000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x1000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x2000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x4000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x8000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_MASKALL (0x1)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IRLR */
|
||||
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IACKLPR */
|
||||
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
|
||||
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_INTC_H__ */
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_PAD_H__
|
||||
#define __MCF52221_PAD_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Common GPIO
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PAD_PSRR (*(vuint32*)(0x40100078))
|
||||
#define MCF_PAD_PDSR (*(vuint32*)(0x4010007C))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PSRR */
|
||||
#define MCF_PAD_PSRR_PSRR0 (0x1)
|
||||
#define MCF_PAD_PSRR_PSRR1 (0x2)
|
||||
#define MCF_PAD_PSRR_PSRR2 (0x4)
|
||||
#define MCF_PAD_PSRR_PSRR3 (0x8)
|
||||
#define MCF_PAD_PSRR_PSRR4 (0x10)
|
||||
#define MCF_PAD_PSRR_PSRR5 (0x20)
|
||||
#define MCF_PAD_PSRR_PSRR6 (0x40)
|
||||
#define MCF_PAD_PSRR_PSRR7 (0x80)
|
||||
#define MCF_PAD_PSRR_PSRR8 (0x100)
|
||||
#define MCF_PAD_PSRR_PSRR9 (0x200)
|
||||
#define MCF_PAD_PSRR_PSRR10 (0x400)
|
||||
#define MCF_PAD_PSRR_PSRR11 (0x800)
|
||||
#define MCF_PAD_PSRR_PSRR12 (0x1000)
|
||||
#define MCF_PAD_PSRR_PSRR13 (0x2000)
|
||||
#define MCF_PAD_PSRR_PSRR14 (0x4000)
|
||||
#define MCF_PAD_PSRR_PSRR15 (0x8000)
|
||||
#define MCF_PAD_PSRR_PSRR16 (0x10000)
|
||||
#define MCF_PAD_PSRR_PSRR17 (0x20000)
|
||||
#define MCF_PAD_PSRR_PSRR18 (0x40000)
|
||||
#define MCF_PAD_PSRR_PSRR19 (0x80000)
|
||||
#define MCF_PAD_PSRR_PSRR20 (0x100000)
|
||||
#define MCF_PAD_PSRR_PSRR21 (0x200000)
|
||||
#define MCF_PAD_PSRR_PSRR22 (0x400000)
|
||||
#define MCF_PAD_PSRR_PSRR23 (0x800000)
|
||||
#define MCF_PAD_PSRR_PSRR24 (0x1000000)
|
||||
#define MCF_PAD_PSRR_PSRR25 (0x2000000)
|
||||
#define MCF_PAD_PSRR_PSRR26 (0x4000000)
|
||||
#define MCF_PAD_PSRR_PSRR27 (0x8000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PDSR */
|
||||
#define MCF_PAD_PDSR_PDSR0 (0x1)
|
||||
#define MCF_PAD_PDSR_PDSR1 (0x2)
|
||||
#define MCF_PAD_PDSR_PDSR2 (0x4)
|
||||
#define MCF_PAD_PDSR_PDSR3 (0x8)
|
||||
#define MCF_PAD_PDSR_PDSR4 (0x10)
|
||||
#define MCF_PAD_PDSR_PDSR5 (0x20)
|
||||
#define MCF_PAD_PDSR_PDSR6 (0x40)
|
||||
#define MCF_PAD_PDSR_PDSR7 (0x80)
|
||||
#define MCF_PAD_PDSR_PDSR8 (0x100)
|
||||
#define MCF_PAD_PDSR_PDSR9 (0x200)
|
||||
#define MCF_PAD_PDSR_PDSR10 (0x400)
|
||||
#define MCF_PAD_PDSR_PDSR11 (0x800)
|
||||
#define MCF_PAD_PDSR_PDSR12 (0x1000)
|
||||
#define MCF_PAD_PDSR_PDSR13 (0x2000)
|
||||
#define MCF_PAD_PDSR_PDSR14 (0x4000)
|
||||
#define MCF_PAD_PDSR_PDSR15 (0x8000)
|
||||
#define MCF_PAD_PDSR_PDSR16 (0x10000)
|
||||
#define MCF_PAD_PDSR_PDSR17 (0x20000)
|
||||
#define MCF_PAD_PDSR_PDSR18 (0x40000)
|
||||
#define MCF_PAD_PDSR_PDSR19 (0x80000)
|
||||
#define MCF_PAD_PDSR_PDSR20 (0x100000)
|
||||
#define MCF_PAD_PDSR_PDSR21 (0x200000)
|
||||
#define MCF_PAD_PDSR_PDSR22 (0x400000)
|
||||
#define MCF_PAD_PDSR_PDSR23 (0x800000)
|
||||
#define MCF_PAD_PDSR_PDSR24 (0x1000000)
|
||||
#define MCF_PAD_PDSR_PDSR25 (0x2000000)
|
||||
#define MCF_PAD_PDSR_PDSR26 (0x4000000)
|
||||
#define MCF_PAD_PDSR_PDSR27 (0x8000000)
|
||||
|
||||
|
||||
#endif /* __MCF52221_PAD_H__ */
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_PIT_H__
|
||||
#define __MCF52221_PIT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))
|
||||
#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))
|
||||
#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))
|
||||
|
||||
#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))
|
||||
#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))
|
||||
#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))
|
||||
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x1)
|
||||
#define MCF_PIT_PCSR_RLD (0x2)
|
||||
#define MCF_PIT_PCSR_PIF (0x4)
|
||||
#define MCF_PIT_PCSR_PIE (0x8)
|
||||
#define MCF_PIT_PCSR_OVW (0x10)
|
||||
#define MCF_PIT_PCSR_DBG (0x20)
|
||||
#define MCF_PIT_PCSR_DOZE (0x40)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_PIT_H__ */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_PMM_H__
|
||||
#define __MCF52221_PMM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Power Management (PMM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))
|
||||
#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPICR */
|
||||
#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_PMM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPCR */
|
||||
#define MCF_PMM_LPCR_STPMD (0x8)
|
||||
#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PMM_LPCR_LPMD_RUN (0)
|
||||
#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_PMM_H__ */
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_PWM_H__
|
||||
#define __MCF52221_PWM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Pulse Width Modulation (PWM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))
|
||||
#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))
|
||||
#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))
|
||||
#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))
|
||||
#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))
|
||||
#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))
|
||||
#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))
|
||||
#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))
|
||||
#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))
|
||||
#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))
|
||||
#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))
|
||||
#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))
|
||||
#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))
|
||||
#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))
|
||||
#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))
|
||||
#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))
|
||||
#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))
|
||||
#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))
|
||||
#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))
|
||||
#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))
|
||||
#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))
|
||||
#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))
|
||||
#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))
|
||||
#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))
|
||||
#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))
|
||||
#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))
|
||||
#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))
|
||||
#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))
|
||||
#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))
|
||||
#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))
|
||||
#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))
|
||||
#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))
|
||||
#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))
|
||||
#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))
|
||||
#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))
|
||||
#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWME */
|
||||
#define MCF_PWM_PWME_PWME0 (0x1)
|
||||
#define MCF_PWM_PWME_PWME1 (0x2)
|
||||
#define MCF_PWM_PWME_PWME2 (0x4)
|
||||
#define MCF_PWM_PWME_PWME3 (0x8)
|
||||
#define MCF_PWM_PWME_PWME4 (0x10)
|
||||
#define MCF_PWM_PWME_PWME5 (0x20)
|
||||
#define MCF_PWM_PWME_PWME6 (0x40)
|
||||
#define MCF_PWM_PWME_PWME7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPOL */
|
||||
#define MCF_PWM_PWMPOL_PPOL0 (0x1)
|
||||
#define MCF_PWM_PWMPOL_PPOL1 (0x2)
|
||||
#define MCF_PWM_PWMPOL_PPOL2 (0x4)
|
||||
#define MCF_PWM_PWMPOL_PPOL3 (0x8)
|
||||
#define MCF_PWM_PWMPOL_PPOL4 (0x10)
|
||||
#define MCF_PWM_PWMPOL_PPOL5 (0x20)
|
||||
#define MCF_PWM_PWMPOL_PPOL6 (0x40)
|
||||
#define MCF_PWM_PWMPOL_PPOL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCLK */
|
||||
#define MCF_PWM_PWMCLK_PCLK0 (0x1)
|
||||
#define MCF_PWM_PWMCLK_PCLK1 (0x2)
|
||||
#define MCF_PWM_PWMCLK_PCLK2 (0x4)
|
||||
#define MCF_PWM_PWMCLK_PCLK3 (0x8)
|
||||
#define MCF_PWM_PWMCLK_PCLK4 (0x10)
|
||||
#define MCF_PWM_PWMCLK_PCLK5 (0x20)
|
||||
#define MCF_PWM_PWMCLK_PCLK6 (0x40)
|
||||
#define MCF_PWM_PWMCLK_PCLK7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
|
||||
#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)
|
||||
#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCAE */
|
||||
#define MCF_PWM_PWMCAE_CAE0 (0x1)
|
||||
#define MCF_PWM_PWMCAE_CAE1 (0x2)
|
||||
#define MCF_PWM_PWMCAE_CAE2 (0x4)
|
||||
#define MCF_PWM_PWMCAE_CAE3 (0x8)
|
||||
#define MCF_PWM_PWMCAE_CAE4 (0x10)
|
||||
#define MCF_PWM_PWMCAE_CAE5 (0x20)
|
||||
#define MCF_PWM_PWMCAE_CAE6 (0x40)
|
||||
#define MCF_PWM_PWMCAE_CAE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCTL */
|
||||
#define MCF_PWM_PWMCTL_PFRZ (0x4)
|
||||
#define MCF_PWM_PWMCTL_PSWAI (0x8)
|
||||
#define MCF_PWM_PWMCTL_CON01 (0x10)
|
||||
#define MCF_PWM_PWMCTL_CON23 (0x20)
|
||||
#define MCF_PWM_PWMCTL_CON45 (0x40)
|
||||
#define MCF_PWM_PWMCTL_CON67 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSCLA */
|
||||
#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSCLB */
|
||||
#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCNT */
|
||||
#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPER */
|
||||
#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMDTY */
|
||||
#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSDN */
|
||||
#define MCF_PWM_PWMSDN_SDNEN (0x1)
|
||||
#define MCF_PWM_PWMSDN_PWM7IL (0x2)
|
||||
#define MCF_PWM_PWMSDN_PWM7IN (0x4)
|
||||
#define MCF_PWM_PWMSDN_LVL (0x10)
|
||||
#define MCF_PWM_PWMSDN_RESTART (0x20)
|
||||
#define MCF_PWM_PWMSDN_IE (0x40)
|
||||
#define MCF_PWM_PWMSDN_IF (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52221_PWM_H__ */
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_QSPI_H__
|
||||
#define __MCF52221_QSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
|
||||
#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x1)
|
||||
#define MCF_QSPI_QIR_ABRT (0x4)
|
||||
#define MCF_QSPI_QIR_WCEF (0x8)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QSPI_QAR_TRANS (0)
|
||||
#define MCF_QSPI_QAR_RECV (0x10)
|
||||
#define MCF_QSPI_QAR_CMD (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDR */
|
||||
#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_QSPI_QDR_CONT (0x8000)
|
||||
#define MCF_QSPI_QDR_BITSE (0x4000)
|
||||
#define MCF_QSPI_QDR_DT (0x2000)
|
||||
#define MCF_QSPI_QDR_DSCK (0x1000)
|
||||
#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
|
||||
#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
|
||||
#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
|
||||
#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
|
||||
|
||||
|
||||
#endif /* __MCF52221_QSPI_H__ */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_RCM_H__
|
||||
#define __MCF52221_RCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Controller Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_LVDE (0x1)
|
||||
#define MCF_RCM_RCR_LVDRE (0x4)
|
||||
#define MCF_RCM_RCR_LVDIE (0x8)
|
||||
#define MCF_RCM_RCR_LVDF (0x10)
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x1)
|
||||
#define MCF_RCM_RSR_LOC (0x2)
|
||||
#define MCF_RCM_RSR_EXT (0x4)
|
||||
#define MCF_RCM_RSR_POR (0x8)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
#define MCF_RCM_RSR_LVD (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF52221_RCM_H__ */
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_RTC_H__
|
||||
#define __MCF52221_RTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Real-Time Clock (RTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RTC_HOURMIN (*(vuint32*)(0x400003C0))
|
||||
#define MCF_RTC_SECONDS (*(vuint32*)(0x400003C4))
|
||||
#define MCF_RTC_ALRM_HM (*(vuint32*)(0x400003C8))
|
||||
#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x400003CC))
|
||||
#define MCF_RTC_RTCCTL (*(vuint32*)(0x400003D0))
|
||||
#define MCF_RTC_RTCISR (*(vuint32*)(0x400003D4))
|
||||
#define MCF_RTC_RTCIENR (*(vuint32*)(0x400003D8))
|
||||
#define MCF_RTC_STPWCH (*(vuint32*)(0x400003DC))
|
||||
#define MCF_RTC_DAYS (*(vuint32*)(0x400003E0))
|
||||
#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x400003E4))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_HOURMIN */
|
||||
#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)
|
||||
#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_SECONDS */
|
||||
#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_HM */
|
||||
#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)
|
||||
#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
|
||||
#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCCTL */
|
||||
#define MCF_RTC_RTCCTL_SWR (0x1)
|
||||
#define MCF_RTC_RTCCTL_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCISR */
|
||||
#define MCF_RTC_RTCISR_SW (0x1)
|
||||
#define MCF_RTC_RTCISR_MIN (0x2)
|
||||
#define MCF_RTC_RTCISR_ALM (0x4)
|
||||
#define MCF_RTC_RTCISR_DAY (0x8)
|
||||
#define MCF_RTC_RTCISR_1HZ (0x10)
|
||||
#define MCF_RTC_RTCISR_HR (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCIENR */
|
||||
#define MCF_RTC_RTCIENR_SW (0x1)
|
||||
#define MCF_RTC_RTCIENR_MIN (0x2)
|
||||
#define MCF_RTC_RTCIENR_ALM (0x4)
|
||||
#define MCF_RTC_RTCIENR_DAY (0x8)
|
||||
#define MCF_RTC_RTCIENR_1HZ (0x10)
|
||||
#define MCF_RTC_RTCIENR_HR (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_STPWCH */
|
||||
#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_DAYS */
|
||||
#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
|
||||
#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52221_RTC_H__ */
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_SCM_H__
|
||||
#define __MCF52221_SCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008))
|
||||
#define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(0x40000010))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(0x40000011))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(0x40000013))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014))
|
||||
#define MCF_SCM_PPMRL (*(vuint32*)(0x40000018))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(0x4000001C))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(0x40000020))
|
||||
#define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021))
|
||||
#define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022))
|
||||
#define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030))
|
||||
#define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031))
|
||||
#define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1)))
|
||||
#define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1)))
|
||||
|
||||
/* Other macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000))
|
||||
#define MCF_SCM_IPSBAR_V (0x1)
|
||||
#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRH */
|
||||
#define MCF_SCM_PPMRH_CDPORTS (0x1)
|
||||
#define MCF_SCM_PPMRH_CDEPORT (0x2)
|
||||
#define MCF_SCM_PPMRH_CDPIT0 (0x8)
|
||||
#define MCF_SCM_PPMRH_CDPIT1 (0x10)
|
||||
#define MCF_SCM_PPMRH_CDADC (0x80)
|
||||
#define MCF_SCM_PPMRH_CDGPT (0x100)
|
||||
#define MCF_SCM_PPMRH_CDPWM (0x200)
|
||||
#define MCF_SCM_PPMRH_CDFCAN (0x400)
|
||||
#define MCF_SCM_PPMRH_CDCFM (0x800)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIF (0x1)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x2)
|
||||
#define MCF_SCM_CWCR_CWTA (0x4)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
|
||||
#define MCF_SCM_CWCR_CWT_2_9 (0)
|
||||
#define MCF_SCM_CWCR_CWT_2_11 (0x8)
|
||||
#define MCF_SCM_CWCR_CWT_2_13 (0x10)
|
||||
#define MCF_SCM_CWCR_CWT_2_15 (0x18)
|
||||
#define MCF_SCM_CWCR_CWT_2_19 (0x20)
|
||||
#define MCF_SCM_CWCR_CWT_2_23 (0x28)
|
||||
#define MCF_SCM_CWCR_CWT_2_27 (0x30)
|
||||
#define MCF_SCM_CWCR_CWT_2_31 (0x38)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWSR */
|
||||
#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRL */
|
||||
#define MCF_SCM_PPMRL_CDG (0x2)
|
||||
#define MCF_SCM_PPMRL_CDDMA (0x10)
|
||||
#define MCF_SCM_PPMRL_CDUART0 (0x20)
|
||||
#define MCF_SCM_PPMRL_CDUART1 (0x40)
|
||||
#define MCF_SCM_PPMRL_CDUART2 (0x80)
|
||||
#define MCF_SCM_PPMRL_CDI2C (0x200)
|
||||
#define MCF_SCM_PPMRL_CDQSPI (0x400)
|
||||
#define MCF_SCM_PPMRL_CDTMR0 (0x2000)
|
||||
#define MCF_SCM_PPMRL_CDTMR1 (0x4000)
|
||||
#define MCF_SCM_PPMRL_CDTMR2 (0x8000)
|
||||
#define MCF_SCM_PPMRL_CDTMR3 (0x10000)
|
||||
#define MCF_SCM_PPMRL_CDINTC0 (0x20000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x1000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x2000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x4000)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x1000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRS */
|
||||
#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
|
||||
#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
|
||||
#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
|
||||
#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
|
||||
#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
|
||||
#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
|
||||
#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
|
||||
#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
|
||||
#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
|
||||
#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
|
||||
#define MCF_SCM_PPMRS_SET_CDG (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRC */
|
||||
#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
|
||||
#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
|
||||
#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
|
||||
#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
|
||||
#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
|
||||
#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
|
||||
#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
|
||||
#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
|
||||
#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
|
||||
#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
|
||||
#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBMT */
|
||||
#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
|
||||
#define MCF_SCM_IPSBMT_BME (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR */
|
||||
#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
|
||||
#define MCF_SCM_PACR_LOCK0 (0x8)
|
||||
#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_SCM_PACR_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR */
|
||||
#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
|
||||
#define MCF_SCM_GPACR_LOCK (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52221_SCM_H__ */
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_UART_H__
|
||||
#define __MCF52221_UART_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200))
|
||||
#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200))
|
||||
#define MCF_UART0_USR (*(vuint8 *)(0x40000204))
|
||||
#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204))
|
||||
#define MCF_UART0_UCR (*(vuint8 *)(0x40000208))
|
||||
#define MCF_UART0_URB (*(vuint8 *)(0x4000020C))
|
||||
#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C))
|
||||
#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210))
|
||||
#define MCF_UART0_UACR (*(vuint8 *)(0x40000210))
|
||||
#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214))
|
||||
#define MCF_UART0_UISR (*(vuint8 *)(0x40000214))
|
||||
#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218))
|
||||
#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C))
|
||||
#define MCF_UART0_UIP (*(vuint8 *)(0x40000234))
|
||||
#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238))
|
||||
#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C))
|
||||
|
||||
#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240))
|
||||
#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240))
|
||||
#define MCF_UART1_USR (*(vuint8 *)(0x40000244))
|
||||
#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244))
|
||||
#define MCF_UART1_UCR (*(vuint8 *)(0x40000248))
|
||||
#define MCF_UART1_URB (*(vuint8 *)(0x4000024C))
|
||||
#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C))
|
||||
#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250))
|
||||
#define MCF_UART1_UACR (*(vuint8 *)(0x40000250))
|
||||
#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254))
|
||||
#define MCF_UART1_UISR (*(vuint8 *)(0x40000254))
|
||||
#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258))
|
||||
#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C))
|
||||
#define MCF_UART1_UIP (*(vuint8 *)(0x40000274))
|
||||
#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278))
|
||||
#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C))
|
||||
|
||||
#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280))
|
||||
#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280))
|
||||
#define MCF_UART2_USR (*(vuint8 *)(0x40000284))
|
||||
#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284))
|
||||
#define MCF_UART2_UCR (*(vuint8 *)(0x40000288))
|
||||
#define MCF_UART2_URB (*(vuint8 *)(0x4000028C))
|
||||
#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C))
|
||||
#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290))
|
||||
#define MCF_UART2_UACR (*(vuint8 *)(0x40000290))
|
||||
#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294))
|
||||
#define MCF_UART2_UISR (*(vuint8 *)(0x40000294))
|
||||
#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298))
|
||||
#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C))
|
||||
#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4))
|
||||
#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8))
|
||||
#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC))
|
||||
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40)))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40)))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40)))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40)))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40)))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40)))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40)))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)
|
||||
#define MCF_UART_UMR_BC_5 (0)
|
||||
#define MCF_UART_UMR_BC_6 (0x1)
|
||||
#define MCF_UART_UMR_BC_7 (0x2)
|
||||
#define MCF_UART_UMR_BC_8 (0x3)
|
||||
#define MCF_UART_UMR_PT (0x4)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0xC)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x8)
|
||||
#define MCF_UART_UMR_PM_ODD (0x4)
|
||||
#define MCF_UART_UMR_PM_EVEN (0)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x1)
|
||||
#define MCF_UART_USR_FFULL (0x2)
|
||||
#define MCF_UART_USR_TXRDY (0x4)
|
||||
#define MCF_UART_USR_TXEMP (0x8)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0xE)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0xF)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x1)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x2)
|
||||
#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x4)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x8)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_UART_UCR_NONE (0)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_URB */
|
||||
#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UTB */
|
||||
#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x1)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x1)
|
||||
#define MCF_UART_UIMR_FFULL_RXRDY (0x2)
|
||||
#define MCF_UART_UIMR_DB (0x4)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x1)
|
||||
#define MCF_UART_UISR_FFULL_RXRDY (0x2)
|
||||
#define MCF_UART_UISR_DB (0x4)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UBG1 */
|
||||
#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UBG2 */
|
||||
#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x1)
|
||||
|
||||
|
||||
#endif /* __MCF52221_UART_H__ */
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_USB_OTG_H__
|
||||
#define __MCF52221_USB_OTG_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Serial Bus - OTG Controller (USB_OTG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_USB_OTG_PER_ID (*(vuint8 *)(0x401C0000))
|
||||
#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(0x401C0004))
|
||||
#define MCF_USB_OTG_REV (*(vuint8 *)(0x401C0008))
|
||||
#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(0x401C000C))
|
||||
#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(0x401C0010))
|
||||
#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(0x401C0014))
|
||||
#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(0x401C0018))
|
||||
#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(0x401C001C))
|
||||
#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(0x401C0080))
|
||||
#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(0x401C0084))
|
||||
#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(0x401C0088))
|
||||
#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(0x401C008C))
|
||||
#define MCF_USB_OTG_STAT (*(vuint8 *)(0x401C0090))
|
||||
#define MCF_USB_OTG_CTL (*(vuint8 *)(0x401C0094))
|
||||
#define MCF_USB_OTG_ADDR (*(vuint8 *)(0x401C0098))
|
||||
#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(0x401C009C))
|
||||
#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(0x401C00A0))
|
||||
#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(0x401C00A4))
|
||||
#define MCF_USB_OTG_TOKEN (*(vuint8 *)(0x401C00A8))
|
||||
#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(0x401C00AC))
|
||||
#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(0x401C00B0))
|
||||
#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(0x401C00B4))
|
||||
#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(0x401C00C0))
|
||||
#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(0x401C00C4))
|
||||
#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(0x401C00C8))
|
||||
#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(0x401C00CC))
|
||||
#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(0x401C00D0))
|
||||
#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(0x401C00D4))
|
||||
#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(0x401C00D8))
|
||||
#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(0x401C00DC))
|
||||
#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(0x401C00E0))
|
||||
#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(0x401C00E4))
|
||||
#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(0x401C00E8))
|
||||
#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(0x401C00EC))
|
||||
#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(0x401C00F0))
|
||||
#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(0x401C00F4))
|
||||
#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(0x401C00F8))
|
||||
#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(0x401C00FC))
|
||||
#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(0x401C0100))
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(0x401C0104))
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(0x401C0108))
|
||||
#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(0x401C00C0 + ((x)*0x4)))
|
||||
|
||||
/* Other macros */
|
||||
#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_PER_ID */
|
||||
#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */
|
||||
#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_REV */
|
||||
#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */
|
||||
#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1)
|
||||
#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1)
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4)
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8)
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20)
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40)
|
||||
#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */
|
||||
#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1)
|
||||
#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4)
|
||||
#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8)
|
||||
#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20)
|
||||
#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40)
|
||||
#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */
|
||||
#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1)
|
||||
#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4)
|
||||
#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8)
|
||||
#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20)
|
||||
#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40)
|
||||
#define MCF_USB_OTG_OTG_STAT_ID (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */
|
||||
#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1)
|
||||
#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2)
|
||||
#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4)
|
||||
#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8)
|
||||
#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10)
|
||||
#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20)
|
||||
#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */
|
||||
#define MCF_USB_OTG_INT_STAT_USB_RST (0x1)
|
||||
#define MCF_USB_OTG_INT_STAT_ERROR (0x2)
|
||||
#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4)
|
||||
#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8)
|
||||
#define MCF_USB_OTG_INT_STAT_SLEEP (0x10)
|
||||
#define MCF_USB_OTG_INT_STAT_RESUME (0x20)
|
||||
#define MCF_USB_OTG_INT_STAT_ATTACH (0x40)
|
||||
#define MCF_USB_OTG_INT_STAT_STALL (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */
|
||||
#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1)
|
||||
#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2)
|
||||
#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4)
|
||||
#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8)
|
||||
#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10)
|
||||
#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20)
|
||||
#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40)
|
||||
#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */
|
||||
#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1)
|
||||
#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2)
|
||||
#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4)
|
||||
#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8)
|
||||
#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10)
|
||||
#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20)
|
||||
#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */
|
||||
#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1)
|
||||
#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2)
|
||||
#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4)
|
||||
#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8)
|
||||
#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10)
|
||||
#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20)
|
||||
#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_STAT */
|
||||
#define MCF_USB_OTG_STAT_ODD (0x4)
|
||||
#define MCF_USB_OTG_STAT_TX (0x8)
|
||||
#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_CTL */
|
||||
#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1)
|
||||
#define MCF_USB_OTG_CTL_ODD_RST (0x2)
|
||||
#define MCF_USB_OTG_CTL_RESUME (0x4)
|
||||
#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8)
|
||||
#define MCF_USB_OTG_CTL_RESET (0x10)
|
||||
#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20)
|
||||
#define MCF_USB_OTG_CTL_SE0 (0x40)
|
||||
#define MCF_USB_OTG_CTL_JSTATE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ADDR */
|
||||
#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0)
|
||||
#define MCF_USB_OTG_ADDR_LS_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40)
|
||||
#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40)
|
||||
#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */
|
||||
#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1)
|
||||
#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2)
|
||||
#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_TOKEN */
|
||||
#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0)
|
||||
#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10)
|
||||
#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90)
|
||||
#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40)
|
||||
#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40)
|
||||
#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40)
|
||||
#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_ENDPT */
|
||||
#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1)
|
||||
#define MCF_USB_OTG_ENDPT_EP_STALL (0x2)
|
||||
#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4)
|
||||
#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8)
|
||||
#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10)
|
||||
#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40)
|
||||
#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */
|
||||
#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0)
|
||||
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1)
|
||||
#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3)
|
||||
#define MCF_USB_OTG_USB_CTRL_PDE (0x40)
|
||||
#define MCF_USB_OTG_USB_CTRL_SUSP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSDIS (0x2)
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSCHG (0x4)
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSE (0x8)
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10)
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40)
|
||||
#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1)
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2)
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4)
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8)
|
||||
#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSD (0x10)
|
||||
|
||||
|
||||
#endif /* __MCF52221_USB_OTG_H__ */
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
# Sample Linker Command File for CodeWarrior for ColdFire
|
||||
|
||||
KEEP_SECTION {.vectortable}
|
||||
|
||||
# Memory ranges
|
||||
|
||||
MEMORY {
|
||||
vectorrom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||
cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000020
|
||||
code (RX) : ORIGIN = 0x00000500, LENGTH = 0x0001FB00
|
||||
userram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00004000
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
|
||||
# Heap and Stack sizes definition
|
||||
___heap_size = 0x4;
|
||||
___stack_size = 0x100;
|
||||
|
||||
|
||||
|
||||
|
||||
# MCF52221 Derivative Memory map definitions from linker command files:
|
||||
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
|
||||
# symbols must be defined in the linker command file.
|
||||
|
||||
# Memory Mapped Registers (IPSBAR= 0x40000000)
|
||||
___IPSBAR = 0x40000000;
|
||||
|
||||
# 16 Kbytes Internal SRAM
|
||||
___RAMBAR = 0x20000000;
|
||||
___RAMBAR_SIZE = 0x00004000;
|
||||
|
||||
# 128 KByte Internal Flash Memory
|
||||
___FLASHBAR = 0x00000000;
|
||||
___FLASHBAR_SIZE = 0x00020000;
|
||||
|
||||
___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;
|
||||
|
||||
.userram : {} > userram
|
||||
.code : {} > code
|
||||
|
||||
.vectors :
|
||||
{
|
||||
exceptions.c(.vectortable)
|
||||
. = ALIGN (0x4);
|
||||
} > vectorrom
|
||||
|
||||
.cfmprotect :
|
||||
{
|
||||
*(.cfmconfig)
|
||||
. = ALIGN (0x4);
|
||||
} > cfmprotrom
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
. = ALIGN (0x4);
|
||||
*(.rodata)
|
||||
. = ALIGN (0x4);
|
||||
___ROM_AT = .;
|
||||
___DATA_ROM = .;
|
||||
} >> code
|
||||
|
||||
.data : AT(___ROM_AT)
|
||||
{
|
||||
___DATA_RAM = .;
|
||||
. = ALIGN(0x4);
|
||||
*(.exception)
|
||||
. = ALIGN(0x4);
|
||||
__exception_table_start__ = .;
|
||||
EXCEPTION
|
||||
__exception_table_end__ = .;
|
||||
|
||||
___sinit__ = .;
|
||||
STATICINIT
|
||||
__START_DATA = .;
|
||||
|
||||
*(.data)
|
||||
. = ALIGN (0x4);
|
||||
__END_DATA = .;
|
||||
|
||||
__START_SDATA = .;
|
||||
*(.sdata)
|
||||
. = ALIGN (0x4);
|
||||
__END_SDATA = .;
|
||||
|
||||
___DATA_END = .;
|
||||
__SDA_BASE = .;
|
||||
. = ALIGN (0x4);
|
||||
} >> userram
|
||||
|
||||
.bss :
|
||||
{
|
||||
___BSS_START = .;
|
||||
__START_SBSS = .;
|
||||
*(.sbss)
|
||||
. = ALIGN (0x4);
|
||||
*(SCOMMON)
|
||||
__END_SBSS = .;
|
||||
|
||||
__START_BSS = .;
|
||||
*(.bss)
|
||||
. = ALIGN (0x4);
|
||||
*(COMMON)
|
||||
__END_BSS = .;
|
||||
___BSS_END = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
} >> userram
|
||||
|
||||
.custom :
|
||||
{
|
||||
___HEAP_START = .;
|
||||
___heap_addr = ___HEAP_START;
|
||||
___HEAP_END = ___HEAP_START + ___heap_size;
|
||||
___SP_END = ___HEAP_END;
|
||||
___SP_INIT = ___SP_END + ___stack_size;
|
||||
|
||||
. = ALIGN (0x4);
|
||||
} >> userram
|
||||
|
||||
# ___VECTOR_RAM = ADDR(.vectorram);
|
||||
|
||||
__SP_INIT = ___SP_INIT;
|
||||
|
||||
_romp_at = ___ROM_AT + SIZEOF(.data);
|
||||
.romp : AT(_romp_at)
|
||||
{
|
||||
__S_romp = _romp_at;
|
||||
WRITEW(___ROM_AT);
|
||||
WRITEW(ADDR(.data));
|
||||
WRITEW(SIZEOF(.data));
|
||||
WRITEW(0);
|
||||
WRITEW(0);
|
||||
WRITEW(0);
|
||||
}
|
||||
|
||||
}
|
||||
160
20091005/Demo/ColdFire_MCF52221_CodeWarrior/readme.txt
Normal file
160
20091005/Demo/ColdFire_MCF52221_CodeWarrior/readme.txt
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
//------------------------------------------------------------------------
|
||||
// Readme.txt
|
||||
//------------------------------------------------------------------------
|
||||
This project is configure to get you up and running quickly using
|
||||
CodeWarrior with the Freescale MCF52221 board.
|
||||
|
||||
This project provides full support for the selected board.
|
||||
The created project provides Standard IO Support through console and terminal window.
|
||||
|
||||
Sample code for the following language:
|
||||
- C
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Memory Maps
|
||||
//------------------------------------------------------------------------
|
||||
The Hardware has the following memory map:
|
||||
|
||||
# MCF52221 Derivative Memory map definitions from linker command files:
|
||||
# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
|
||||
# symbols must be defined in the linker command file.
|
||||
|
||||
# Memory Mapped Registers (IPSBAR= 0x40000000)
|
||||
___IPSBAR = 0x40000000;
|
||||
|
||||
# 16 Kbytes Internal SRAM
|
||||
___RAMBAR = 0x20000000;
|
||||
___RAMBAR_SIZE = 0x00004000;
|
||||
|
||||
# 128 KByte Internal Flash Memory
|
||||
___FLASHBAR = 0x00000000;
|
||||
___FLASHBAR_SIZE = 0x00020000;
|
||||
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Project Structure
|
||||
//------------------------------------------------------------------------
|
||||
The project generated contains various files/groups:
|
||||
- readme.txt: information for this project
|
||||
- Sources: application source codes, user customizable startup
|
||||
code, uart library, exception table
|
||||
- Includes: derivative and board header files, ...
|
||||
- Libs: runtime and libs
|
||||
- Project Settings: linker command files for the different build
|
||||
targets, the initialization and memory configuration files for
|
||||
the hardware debugging, the common startup code, etc...
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Build Targets
|
||||
//------------------------------------------------------------------------
|
||||
- CONSOLE_INTERNAL_RAM:
|
||||
This project target is setup to load and debug code from internal RAM.
|
||||
It should be used during your application development.
|
||||
The application outputs to the CodeWarrior's console window.
|
||||
|
||||
- INTERNAL_RAM:
|
||||
This project target is setup to load and debug code from internal RAM.
|
||||
It should be used during your application development.
|
||||
This is the very basic project that outputs to the UART.
|
||||
You needs to connect a Terminal Program to see the output.
|
||||
|
||||
- INTERNAL_FLASH:
|
||||
This project target is setup to load and debug code in Internal FLASH.
|
||||
This is the very basic project that outputs to the UART. User needs
|
||||
to connect the terminal to see the output.
|
||||
|
||||
|
||||
|
||||
===================================================================
|
||||
WARNING regarding debugging new project wizard code with CCS-SIM
|
||||
===================================================================
|
||||
The CCS-SIM is an instruction set simulator, it does not implement
|
||||
any peripherals.
|
||||
The new project generated by the wizard are using startup code
|
||||
performing some hardware peripheral initializations.
|
||||
When debugging with the CCS-SIM it might happen that the simulation
|
||||
stuck on loop using non implemented peripheral register flag as
|
||||
condition (PLL initialization as example).
|
||||
In this case, you should either:
|
||||
- move the PC to next statement
|
||||
- use a skip point
|
||||
- define a simulator specific macro which used when define allos you
|
||||
to comment out the unwanted code in order to debug with CCS-SIM
|
||||
|
||||
|
||||
===================================================================
|
||||
WARNING regarding code located in RAM
|
||||
===================================================================
|
||||
Many possible ColdFire target processors have an external bus, so
|
||||
you can use large external RAM devices for debugging applications
|
||||
during development. But some processors do not have an external
|
||||
bus, so you must accommodate applications in on-chip memory.
|
||||
Although this on-chip RAM accommodates this CodeWarrior project,
|
||||
it probably is too small for full development of your application.
|
||||
Accordingly, for a processor without external bus, you should locate
|
||||
your applications in flash memory.
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Flashing the code
|
||||
//------------------------------------------------------------------------
|
||||
1. Select the appropriate project target and build it
|
||||
2. Make sure the correct remote connection is selected in the Remote
|
||||
Connection debugger panel
|
||||
3. In the CodeWarrior IDE menu, select Project > Set Default Project
|
||||
and select your project
|
||||
4. In the CodeWarrior IDE menu, select Project > Set Default Target
|
||||
and select the project target that has the code you want to flash
|
||||
5. In the CodeWarrior IDE menu, select Tools > Flash Programmer
|
||||
6. Go to the flash programmer Target Configuration panel, click Load
|
||||
Settings
|
||||
7. Browse to the <your project location>\cfg sub folder and
|
||||
select the flash settings xml file matching your build target
|
||||
8. Check that Use Custom Settings checkbox is not selected
|
||||
9. Go to the Erase/Blank Check panel, select the All Sectors option and
|
||||
click Erase
|
||||
10. Go to Program/Verify panel, click Program
|
||||
11. Your code should now be flashed
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Terminal Settings
|
||||
//------------------------------------------------------------------------
|
||||
In case the UART is supported, the terminal should be setup with:
|
||||
- 19200 bauds,
|
||||
- 8 data bits,
|
||||
- no parity,
|
||||
- 1 stop bit,
|
||||
- no flow control.
|
||||
|
||||
Please check this file in the project.
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Getting Started
|
||||
//------------------------------------------------------------------------
|
||||
To build/debug your project, use the CodeWarrior IDE menu Project > Debug
|
||||
or press F5. This will launch the debugger. Press again F5 in the
|
||||
debugger (or the CodeWarrior IDE menu Project > Run) to start the
|
||||
application. The CodeWarrior IDE menu Project > Break stops the
|
||||
application.
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Adding your own code
|
||||
//------------------------------------------------------------------------
|
||||
Once everything is working as expected, you can begin adding your own code
|
||||
to the project. Keep in mind that we provide this as an example of how to
|
||||
get up and running quickly with CodeWarrior. There are certainly other
|
||||
ways to handle interrupts and set up your linker command file. Feel free
|
||||
to modify any of the source files provided.
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Additional documentation
|
||||
//------------------------------------------------------------------------
|
||||
Read the online documentation provided. In CodeWarrior IDE menu, select
|
||||
Help > CodeWarrior Help.
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Contacting Freescale
|
||||
//------------------------------------------------------------------------
|
||||
For bug reports, technical questions, and suggestions, please use the
|
||||
forms installed in the Release_Notes folder.
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation and modified by the FreeRTOS exception.
|
||||
**NOTE** The exception to the GPL is included to allow you to distribute a
|
||||
combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
Alternative commercial license and support terms are also available upon
|
||||
request. See the licensing section of http://www.FreeRTOS.org for full
|
||||
license details.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
|
||||
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Looking for a quick start? Then check out the FreeRTOS eBook! *
|
||||
* See http://www.FreeRTOS.org/Documentation for details *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/* CodeWarrior often thinks it knows better than you which files you want to
|
||||
build - and changes the port.c and portasm.S files included in the project from
|
||||
the ColdFire V1 versions to the x86 versions. If you get lots of errors output
|
||||
when either file is compiled then delete the files from the project and then
|
||||
add back in the port.c and portasm.S files that are located in the
|
||||
FreeRTOS\Source\portable\GCC\ColdFire_V2 directory. Remove the line below
|
||||
before compiling. */
|
||||
|
||||
#error Read the comment above this line, then delete this error statement!
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#include "support_common.h"
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 )
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 100 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15000 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 12 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 0
|
||||
#define configUSE_CO_ROUTINES 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 0
|
||||
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1
|
||||
|
||||
#define configYIELD_INTERRUPT_VECTOR 16UL
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 1
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
|
||||
|
||||
void vApplicationSetupInterrupts( void );
|
||||
|
||||
/* Ethernet configuration. */
|
||||
#define configMAC_0 0x00
|
||||
#define configMAC_1 0x04
|
||||
#define configMAC_2 0x9F
|
||||
#define configMAC_3 0x00
|
||||
#define configMAC_4 0xAB
|
||||
#define configMAC_5 0x2B
|
||||
|
||||
#define configIP_ADDR0 192
|
||||
#define configIP_ADDR1 168
|
||||
#define configIP_ADDR2 0
|
||||
#define configIP_ADDR3 11
|
||||
|
||||
#define configGW_ADDR0 172
|
||||
#define configGW_ADDR1 25
|
||||
#define configGW_ADDR2 218
|
||||
#define configGW_ADDR3 3
|
||||
|
||||
#define configNET_MASK0 255
|
||||
#define configNET_MASK1 255
|
||||
#define configNET_MASK2 255
|
||||
#define configNET_MASK3 0
|
||||
|
||||
#define configNUM_FEC_TX_BUFFERS 2
|
||||
#define configNUM_FEC_RX_BUFFERS 4
|
||||
#define configFEC_BUFFER_SIZE 1520
|
||||
#define configUSE_PROMISCUOUS_MODE 0
|
||||
#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )
|
||||
#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
|
||||
|
||||
#define configPHY_ADDRESS 1
|
||||
|
||||
#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0
|
||||
#error configFEC_BUFFER_SIZE must be a multiple of 16.
|
||||
#endif
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation and modified by the FreeRTOS exception.
|
||||
**NOTE** The exception to the GPL is included to allow you to distribute a
|
||||
combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
Alternative commercial license and support terms are also available upon
|
||||
request. See the licensing section of http://www.FreeRTOS.org for full
|
||||
license details.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
|
||||
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Looking for a quick start? Then check out the FreeRTOS eBook! *
|
||||
* See http://www.FreeRTOS.org/Documentation for details *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
__declspec(interrupt:0) void vPIT0InterruptHandler( void );
|
||||
|
||||
/* Constants used to configure the interrupts. */
|
||||
#define portPRESCALE_VALUE 64
|
||||
#define portPRESCALE_REG_SETTING ( 5 << 8 )
|
||||
#define portPIT_INTERRUPT_ENABLED ( 0x08 )
|
||||
#define configPIT0_INTERRUPT_VECTOR ( 55 )
|
||||
|
||||
/*
|
||||
* FreeRTOS.org requires two interrupts - a tick interrupt generated from a
|
||||
* timer source, and a spare interrupt vector used for context switching.
|
||||
* The configuration below uses PIT0 for the former, and vector 16 for the
|
||||
* latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO
|
||||
* NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided
|
||||
* here for using alternative interrupt sources.
|
||||
*
|
||||
* To change the tick interrupt source:
|
||||
*
|
||||
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
|
||||
* peripheral is to be used to generate the tick interrupt.
|
||||
*
|
||||
* 2) Change the name of the function __cs3_isr_interrupt_119() defined within
|
||||
* this file to be correct for the interrupt vector used by the timer peripheral.
|
||||
* The name of the function should contain the vector number, so by default vector
|
||||
* number 119 is being used.
|
||||
*
|
||||
* 3) Make sure the tick interrupt is cleared within the interrupt handler function.
|
||||
* Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt.
|
||||
*
|
||||
* To change the spare interrupt source:
|
||||
*
|
||||
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
|
||||
* interrupt vector is to be used. Make sure you use a spare interrupt on interrupt
|
||||
* controller 0, otherwise the register used to request context switches will also
|
||||
* require modification.
|
||||
*
|
||||
* 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h
|
||||
* to be correct for your chosen interrupt vector.
|
||||
*
|
||||
* 3) Change the name of the function __cs3_isr_interrupt_127() within portasm.S
|
||||
* to be correct for whichever vector number is being used. By default interrupt
|
||||
* controller 0 number 16 is used, which corresponds to vector number 127.
|
||||
*/
|
||||
void vApplicationSetupInterrupts( void )
|
||||
{
|
||||
const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );
|
||||
|
||||
/* Configure interrupt priority and level and unmask interrupt for PIT0. */
|
||||
MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );
|
||||
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );
|
||||
|
||||
/* Do the same for vector 63 (interrupt controller 0. I don't think the
|
||||
write to MCF_INTC0_IMRH is actually required here but is included for
|
||||
completeness. */
|
||||
MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 );
|
||||
MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 );
|
||||
|
||||
/* Configure PIT0 to generate the RTOS tick. */
|
||||
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
|
||||
MCF_PIT0_PMR = usCompareMatchValue;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__declspec(interrupt:0) void vPIT0InterruptHandler( void )
|
||||
{
|
||||
unsigned portLONG ulSavedInterruptMask;
|
||||
|
||||
/* Clear the PIT0 interrupt. */
|
||||
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
|
||||
/* Increment the RTOS tick. */
|
||||
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
vTaskIncrementTick();
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
|
||||
|
||||
/* If we are using the pre-emptive scheduler then also request a
|
||||
context switch as incrementing the tick could have unblocked a task. */
|
||||
#if configUSE_PREEMPTION == 1
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* File: mcf52221_sysinit.c
|
||||
* Purpose: Power-on Reset configuration of the MCF52221.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
#include "support_common.h"
|
||||
#include "exceptions.h"
|
||||
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
static void pll_init(void)
|
||||
{
|
||||
|
||||
MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 48MHz / 6 = 8MHz
|
||||
|
||||
/* The PLL pre-divider affects this!!!
|
||||
* Multiply 8Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
|
||||
*/
|
||||
|
||||
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
|
||||
|
||||
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
|
||||
{
|
||||
}
|
||||
}
|
||||
/********************************************************************/
|
||||
static void scm_init(void)
|
||||
{
|
||||
/*
|
||||
* Enable on-chip modules to access internal SRAM
|
||||
*/
|
||||
MCF_SCM_RAMBAR = (0
|
||||
| MCF_SCM_RAMBAR_BA(RAMBAR_ADDRESS)
|
||||
| MCF_SCM_RAMBAR_BDE);
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/*
|
||||
* Out of reset, the low-level assembly code calls this routine to
|
||||
* initialize the mcf5206e for this board. A temporary stack has been
|
||||
* setup in the internal SRAM, and the stack pointer will be changed
|
||||
* to point to DRAM once this routine returns.
|
||||
*/
|
||||
void __initialize_hardware(void)
|
||||
{
|
||||
/*******************************************************
|
||||
* Out of reset, the low-level assembly code calls this
|
||||
* routine to initialize the MCF52221 modules for the
|
||||
* M522223EVB board.
|
||||
********************************************************/
|
||||
|
||||
|
||||
asm
|
||||
{
|
||||
/* Initialize IPSBAR */
|
||||
move.l #__IPSBAR,d0
|
||||
andi.l #0xC0000000,d0 // need to mask
|
||||
add.l #0x1,d0
|
||||
move.l d0,0x40000000
|
||||
|
||||
|
||||
|
||||
/* Initialize FLASHBAR */
|
||||
move.l #__FLASHBAR,d0
|
||||
andi.l #0xFFF80000,d0 // need to mask
|
||||
add.l #0x61,d0
|
||||
movec d0,FLASHBAR
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* Set real time clock freq */
|
||||
MCF_CLOCK_RTCDR = 48000000;
|
||||
|
||||
pll_init();
|
||||
scm_init();
|
||||
|
||||
initialize_exceptions();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* File: mcf52221demo_sysinit.h
|
||||
* Purpose: Power-on Reset configuration of the MCF52221.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221DEMO_SYSINIT_H__
|
||||
#define __MCF52221DEMO_SYSINIT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if ENABLE_UART_SUPPORT==1
|
||||
|
||||
#define TERMINAL_PORT 0
|
||||
#define TERMINAL_BAUD kBaud19200
|
||||
|
||||
#endif /* ENABLE_UART_SUPPORT==1 */
|
||||
|
||||
#define SYSTEM_CLOCK_KHZ 80000 /* system bus frequency in kHz */
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
/* __initialize_hardware Startup code routine
|
||||
*
|
||||
* __initialize_hardware is called by the startup code right after reset,
|
||||
* with interrupt disabled and SP pre-set to a valid memory area.
|
||||
* Here you should initialize memory and some peripherics;
|
||||
* at this point global variables are not initialized yet.
|
||||
* The startup code will initialize SP on return of this function.
|
||||
*/
|
||||
void __initialize_hardware(void);
|
||||
|
||||
/********************************************************************/
|
||||
/* __initialize_system Startup code routine
|
||||
*
|
||||
* __initialize_system is called by the startup code when all languages
|
||||
* specific initialization are done to allow additional hardware setup.
|
||||
*/
|
||||
void __initialize_system(void);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MCF52221DEMO_SYSINIT_H__ */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation and modified by the FreeRTOS exception.
|
||||
**NOTE** The exception to the GPL is included to allow you to distribute a
|
||||
combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
Alternative commercial license and support terms are also available upon
|
||||
request. See the licensing section of http://www.FreeRTOS.org for full
|
||||
license details.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
|
||||
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Looking for a quick start? Then check out the FreeRTOS eBook! *
|
||||
* See http://www.FreeRTOS.org/Documentation for details *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
/*
|
||||
Changes from V2.5.2
|
||||
|
||||
+ All LED's are turned off to start.
|
||||
*/
|
||||
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "partest.h"
|
||||
|
||||
#define partstNUM_LEDs 4
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Simple parallel port IO routines.
|
||||
*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
/* Enable signals as GPIO */
|
||||
MCF_GPIO_PTCPAR = 0
|
||||
| MCF_GPIO_PTCPAR_DTIN3_GPIO
|
||||
| MCF_GPIO_PTCPAR_DTIN2_GPIO
|
||||
| MCF_GPIO_PTCPAR_DTIN1_GPIO
|
||||
| MCF_GPIO_PTCPAR_DTIN0_GPIO;
|
||||
|
||||
/* Enable signals as digital outputs */
|
||||
MCF_GPIO_DDRTC = 0
|
||||
| MCF_GPIO_DDRTC_DDRTC3
|
||||
| MCF_GPIO_DDRTC_DDRTC2
|
||||
| MCF_GPIO_DDRTC_DDRTC1
|
||||
| MCF_GPIO_DDRTC_DDRTC0;
|
||||
|
||||
MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDMask;
|
||||
|
||||
if( uxLED < partstNUM_LEDs )
|
||||
{
|
||||
uxLEDMask = 1UL << uxLED;
|
||||
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
if( xValue )
|
||||
{
|
||||
MCF_GPIO_PORTTC |= uxLEDMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
MCF_GPIO_PORTTC &= ~uxLEDMask;
|
||||
}
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDMask;
|
||||
|
||||
if( uxLED < partstNUM_LEDs )
|
||||
{
|
||||
uxLEDMask = 1UL << uxLED;
|
||||
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
if( MCF_GPIO_PORTTC & uxLEDMask )
|
||||
{
|
||||
MCF_GPIO_PORTTC &= ~uxLEDMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
MCF_GPIO_PORTTC |= uxLEDMask;
|
||||
}
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
|
||||
21
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c
Normal file
21
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/cfm.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
|
||||
/* CFM init */
|
||||
|
||||
#define KEY_UPPER 0
|
||||
#define KEY_LOWER 0
|
||||
#define CFMPROT 0
|
||||
#define CFMSACC 0
|
||||
#define CFMDACC 0
|
||||
#define CFMSEC 0
|
||||
|
||||
#pragma define_section cfmconfig ".cfmconfig" far_absolute R
|
||||
#pragma explicit_zero_data on
|
||||
|
||||
__declspec(cfmconfig) unsigned long _cfm[6] = {
|
||||
KEY_UPPER, /* 0x00000400 */
|
||||
KEY_LOWER, /* 0x00000404 */
|
||||
CFMPROT, /* 0x00000408 */
|
||||
CFMSACC, /* 0x0000040C */
|
||||
CFMDACC, /* 0x00000410 */
|
||||
CFMSEC, /* 0x00000414 */
|
||||
};
|
||||
633
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c
Normal file
633
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/exceptions.c
Normal file
|
|
@ -0,0 +1,633 @@
|
|||
/*
|
||||
* File: exceptions.c
|
||||
* Purpose: Generic exception handling for ColdFire processors
|
||||
*
|
||||
*/
|
||||
#include "exceptions.h"
|
||||
#include "startcf.h"
|
||||
#include "support_common.h"
|
||||
#include <ansi_parms.h>
|
||||
|
||||
#define REGISTER_ABI __REGABI__
|
||||
|
||||
|
||||
extern void vPIT0InterruptHandler( void );
|
||||
extern void vUART0InterruptHandler( void );
|
||||
extern void vPortYieldISR( void );
|
||||
extern void vFECISRHandler( void );
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Set NO_PRINTF to 0 in order the exceptions.c interrupt handler
|
||||
* to output messages to the standard io.
|
||||
*
|
||||
*/
|
||||
#define NO_PRINTF 1
|
||||
|
||||
#if NO_PRINTF
|
||||
#define VECTORDISPLAY(MESSAGE) asm { nop; };
|
||||
#define VECTORDISPLAY2(MESSAGE,MESSAGE2) asm { nop; };
|
||||
#define VECTORDISPLAY3(MESSAGE,MESSAGE2,MESSAGE3) asm { nop; };
|
||||
#else
|
||||
#include <stdio.h>
|
||||
#define VECTORDISPLAY(MESSAGE1) printf(MESSAGE1);
|
||||
#define VECTORDISPLAY2(MESSAGE1,MESSAGE2) printf(MESSAGE1,MESSAGE2);
|
||||
#define VECTORDISPLAY3(MESSAGE1,MESSAGE2,MESSAGE3) printf(MESSAGE1,MESSAGE2,MESSAGE3);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern unsigned long far _SP_INIT[];
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Handling of the TRK ColdFire libs (printf support in Debugger Terminal)
|
||||
*
|
||||
* To enable this support (setup by default in CONSOLE_RAM build target
|
||||
* if available):
|
||||
* - Set CONSOLE_IO_SUPPORT to 1 in this file; this will enable
|
||||
* TrapHandler_printf for the trap #14 exception.
|
||||
* (this is set by default to 1 in the ColdFire Pre-Processor panel for
|
||||
* the CONSOLE_RAM build target)
|
||||
*
|
||||
* - Make sure the file:
|
||||
* {Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Src\console_io_cf.c
|
||||
* is referenced from your project.
|
||||
*
|
||||
* - Make sure that in the CF Exceptions panel the check box
|
||||
* "46 TRAP #14 for Console I/O", in the "User Application Exceptions"
|
||||
* area is set.
|
||||
*
|
||||
*/
|
||||
#ifndef CONSOLE_IO_SUPPORT
|
||||
#define CONSOLE_IO_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if CONSOLE_IO_SUPPORT
|
||||
asm void TrapHandler_printf(void) {
|
||||
HALT
|
||||
RTE
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* This is the handler for all exceptions which are not common to all
|
||||
* ColdFire Chips.
|
||||
*
|
||||
* Called by mcf_exception_handler
|
||||
*
|
||||
*/
|
||||
void derivative_interrupt(unsigned long vector)
|
||||
{
|
||||
if (vector < 64 || vector > 192) {
|
||||
VECTORDISPLAY2("User Defined Vector #%d\n",vector);
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* This is the exception handler for all exceptions common to all
|
||||
* chips ColdFire. Most exceptions do nothing, but some of the more
|
||||
* important ones are handled to some extent.
|
||||
*
|
||||
* Called by asm_exception_handler
|
||||
*
|
||||
* The ColdFire family of processors has a simplified exception stack
|
||||
* frame that looks like the following:
|
||||
*
|
||||
* 3322222222221111 111111
|
||||
* 1098765432109876 5432109876543210
|
||||
* 8 +----------------+----------------+
|
||||
* | Program Counter |
|
||||
* 4 +----------------+----------------+
|
||||
* |FS/Fmt/Vector/FS| SR |
|
||||
* SP --> 0 +----------------+----------------+
|
||||
*
|
||||
* The stack self-aligns to a 4-byte boundary at an exception, with
|
||||
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
|
||||
* (SP += 0,1,2,3 bytes).
|
||||
* 31 28 27 26 25 18 17 16 15 0
|
||||
* 4 +---------------------------------------+------------------------------------+
|
||||
* | Format | FS[3..2] | Vector | FS[1..0] | SR |
|
||||
* SP --> 0 +---------------------------------------+------------------------------------+
|
||||
*/
|
||||
#define MCF5XXX_RD_SF_FORMAT(PTR) \
|
||||
((*((unsigned short *)(PTR)) >> 12) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_VECTOR(PTR) \
|
||||
((*((unsigned short *)(PTR)) >> 2) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_FS(PTR) \
|
||||
( ((*((unsigned short *)(PTR)) & 0x0C00) >> 8) | (*((unsigned short *)(PTR)) & 0x0003) )
|
||||
|
||||
#define MCF5XXX_SF_SR(PTR) *(((unsigned short *)(PTR))+1)
|
||||
|
||||
#define MCF5XXX_SF_PC(PTR) *((unsigned long *)(PTR)+1)
|
||||
|
||||
#define MCF5XXX_EXCEPTFMT "%s -- PC = %#08X\n"
|
||||
|
||||
|
||||
void mcf_exception_handler(void *framepointer)
|
||||
{
|
||||
volatile unsigned long exceptionStackFrame = (*(unsigned long *)(framepointer));
|
||||
volatile unsigned short stackFrameSR = MCF5XXX_SF_SR(framepointer);
|
||||
volatile unsigned short stackFrameWord = (*(unsigned short *)(framepointer));
|
||||
volatile unsigned long stackFrameFormat = (unsigned long)MCF5XXX_RD_SF_FORMAT(&stackFrameWord);
|
||||
volatile unsigned long stackFrameFS = (unsigned long)MCF5XXX_RD_SF_FS(&stackFrameWord);
|
||||
volatile unsigned long stackFrameVector = (unsigned long)MCF5XXX_RD_SF_VECTOR(&stackFrameWord);
|
||||
volatile unsigned long stackFramePC = MCF5XXX_SF_PC(framepointer);
|
||||
|
||||
switch (stackFrameFormat)
|
||||
{
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
break;
|
||||
default:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT,"Illegal stack type", stackFramePC);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (stackFrameVector)
|
||||
{
|
||||
case 2:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Access Error", stackFramePC);
|
||||
switch (stackFrameFS)
|
||||
{
|
||||
case 4:
|
||||
VECTORDISPLAY("Error on instruction fetch\n");
|
||||
break;
|
||||
case 8:
|
||||
VECTORDISPLAY("Error on operand write\n");
|
||||
break;
|
||||
case 9:
|
||||
VECTORDISPLAY("Attempted write to write-protected space\n");
|
||||
break;
|
||||
case 12:
|
||||
VECTORDISPLAY("Error on operand read\n");
|
||||
break;
|
||||
default:
|
||||
VECTORDISPLAY("Reserved Fault Status Encoding\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Address Error", stackFramePC);
|
||||
switch (stackFrameFS)
|
||||
{
|
||||
case 4:
|
||||
VECTORDISPLAY("Error on instruction fetch\n");
|
||||
break;
|
||||
case 8:
|
||||
VECTORDISPLAY("Error on operand write\n");
|
||||
break;
|
||||
case 9:
|
||||
VECTORDISPLAY("Attempted write to write-protected space\n");
|
||||
break;
|
||||
case 12:
|
||||
VECTORDISPLAY("Error on operand read\n");
|
||||
break;
|
||||
default:
|
||||
VECTORDISPLAY("Reserved Fault Status Encoding\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Illegal instruction", stackFramePC);
|
||||
break;
|
||||
case 8:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Privilege violation", stackFramePC);
|
||||
break;
|
||||
case 9:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Trace Exception", stackFramePC);
|
||||
break;
|
||||
case 10:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented A-Line Instruction", stackFramePC);
|
||||
break;
|
||||
case 11:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented F-Line Instruction", stackFramePC);
|
||||
break;
|
||||
case 12:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Debug Interrupt", stackFramePC);
|
||||
break;
|
||||
case 14:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Format Error", stackFramePC);
|
||||
break;
|
||||
case 15:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unitialized Interrupt", stackFramePC);
|
||||
break;
|
||||
case 24:
|
||||
VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Spurious Interrupt", stackFramePC);
|
||||
break;
|
||||
case 25:
|
||||
case 26:
|
||||
case 27:
|
||||
case 28:
|
||||
case 29:
|
||||
case 30:
|
||||
case 31:
|
||||
VECTORDISPLAY2("Autovector interrupt level %d\n", stackFrameVector - 24);
|
||||
break;
|
||||
case 32:
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 36:
|
||||
case 37:
|
||||
case 38:
|
||||
case 39:
|
||||
case 40:
|
||||
case 41:
|
||||
case 42:
|
||||
case 43:
|
||||
case 44:
|
||||
case 45:
|
||||
case 46:
|
||||
case 47:
|
||||
VECTORDISPLAY2("TRAP #%d\n", stackFrameVector - 32);
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
case 13:
|
||||
case 16:
|
||||
case 17:
|
||||
case 18:
|
||||
case 19:
|
||||
case 20:
|
||||
case 21:
|
||||
case 22:
|
||||
case 23:
|
||||
case 48:
|
||||
case 49:
|
||||
case 50:
|
||||
case 51:
|
||||
case 52:
|
||||
case 53:
|
||||
case 54:
|
||||
case 55:
|
||||
case 56:
|
||||
case 57:
|
||||
case 58:
|
||||
case 59:
|
||||
case 60:
|
||||
case 61:
|
||||
case 62:
|
||||
case 63:
|
||||
VECTORDISPLAY2("Reserved: #%d\n", stackFrameVector);
|
||||
break;
|
||||
default:
|
||||
derivative_interrupt(stackFrameVector);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if REGISTER_ABI
|
||||
asm void asm_exception_handler(void)
|
||||
{
|
||||
link a6,#0
|
||||
lea -20(sp), sp
|
||||
movem.l d0-d2/a0-a1, (sp)
|
||||
lea 24(sp),a0 /* A0 point to exception stack frame on the stack */
|
||||
jsr mcf_exception_handler
|
||||
movem.l (sp), d0-d2/a0-a1
|
||||
lea 20(sp), sp
|
||||
unlk a6
|
||||
rte
|
||||
}
|
||||
#else
|
||||
asm void asm_exception_handler(void)
|
||||
{
|
||||
link a6,#0
|
||||
lea -20(sp), sp
|
||||
movem.l d0-d2/a0-a1, (sp)
|
||||
pea 24(sp) /* push exception frame address */
|
||||
jsr mcf_exception_handler
|
||||
movem.l 4(sp), d0-d2/a0-a1
|
||||
lea 24(sp), sp
|
||||
unlk a6
|
||||
rte
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef void (* vectorTableEntryType)(void);
|
||||
|
||||
#pragma define_section vectortable ".vectortable" far_absolute R
|
||||
|
||||
/* CF have 255 vector + SP_INIT in the vector table (256 entries)
|
||||
*/
|
||||
__declspec(vectortable) vectorTableEntryType _vect[256] = { /* Interrupt vector table */
|
||||
(vectorTableEntryType)__SP_AFTER_RESET, /* 0 (0x000) Initial supervisor SP */
|
||||
_startup, /* 1 (0x004) Initial PC */
|
||||
asm_exception_handler, /* 2 (0x008) Access Error */
|
||||
asm_exception_handler, /* 3 (0x00C) Address Error */
|
||||
asm_exception_handler, /* 4 (0x010) Illegal Instruction */
|
||||
asm_exception_handler, /* 5 (0x014) Reserved */
|
||||
asm_exception_handler, /* 6 (0x018) Reserved */
|
||||
asm_exception_handler, /* 7 (0x01C) Reserved */
|
||||
asm_exception_handler, /* 8 (0x020) Privilege Violation */
|
||||
asm_exception_handler, /* 9 (0x024) Trace */
|
||||
asm_exception_handler, /* 10 (0x028) Unimplemented A-Line */
|
||||
asm_exception_handler, /* 11 (0x02C) Unimplemented F-Line */
|
||||
asm_exception_handler, /* 12 (0x030) Debug Interrupt */
|
||||
asm_exception_handler, /* 13 (0x034) Reserved */
|
||||
asm_exception_handler, /* 14 (0x038) Format Error */
|
||||
asm_exception_handler, /* 15 (0x03C) Unitialized Int */
|
||||
asm_exception_handler, /* 16 (0x040) Reserved */
|
||||
asm_exception_handler, /* 17 (0x044) Reserved */
|
||||
asm_exception_handler, /* 18 (0x048) Reserved */
|
||||
asm_exception_handler, /* 19 (0x04C) Reserved */
|
||||
asm_exception_handler, /* 20 (0x050) Reserved */
|
||||
asm_exception_handler, /* 21 (0x054) Reserved */
|
||||
asm_exception_handler, /* 22 (0x058) Reserved */
|
||||
asm_exception_handler, /* 23 (0x05C) Reserved */
|
||||
asm_exception_handler, /* 24 (0x060) Spurious Interrupt */
|
||||
asm_exception_handler, /* 25 (0x064) Autovector Level 1 */
|
||||
asm_exception_handler, /* 26 (0x068) Autovector Level 2 */
|
||||
asm_exception_handler, /* 27 (0x06C) Autovector Level 3 */
|
||||
asm_exception_handler, /* 28 (0x070) Autovector Level 4 */
|
||||
asm_exception_handler, /* 29 (0x074) Autovector Level 5 */
|
||||
asm_exception_handler, /* 30 (0x078) Autovector Level 6 */
|
||||
asm_exception_handler, /* 31 (0x07C) Autovector Level 7 */
|
||||
asm_exception_handler, /* 32 (0x080) TRAP #0 */
|
||||
asm_exception_handler, /* 33 (0x084) TRAP #1 */
|
||||
asm_exception_handler, /* 34 (0x088) TRAP #2 */
|
||||
asm_exception_handler, /* 35 (0x08C) TRAP #3 */
|
||||
asm_exception_handler, /* 36 (0x090) TRAP #4 */
|
||||
asm_exception_handler, /* 37 (0x094) TRAP #5 */
|
||||
asm_exception_handler, /* 38 (0x098) TRAP #6 */
|
||||
asm_exception_handler, /* 39 (0x09C) TRAP #7 */
|
||||
asm_exception_handler, /* 40 (0x0A0) TRAP #8 */
|
||||
asm_exception_handler, /* 41 (0x0A4) TRAP #9 */
|
||||
asm_exception_handler, /* 42 (0x0A8) TRAP #10 */
|
||||
asm_exception_handler, /* 43 (0x0AC) TRAP #11 */
|
||||
asm_exception_handler, /* 44 (0x0B0) TRAP #12 */
|
||||
asm_exception_handler, /* 45 (0x0B4) TRAP #13 */
|
||||
#if CONSOLE_IO_SUPPORT
|
||||
TrapHandler_printf, /* 46 (0x0B8) TRAP #14 */
|
||||
#else
|
||||
asm_exception_handler, /* 46 (0x0B8) TRAP #14 */
|
||||
#endif
|
||||
asm_exception_handler, /* 47 (0x0BC) TRAP #15 */
|
||||
asm_exception_handler, /* 48 (0x0C0) Reserved */
|
||||
asm_exception_handler, /* 49 (0x0C4) Reserved */
|
||||
asm_exception_handler, /* 50 (0x0C8) Reserved */
|
||||
asm_exception_handler, /* 51 (0x0CC) Reserved */
|
||||
asm_exception_handler, /* 52 (0x0D0) Reserved */
|
||||
asm_exception_handler, /* 53 (0x0D4) Reserved */
|
||||
asm_exception_handler, /* 54 (0x0D8) Reserved */
|
||||
asm_exception_handler, /* 55 (0x0DC) Reserved */
|
||||
asm_exception_handler, /* 56 (0x0E0) Reserved */
|
||||
asm_exception_handler, /* 57 (0x0E4) Reserved */
|
||||
asm_exception_handler, /* 58 (0x0E8) Reserved */
|
||||
asm_exception_handler, /* 59 (0x0EC) Reserved */
|
||||
asm_exception_handler, /* 60 (0x0F0) Reserved */
|
||||
asm_exception_handler, /* 61 (0x0F4) Reserved */
|
||||
asm_exception_handler, /* 62 (0x0F8) Reserved */
|
||||
asm_exception_handler, /* 63 (0x0FC) Reserved */
|
||||
asm_exception_handler, /* 64 (0x100) Device-specific interrupts */
|
||||
asm_exception_handler, /* 65 (0x104) Device-specific interrupts */
|
||||
asm_exception_handler, /* 66 (0x108) Device-specific interrupts */
|
||||
asm_exception_handler, /* 67 (0x10C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 68 (0x110) Device-specific interrupts */
|
||||
asm_exception_handler, /* 69 (0x114) Device-specific interrupts */
|
||||
asm_exception_handler, /* 70 (0x118) Device-specific interrupts */
|
||||
asm_exception_handler, /* 71 (0x11C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 72 (0x120) Device-specific interrupts */
|
||||
asm_exception_handler, /* 73 (0x124) Device-specific interrupts */
|
||||
asm_exception_handler, /* 74 (0x128) Device-specific interrupts */
|
||||
asm_exception_handler, /* 75 (0x12C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 76 (0x130) Device-specific interrupts */
|
||||
vUART0InterruptHandler, /* 77 (0x134) Device-specific interrupts */
|
||||
asm_exception_handler, /* 78 (0x138) Device-specific interrupts */
|
||||
asm_exception_handler, /* 79 (0x13C) Device-specific interrupts */
|
||||
vPortYieldISR, /* 80 (0x140) Device-specific interrupts */
|
||||
asm_exception_handler, /* 81 (0x144) Device-specific interrupts */
|
||||
asm_exception_handler, /* 82 (0x148) Device-specific interrupts */
|
||||
asm_exception_handler, /* 83 (0x14C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 84 (0x150) Device-specific interrupts */
|
||||
asm_exception_handler, /* 85 (0x154) Device-specific interrupts */
|
||||
asm_exception_handler, /* 86 (0x158) Device-specific interrupts */
|
||||
asm_exception_handler, /* 87 (0x15C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 88 (0x160) Device-specific interrupts */
|
||||
asm_exception_handler, /* 89 (0x164) Device-specific interrupts */
|
||||
asm_exception_handler, /* 90 (0x168) Device-specific interrupts */
|
||||
asm_exception_handler, /* 91 (0x16C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 92 (0x170) Device-specific interrupts */
|
||||
asm_exception_handler, /* 93 (0x174) Device-specific interrupts */
|
||||
asm_exception_handler, /* 94 (0x178) Device-specific interrupts */
|
||||
asm_exception_handler, /* 95 (0x17C) Device-specific interrupts */
|
||||
asm_exception_handler, /* 96 (0x180) Level 1 software interrupt */
|
||||
asm_exception_handler, /* 97 (0x184) Level 2 software interrupt */
|
||||
asm_exception_handler, /* 98 (0x188) Level 3 software interrupt */
|
||||
asm_exception_handler, /* 99 (0x18C) Level 4 software interrupt */
|
||||
asm_exception_handler, /* 100 (0x190) Level 5 software interrupt */
|
||||
asm_exception_handler, /* 101 (0x194) Level 6 software interrupt */
|
||||
asm_exception_handler, /* 102 (0x198) Level 7 software interrupt */
|
||||
asm_exception_handler, /* 103 (0x19C) Reserved */
|
||||
asm_exception_handler, /* 104 (0x1A0) Reserved */
|
||||
asm_exception_handler, /* 105 (0x1A4) Reserved */
|
||||
asm_exception_handler, /* 106 (0x1A8) Reserved */
|
||||
asm_exception_handler, /* 107 (0x___) Reserved */
|
||||
asm_exception_handler, /* 108 (0x___) Reserved */
|
||||
asm_exception_handler, /* 109 (0x___) Reserved */
|
||||
asm_exception_handler, /* 110 (0x___) Reserved */
|
||||
asm_exception_handler, /* 111 (0x___) Reserved */
|
||||
asm_exception_handler, /* 112 (0x___) Reserved */
|
||||
asm_exception_handler, /* 113 (0x___) Reserved */
|
||||
asm_exception_handler, /* 114 (0x___) Reserved */
|
||||
asm_exception_handler, /* 115 (0x___) Reserved */
|
||||
asm_exception_handler, /* 116 (0x___) Reserved */
|
||||
asm_exception_handler, /* 117 (0x___) Reserved */
|
||||
asm_exception_handler, /* 118 (0x___) Reserved */
|
||||
vPIT0InterruptHandler, /* 119 (0x___) Reserved */
|
||||
asm_exception_handler, /* 120 (0x___) Reserved */
|
||||
asm_exception_handler, /* 121 (0x___) Reserved */
|
||||
asm_exception_handler, /* 122 (0x___) Reserved */
|
||||
asm_exception_handler, /* 123 (0x___) Reserved */
|
||||
asm_exception_handler, /* 124 (0x___) Reserved */
|
||||
asm_exception_handler, /* 125 (0x___) Reserved */
|
||||
asm_exception_handler, /* 126 (0x___) Reserved */
|
||||
asm_exception_handler, /* 127 (0x___) Reserved */
|
||||
asm_exception_handler, /* 128 (0x___) Reserved */
|
||||
asm_exception_handler, /* 129 (0x___) Reserved */
|
||||
asm_exception_handler, /* 130 (0x___) Reserved */
|
||||
asm_exception_handler, /* 131 (0x___) Reserved */
|
||||
asm_exception_handler, /* 132 (0x___) Reserved */
|
||||
asm_exception_handler, /* 133 (0x___) Reserved */
|
||||
asm_exception_handler, /* 134 (0x___) Reserved */
|
||||
asm_exception_handler, /* 135 (0x___) Reserved */
|
||||
asm_exception_handler, /* 136 (0x___) Reserved */
|
||||
asm_exception_handler, /* 137 (0x___) Reserved */
|
||||
asm_exception_handler, /* 138 (0x___) Reserved */
|
||||
asm_exception_handler, /* 139 (0x___) Reserved */
|
||||
asm_exception_handler, /* 140 (0x___) Reserved */
|
||||
asm_exception_handler, /* 141 (0x___) Reserved */
|
||||
asm_exception_handler, /* 142 (0x___) Reserved */
|
||||
asm_exception_handler, /* 143 (0x___) Reserved */
|
||||
asm_exception_handler, /* 144 (0x___) Reserved */
|
||||
asm_exception_handler, /* 145 (0x___) Reserved */
|
||||
asm_exception_handler, /* 146 (0x___) Reserved */
|
||||
asm_exception_handler, /* 147 (0x___) Reserved */
|
||||
asm_exception_handler, /* 148 (0x___) Reserved */
|
||||
asm_exception_handler, /* 149 (0x___) Reserved */
|
||||
asm_exception_handler, /* 150 (0x___) Reserved */
|
||||
asm_exception_handler, /* 151 (0x___) Reserved */
|
||||
asm_exception_handler, /* 152 (0x___) Reserved */
|
||||
asm_exception_handler, /* 153 (0x___) Reserved */
|
||||
asm_exception_handler, /* 154 (0x___) Reserved */
|
||||
asm_exception_handler, /* 155 (0x___) Reserved */
|
||||
asm_exception_handler, /* 156 (0x___) Reserved */
|
||||
asm_exception_handler, /* 157 (0x___) Reserved */
|
||||
asm_exception_handler, /* 158 (0x___) Reserved */
|
||||
asm_exception_handler, /* 159 (0x___) Reserved */
|
||||
asm_exception_handler, /* 160 (0x___) Reserved */
|
||||
asm_exception_handler, /* 161 (0x___) Reserved */
|
||||
asm_exception_handler, /* 162 (0x___) Reserved */
|
||||
asm_exception_handler, /* 163 (0x___) Reserved */
|
||||
asm_exception_handler, /* 164 (0x___) Reserved */
|
||||
asm_exception_handler, /* 165 (0x___) Reserved */
|
||||
asm_exception_handler, /* 166 (0x___) Reserved */
|
||||
asm_exception_handler, /* 167 (0x___) Reserved */
|
||||
asm_exception_handler, /* 168 (0x___) Reserved */
|
||||
asm_exception_handler, /* 169 (0x___) Reserved */
|
||||
asm_exception_handler, /* 170 (0x___) Reserved */
|
||||
asm_exception_handler, /* 171 (0x___) Reserved */
|
||||
asm_exception_handler, /* 172 (0x___) Reserved */
|
||||
asm_exception_handler, /* 173 (0x___) Reserved */
|
||||
asm_exception_handler, /* 174 (0x___) Reserved */
|
||||
asm_exception_handler, /* 175 (0x___) Reserved */
|
||||
asm_exception_handler, /* 176 (0x___) Reserved */
|
||||
asm_exception_handler, /* 177 (0x___) Reserved */
|
||||
asm_exception_handler, /* 178 (0x___) Reserved */
|
||||
asm_exception_handler, /* 179 (0x___) Reserved */
|
||||
asm_exception_handler, /* 180 (0x___) Reserved */
|
||||
asm_exception_handler, /* 181 (0x___) Reserved */
|
||||
asm_exception_handler, /* 182 (0x___) Reserved */
|
||||
asm_exception_handler, /* 183 (0x___) Reserved */
|
||||
asm_exception_handler, /* 184 (0x___) Reserved */
|
||||
asm_exception_handler, /* 185 (0x___) Reserved */
|
||||
asm_exception_handler, /* 186 (0x___) Reserved */
|
||||
asm_exception_handler, /* 187 (0x___) Reserved */
|
||||
asm_exception_handler, /* 188 (0x___) Reserved */
|
||||
asm_exception_handler, /* 189 (0x___) Reserved */
|
||||
asm_exception_handler, /* 190 (0x___) Reserved */
|
||||
asm_exception_handler, /* 191 (0x___) Reserved */
|
||||
asm_exception_handler, /* 192 (0x___) Reserved */
|
||||
asm_exception_handler, /* 193 (0x___) Reserved */
|
||||
asm_exception_handler, /* 194 (0x___) Reserved */
|
||||
asm_exception_handler, /* 195 (0x___) Reserved */
|
||||
asm_exception_handler, /* 196 (0x___) Reserved */
|
||||
asm_exception_handler, /* 197 (0x___) Reserved */
|
||||
asm_exception_handler, /* 198 (0x___) Reserved */
|
||||
asm_exception_handler, /* 199 (0x___) Reserved */
|
||||
asm_exception_handler, /* 200 (0x___) Reserved */
|
||||
asm_exception_handler, /* 201 (0x___) Reserved */
|
||||
asm_exception_handler, /* 202 (0x___) Reserved */
|
||||
asm_exception_handler, /* 203 (0x___) Reserved */
|
||||
asm_exception_handler, /* 204 (0x___) Reserved */
|
||||
asm_exception_handler, /* 205 (0x___) Reserved */
|
||||
asm_exception_handler, /* 206 (0x___) Reserved */
|
||||
asm_exception_handler, /* 207 (0x___) Reserved */
|
||||
asm_exception_handler, /* 208 (0x___) Reserved */
|
||||
asm_exception_handler, /* 209 (0x___) Reserved */
|
||||
asm_exception_handler, /* 210 (0x___) Reserved */
|
||||
asm_exception_handler, /* 211 (0x___) Reserved */
|
||||
asm_exception_handler, /* 212 (0x___) Reserved */
|
||||
asm_exception_handler, /* 213 (0x___) Reserved */
|
||||
asm_exception_handler, /* 214 (0x___) Reserved */
|
||||
asm_exception_handler, /* 215 (0x___) Reserved */
|
||||
asm_exception_handler, /* 216 (0x___) Reserved */
|
||||
asm_exception_handler, /* 217 (0x___) Reserved */
|
||||
asm_exception_handler, /* 218 (0x___) Reserved */
|
||||
asm_exception_handler, /* 219 (0x___) Reserved */
|
||||
asm_exception_handler, /* 220 (0x___) Reserved */
|
||||
asm_exception_handler, /* 221 (0x___) Reserved */
|
||||
asm_exception_handler, /* 222 (0x___) Reserved */
|
||||
asm_exception_handler, /* 223 (0x___) Reserved */
|
||||
asm_exception_handler, /* 224 (0x___) Reserved */
|
||||
asm_exception_handler, /* 225 (0x___) Reserved */
|
||||
asm_exception_handler, /* 226 (0x___) Reserved */
|
||||
asm_exception_handler, /* 227 (0x___) Reserved */
|
||||
asm_exception_handler, /* 228 (0x___) Reserved */
|
||||
asm_exception_handler, /* 229 (0x___) Reserved */
|
||||
asm_exception_handler, /* 230 (0x___) Reserved */
|
||||
asm_exception_handler, /* 231 (0x___) Reserved */
|
||||
asm_exception_handler, /* 232 (0x___) Reserved */
|
||||
asm_exception_handler, /* 233 (0x___) Reserved */
|
||||
asm_exception_handler, /* 234 (0x___) Reserved */
|
||||
asm_exception_handler, /* 235 (0x___) Reserved */
|
||||
asm_exception_handler, /* 236 (0x___) Reserved */
|
||||
asm_exception_handler, /* 237 (0x___) Reserved */
|
||||
asm_exception_handler, /* 238 (0x___) Reserved */
|
||||
asm_exception_handler, /* 239 (0x___) Reserved */
|
||||
asm_exception_handler, /* 240 (0x___) Reserved */
|
||||
asm_exception_handler, /* 241 (0x___) Reserved */
|
||||
asm_exception_handler, /* 242 (0x___) Reserved */
|
||||
asm_exception_handler, /* 243 (0x___) Reserved */
|
||||
asm_exception_handler, /* 244 (0x___) Reserved */
|
||||
asm_exception_handler, /* 245 (0x___) Reserved */
|
||||
asm_exception_handler, /* 246 (0x___) Reserved */
|
||||
asm_exception_handler, /* 247 (0x___) Reserved */
|
||||
asm_exception_handler, /* 248 (0x___) Reserved */
|
||||
asm_exception_handler, /* 249 (0x___) Reserved */
|
||||
asm_exception_handler, /* 250 (0x___) Reserved */
|
||||
asm_exception_handler, /* 251 (0x___) Reserved */
|
||||
asm_exception_handler, /* 252 (0x___) Reserved */
|
||||
asm_exception_handler, /* 253 (0x___) Reserved */
|
||||
asm_exception_handler, /* 254 (0x___) Reserved */
|
||||
asm_exception_handler, /* 255 (0x___) Reserved */
|
||||
};
|
||||
|
||||
/********************************************************************
|
||||
* MCF5xxx ASM utility functions
|
||||
*/
|
||||
asm void mcf5xxx_wr_vbr(unsigned long) { /* Set VBR */
|
||||
move.l 4(SP),D0
|
||||
movec d0,VBR
|
||||
nop
|
||||
rts
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* MCF5xxx startup copy functions:
|
||||
*
|
||||
* Set VBR and performs RAM vector table initializatiom.
|
||||
* The following symbol should be defined in the lcf:
|
||||
* __VECTOR_RAM
|
||||
*
|
||||
* _vect is the start of the exception table in the code
|
||||
* In case _vect address is different from __VECTOR_RAM,
|
||||
* the vector table is copied from _vect to __VECTOR_RAM.
|
||||
* In any case VBR is set to __VECTOR_RAM.
|
||||
*/
|
||||
void initialize_exceptions(void)
|
||||
{
|
||||
#if 0
|
||||
/*
|
||||
* Memory map definitions from linker command files used by mcf5xxx_startup
|
||||
*/
|
||||
|
||||
register uint32 n;
|
||||
|
||||
/*
|
||||
* Copy the vector table to RAM
|
||||
*/
|
||||
if (__VECTOR_RAM != (unsigned long*)_vect)
|
||||
{
|
||||
for (n = 0; n < 256; n++)
|
||||
__VECTOR_RAM[n] = (unsigned long)_vect[n];
|
||||
}
|
||||
mcf5xxx_wr_vbr((unsigned long)__VECTOR_RAM);
|
||||
#endif
|
||||
|
||||
mcf5xxx_wr_vbr((unsigned long)_vect);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* File: exceptions.h
|
||||
* Purpose: Generic exception handling for ColdFire processors
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _MCF_EXCEPTIONS_H
|
||||
#define _MCF_EXCEPTIONS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* This is the handler for all exceptions which are not common to all
|
||||
* ColdFire Chips.
|
||||
*
|
||||
* Called by mcf_exception_handler
|
||||
*
|
||||
*/
|
||||
void derivative_interrupt(unsigned long vector);
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* This is the exception handler for all exceptions common to all
|
||||
* chips ColdFire. Most exceptions do nothing, but some of the more
|
||||
* important ones are handled to some extent.
|
||||
*
|
||||
* Called by asm_exception_handler
|
||||
*/
|
||||
void mcf_exception_handler(void *framepointer);
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* This is the assembly exception handler defined in the vector table.
|
||||
* This function is in assembler so that the frame pointer can be read
|
||||
* from the stack.
|
||||
* Note that the way to give the stack frame as argument to the c handler
|
||||
* depends on the used ABI (Register, Compact or Standard).
|
||||
*
|
||||
*/
|
||||
asm void asm_exception_handler(void);
|
||||
|
||||
/***********************************************************************/
|
||||
/* MCF5xxx exceptions table initialization:
|
||||
*
|
||||
* Set VBR and performs RAM vector table initialization.
|
||||
* The following symbol should be defined in the lcf:
|
||||
* __VECTOR_RAM
|
||||
*
|
||||
* _vect is the start of the exception table in the code
|
||||
* In case _vect address is different from __VECTOR_RAM,
|
||||
* the vector table is copied from _vect to __VECTOR_RAM.
|
||||
* In any case VBR is set to __VECTOR_RAM.
|
||||
*/
|
||||
void initialize_exceptions(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MCF_EXCEPTIONS_H */
|
||||
|
||||
238
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h
Normal file
238
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/lwipopts.h
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
#ifndef __LWIPOPTS_H__
|
||||
#define __LWIPOPTS_H__
|
||||
|
||||
#define TCPIP_THREAD_NAME "tcp/ip"
|
||||
#define TCPIP_THREAD_STACKSIZE 350
|
||||
#define TCPIP_THREAD_PRIO 2
|
||||
|
||||
#define DEFAULT_THREAD_STACKSIZE 200
|
||||
#define DEFAULT_THREAD_PRIO 1
|
||||
|
||||
#define ETH_PAD_SIZE 2
|
||||
|
||||
#define NOT_LWIP_DEBUG 0
|
||||
#define DBG_TYPES_ON 0x00
|
||||
#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF
|
||||
|
||||
#define ETHARP_DEBUG LWIP_DBG_OFF
|
||||
#define NETIF_DEBUG LWIP_DBG_OFF
|
||||
#define PBUF_DEBUG LWIP_DBG_OFF
|
||||
#define API_LIB_DEBUG LWIP_DBG_OFF
|
||||
#define API_MSG_DEBUG LWIP_DBG_OFF
|
||||
#define SOCKETS_DEBUG LWIP_DBG_OFF
|
||||
#define ICMP_DEBUG LWIP_DBG_OFF
|
||||
#define IGMP_DEBUG LWIP_DBG_OFF
|
||||
#define INET_DEBUG LWIP_DBG_OFF
|
||||
#define IP_DEBUG LWIP_DBG_OFF
|
||||
#define IP_REASS_DEBUG LWIP_DBG_OFF
|
||||
#define RAW_DEBUG LWIP_DBG_OFF
|
||||
#define MEM_DEBUG LWIP_DBG_OFF
|
||||
#define MEMP_DEBUG LWIP_DBG_OFF
|
||||
#define SYS_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_INPUT_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_FR_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_RTO_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_CWND_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_WND_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_RST_DEBUG LWIP_DBG_OFF
|
||||
#define TCP_QLEN_DEBUG LWIP_DBG_OFF
|
||||
#define UDP_DEBUG LWIP_DBG_OFF
|
||||
#define TCPIP_DEBUG LWIP_DBG_OFF
|
||||
#define PPP_DEBUG LWIP_DBG_OFF
|
||||
#define SLIP_DEBUG LWIP_DBG_OFF
|
||||
#define DHCP_DEBUG LWIP_DBG_OFF
|
||||
#define AUTOIP_DEBUG LWIP_DBG_OFF
|
||||
#define SNMP_MSG_DEBUG LWIP_DBG_OFF
|
||||
#define SNMP_MIB_DEBUG LWIP_DBG_OFF
|
||||
#define DNS_DEBUG LWIP_DBG_OFF
|
||||
#define LWIP_NOASSERT 0
|
||||
|
||||
#define ETHARP_TRUST_IP_MAC 0
|
||||
#define LWIP_UDP 0
|
||||
|
||||
/**
|
||||
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
|
||||
* critical regions during buffer allocation, deallocation and memory
|
||||
* allocation and deallocation.
|
||||
*/
|
||||
#define SYS_LIGHTWEIGHT_PROT 1
|
||||
|
||||
/*
|
||||
------------------------------------
|
||||
---------- Memory options ----------
|
||||
------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* MEM_ALIGNMENT: should be set to the alignment of the CPU
|
||||
* 4 byte alignment -> #define MEM_ALIGNMENT 4
|
||||
* 2 byte alignment -> #define MEM_ALIGNMENT 2
|
||||
*/
|
||||
#define MEM_ALIGNMENT 4
|
||||
|
||||
/**
|
||||
* MEM_SIZE: the size of the heap memory. If the application will send
|
||||
* a lot of data that needs to be copied, this should be set high.
|
||||
*/
|
||||
#define MEM_SIZE (8*1024)
|
||||
|
||||
/*
|
||||
------------------------------------------------
|
||||
---------- Internal Memory Pool Sizes ----------
|
||||
------------------------------------------------
|
||||
*/
|
||||
/**
|
||||
* MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
|
||||
* If the application sends a lot of data out of ROM (or other static memory),
|
||||
* this should be set high.
|
||||
*/
|
||||
#define MEMP_NUM_PBUF 20
|
||||
|
||||
/**
|
||||
* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
|
||||
* (requires the LWIP_TCP option)
|
||||
*/
|
||||
#define MEMP_NUM_TCP_PCB 10
|
||||
|
||||
/**
|
||||
* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
|
||||
* (requires the LWIP_TCP option)
|
||||
*/
|
||||
#define MEMP_NUM_TCP_SEG 8
|
||||
|
||||
/**
|
||||
* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
|
||||
* (requires NO_SYS==0)
|
||||
*/
|
||||
#define MEMP_NUM_SYS_TIMEOUT 5
|
||||
|
||||
/**
|
||||
* MEMP_NUM_NETBUF: the number of struct netbufs.
|
||||
* (only needed if you use the sequential API, like api_lib.c)
|
||||
*/
|
||||
#define MEMP_NUM_NETBUF 4
|
||||
|
||||
/**
|
||||
* PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
|
||||
*/
|
||||
#define PBUF_POOL_SIZE 4
|
||||
|
||||
|
||||
/*
|
||||
----------------------------------
|
||||
---------- Pbuf options ----------
|
||||
----------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
|
||||
* designed to accomodate single full size TCP frame in one pbuf, including
|
||||
* TCP_MSS, IP header, and link header.
|
||||
*/
|
||||
#define PBUF_POOL_BUFSIZE 1500
|
||||
|
||||
/*
|
||||
---------------------------------
|
||||
---------- TCP options ----------
|
||||
---------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_TCP==1: Turn on TCP.
|
||||
*/
|
||||
#define LWIP_TCP 1
|
||||
|
||||
/* TCP Maximum segment size. */
|
||||
#define TCP_MSS 1500
|
||||
|
||||
/* TCP sender buffer space (bytes). */
|
||||
#define TCP_SND_BUF 1500
|
||||
|
||||
/**
|
||||
* TCP_WND: The size of a TCP window.
|
||||
*/
|
||||
#define TCP_WND 1500
|
||||
|
||||
/**
|
||||
* TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
|
||||
*/
|
||||
#define TCP_SYNMAXRTX 4
|
||||
|
||||
/*
|
||||
---------------------------------
|
||||
---------- RAW options ----------
|
||||
---------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
|
||||
*/
|
||||
#define LWIP_RAW 0
|
||||
|
||||
|
||||
/*
|
||||
------------------------------------
|
||||
---------- Socket options ----------
|
||||
------------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
|
||||
*/
|
||||
#define LWIP_SOCKET 0
|
||||
|
||||
|
||||
/*
|
||||
----------------------------------------
|
||||
---------- Statistics options ----------
|
||||
----------------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_STATS==1: Enable statistics collection in lwip_stats.
|
||||
*/
|
||||
#define LWIP_STATS 0
|
||||
|
||||
/*
|
||||
----------------------------------
|
||||
---------- DHCP options ----------
|
||||
----------------------------------
|
||||
*/
|
||||
/**
|
||||
* LWIP_DHCP==1: Enable DHCP module.
|
||||
*/
|
||||
#define LWIP_DHCP 0
|
||||
|
||||
|
||||
#define LWIP_PROVIDE_ERRNO 0
|
||||
|
||||
#endif /* __LWIPOPTS_H__ */
|
||||
453
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c
Normal file
453
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/main.c
Normal file
|
|
@ -0,0 +1,453 @@
|
|||
/*
|
||||
FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation and modified by the FreeRTOS exception.
|
||||
**NOTE** The exception to the GPL is included to allow you to distribute a
|
||||
combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
Alternative commercial license and support terms are also available upon
|
||||
request. See the licensing section of http://www.FreeRTOS.org for full
|
||||
license details.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
|
||||
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Looking for a quick start? Then check out the FreeRTOS eBook! *
|
||||
* See http://www.FreeRTOS.org/Documentation for details *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Creates all the demo application tasks, then starts the scheduler. The WEB
|
||||
* documentation provides more details of the standard demo application tasks.
|
||||
* In addition to the standard demo tasks, the following tasks and tests are
|
||||
* defined and/or created within this file:
|
||||
*
|
||||
* "Check" task - This only executes every five seconds but has a high priority
|
||||
* to ensure it gets processor time. Its main function is to check that all the
|
||||
* standard demo tasks are still operational. While no errors have been
|
||||
* discovered the check task will toggle an LED every 5 seconds - the toggle
|
||||
* rate increasing to 500ms being a visual indication that at least one task has
|
||||
* reported unexpected behaviour.
|
||||
*
|
||||
* "Reg test" tasks - These fill the registers with known values, then check
|
||||
* that each register still contains its expected value. Each task uses
|
||||
* different values. The tasks run with very low priority so get preempted very
|
||||
* frequently. A register containing an unexpected value is indicative of an
|
||||
* error in the context switching mechanism.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Demo app includes. */
|
||||
#include "BlockQ.h"
|
||||
#include "crflash.h"
|
||||
#include "partest.h"
|
||||
#include "semtest.h"
|
||||
#include "GenQTest.h"
|
||||
#include "QPeek.h"
|
||||
#include "comtest2.h"
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The time between cycles of the 'check' functionality - as described at the
|
||||
top of this file. */
|
||||
#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS )
|
||||
|
||||
/* The rate at which the LED controlled by the 'check' task will flash should an
|
||||
error have been detected. */
|
||||
#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
|
||||
|
||||
/* The LED controlled by the 'check' task. */
|
||||
#define mainCHECK_LED ( 3 )
|
||||
|
||||
/* ComTest constants - there is no free LED for the comtest tasks. */
|
||||
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )
|
||||
#define mainCOM_TEST_LED ( 5 )
|
||||
|
||||
/* Task priorities. */
|
||||
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
|
||||
|
||||
/* Co-routines are used to flash the LEDs. */
|
||||
#define mainNUM_FLASH_CO_ROUTINES ( 3 )
|
||||
|
||||
/* The baud rate used by the comtest tasks. */
|
||||
#define mainBAUD_RATE ( 38400 )
|
||||
|
||||
/* There is no spare LED for the comtest tasks, so this is set to an invalid
|
||||
number. */
|
||||
#define mainCOM_LED ( 4 )
|
||||
|
||||
/*
|
||||
* Configure the hardware for the demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* Implements the 'check' task functionality as described at the top of this
|
||||
* file.
|
||||
*/
|
||||
static void prvCheckTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Implement the 'Reg test' functionality as described at the top of this file.
|
||||
*/
|
||||
static void vRegTest1Task( void *pvParameters );
|
||||
static void vRegTest2Task( void *pvParameters );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Counters used to detect errors within the reg test tasks. */
|
||||
static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main( void )
|
||||
{
|
||||
/* Setup the hardware ready for this demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Start the standard demo tasks. */
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
|
||||
vStartQueuePeekTasks();
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_LED );
|
||||
|
||||
/* For demo purposes use some co-routines to flash the LEDs. */
|
||||
vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );
|
||||
|
||||
/* Create the check task. */
|
||||
xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
|
||||
|
||||
|
||||
/* Start the reg test tasks - defined in this file. */
|
||||
xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Will only get here if there was insufficient memory to create the idle
|
||||
task. */
|
||||
for( ;; )
|
||||
{
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckTask( void *pvParameters )
|
||||
{
|
||||
unsigned portLONG ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;
|
||||
portTickType xLastExecutionTime;
|
||||
volatile unsigned portBASE_TYPE uxUnusedStack;
|
||||
|
||||
( void ) pvParameters;
|
||||
|
||||
/* Initialise the variable used to control our iteration rate prior to
|
||||
its first use. */
|
||||
xLastExecutionTime = xTaskGetTickCount();
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait until it is time to run the tests again. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );
|
||||
|
||||
/* Has an error been found in any task? */
|
||||
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulError |= 0x01UL;
|
||||
}
|
||||
|
||||
if( xAreQueuePeekTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulError |= 0x02UL;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulError |= 0x04UL;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulError |= 0x20UL;
|
||||
}
|
||||
|
||||
if( xAreComTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulError |= 0x40UL;
|
||||
}
|
||||
|
||||
if( ulLastRegTest1Count == ulRegTest1Counter )
|
||||
{
|
||||
ulError |= 0x1000UL;
|
||||
}
|
||||
|
||||
if( ulLastRegTest2Count == ulRegTest2Counter )
|
||||
{
|
||||
ulError |= 0x1000UL;
|
||||
}
|
||||
|
||||
ulLastRegTest1Count = ulRegTest1Counter;
|
||||
ulLastRegTest2Count = ulRegTest2Counter;
|
||||
|
||||
/* If an error has been found then increase our cycle rate, and in so
|
||||
doing increase the rate at which the check task LED toggles. */
|
||||
if( ulError != 0 )
|
||||
{
|
||||
ulTicksToWait = mainERROR_PERIOD;
|
||||
}
|
||||
|
||||
/* Toggle the LED each itteration. */
|
||||
vParTestToggleLED( mainCHECK_LED );
|
||||
|
||||
/* For demo only - how much unused stack does this task have? */
|
||||
uxUnusedStack = uxTaskGetStackHighWaterMark( NULL );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void prvSetupHardware( void )
|
||||
{
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/* Setup the port used to toggle LEDs. */
|
||||
vParTestInitialise();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
|
||||
{
|
||||
/* This will get called if a stack overflow is detected during the context
|
||||
switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack
|
||||
problems within nested interrupts, but only do this for debug purposes as
|
||||
it will increase the context switch time. */
|
||||
|
||||
( void ) pxTask;
|
||||
( void ) pcTaskName;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void );
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* The co-routines run in the idle task. */
|
||||
vCoRoutineSchedule();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void exit( int n )
|
||||
{
|
||||
/* To keep the linker happy only as the libraries have been removed from
|
||||
the build. */
|
||||
( void ) n;
|
||||
for( ;; ) {}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vRegTest1Task( void *pvParameters )
|
||||
{
|
||||
/* Sanity check - did we receive the parameter expected? */
|
||||
if( pvParameters != &ulRegTest1Counter )
|
||||
{
|
||||
/* Change here so the check task can detect that an error occurred. */
|
||||
for( ;; )
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* Set all the registers to known values, then check that each retains its
|
||||
expected value - as described at the top of this file. If an error is
|
||||
found then the loop counter will no longer be incremented allowing the check
|
||||
task to recognise the error. */
|
||||
asm volatile ( "reg_test_1_start: \n\t"
|
||||
" moveq #1, d0 \n\t"
|
||||
" moveq #2, d1 \n\t"
|
||||
" moveq #3, d2 \n\t"
|
||||
" moveq #4, d3 \n\t"
|
||||
" moveq #5, d4 \n\t"
|
||||
" moveq #6, d5 \n\t"
|
||||
" moveq #7, d6 \n\t"
|
||||
" moveq #8, d7 \n\t"
|
||||
" move #9, a0 \n\t"
|
||||
" move #10, a1 \n\t"
|
||||
" move #11, a2 \n\t"
|
||||
" move #12, a3 \n\t"
|
||||
" move #13, a4 \n\t"
|
||||
" move #14, a5 \n\t"
|
||||
" move #15, a6 \n\t"
|
||||
" \n\t"
|
||||
" cmpi.l #1, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #2, d1 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #3, d2 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #4, d3 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #5, d4 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #6, d5 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #7, d6 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" cmpi.l #8, d7 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a0, d0 \n\t"
|
||||
" cmpi.l #9, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a1, d0 \n\t"
|
||||
" cmpi.l #10, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a2, d0 \n\t"
|
||||
" cmpi.l #11, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a3, d0 \n\t"
|
||||
" cmpi.l #12, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a4, d0 \n\t"
|
||||
" cmpi.l #13, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a5, d0 \n\t"
|
||||
" cmpi.l #14, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move a6, d0 \n\t"
|
||||
" cmpi.l #15, d0 \n\t"
|
||||
" bne reg_test_1_error \n\t"
|
||||
" move ulRegTest1Counter, d0 \n\t"
|
||||
" addq #1, d0 \n\t"
|
||||
" move d0, ulRegTest1Counter \n\t"
|
||||
" bra reg_test_1_start \n\t"
|
||||
"reg_test_1_error: \n\t"
|
||||
" bra reg_test_1_error \n\t"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vRegTest2Task( void *pvParameters )
|
||||
{
|
||||
/* Sanity check - did we receive the parameter expected? */
|
||||
if( pvParameters != &ulRegTest2Counter )
|
||||
{
|
||||
/* Change here so the check task can detect that an error occurred. */
|
||||
for( ;; )
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* Set all the registers to known values, then check that each retains its
|
||||
expected value - as described at the top of this file. If an error is
|
||||
found then the loop counter will no longer be incremented allowing the check
|
||||
task to recognise the error. */
|
||||
asm volatile ( "reg_test_2_start: \n\t"
|
||||
" moveq #10, d0 \n\t"
|
||||
" moveq #20, d1 \n\t"
|
||||
" moveq #30, d2 \n\t"
|
||||
" moveq #40, d3 \n\t"
|
||||
" moveq #50, d4 \n\t"
|
||||
" moveq #60, d5 \n\t"
|
||||
" moveq #70, d6 \n\t"
|
||||
" moveq #80, d7 \n\t"
|
||||
" move #90, a0 \n\t"
|
||||
" move #100, a1 \n\t"
|
||||
" move #110, a2 \n\t"
|
||||
" move #120, a3 \n\t"
|
||||
" move #130, a4 \n\t"
|
||||
" move #140, a5 \n\t"
|
||||
" move #150, a6 \n\t"
|
||||
" \n\t"
|
||||
" cmpi.l #10, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #20, d1 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #30, d2 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #40, d3 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #50, d4 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #60, d5 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #70, d6 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" cmpi.l #80, d7 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a0, d0 \n\t"
|
||||
" cmpi.l #90, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a1, d0 \n\t"
|
||||
" cmpi.l #100, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a2, d0 \n\t"
|
||||
" cmpi.l #110, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a3, d0 \n\t"
|
||||
" cmpi.l #120, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a4, d0 \n\t"
|
||||
" cmpi.l #130, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a5, d0 \n\t"
|
||||
" cmpi.l #140, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move a6, d0 \n\t"
|
||||
" cmpi.l #150, d0 \n\t"
|
||||
" bne reg_test_2_error \n\t"
|
||||
" move ulRegTest1Counter, d0 \n\t"
|
||||
" addq #1, d0 \n\t"
|
||||
" move d0, ulRegTest2Counter \n\t"
|
||||
" bra reg_test_2_start \n\t"
|
||||
"reg_test_2_error: \n\t"
|
||||
" bra reg_test_2_error \n\t"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,293 @@
|
|||
/*
|
||||
Copyright 2001, 2002 Georges Menie (www.menie.org)
|
||||
stdarg version contributed by Christian Ettinger
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU Lesser General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
putchar is the only external dependency for this file,
|
||||
if you have a working putchar, leave it commented out.
|
||||
If not, uncomment the define below and
|
||||
replace outbyte(c) by your own function call.
|
||||
|
||||
*/
|
||||
|
||||
#define putchar(c) c
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
static void printchar(char **str, int c)
|
||||
{
|
||||
//extern int putchar(int c);
|
||||
|
||||
if (str) {
|
||||
**str = (char)c;
|
||||
++(*str);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)putchar(c);
|
||||
}
|
||||
}
|
||||
|
||||
#define PAD_RIGHT 1
|
||||
#define PAD_ZERO 2
|
||||
|
||||
static int prints(char **out, const char *string, int width, int pad)
|
||||
{
|
||||
register int pc = 0, padchar = ' ';
|
||||
|
||||
if (width > 0) {
|
||||
register int len = 0;
|
||||
register const char *ptr;
|
||||
for (ptr = string; *ptr; ++ptr) ++len;
|
||||
if (len >= width) width = 0;
|
||||
else width -= len;
|
||||
if (pad & PAD_ZERO) padchar = '0';
|
||||
}
|
||||
if (!(pad & PAD_RIGHT)) {
|
||||
for ( ; width > 0; --width) {
|
||||
printchar (out, padchar);
|
||||
++pc;
|
||||
}
|
||||
}
|
||||
for ( ; *string ; ++string) {
|
||||
printchar (out, *string);
|
||||
++pc;
|
||||
}
|
||||
for ( ; width > 0; --width) {
|
||||
printchar (out, padchar);
|
||||
++pc;
|
||||
}
|
||||
|
||||
return pc;
|
||||
}
|
||||
|
||||
/* the following should be enough for 32 bit int */
|
||||
#define PRINT_BUF_LEN 12
|
||||
|
||||
static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
|
||||
{
|
||||
char print_buf[PRINT_BUF_LEN];
|
||||
register char *s;
|
||||
register int t, neg = 0, pc = 0;
|
||||
register unsigned int u = (unsigned int)i;
|
||||
|
||||
if (i == 0) {
|
||||
print_buf[0] = '0';
|
||||
print_buf[1] = '\0';
|
||||
return prints (out, print_buf, width, pad);
|
||||
}
|
||||
|
||||
if (sg && b == 10 && i < 0) {
|
||||
neg = 1;
|
||||
u = (unsigned int)-i;
|
||||
}
|
||||
|
||||
s = print_buf + PRINT_BUF_LEN-1;
|
||||
*s = '\0';
|
||||
|
||||
while (u) {
|
||||
t = (unsigned int)u % b;
|
||||
if( t >= 10 )
|
||||
t += letbase - '0' - 10;
|
||||
*--s = (char)(t + '0');
|
||||
u /= b;
|
||||
}
|
||||
|
||||
if (neg) {
|
||||
if( width && (pad & PAD_ZERO) ) {
|
||||
printchar (out, '-');
|
||||
++pc;
|
||||
--width;
|
||||
}
|
||||
else {
|
||||
*--s = '-';
|
||||
}
|
||||
}
|
||||
|
||||
return pc + prints (out, s, width, pad);
|
||||
}
|
||||
|
||||
static int print( char **out, const char *format, va_list args )
|
||||
{
|
||||
register int width, pad;
|
||||
register int pc = 0;
|
||||
char scr[2];
|
||||
|
||||
for (; *format != 0; ++format) {
|
||||
if (*format == '%') {
|
||||
++format;
|
||||
width = pad = 0;
|
||||
if (*format == '\0') break;
|
||||
if (*format == '%') goto out;
|
||||
if (*format == '-') {
|
||||
++format;
|
||||
pad = PAD_RIGHT;
|
||||
}
|
||||
while (*format == '0') {
|
||||
++format;
|
||||
pad |= PAD_ZERO;
|
||||
}
|
||||
for ( ; *format >= '0' && *format <= '9'; ++format) {
|
||||
width *= 10;
|
||||
width += *format - '0';
|
||||
}
|
||||
if( *format == 's' ) {
|
||||
register char *s = (char *)va_arg( args, int );
|
||||
pc += prints (out, s?s:"(null)", width, pad);
|
||||
continue;
|
||||
}
|
||||
if( *format == 'd' ) {
|
||||
pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
|
||||
continue;
|
||||
}
|
||||
if( *format == 'x' ) {
|
||||
pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
|
||||
continue;
|
||||
}
|
||||
if( *format == 'X' ) {
|
||||
pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
|
||||
continue;
|
||||
}
|
||||
if( *format == 'u' ) {
|
||||
pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
|
||||
continue;
|
||||
}
|
||||
if( *format == 'c' ) {
|
||||
/* char are converted to int then pushed on the stack */
|
||||
scr[0] = (char)va_arg( args, int );
|
||||
scr[1] = '\0';
|
||||
pc += prints (out, scr, width, pad);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else {
|
||||
out:
|
||||
printchar (out, *format);
|
||||
++pc;
|
||||
}
|
||||
}
|
||||
if (out) **out = '\0';
|
||||
va_end( args );
|
||||
return pc;
|
||||
}
|
||||
|
||||
int printf(const char *format, ...)
|
||||
{
|
||||
va_list args;
|
||||
|
||||
va_start( args, format );
|
||||
return print( 0, format, args );
|
||||
}
|
||||
|
||||
int sprintf(char *out, const char *format, ...)
|
||||
{
|
||||
va_list args;
|
||||
|
||||
va_start( args, format );
|
||||
return print( &out, format, args );
|
||||
}
|
||||
|
||||
|
||||
int snprintf( char *buf, unsigned int count, const char *format, ... )
|
||||
{
|
||||
va_list args;
|
||||
|
||||
( void ) count;
|
||||
|
||||
va_start( args, format );
|
||||
return print( &buf, format, args );
|
||||
}
|
||||
|
||||
|
||||
#ifdef TEST_PRINTF
|
||||
int main(void)
|
||||
{
|
||||
char *ptr = "Hello world!";
|
||||
char *np = 0;
|
||||
int i = 5;
|
||||
unsigned int bs = sizeof(int)*8;
|
||||
int mi;
|
||||
char buf[80];
|
||||
|
||||
mi = (1 << (bs-1)) + 1;
|
||||
printf("%s\n", ptr);
|
||||
printf("printf test\n");
|
||||
printf("%s is null pointer\n", np);
|
||||
printf("%d = 5\n", i);
|
||||
printf("%d = - max int\n", mi);
|
||||
printf("char %c = 'a'\n", 'a');
|
||||
printf("hex %x = ff\n", 0xff);
|
||||
printf("hex %02x = 00\n", 0);
|
||||
printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
|
||||
printf("%d %s(s)%", 0, "message");
|
||||
printf("\n");
|
||||
printf("%d %s(s) with %%\n", 0, "message");
|
||||
sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
|
||||
sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
|
||||
sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
|
||||
sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
|
||||
sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
|
||||
sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
|
||||
sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
|
||||
sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* if you compile this file with
|
||||
* gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
|
||||
* you will get a normal warning:
|
||||
* printf.c:214: warning: spurious trailing `%' in format
|
||||
* this line is testing an invalid % at the end of the format string.
|
||||
*
|
||||
* this should display (on 32bit int machine) :
|
||||
*
|
||||
* Hello world!
|
||||
* printf test
|
||||
* (null) is null pointer
|
||||
* 5 = 5
|
||||
* -2147483647 = - max int
|
||||
* char a = 'a'
|
||||
* hex ff = ff
|
||||
* hex 00 = 00
|
||||
* signed -3 = unsigned 4294967293 = hex fffffffd
|
||||
* 0 message(s)
|
||||
* 0 message(s) with %
|
||||
* justif: "left "
|
||||
* justif: " right"
|
||||
* 3: 0003 zero padded
|
||||
* 3: 3 left justif.
|
||||
* 3: 3 right justif.
|
||||
* -3: -003 zero padded
|
||||
* -3: -3 left justif.
|
||||
* -3: -3 right justif.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* To keep linker happy. */
|
||||
int write( int i, char* c, int n)
|
||||
{
|
||||
(void)i;
|
||||
(void)n;
|
||||
(void)c;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
/*
|
||||
FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation and modified by the FreeRTOS exception.
|
||||
**NOTE** The exception to the GPL is included to allow you to distribute a
|
||||
combined work that includes FreeRTOS without being obliged to provide the
|
||||
source code for proprietary components outside of the FreeRTOS kernel.
|
||||
Alternative commercial license and support terms are also available upon
|
||||
request. See the licensing section of http://www.FreeRTOS.org for full
|
||||
license details.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
|
||||
Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* Looking for a quick start? Then check out the FreeRTOS eBook! *
|
||||
* See http://www.FreeRTOS.org/Documentation for details *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
1 tab == 4 spaces!
|
||||
|
||||
Please ensure to read the configuration and relevant port sections of the
|
||||
online documentation.
|
||||
|
||||
http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
contact details.
|
||||
|
||||
http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
critical systems.
|
||||
|
||||
http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
licensing and training services.
|
||||
*/
|
||||
|
||||
|
||||
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
|
||||
|
||||
NOTE: This driver is primarily to test the scheduler functionality. It does
|
||||
not effectively use the buffers or DMA and is therefore not intended to be
|
||||
an example of an efficient driver. */
|
||||
|
||||
/* Standard include file. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "queue.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Demo app include files. */
|
||||
#include "serial.h"
|
||||
|
||||
/* Hardware definitions. */
|
||||
#define serNO_PARITY ( ( unsigned portCHAR ) 0x02 << 3 )
|
||||
#define ser8DATA_BITS ( ( unsigned portCHAR ) 0x03 )
|
||||
#define ser1STOP_BIT ( ( unsigned portCHAR ) 0x07 )
|
||||
#define serSYSTEM_CLOCK ( ( unsigned portCHAR ) 0xdd )
|
||||
#define serTX_ENABLE ( ( unsigned portCHAR ) 0x04 )
|
||||
#define serRX_ENABLE ( ( unsigned portCHAR ) 0x01 )
|
||||
#define serTX_INT ( ( unsigned portCHAR ) 0x01 )
|
||||
#define serRX_INT ( ( unsigned portCHAR ) 0x02 )
|
||||
|
||||
|
||||
/* The queues used to communicate between tasks and ISR's. */
|
||||
static xQueueHandle xRxedChars;
|
||||
static xQueueHandle xCharsForTx;
|
||||
|
||||
/* Flag used to indicate the tx status. */
|
||||
static portBASE_TYPE xTxHasEnded = pdTRUE;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
const unsigned portLONG ulBaudRateDivisor = ( configCPU_CLOCK_HZ / ( 32UL * ulWantedBaud ) );
|
||||
|
||||
/* Create the queues used by the com test task. */
|
||||
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
|
||||
xTxHasEnded = pdTRUE;
|
||||
|
||||
/* Set the pins to UART mode. */
|
||||
MCF_GPIO_PUAPAR |= MCF_GPIO_PUAPAR_UTXD0_UTXD0;
|
||||
MCF_GPIO_PUAPAR |= MCF_GPIO_PUAPAR_URXD0_URXD0;
|
||||
|
||||
/* Reset the peripheral. */
|
||||
MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
|
||||
MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
|
||||
MCF_UART0_UCR = MCF_UART_UCR_RESET_ERROR;
|
||||
MCF_UART0_UCR = MCF_UART_UCR_RESET_BKCHGINT;
|
||||
MCF_UART0_UCR = MCF_UART_UCR_RESET_MR | MCF_UART_UCR_RX_DISABLED | MCF_UART_UCR_TX_DISABLED;
|
||||
|
||||
/* Configure the UART. */
|
||||
MCF_UART0_UMR1 = serNO_PARITY | ser8DATA_BITS;
|
||||
MCF_UART0_UMR2 = ser1STOP_BIT;
|
||||
MCF_UART0_UCSR = serSYSTEM_CLOCK;
|
||||
|
||||
MCF_UART0_UBG1 = ( unsigned portCHAR ) ( ( ulBaudRateDivisor >> 8UL ) & 0xffUL );
|
||||
MCF_UART0_UBG2 = ( unsigned portCHAR ) ( ulBaudRateDivisor & 0xffUL );
|
||||
|
||||
/* Turn it on. */
|
||||
MCF_UART0_UCR = serTX_ENABLE | serRX_ENABLE;
|
||||
|
||||
/* Configure the interrupt controller. Run the UARTs above the kernel
|
||||
interrupt priority for demo purposes. */
|
||||
MCF_INTC0_ICR13 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) << 3 );
|
||||
MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK13 | 0x01 );
|
||||
|
||||
/* The Tx interrupt is not enabled until there is data to send. */
|
||||
MCF_UART0_UIMR = serRX_INT;
|
||||
|
||||
/* Only a single port is implemented so we don't need to return anything. */
|
||||
return NULL;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Get the next character from the buffer. Return false if no characters
|
||||
are available or arrive before xBlockTime expires. */
|
||||
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
|
||||
{
|
||||
return pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
return pdFALSE;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Return false if after the block time there is no room on the Tx queue. */
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
return pdFAIL;
|
||||
}
|
||||
|
||||
/* A critical section should not be required as xTxHasEnded will not be
|
||||
written to by the ISR if it is already 0 (is this correct?). */
|
||||
if( xTxHasEnded != pdFALSE )
|
||||
{
|
||||
xTxHasEnded = pdFALSE;
|
||||
MCF_UART0_UIMR = serRX_INT | serTX_INT;
|
||||
}
|
||||
|
||||
return pdPASS;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialClose( xComPortHandle xPort )
|
||||
{
|
||||
( void ) xPort;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__declspec(interrupt:0) void vUART0InterruptHandler( void )
|
||||
{
|
||||
unsigned portCHAR ucChar;
|
||||
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, xDoneSomething = pdTRUE;
|
||||
|
||||
while( xDoneSomething != pdFALSE )
|
||||
{
|
||||
xDoneSomething = pdFALSE;
|
||||
|
||||
/* Does the tx buffer contain space? */
|
||||
if( ( MCF_UART0_USR & MCF_UART_USR_TXRDY ) != 0x00 )
|
||||
{
|
||||
/* Are there any characters queued to be sent? */
|
||||
if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE )
|
||||
{
|
||||
/* Send the next char. */
|
||||
MCF_UART0_UTB = ucChar;
|
||||
xDoneSomething = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Turn off the Tx interrupt until such time as another character
|
||||
is being transmitted. */
|
||||
MCF_UART0_UIMR = serRX_INT;
|
||||
xTxHasEnded = pdTRUE;
|
||||
}
|
||||
}
|
||||
|
||||
if( MCF_UART0_USR & MCF_UART_USR_RXRDY )
|
||||
{
|
||||
ucChar = MCF_UART0_URB;
|
||||
xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken );
|
||||
xDoneSomething = pdTRUE;
|
||||
}
|
||||
}
|
||||
|
||||
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
312
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c
Normal file
312
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/startcf.c
Normal file
|
|
@ -0,0 +1,312 @@
|
|||
/*
|
||||
* CF_Startup.c - Default init/startup/termination routines for
|
||||
* Embedded Metrowerks C++
|
||||
*
|
||||
* Copyright © 1993-1998 Metrowerks, Inc. All Rights Reserved.
|
||||
* Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved.
|
||||
*
|
||||
*
|
||||
* THEORY OF OPERATION
|
||||
*
|
||||
* This version of thestartup code is intended for linker relocated
|
||||
* executables. The startup code will assign the stack pointer to
|
||||
* __SP_INIT, assign the address of the data relative base address
|
||||
* to a5, initialize the .bss/.sbss sections to zero, call any
|
||||
* static C++ initializers and then call main. Upon returning from
|
||||
* main it will call C++ destructors and call exit to terminate.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma cplusplus off
|
||||
#endif
|
||||
#pragma PID off
|
||||
#pragma PIC off
|
||||
|
||||
#include "startcf.h"
|
||||
#include "RuntimeConfig.h"
|
||||
|
||||
/* imported data */
|
||||
|
||||
extern unsigned long far _SP_INIT, _SDA_BASE;
|
||||
extern unsigned long far _START_BSS, _END_BSS;
|
||||
extern unsigned long far _START_SBSS, _END_SBSS;
|
||||
extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
|
||||
|
||||
/* imported routines */
|
||||
|
||||
extern void __call_static_initializers(void);
|
||||
extern int main(int, char **);
|
||||
extern void exit(int);
|
||||
|
||||
/* exported routines */
|
||||
|
||||
extern void _ExitProcess(void);
|
||||
extern asm void _startup(void);
|
||||
extern void __initialize_hardware(void);
|
||||
extern void __initialize_system(void);
|
||||
|
||||
|
||||
/*
|
||||
* Dummy routine for initializing hardware. For user's custom systems, you
|
||||
* can create your own routine of the same name that will perform HW
|
||||
* initialization. The linker will do the right thing to ignore this
|
||||
* definition and use the version in your file.
|
||||
*/
|
||||
#pragma overload void __initialize_hardware(void);
|
||||
void __initialize_hardware(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Dummy routine for initializing systems. For user's custom systems,
|
||||
* you can create your own routine of the same name that will perform
|
||||
* initialization. The linker will do the right thing to ignore this
|
||||
* definition and use the version in your file.
|
||||
*/
|
||||
#pragma overload void __initialize_system(void);
|
||||
void __initialize_system(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Dummy routine for initializing C++. This routine will get overloaded by the C++ runtime.
|
||||
*/
|
||||
#pragma overload void __call_static_initializers(void);
|
||||
void __call_static_initializers(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine to copy a single section from ROM to RAM ...
|
||||
*/
|
||||
static __declspec(register_abi) void __copy_rom_section(char* dst, const char* src, unsigned long size)
|
||||
{
|
||||
if (dst != src)
|
||||
while (size--)
|
||||
*dst++ = *src++;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine that copies all sections the user marked as ROM into
|
||||
* their target RAM addresses ...
|
||||
*
|
||||
* __S_romp is automatically generated by the linker if it
|
||||
* is referenced by the program. It is a table of RomInfo
|
||||
* structures. The final entry in the table has all-zero
|
||||
* fields.
|
||||
*/
|
||||
static void __copy_rom_sections_to_ram(void)
|
||||
{
|
||||
RomInfo *info;
|
||||
|
||||
/*
|
||||
* Go through the entire table, copying sections from ROM to RAM.
|
||||
*/
|
||||
for (info = _S_romp; info->Source != 0L || info->Target != 0L || info->Size != 0; ++info)
|
||||
__copy_rom_section( (char *)info->Target,(char *)info->Source, info->Size);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Exit handler called from the exit routine, if your OS needs
|
||||
* to do something special for exit handling just replace this
|
||||
* routines with what the OS needs to do ...
|
||||
*/
|
||||
asm void _ExitProcess(void)
|
||||
{
|
||||
illegal
|
||||
rts
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine to clear out blocks of memory should give good
|
||||
* performance regardless of 68k or ColdFire part.
|
||||
*/
|
||||
static __declspec(register_abi) void clear_mem(char *dst, unsigned long n)
|
||||
{
|
||||
unsigned long i;
|
||||
long *lptr;
|
||||
|
||||
if (n >= 32)
|
||||
{
|
||||
/* align start address to a 4 byte boundary */
|
||||
i = (- (unsigned long) dst) & 3;
|
||||
|
||||
if (i)
|
||||
{
|
||||
n -= i;
|
||||
do
|
||||
*dst++ = 0;
|
||||
while (--i);
|
||||
}
|
||||
|
||||
/* use an unrolled loop to zero out 32byte blocks */
|
||||
i = n >> 5;
|
||||
if (i)
|
||||
{
|
||||
lptr = (long *)dst;
|
||||
dst += i * 32;
|
||||
do
|
||||
{
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
*lptr++ = 0;
|
||||
}
|
||||
while (--i);
|
||||
}
|
||||
i = (n & 31) >> 2;
|
||||
|
||||
/* handle any 4 byte blocks left */
|
||||
if (i)
|
||||
{
|
||||
lptr = (long *)dst;
|
||||
dst += i * 4;
|
||||
do
|
||||
*lptr++ = 0;
|
||||
while (--i);
|
||||
}
|
||||
n &= 3;
|
||||
}
|
||||
|
||||
/* handle any byte blocks left */
|
||||
if (n)
|
||||
do
|
||||
*dst++ = 0;
|
||||
while (--n);
|
||||
}
|
||||
|
||||
/*
|
||||
* Startup routine for embedded application ...
|
||||
*/
|
||||
|
||||
asm void _startup(void)
|
||||
{
|
||||
/* disable interrupts */
|
||||
move.w #0x2700,sr
|
||||
|
||||
/* Pre-init SP, in case memory for stack is not valid it should be setup using
|
||||
MEMORY_INIT before __initialize_hardware is called
|
||||
*/
|
||||
lea __SP_AFTER_RESET,a7;
|
||||
|
||||
/* initialize memory */
|
||||
MEMORY_INIT
|
||||
|
||||
/* initialize any hardware specific issues */
|
||||
jsr __initialize_hardware
|
||||
|
||||
/* setup the stack pointer */
|
||||
lea _SP_INIT,a7
|
||||
|
||||
/* setup A6 dummy stackframe */
|
||||
movea.l #0,a6
|
||||
link a6,#0
|
||||
|
||||
/* setup A5 */
|
||||
lea _SDA_BASE,a5
|
||||
|
||||
|
||||
/* zero initialize the .bss section */
|
||||
|
||||
lea _END_BSS, a0
|
||||
lea _START_BSS, a1
|
||||
suba.l a1, a0
|
||||
move.l a0, d0
|
||||
|
||||
beq __skip_bss__
|
||||
|
||||
lea _START_BSS, a0
|
||||
|
||||
/* call clear_mem with base pointer in a0 and size in d0 */
|
||||
jsr clear_mem
|
||||
|
||||
__skip_bss__:
|
||||
|
||||
/* zero initialize the .sbss section */
|
||||
|
||||
lea _END_SBSS, a0
|
||||
lea _START_SBSS, a1
|
||||
suba.l a1, a0
|
||||
move.l a0, d0
|
||||
|
||||
beq __skip_sbss__
|
||||
|
||||
lea _START_SBSS, a0
|
||||
|
||||
/* call clear_mem with base pointer in a0 and size in d0 */
|
||||
jsr clear_mem
|
||||
|
||||
__skip_sbss__:
|
||||
|
||||
/* copy all ROM sections to their RAM locations ... */
|
||||
#if SUPPORT_ROM_TO_RAM
|
||||
|
||||
/*
|
||||
* _S_romp is a null terminated array of
|
||||
* typedef struct RomInfo {
|
||||
* unsigned long Source;
|
||||
* unsigned long Target;
|
||||
* unsigned long Size;
|
||||
* } RomInfo;
|
||||
*
|
||||
* Watch out if you're rebasing using _PICPID_DELTA
|
||||
*/
|
||||
|
||||
lea _S_romp, a0
|
||||
move.l a0, d0
|
||||
beq __skip_rom_copy__
|
||||
jsr __copy_rom_sections_to_ram
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* There's a single block to copy from ROM to RAM, perform
|
||||
* the copy directly without using the __S_romp structure
|
||||
*/
|
||||
|
||||
lea __DATA_RAM, a0
|
||||
lea __DATA_ROM, a1
|
||||
|
||||
cmpa a0,a1
|
||||
beq __skip_rom_copy__
|
||||
|
||||
move.l #__DATA_END, d0
|
||||
sub.l a0, d0
|
||||
|
||||
jsr __copy_rom_section
|
||||
|
||||
#endif
|
||||
__skip_rom_copy__:
|
||||
|
||||
/* call C++ static initializers (__sinit__(void)) */
|
||||
jsr __call_static_initializers
|
||||
|
||||
jsr __initialize_system
|
||||
|
||||
/* call main(int, char **) */
|
||||
pea __argv
|
||||
clr.l -(sp) /* clearing a long is ok since it's caller cleanup */
|
||||
jsr main
|
||||
addq.l #8, sp
|
||||
|
||||
unlk a6
|
||||
|
||||
/* now call exit(0) to terminate the application */
|
||||
clr.l -(sp)
|
||||
jsr exit
|
||||
addq.l #4, sp
|
||||
|
||||
/* should never reach here but just in case */
|
||||
illegal
|
||||
rts
|
||||
|
||||
/* exit will never return */
|
||||
__argv:
|
||||
dc.l 0
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/******************************************************************************
|
||||
FILE : startcf.h
|
||||
PURPOSE : startup code for ColdFire
|
||||
LANGUAGE: C
|
||||
|
||||
|
||||
Notes:
|
||||
1) Default entry point is _startup.
|
||||
. disable interrupts
|
||||
. the SP is set to __SP_AFTER_RESET
|
||||
. SP must be initialized to valid memory
|
||||
in case the memory it points to is not valid using MEMORY_INIT macro
|
||||
2) __initialize_hardware is called. Here you can initialize memory and some peripherics
|
||||
at this point global variables are not initialized yet
|
||||
3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform
|
||||
needed initialisations for the language (clear memory, data rom copy).
|
||||
4) void __initialize_system(void); is called
|
||||
to allow additional hardware initialization (UART, GPIOs, etc...)
|
||||
5) Jump to main
|
||||
|
||||
*/
|
||||
/********************************************************************************/
|
||||
|
||||
#ifndef STARTCF_H
|
||||
#define STARTCF_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "support_common.h"
|
||||
|
||||
extern unsigned long far __SP_INIT[];
|
||||
extern unsigned long far __SP_AFTER_RESET[];
|
||||
|
||||
|
||||
#ifndef MEMORY_INIT
|
||||
/* If MEMORY_INIT is set then it performs
|
||||
minimal memory initialization (to preset SP to __SP_AFTER_RESET, etc...)
|
||||
*/
|
||||
#define MEMORY_INIT
|
||||
#endif
|
||||
|
||||
|
||||
void _startup(void);
|
||||
|
||||
#ifndef SUPPORT_ROM_TO_RAM
|
||||
/*
|
||||
* If SUPPORT_ROM_TO_RAM is set, _S_romp is used to define the copy to be performed.
|
||||
* If it is not set, there's a single block to copy, performed directly without
|
||||
* using the __S_romp structure, based on __DATA_RAM, __DATA_ROM and
|
||||
* __DATA_END symbols.
|
||||
*
|
||||
* Set to 0 for more aggressive dead stripping ...
|
||||
*/
|
||||
#define SUPPORT_ROM_TO_RAM 1
|
||||
#endif
|
||||
|
||||
/* format of the ROM table info entry ... */
|
||||
typedef struct RomInfo {
|
||||
void *Source;
|
||||
void *Target;
|
||||
unsigned long Size;
|
||||
} RomInfo;
|
||||
|
||||
/* imported data */
|
||||
extern far RomInfo _S_romp[]; /* linker defined symbol */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
509
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c
Normal file
509
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.c
Normal file
|
|
@ -0,0 +1,509 @@
|
|||
/* FILENAME: stdlib.c
|
||||
*
|
||||
* Functions normally found in a standard C lib.
|
||||
*
|
||||
* 12/28/2005 - added memcmp and memmove
|
||||
*
|
||||
* Notes: These functions support ASCII only!!!
|
||||
*/
|
||||
|
||||
#include "support_common.h"
|
||||
#include "stdlib.h"
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Misc. Defines
|
||||
*/
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
#define FALSE (0)
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
#define TRUE (1)
|
||||
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL (0)
|
||||
|
||||
#ifdef ON
|
||||
#undef ON
|
||||
#endif
|
||||
#define ON (1)
|
||||
|
||||
#ifdef OFF
|
||||
#undef OFF
|
||||
#endif
|
||||
#define OFF (0)
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
isspace (int ch)
|
||||
{
|
||||
if ((ch == ' ') || (ch == '\t')) /* \n ??? */
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
isalnum (int ch)
|
||||
{
|
||||
/* ASCII only */
|
||||
if (((ch >= '0') && (ch <= '9')) ||
|
||||
((ch >= 'A') && (ch <= 'Z')) ||
|
||||
((ch >= 'a') && (ch <= 'z')))
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
isdigit (int ch)
|
||||
{
|
||||
/* ASCII only */
|
||||
if ((ch >= '0') && (ch <= '9'))
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
isupper (int ch)
|
||||
{
|
||||
/* ASCII only */
|
||||
if ((ch >= 'A') && (ch <= 'Z'))
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strcasecmp (const char *s1, const char *s2)
|
||||
{
|
||||
char c1, c2;
|
||||
int result = 0;
|
||||
|
||||
while (result == 0)
|
||||
{
|
||||
c1 = *s1++;
|
||||
c2 = *s2++;
|
||||
if ((c1 >= 'a') && (c1 <= 'z'))
|
||||
c1 = (char)(c1 - ' ');
|
||||
if ((c2 >= 'a') && (c2 <= 'z'))
|
||||
c2 = (char)(c2 - ' ');
|
||||
if ((result = (c1 - c2)) != 0)
|
||||
break;
|
||||
if ((c1 == 0) || (c2 == 0))
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
stricmp (const char *s1, const char *s2)
|
||||
{
|
||||
return (strcasecmp(s1, s2));
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strncasecmp (const char *s1, const char *s2, int n)
|
||||
{
|
||||
char c1, c2;
|
||||
int k = 0;
|
||||
int result = 0;
|
||||
|
||||
while ( k++ < n )
|
||||
{
|
||||
c1 = *s1++;
|
||||
c2 = *s2++;
|
||||
if ((c1 >= 'a') && (c1 <= 'z'))
|
||||
c1 = (char)(c1 - ' ');
|
||||
if ((c2 >= 'a') && (c2 <= 'z'))
|
||||
c2 = (char)(c2 - ' ');
|
||||
if ((result = (c1 - c2)) != 0)
|
||||
break;
|
||||
if ((c1 == 0) || (c2 == 0))
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strnicmp (const char *s1, const char *s2, int n)
|
||||
{
|
||||
return (strncasecmp(s1, s2, n));
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
uint32
|
||||
strtoul (char *str, char **ptr, int base)
|
||||
{
|
||||
unsigned long rvalue = 0;
|
||||
int neg = 0;
|
||||
int c;
|
||||
|
||||
/* Validate parameters */
|
||||
if ((str != NULL) && (base >= 0) && (base <= 36))
|
||||
{
|
||||
/* Skip leading white spaces */
|
||||
while (isspace(*str))
|
||||
{
|
||||
++str;
|
||||
}
|
||||
|
||||
/* Check for notations */
|
||||
switch (str[0])
|
||||
{
|
||||
case '0':
|
||||
if (base == 0)
|
||||
{
|
||||
if ((str[1] == 'x') || (str[1] == 'X'))
|
||||
{
|
||||
base = 16;
|
||||
str += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
base = 8;
|
||||
str++;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case '-':
|
||||
neg = 1;
|
||||
str++;
|
||||
break;
|
||||
|
||||
case '+':
|
||||
str++;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (base == 0)
|
||||
base = 10;
|
||||
|
||||
/* Valid "digits" are 0..9, A..Z, a..z */
|
||||
while (isalnum(c = *str))
|
||||
{
|
||||
/* Convert char to num in 0..36 */
|
||||
if ((c -= ('a' - 10)) < 10) /* 'a'..'z' */
|
||||
{
|
||||
if ((c += ('a' - 'A')) < 10) /* 'A'..'Z' */
|
||||
{
|
||||
c += ('A' - '0' - 10); /* '0'..'9' */
|
||||
}
|
||||
}
|
||||
|
||||
/* check c against base */
|
||||
if (c >= base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if (neg)
|
||||
{
|
||||
rvalue = (rvalue * base) - c;
|
||||
}
|
||||
else
|
||||
{
|
||||
rvalue = (rvalue * base) + c;
|
||||
}
|
||||
|
||||
++str;
|
||||
}
|
||||
}
|
||||
|
||||
/* Upon exit, 'str' points to the character at which valid info */
|
||||
/* STOPS. No chars including and beyond 'str' are used. */
|
||||
|
||||
if (ptr != NULL)
|
||||
*ptr = str;
|
||||
|
||||
return rvalue;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
atoi (const char *str)
|
||||
{
|
||||
char *s = (char *)str;
|
||||
|
||||
return ((int)strtoul(s, NULL, 10));
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strlen (const char *str)
|
||||
{
|
||||
char *s = (char *)str;
|
||||
int len = 0;
|
||||
|
||||
if (s == NULL)
|
||||
return 0;
|
||||
|
||||
while (*s++ != '\0')
|
||||
++len;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strcat (char *dest, const char *src)
|
||||
{
|
||||
char *dp;
|
||||
char *sp = (char *)src;
|
||||
|
||||
if ((dest != NULL) && (src != NULL))
|
||||
{
|
||||
dp = &dest[strlen(dest)];
|
||||
|
||||
while (*sp != '\0')
|
||||
{
|
||||
*dp++ = *sp++;
|
||||
}
|
||||
*dp = '\0';
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strncat (char *dest, const char *src, int n)
|
||||
{
|
||||
char *dp;
|
||||
char *sp = (char *)src;
|
||||
|
||||
if ((dest != NULL) && (src != NULL) && (n > 0))
|
||||
{
|
||||
dp = &dest[strlen(dest)];
|
||||
|
||||
while ((*sp != '\0') && (n-- > 0))
|
||||
{
|
||||
*dp++ = *sp++;
|
||||
}
|
||||
*dp = '\0';
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strcpy (char *dest, const char *src)
|
||||
{
|
||||
char *dp = (char *)dest;
|
||||
char *sp = (char *)src;
|
||||
|
||||
if ((dest != NULL) && (src != NULL))
|
||||
{
|
||||
while (*sp != '\0')
|
||||
{
|
||||
*dp++ = *sp++;
|
||||
}
|
||||
*dp = '\0';
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strncpy (char *dest, const char *src, int n)
|
||||
{
|
||||
char *dp = (char *)dest;
|
||||
char *sp = (char *)src;
|
||||
|
||||
if ((dest != NULL) && (src != NULL) && (n > 0))
|
||||
{
|
||||
while ((*sp != '\0') && (n-- > 0))
|
||||
{
|
||||
*dp++ = *sp++;
|
||||
}
|
||||
*dp = '\0';
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strcmp (const char *s1, const char *s2)
|
||||
{
|
||||
/* No checks for NULL */
|
||||
char *s1p = (char *)s1;
|
||||
char *s2p = (char *)s2;
|
||||
|
||||
while (*s2p != '\0')
|
||||
{
|
||||
if (*s1p != *s2p)
|
||||
break;
|
||||
|
||||
++s1p;
|
||||
++s2p;
|
||||
}
|
||||
return (*s1p - *s2p);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
strncmp (const char *s1, const char *s2, int n)
|
||||
{
|
||||
/* No checks for NULL */
|
||||
char *s1p = (char *)s1;
|
||||
char *s2p = (char *)s2;
|
||||
|
||||
if (n <= 0)
|
||||
return 0;
|
||||
|
||||
while (*s2p != '\0')
|
||||
{
|
||||
if (*s1p != *s2p)
|
||||
break;
|
||||
|
||||
if (--n == 0)
|
||||
break;
|
||||
|
||||
++s1p;
|
||||
++s2p;
|
||||
}
|
||||
return (*s1p - *s2p);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strstr(const char *s1, const char *s2)
|
||||
{
|
||||
char *sp = (char *)s1;
|
||||
int len1 = strlen(s1);
|
||||
int len2 = strlen(s2);
|
||||
|
||||
while (len1 >= len2)
|
||||
{
|
||||
if (strncmp(sp, s2, len2) == 0)
|
||||
{
|
||||
return (sp);
|
||||
}
|
||||
++sp;
|
||||
--len1;
|
||||
}
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
char *
|
||||
strchr(const char *str, int c)
|
||||
{
|
||||
char *sp = (char *)str;
|
||||
char ch = (char)(c & 0xff);
|
||||
|
||||
while (*sp != '\0')
|
||||
{
|
||||
if (*sp == ch)
|
||||
{
|
||||
return (sp);
|
||||
}
|
||||
++sp;
|
||||
}
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
void *
|
||||
memcpy (void *dest, const void *src, unsigned n)
|
||||
{
|
||||
unsigned char *dbp = (unsigned char *)dest;
|
||||
unsigned char *sbp = (unsigned char *)src;
|
||||
|
||||
if ((dest != NULL) && (src != NULL) && (n > 0))
|
||||
{
|
||||
while (n--)
|
||||
*dbp++ = *sbp++;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
void *
|
||||
memset (void *s, int c, unsigned n)
|
||||
{
|
||||
/* Not optimized, but very portable */
|
||||
unsigned char *sp = (unsigned char *)s;
|
||||
|
||||
if ((s != NULL) && (n > 0))
|
||||
{
|
||||
while (n--)
|
||||
{
|
||||
*sp++ = (unsigned char)c;
|
||||
}
|
||||
}
|
||||
return s;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
int
|
||||
memcmp (const void *s1, const void *s2, unsigned n)
|
||||
{
|
||||
unsigned char *s1p, *s2p;
|
||||
|
||||
if (s1 && s2 && (n > 0))
|
||||
{
|
||||
s1p = (unsigned char *)s1;
|
||||
s2p = (unsigned char *)s2;
|
||||
|
||||
while ((--n >= 0) && (*s1p == *s2p))
|
||||
{
|
||||
if (*s1p != *s2p)
|
||||
return (*s1p - *s2p);
|
||||
++s1p;
|
||||
++s2p;
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
void *
|
||||
memmove (void *dest, const void *src, unsigned n)
|
||||
{
|
||||
unsigned char *dbp = (unsigned char *)dest;
|
||||
unsigned char *sbp = (unsigned char *)src;
|
||||
unsigned char *dend = dbp + n;
|
||||
unsigned char *send = sbp + n;
|
||||
|
||||
if ((dest != NULL) && (src != NULL) && (n > 0))
|
||||
{
|
||||
/* see if a memcpy would overwrite source buffer */
|
||||
if ((sbp < dbp) && (dbp < send))
|
||||
{
|
||||
while (n--)
|
||||
*(--dend) = *(--send);
|
||||
}
|
||||
else
|
||||
{
|
||||
while (n--)
|
||||
*dbp++ = *sbp++;
|
||||
}
|
||||
}
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
/****************************************************************/
|
||||
79
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h
Normal file
79
20091005/Demo/ColdFire_MCF52221_CodeWarrior/sources/stdlib.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* File: stdlib.h
|
||||
* Purpose: Function prototypes for standard library functions
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _STDLIB_H
|
||||
#define _STDLIB_H
|
||||
|
||||
/********************************************************************
|
||||
* Standard library functions
|
||||
********************************************************************/
|
||||
|
||||
int
|
||||
isspace (int);
|
||||
|
||||
int
|
||||
isalnum (int);
|
||||
|
||||
int
|
||||
isdigit (int);
|
||||
|
||||
int
|
||||
isupper (int);
|
||||
|
||||
int
|
||||
strcasecmp (const char *, const char *);
|
||||
|
||||
int
|
||||
strncasecmp (const char *, const char *, int);
|
||||
|
||||
unsigned long
|
||||
strtoul (char *, char **, int);
|
||||
|
||||
int
|
||||
strlen (const char *);
|
||||
|
||||
char *
|
||||
strcat (char *, const char *);
|
||||
|
||||
char *
|
||||
strncat (char *, const char *, int);
|
||||
|
||||
char *
|
||||
strcpy (char *, const char *);
|
||||
|
||||
char *
|
||||
strncpy (char *, const char *, int);
|
||||
|
||||
int
|
||||
strcmp (const char *, const char *);
|
||||
|
||||
int
|
||||
strncmp (const char *, const char *, int);
|
||||
|
||||
void *
|
||||
memcpy (void *, const void *, unsigned);
|
||||
|
||||
void *
|
||||
memset (void *, int, unsigned);
|
||||
|
||||
void
|
||||
free (void *);
|
||||
|
||||
void *
|
||||
malloc (unsigned);
|
||||
|
||||
#define RAND_MAX 32767
|
||||
|
||||
int
|
||||
rand (void);
|
||||
|
||||
void
|
||||
srand (int);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* File: support_common.h
|
||||
* Purpose: Various project configurations.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _SUPPORT_COMMON_H_
|
||||
#define _SUPPORT_COMMON_H_
|
||||
|
||||
/* Enable UART Support. */
|
||||
#define ENABLE_UART_SUPPORT 0
|
||||
|
||||
|
||||
#define MEMORY_INIT \
|
||||
/* Initialize RAMBAR: locate SRAM and validate it */ \
|
||||
move.l %#__RAMBAR + 0x21,d0; \
|
||||
movec d0,RAMBAR;
|
||||
|
||||
#define SUPPORT_ROM_TO_RAM 1
|
||||
|
||||
/*
|
||||
* Include the derivative header files
|
||||
*/
|
||||
#include "MCF52221.h"
|
||||
|
||||
/*
|
||||
* Include the board specific header files
|
||||
*/
|
||||
#include "MCF52221_sysinit.h"
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _SUPPORT_COMMON_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* File: uart_support.c
|
||||
* Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed
|
||||
* for MSL Support (printf\cout to terminal), defined in <UART.h>
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
#include "support_common.h"
|
||||
#include "uart_support.h"
|
||||
|
||||
#if ENABLE_UART_SUPPORT==1
|
||||
|
||||
|
||||
#if UART_SUPPORT_TYPE==UART_PSC
|
||||
/* 5475 & 5485 boards have different names for uart access registers */
|
||||
void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate)
|
||||
{
|
||||
register uint16 ubgs;
|
||||
|
||||
/*
|
||||
* On Verdi, only PSC 0 & 1 are brought out to RS232 transceivers
|
||||
*/
|
||||
|
||||
/* Put PSC in UART mode */
|
||||
MCF_PSC_PSCSICR(channel) = MCF_PSC_PSCSICR_SIM_UART;
|
||||
|
||||
/* Rx and Tx baud rate from timers */
|
||||
MCF_PSC_PSCCSR(channel) = (0
|
||||
| MCF_PSC_PSCCSR_RCSEL_SYS_CLK
|
||||
| MCF_PSC_PSCCSR_TCSEL_SYS_CLK);
|
||||
|
||||
/*
|
||||
* Calculate baud settings
|
||||
*/
|
||||
ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32));
|
||||
|
||||
MCF_PSC_PSCCTUR(channel) = (uint8) ((ubgs >> 8) & 0xFF);
|
||||
MCF_PSC_PSCCTLR(channel) = (uint8) (ubgs & 0xFF);
|
||||
|
||||
/* Reset transmitter, receiver, mode register, and error conditions */
|
||||
MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_RX;
|
||||
MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_TX;
|
||||
MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_ERROR;
|
||||
MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_BKCHGINT;
|
||||
MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_MR;
|
||||
|
||||
/* 8-bit data, no parity */
|
||||
MCF_PSC_PSCMR(channel) = (0
|
||||
#ifdef UART_HARDWARE_FLOW_CONTROL
|
||||
| MCF_PSC_PSCMR_RXRTS
|
||||
#endif
|
||||
| MCF_PSC_PSCMR_PM_NONE
|
||||
| MCF_PSC_PSCMR_BC_8);
|
||||
|
||||
/* No echo or loopback, 1 stop bit */
|
||||
MCF_PSC_PSCMR(channel) = (0
|
||||
#ifdef UART_HARDWARE_FLOW_CONTROL
|
||||
| MCF_PSC_PSCMR_TXCTS
|
||||
#endif
|
||||
| MCF_PSC_PSCMR_CM_NORMAL
|
||||
| MCF_PSC_PSCMR_SB_STOP_BITS_1);
|
||||
|
||||
/* Mask all UART interrupts */
|
||||
MCF_PSC_PSCIMR(channel) = 0x0000;
|
||||
|
||||
/* Enable RTS to send */
|
||||
MCF_PSC_PSCOPSET(channel) = MCF_PSC_PSCOPSET_RTS;
|
||||
|
||||
/* Setup FIFO Alarms */
|
||||
MCF_PSC_PSCRFAR(channel) = MCF_PSC_PSCRFAR_ALARM(248);
|
||||
MCF_PSC_PSCTFAR(channel) = MCF_PSC_PSCTFAR_ALARM(248);
|
||||
|
||||
/* Enable receiver and transmitter */
|
||||
MCF_PSC_PSCCR(channel) =(0
|
||||
| MCF_PSC_PSCCR_RX_ENABLED
|
||||
| MCF_PSC_PSCCR_TX_ENABLED);
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for a character to be received on the specified UART
|
||||
*
|
||||
* Return Values:
|
||||
* the received character
|
||||
*/
|
||||
char uart_getchar (int channel)
|
||||
{
|
||||
/* Wait until character has been received */
|
||||
while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_RXRDY))
|
||||
{
|
||||
|
||||
}
|
||||
return (char)(*((uint8 *) &MCF_PSC_PSCRB_8BIT(channel)));
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for space in the UART Tx FIFO and then send a character
|
||||
*/
|
||||
void uart_putchar (int channel, char ch)
|
||||
{
|
||||
/* Wait until space is available in the FIFO */
|
||||
while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_TXRDY))
|
||||
;
|
||||
*((uint8 *) &MCF_PSC_PSCTB_8BIT(channel)) = (uint8)ch;
|
||||
}
|
||||
|
||||
|
||||
#else /* UART_SUPPORT_TYPE==UART_PSC */
|
||||
|
||||
#if UART_SUPPORT_TYPE == UART_5407
|
||||
/********************************************************************/
|
||||
/*
|
||||
* 5407 derivative doesn't have macros to access URB/UTB by channel number
|
||||
* because they have different sizes for UART0 & UART1
|
||||
* But in UART mode only 8 bits of UART1 URB/UTB is used, so define these macros here
|
||||
* if they doesn't defined before
|
||||
*/
|
||||
#ifndef MCF_UART_URB
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)]))
|
||||
#endif /* MCF_UART_URB */
|
||||
|
||||
#ifndef MCF_UART_UTB
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)]))
|
||||
#endif /* MCF_UART_UTB */
|
||||
|
||||
#endif /* UART_SUPPORT_TYPE == UART_5407 */
|
||||
|
||||
void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate)
|
||||
{
|
||||
/*
|
||||
* Initialize UART for serial communications
|
||||
*/
|
||||
|
||||
register uint16 ubgs;
|
||||
|
||||
#if UART_SUPPORT_TYPE==UART_54451
|
||||
uint32 vco;
|
||||
uint32 divider;
|
||||
uint32 bus_clk;
|
||||
|
||||
divider = ((MCF_CLOCK_PCR & 0x000000F0) >> 4) + 1;
|
||||
vco = ((MCF_CLOCK_PCR >> 24) * systemClockKHz * 1000);
|
||||
bus_clk = (vco / divider);
|
||||
#endif
|
||||
/*
|
||||
* Reset Transmitter
|
||||
*/
|
||||
MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_TX;
|
||||
|
||||
/*
|
||||
* Reset Receiver
|
||||
*/
|
||||
MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_RX;
|
||||
|
||||
/*
|
||||
* Reset Mode Register
|
||||
*/
|
||||
MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_MR;
|
||||
|
||||
/*
|
||||
* No parity, 8-bits per character
|
||||
*/
|
||||
MCF_UART_UMR(channel) = (0
|
||||
| MCF_UART_UMR_PM_NONE
|
||||
| MCF_UART_UMR_BC_8 );
|
||||
|
||||
/*
|
||||
* No echo or loopback, 1 stop bit
|
||||
*/
|
||||
MCF_UART_UMR(channel) = (0
|
||||
| MCF_UART_UMR_CM_NORMAL
|
||||
| MCF_UART_UMR_SB_STOP_BITS_1);
|
||||
|
||||
/*
|
||||
* Set Rx and Tx baud by SYSTEM CLOCK
|
||||
*/
|
||||
MCF_UART_UCSR(channel) = (0
|
||||
| MCF_UART_UCSR_RCS_SYS_CLK
|
||||
| MCF_UART_UCSR_TCS_SYS_CLK);
|
||||
|
||||
/*
|
||||
* Mask all UART interrupts
|
||||
*/
|
||||
MCF_UART_UIMR(channel) = 0;
|
||||
|
||||
/*
|
||||
* Calculate baud settings
|
||||
*/
|
||||
#if UART_SUPPORT_TYPE==UART_54451
|
||||
ubgs = (uint16)(((bus_clk >> 5) + (baudRate >> 1)) / baudRate);
|
||||
#else
|
||||
ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32));
|
||||
#endif
|
||||
|
||||
#if UART_SUPPORT_TYPE==UART_DIVIDER || UART_SUPPORT_TYPE == UART_5407
|
||||
MCF_UART_UDU(channel) = (uint8)((ubgs & 0xFF00) >> 8);
|
||||
MCF_UART_UDL(channel) = (uint8)(ubgs & 0x00FF);
|
||||
#else /* UART_SUPPORT_TYPE!=UART_DIVIDER */
|
||||
MCF_UART_UBG1(channel) = (uint8)((ubgs & 0xFF00) >> 8);
|
||||
MCF_UART_UBG2(channel) = (uint8)(ubgs & 0x00FF);
|
||||
#endif /* UART_SUPPORT_TYPE==UART_DIVIDER */
|
||||
|
||||
/*
|
||||
* Enable receiver and transmitter
|
||||
*/
|
||||
MCF_UART_UCR(channel) = (0
|
||||
| MCF_UART_UCR_TX_ENABLED
|
||||
| MCF_UART_UCR_RX_ENABLED);
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for a character to be received on the specified UART
|
||||
*
|
||||
* Return Values:
|
||||
* the received character
|
||||
*/
|
||||
char uart_getchar (int channel)
|
||||
{
|
||||
/* Wait until character has been received */
|
||||
while (!(MCF_UART_USR(channel) & MCF_UART_USR_RXRDY))
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
return (char)MCF_UART_URB(channel);
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for space in the UART Tx FIFO and then send a character
|
||||
*/
|
||||
void uart_putchar (int channel, char ch)
|
||||
{
|
||||
/* Wait until space is available in the FIFO */
|
||||
while (!(MCF_UART_USR(channel) & MCF_UART_USR_TXRDY))
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
/* Send the character */
|
||||
MCF_UART_UTB(channel) = (uint8)ch;
|
||||
}
|
||||
|
||||
#endif /* UART_SUPPORT_TYPE==UART_PSC */
|
||||
/********************************************************************/
|
||||
|
||||
/********************************************************************/
|
||||
/** <UART.h> Neeeded functions **/
|
||||
/********************************************************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
* Implementation for CodeWarror MSL interface to serial device (UART.h).
|
||||
* Needed for printf, etc...
|
||||
* Only InitializeUART, ReadUARTN, and WriteUARTN are implemented.
|
||||
*
|
||||
*/
|
||||
UARTError InitializeUART(UARTBaudRate baudRate)
|
||||
{
|
||||
#if UART_SUPPORT_TYPE==UART_54451
|
||||
baudRate = kBaud115200;
|
||||
#endif
|
||||
uart_init(TERMINAL_PORT, SYSTEM_CLOCK_KHZ, baudRate);
|
||||
return kUARTNoError;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
ReadUARTN
|
||||
|
||||
Read N bytes from the UART.
|
||||
|
||||
bytes pointer to result buffer
|
||||
limit size of buffer and # of bytes to read
|
||||
*/
|
||||
/****************************************************************************/
|
||||
UARTError ReadUARTN(void* bytes, unsigned long limit)
|
||||
{
|
||||
int count;
|
||||
for (count = 0; count < limit; count++) {
|
||||
*( (char *)bytes + count ) = uart_getchar(TERMINAL_PORT);
|
||||
}
|
||||
return kUARTNoError;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
UARTError WriteUARTN(const void* bytes, unsigned long length)
|
||||
{
|
||||
int count;
|
||||
for (count = 0; count < length; count++) {
|
||||
uart_putchar(TERMINAL_PORT, *( ((char *)bytes) + count));
|
||||
}
|
||||
return kUARTNoError;
|
||||
}
|
||||
#endif /* ENABLE_UART_SUPPORT */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* File: uart_support.h
|
||||
* Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed
|
||||
* for MSL Support (printf\cout to terminal), defined in <UART.h>
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __UART_SUPPORT_H__
|
||||
#define __UART_SUPPORT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "support_common.h"
|
||||
|
||||
#if ENABLE_UART_SUPPORT==1
|
||||
|
||||
/*
|
||||
* Include the Freescale UART specific header file for printf/cout/scanf support
|
||||
*/
|
||||
#include <ansi_parms.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <UART.h>
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#define UART_STANDARD 0
|
||||
#define UART_DIVIDER 1
|
||||
#define UART_5407 2
|
||||
#define UART_PSC 3
|
||||
#define UART_54451 4
|
||||
|
||||
#define UART_SUPPORT_TYPE UART_STANDARD
|
||||
|
||||
void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate);
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for a character to be received on the specified UART
|
||||
*
|
||||
* Return Values:
|
||||
* the received character
|
||||
*/
|
||||
char uart_getchar (int channel);
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Wait for space in the UART Tx FIFO and then send a character
|
||||
*/
|
||||
void uart_putchar (int channel, char ch);
|
||||
|
||||
|
||||
#endif /* ENABLE_UART_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __UART_SUPPORT_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue