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Start of SAMA5D3 XPlained demo.

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Richard Barry 2014-07-09 21:19:01 +00:00
parent 8aa5fa3459
commit 5b96c12e92
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53
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_DDRAM_end__ = 0x20FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF;
define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x23000000;
define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x23FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x200;
define symbol __ICFEDIT_size_vectors__ = 0x200;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_sysstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x0;
/*-Exports-*/
export symbol __ICFEDIT_region_DDRAM_start__;
export symbol __ICFEDIT_region_DDRAM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_sysstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__];
define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_DDRAM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in VEC_region { section .vectors };
place in DDRAM_region { readonly };
place in DDRAM_region { readwrite };
place in DDRAM_region { zeroinit };
place in DMA_BUF_region {section region_dma_nocache };
place in DDRAM_region { block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0;
define symbol __ICFEDIT_region_RAM_start__ = 0x70000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x73FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_svcstack__ = 0x0;
define symbol __ICFEDIT_size_irqstack__ = 0x0;
define symbol __ICFEDIT_size_fiqstack__ = 0x0;
define symbol __ICFEDIT_size_undstack__ = 0x0;
define symbol __ICFEDIT_size_abtstack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
//initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ {section .intvec };
place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}};
place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .noinit,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP}};

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/**** start of ICF editor section. ###ICF###*/
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
define symbol __ICFEDIT_region_SRAM0_start__ = 0x00300000;
define symbol __ICFEDIT_region_SRAM0_end__ = 0x0030FFFF;
define symbol __ICFEDIT_region_SRAM1_start__ = 0x00310000;
define symbol __ICFEDIT_region_SRAM1_end__ = 0x0031FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_svcstack__ = 0x40;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region SRAM0 = mem:[from __ICFEDIT_region_SRAM0_start__ to __ICFEDIT_region_SRAM0_end__];
define region SRAM1 = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors };
place in ROM { readonly };
place in SRAM0 { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
define exported symbol fl_ram_end = (__ICFEDIT_region_SRAM0_end__ & 0xFFFFFFF8);

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_sysstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x0;
/*-Exports-*/
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_sysstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing=none { readwrite };
do not initialize { readonly section .noinit };
place in VEC_region { section .vectors };
place in RAM_region { readonly };
place in RAM_region { section .cstartup };
place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \page sama5d3x_ek_board_desc sama5d3-xplained - Board Description
*
* \section Purpose
*
* This file is dedicated to describe the sama5d3-xplained board.
*
* \section Contents
*
* - sama5d3-xplained
* - For sama5d3-xplained information, see \subpage sama5d3x_ek_board_info.
* - For operating frequency information, see \subpage sama5d3x_ek_opfreq.
* - For using portable PIO definitions, see \subpage sama5d3x_ek_piodef.
* - For on-board memories, see \subpage sama5d3x_ek_mem.
* - Several USB definitions are included here, see \subpage sama5d3x_ek_usb.
* - For External components, see \subpage sama5d3x_ek_extcomp.
* - For Individual chip definition, see \subpage sama5d3x_ek_chipdef.
*
* To get more software details and the full list of parameters related to the
* sama5d3-xplained board configuration, please have a look at the source file:
* \ref board.h\n
*
* \section Usage
*
* - The code for booting the board is provided by board_cstartup_xxx.c and
* board_lowlevel.c.
* - For using board PIOs, board characteristics (clock, etc.) and external
* components, see board.h.
* - For manipulating memories, see board_memories.h.
*
* This file can be used as a template and modified to fit a custom board, with
* specific PIOs usage or memory connections.
*/
/**
* \file board.h
*
* Definition of sama5d3-xplained
* characteristics, sama5d3x-dependant PIOs and external components interfacing.
*/
#ifndef _BOARD_
#define _BOARD_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/**
* Libc porting layers
*/
#if defined ( __CC_ARM ) /* Keil uvision 4 */
# include "include/rand.h"
#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
# include "include/rand.h"
#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68/2010q1-188 */
# include "include/rand.h"
# include "include/syscalls.h" /** RedHat Newlib minimal stub */
#endif
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_board_info "sama5d3-xplained - Board informations"
* This page lists several definition related to the board description.
*
* \section Definitions
* - \ref BOARD_NAME
*/
/** Name of the board */
#define BOARD_NAME "sama5d3-xplained"
/** Board definition */
#define sama5d3xek
/** Family definition (already defined) */
#if !defined sama5d3x
#define sama5d3x
#endif
/** Core definition */
#define cortexa5
#define BOARD_XPLAINED
//#define BOARD_EK
//#define BOARD_VB
// #define BOARD_REV_A_EK
// #define BOARD_REV_B_EK
// #define BOARD_REV_C_EK
// #define BOARD_REV_D_EK
// Low cost board
// #define BOARD_LCB
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_opfreq "sama5d3-xplained - Operating frequencies"
* This page lists several definition related to the board operating frequency
* (when using the initialization done by board_lowlevel.c).
*
* \section Definitions
* - \ref BOARD_MAINOSC
* - \ref BOARD_MCK
*/
/** Frequency of the board main oscillator */
#define BOARD_MAINOSC 12000000
/** Master clock frequency (when using board_lowlevel.c) */
#define BOARD_MCK ((unsigned long)((BOARD_MAINOSC / 3 / 2) * 66 ))
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_piodef "sama5d3-xplained - PIO definitions"
* This pages lists all the pio definitions contained in board.h. The constants
* are named using the following convention: PIN_* for a constant which defines
* a single Pin instance (but may include several PIOs sharing the same
* controller), and PINS_* for a list of Pin instances.
*
* DBGU
* - \ref PINS_DBGU
*
* USART0
* - \ref PIN_USART0_TXD
* - \ref PIN_USART0_RXD
* - \ref PIN_USART0_RTS
* - \ref PIN_USART0_CTS
* - \ref PIN_USART0_SCK
*
* TWI0
* - \ref PIN_TWI_TWD0
* - \ref PIN_TWI_TWCK0
* - \ref PINS_TWI0
*
* SPI0
* - \ref PIN_SPI0_MISO
* - \ref PIN_SPI0_MOSI
* - \ref PIN_SPI0_SPCK
* - \ref PIN_SPI0_NPCS0
* - \ref PINS_SPI0
*
* SSC
* - \ref PIN_SSC_TD
* - \ref PIN_SSC_TK
* - \ref PIN_SSC_TF
* - \ref PIN_SSC_RD
* - \ref PIN_SSC_RK
* - \ref PIN_SSC_RF
* - \ref PINS_SSC_CODEC
*
* EMAC0
* - \ref PIN_EMAC0_TXCK
* - \ref PIN_EMAC0_TX0
* - \ref PIN_EMAC0_TX1
* - \ref PIN_EMAC0_TX2
* - \ref PIN_EMAC0_TX3
* - \ref PIN_EMAC0_TXEN
* - \ref PIN_EMAC0_RXER
* - \ref PIN_EMAC0_RXDV
* - \ref PIN_EMAC0_RX0
* - \ref PIN_EMAC0_RX1
* - \ref PIN_EMAC0_RX2
* - \ref PIN_EMAC0_RX3
* - \ref PIN_EMAC0_MDC
* - \ref PIN_EMAC0_MDIO
* - \ref PIN_EMAC0_INTR
* - \ref PINS_EMAC0_MII
* - \ref PINS_EMAC0_RMII
* LCD
* - \ref PINS_LCD
*
* ADC
* - \ref PIN_ADTRG
*
* ISI
* - \ref PIN_ISI_MCK
* - \ref PIN_ISI_VSYNC
* - \ref PIN_ISI_HSYNC
* - \ref PIN_ISI_PCK
* - \ref PIN_ISI_PINS_DATA
* - \ref PINS_ISI
*/
/** List of all DBGU pin definitions. */
/** DBGU Monitor IO pin (detect any DBGU operation). */
#define PIN_DBGU_MON {PIO_PB30A_DRXD, PIOB, ID_PIOB, PIO_INPUT, PIO_IT_RISE_EDGE}
/** DBGU pin definition. */
#define PINS_DBGU {PIO_PB30A_DRXD | PIO_PB31A_DTXD, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** List of all USART pin definitions. */
/** USART0 TXD pin definition. */
#define PIN_USART0_TXD {PIO_PD18A_TXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 RXD pin definition. */
#define PIN_USART0_RXD {PIO_PD17A_RXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 RTS pin definition. */
#define PIN_USART0_RTS {PIO_PD16A_RTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 CTS pin definition. */
#define PIN_USART0_CTS {PIO_PD15A_CTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART0 SCK pin definition. */
#define PIN_USART0_SCK {PIO_PD14A_SCK0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 TXD pin definition. */
#define PIN_USART1_TXD {PIO_PB29A_TXD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 RXD pin definition. */
#define PIN_USART1_RXD {PIO_PB28A_RXD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 RTS pin definition. */
#define PIN_USART1_RTS {PIO_PB27A_RTS1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 CTS pin definition. */
#define PIN_USART1_CTS {PIO_PB26A_CTS1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** USART1 SCK pin definition. */
#define PIN_USART1_SCK {PIO_PB25A_SCK1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** USART2 TXD pin definition. */
#define PIN_USART2_TXD {PIO_PE26B_TXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 RXD pin definition. */
#define PIN_USART2_RXD {PIO_PE25B_RXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 RTS pin definition. */
#define PIN_USART2_RTS {PIO_PE24B_RTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 CTS pin definition. */
#define PIN_USART2_CTS {PIO_PE23B_CTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** USART2 SCK pin definition. */
#define PIN_USART2_SCK {PIO_PE20B_SCK2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}
/** PIN used for reset the smartcard */
#define PIN_ISO7816_RSTMC {1 << 2, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
/** Pins used for connect the smartcard */
#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK, PIN_ISO7816_RSTMC
/** List of all TWI pin definitions. */
/** TWI0 data pin */
#define PIN_TWI_TWD0 {PIO_PA30A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI0 clock pin */
#define PIN_TWI_TWCK0 {PIO_PA31A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
/** TWI0 pins */
#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0
/** TWI1 data pin */
#define PIN_TWI_TWD1 {PIO_PC26B_TWD1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** TWI1 clock pin */
#define PIN_TWI_TWCK1 {PIO_PC27B_TWCK1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** TWI1 pins */
#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1
/** List of all CAN pin deinitions. */
/** CAN0 pin TX */
#define PIN_CAN0_TX {PIO_PD15C_CANTX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
/** CAN0 pin RX */
#define PIN_CAN0_RX {PIO_PD14C_CANRX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT}
/** CAN0 pins */
#define PINS_CAN0 PIN_CAN0_TX, PIN_CAN0_RX
/** CAN1 pin TX */
#define PIN_CAN1_TX {PIO_PB15B_CANTX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** CAN1 pin RX */
#define PIN_CAN1_RX {PIO_PB14B_CANRX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}
/** CAN0 pins */
#define PINS_CAN1 PIN_CAN1_TX, PIN_CAN1_RX
/** List of all SPI pin definitions. */
/** SPI0 MISO pin definition. */
#define PIN_SPI0_MISO {PIO_PD10A_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 MOSI pin definition. */
#define PIN_SPI0_MOSI {PIO_PD11A_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 SPCK pin definition. */
#define PIN_SPI0_SPCK {PIO_PD12A_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI0 chip select pin definition. */
#define PIN_SPI0_NPCS0 {PIO_PD13A_SPI0_NPCS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** List of SPI0 pin definitions (MISO, MOSI & SPCK). */
#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK
/** SPI1 MISO pin definition. */
#define PIN_SPI1_MISO {PIO_PC22A_SPI1_MISO, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 MOSI pin definition. */
#define PIN_SPI1_MOSI {PIO_PC23A_SPI1_MOSI, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 SPCK pin definition. */
#define PIN_SPI1_SPCK {PIO_PC24A_SPI1_SPCK, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SPI1 chip select pin definition. */
#define PIN_SPI1_NPCS0 {PIO_PC25A_SPI1_NPCS0, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** List of SPI1 pin definitions (MISO, MOSI & SPCK). */
#define PINS_SPI1 PIN_SPI1_MISO, PIN_SPI1_MOSI, PIN_SPI1_SPCK
/** List of all SSC pin definitions. */
/** SSC pin Transmitter Data (TD) */
#define PIN_SSC_TD {0x1 << 18, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pin Transmitter Clock (TK) */
#define PIN_SSC_TK {0x1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pin Transmitter FrameSync (TF) */
#define PIN_SSC_TF {0x1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pin RD */
#define PIN_SSC_RD {0x1 << 21, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pin RK */
#define PIN_SSC_RK {0x1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pin RF */
#define PIN_SSC_RF {0x1 << 20, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
/** SSC pins definition for codec. */
#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF, PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF
#define PINS_SSC_HDMI PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF
/** LCD pin list. */
#define PINS_LCD_PIOA {0x3F00FFFF, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
#define PINS_LCD_PIOC {0x0000FC00, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
#define PINS_LCD_PIOE {0x18000000, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT}
#define PINS_LCD PINS_LCD_PIOA, PINS_LCD_PIOC ,PINS_LCD_PIOE
//#define PINS_LCD PINS_LCD_PIOA
/** ADC ADTRG pin (PD19). */
#define PIN_ADTRG {PIO_PD19A_ADTRG, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP}
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_usb "sama5d3-xplained - USB device"
*
* \section Definitions
* - \ref BOARD_USB_BMATTRIBUTES
* - \ref CHIP_USB_UDP
* - \ref CHIP_USB_PULLUP_INTERNAL
* - \ref CHIP_USB_NUMENDPOINTS
* - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE
* - \ref CHIP_USB_ENDPOINTS_BANKS
*/
/** USB VBus pin */
#define PIN_USB_VBUS {PIO_PE9, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** USB OverCurrent detection*/
#define PIN_USB_OVCUR {PIO_PE5, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** USB attributes configuration descriptor (bus or self powered, remote wakeup) */
#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_mem "sama5d3-xplained - Memories"
* This page lists definitions related to internal & external on-board memories.
*
* \section Sdram
*
* - \ref EBI_SDRAM_PINS
*
* \section Nandflash
* - \ref PINS_NANDFLASH
* - \ref BOARD_NF_IO_PINS
* - \ref BOARD_NF_CE_PIN
* - \ref BOARD_NF_RB_PIN
*/
/** Nandflash IO pin definition.*/
#define BOARD_NF_IO_PINS {0, 0, 0, 0, 0}
#define BOARD_NF_CE_PIN {0, 0, 0, 0, 0}
/** Nandflash controller peripheral pins definition. */
#define PINS_NANDFLASH BOARD_NF_IO_PINS
/** Address for transferring command bytes to the nandflash, CLE A22*/
#define BOARD_NF_COMMAND_ADDR 0x60400000
/** Address for transferring address bytes to the nandflash, ALE A21*/
#define BOARD_NF_ADDRESS_ADDR 0x60200000
/** Address for transferring data bytes to the nandflash.*/
#define BOARD_NF_DATA_ADDR 0x60000000
/** Address for transferring command bytes to the norflash. */
#define BOARD_NORFLASH_ADDR 0x10000000
/** Default NOR bus size after power up reset */
#define BOARD_NORFLASH_DFT_BUS_SIZE 16
/** Ddram type */
#define DDRAM_MT47H64M16HR 0
#define DDRAM_MT47H128M16RT 1
#define BOARD_DDRAM_TYPE DDRAM_MT47H128M16RT
/** PHY address */
#define BOARD_EMAC_PHY_ADDR 1
/** PHY Component */
#define BOARD_EMAC_PHY_COMP_KSZ8051RNL 1
/** Board EMAC power control - ALWAYS ON */
#define BOARD_EMAC_POWER_ALWAYS_ON
/** Board EMAC work mode - RMII/MII ( 1 / 0 ) */
#define BOARD_EMAC_MODE_RMII 1
/** The PIN list of PIO for EMAC */
#define BOARD_EMAC_PINS {0x3FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT},\
{(1<<12),PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP}
/** The runtime pin configure list for EMAC */
#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS
/** PHY address */
#define BOARD_GMAC_PHY_ADDR 7
#define BOARD_GMAC_PHY_COMP_KSZ9021RNL 1
#define BOARD_GMAC_POWER_ALWAYS_ON
#define BOARD_GMAC_MODE_RGMII 1
/** The PIN list of PIO for GMAC 0x7FFFF 0x73BFF */
#define BOARD_GMAC_PINS {0x73BFF, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT},\
{(1<<25),PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP}
#define BOARD_GMAC_MODE_PINS {0xF0, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}
/** The runtime pin configure list for EMAC */
#define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_extcomp "sama5d3-xplained - External components"
* This page lists the definitions related to external on-board components
* located in the board.h file for the sama5d3-xplained.
*
* \section board_sdmmc SD/MMC
* - \ref BOARD_MCI0_PINS
* - \ref BOARD_MCI0_PIN_CD
* - \ref BOARD_MCI1_PINS
* - \ref BOARD_MCI1_PIN_CD
* - \ref BOARD_NUM_MCI
*
* \section board_emac EMAC
* - \ref BOARD_EMAC_RST_PINS
* - \ref BOARD_EMAC_PHY_ADDR
* - \ref BOARD_EMAC_RUN_PINS
*
* \section board_lcd LCD Properties
* - \ref BOARD_LCD_WIDTH
* - \ref BOARD_LCD_HEIGHT
* - \ref BOARD_LCD_IFWIDTH
* - \ref BOARD_LCD_FRAMESIZE
* - \ref BOARD_LCD_TIMING_VFP
* - \ref BOARD_LCD_TIMING_VBP
* - \ref BOARD_LCD_TIMING_VPW
* - \ref BOARD_LCD_TIMING_HFP
* - \ref BOARD_LCD_TIMING_HBP
* - \ref BOARD_LCD_TIMING_HPW
* - \ref BOARD_LCD_FRAMERATE
* - \ref BOARD_LCD_PIXELCLOCK
*
* \section board_ts Touchscreen ADC Properties
* - \ref BOARD_TOUCHSCREEN_ADCCLK
* - \ref BOARD_TOUCHSCREEN_STARTUP
* - \ref BOARD_TOUCHSCREEN_SHTIM
* - \ref BOARD_TOUCHSCREEN_DEBOUNCE
*/
/** MCI0 Card detect pin definition. (PE0) */
#define BOARD_MCI0_PIN_CD {PIO_PE0, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** MCI0 has no WriteProtect pin */
/** MCI1 Card detect pin definition. (PE1) */
#define BOARD_MCI1_PIN_CD {PIO_PE1, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}
/** MCI1 Write Protect pin Always to GND */
/** MCI0 power control. */
#define BOARD_MCI0_PIN_POWER {PIO_PE2, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_PULLUP}
/** Total number of MCI interface */
#define BOARD_NUM_MCI 2
/** MCI0 IO pins definition. (PD0-PD9) */
#define BOARD_MCI0_PINS {0x3FF, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}
/** MCI1 IO pins definition. (PA2-PA4, PA11-PA13) */
#define BOARD_MCI1_PINS {0x1F80000, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
/** Display width in pixels. */
#define BOARD_LCD_WIDTH 800
/** Display height in pixels. */
#define BOARD_LCD_HEIGHT 480
/** Display interface width in bits. */
#define BOARD_LCD_IFWIDTH 24
/** Frame size in words (height * width * bpp / 32) */
#define BOARD_LCD_FRAMESIZE (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT * BOARD_LCD_IFWIDTH / 32)
/** Vertical front porch in number of lines. */
#define BOARD_LCD_TIMING_VFP 22
/** Vertical back porch in number of lines. */
#define BOARD_LCD_TIMING_VBP 21
/** Vertical pulse width in number of lines. */
#define BOARD_LCD_TIMING_VPW 2
/** Horizontal front porch in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HFP 64
/** Horizontal back porch in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HBP 64
/** Horizontal pulse width in LCDDOTCLK cycles. */
#define BOARD_LCD_TIMING_HPW 128
/** Frame rate in Hz. */
#define BOARD_LCD_FRAMERATE 40
/** Pixel clock rate in Hz (HS period * VS period * BOARD_LCD_FRAMERATE). */
#define BOARD_LCD_PIXELCLOCK ((BOARD_LCD_TIMING_HPW+BOARD_LCD_TIMING_HBP+BOARD_LCD_WIDTH+BOARD_LCD_TIMING_HFP)\
*(BOARD_LCD_TIMING_VPW+BOARD_LCD_TIMING_VBP+BOARD_LCD_HEIGHT+BOARD_LCD_TIMING_VFP)\
*BOARD_LCD_FRAMERATE)
#define BOARD_ISI_VSYNC {PIO_PA30C_ISI_VSYNC, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_HSYNC {PIO_PA31C_ISI_HSYNC, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_PCK {PIO_PC30C_ISI_PCK, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT}
#define BOARD_ISI_PINS_DATA {0x00FF0000, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}
#define PIN_ISI_RST {1 << 24, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
#define PIN_ISI_RSTN {1 << 29, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
#define PINS_ISI BOARD_ISI_VSYNC, BOARD_ISI_HSYNC, BOARD_ISI_PCK , BOARD_ISI_PINS_DATA
/** Touchscreen ADC clock frequency to use. */
#define BOARD_TOUCHSCREEN_ADCCLK 300000 /* 8MHz max */
/** Touchscreen ADC startup time in µseconds. */
#define BOARD_TOUCHSCREEN_STARTUP 40
/** Touchscreen ADC track and hold time in nanoseconds. */
#define BOARD_TOUCHSCREEN_SHTIM 2000 /* min 1µs at 8MHz */
/** Touchscreen pen debounce time in nanoseconds. */
#define BOARD_TOUCHSCREEN_DEBOUNCE 10000000
/** HDMI reset pins. */
#define PIN_HDMI_RESET_L {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}
#define PIN_HDMI_RESET_H {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
/*----------------------------------------------------------------------------*/
/**
* \page sama5d3x_ek_chipdef "sama5d3-xplained - Individual chip definition"
* This page lists the definitions related to different chip's definition
* located in the board.h file for the sama5d3-xplained.
*
* LEDs
* - \ref PIN_LED_0
* - \ref PIN_LED_1
* - \ref PIN_LED_2
* - \ref PINS_LEDS
*
* Push buttons
* - \ref PIN_PUSHBUTTON_1
* - \ref PINS_PUSHBUTTONS
*
* PCK0
* - \ref PIN_PCK0
*
* PCK1
* - \ref PIN_PCK1
*/
#ifdef BOARD_VB
#define LED_BLUE 0
#define LED_GREEN 1
#define LED_RED 2
#define LED_YELLOW 3
/** LED #0 pin definition (BLUE). */
#define PIN_LED_0 {(1<<23), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
/** LED #1 pin definition (GREEN). */
#define PIN_LED_1 {(1<<21), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
/** LED #2 pin definition (RED). */
#define PIN_LED_2 {(1<<22), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
/** LED #3 pin definition (YELLOW). */
#define PIN_LED_3 {(1<<5), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT}
/** List of all LEDs definitions. */
#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2, PIN_LED_3
#endif
#if defined(BOARD_XPLAINED)
#define LED_BLUE 0
#define LED_RED 1
/** LED #0 pin definition (LED_BLUE). */
#define PIN_LED_0 {(PIO_PE23), PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT}
/** LED #1 pin definition (LED_RED). */
#define PIN_LED_1 {(PIO_PE24), PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT}
/** List of all LEDs definitions. */
#define PINS_LEDS PIN_LED_0, PIN_LED_1
#endif
/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
#define PIN_PUSHBUTTON_1 {PIO_PE29, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}
/** List of all push button definitions. */
#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1
/** Push button #1 index. */
#define PUSHBUTTON_BP1 0
/** Push button #2 index. */
#define PUSHBUTTON_BP2 1
/** Simulate Joystick Left */
#define JOYSTICK_LEFT 1
/** Simulate Joystick Right */
#define JOYSTICK_RIGHT 0
#define NO_PUSHBUTTON
/** PCK0 */
#define PIN_PCK0 {PIO_PD30B_PCK0, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** PCK1 */
#define PIN_PCK1 {PIO_PD31B_PCK1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}
/** PCK2 */
#define PIN_PCK2 {PIO_PC15B_PCK2, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/** PWM0 */
#define PIN_PWM0_H {PIO_PA20B_PWMH0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_PWM0_L {PIO_PA21B_PWML0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_PWM0_FI {PIO_PC28B_PWMFI0, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_PWM1_H {PIO_PA22B_PWMH1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_PWM1_L {PIO_PA23B_PWML1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
#define PIN_PWM1_FI {PIO_PC31B_PWMFI1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
/*----------------------------------------------------------------------------
* Headers for board
*----------------------------------------------------------------------------*/
#include "include/board_lowlevel.h"
#include "include/board_memories.h"
#include "include/bmp.h"
#include "include/mii.h"
#include "include/gmii.h"
#include "include/emacd.h"
#include "include/macb.h"
#include "include/gmacd.h"
#include "include/gmacb.h"
#include "include/clock.h"
#include "include/dbgu_console.h"
#include "include/dbg_util.h"
#include "include/iso7816_4.h"
#include "include/dmad.h"
#include "include/dma_hardware_interface.h"
#include "include/hamming.h"
#include "include/led.h"
#include "include/math.h"
#include "include/mcid.h"
#include "include/timetick.h"
#include "include/wav.h"
#include "include/wm8904.h"
#include "include/qt1070.h"
#include "include/lcdd.h"
#include "include/lcd_draw.h"
#include "include/lcd_font10x14.h"
#include "include/lcd_font.h"
#include "include/lcd_color.h"
#include "include/tsd.h"
#include "include/tsd_com.h"
#include "include/cand.h"
#include "include/ov.h"
#include "include/omnivision.h"
#include "include/ovyuv.h"
#endif /* #ifndef _BOARD_ */

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FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ads7843.h Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for ADS7843 driver.
*/
#ifndef _ADS7843_
#define _ADS7843_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ADS7843_Initialize( void ) ;
extern void ADS7843_Reset( void ) ;
extern void ADS7843_GetPosition( uint32_t *px_pos, uint32_t *py_pos ) ;
#endif /* #ifndef _ADS7843_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* \section Purpose
*
* Utility for BMP
*
*/
#ifndef BMP_H
#define BMP_H
/** BMP magic number ('BM'). */
#define BMP_TYPE 0x4D42
/** headerSize must be set to 40 */
#define BITMAPINFOHEADER 40
/*------------------------------------------------------------------------------
* Exported types
*------------------------------------------------------------------------------*/
/*
* In case of IAR EWARM use, we define an empty macro to turn useless GCC and MDK __attribute__ keyword
*/
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack( 1 )
#endif
/** BMP (Windows) File Header Format */
typedef struct _BMPFileHeader
{
/** signature, must be 4D42 hex */
uint16_t type;
/** size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/** reserved, must be zero */
uint16_t reserved1;
/** reserved, must be zero */
uint16_t reserved2;
/** offset to start of image data in bytes */
uint32_t offset;
} BMPFileHeader;
/** BMP (Windows 2.x) Header */
typedef struct _BMP2XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
uint16_t width;
/** image height in pixels */
uint16_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
} BMP2XHeader;
/** BMP (Windows 3.x) Header, 40 bytes */
typedef struct _BMP3XHeader
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
} BMP3XHeader;
/** BMP (Windows 95, V4) Header, 108 bytes */
typedef struct _BMP4Header
{
/** size of this header in bytes */
uint32_t size;
/** image width in pixels */
int32_t width;
/** image height in pixels */
int32_t height;
/** number of color planes */
uint16_t planes;
/** number of bits per pixel */
uint16_t bitsPerPixel;
/** Compression methods used */
uint32_t compression;
/** Size of bitmap in bytes */
uint32_t sizeOfBitmap;
/** horizontal resolution in pixels per meter */
int32_t xResolution;
/** vertical resolution in pixels per meter */
int32_t yResolution;
/** number of colors in the image */
uint32_t colorsUsed;
/** minimum number of important colors */
uint32_t colorsImportant;
/** Mask identifying bits of red component */
uint32_t redMask;
/** Mask identifying bits of green component */
uint32_t greenMask;
/** Mask identifying bits of blue component */
uint32_t blueMask;
/** Mask identifying bits of alpha component */
uint32_t alphaMask;
/** Color space type */
uint32_t csType;
/** X coordinate of red endpoint */
int32_t redX;
/** Y coordinate of red endpoint */
int32_t redY;
/** Z coordinate of red endpoint */
int32_t redZ;
/** X coordinate of green endpoint */
int32_t greenX;
/** Y coordinate of green endpoint */
int32_t greenY;
/** Z coordinate of green endpoint */
int32_t greenZ;
/** X coordinate of blue endpoint */
int32_t blueX;
/** Y coordinate of blue endpoint */
int32_t blueY;
/** Z coordinate of blue endpoint */
int32_t blueZ;
/** Gamma red coordinate scale value */
uint32_t gammaRed;
/** Gamma green coordinate scale value */
uint32_t gammaGreen;
/** Gamma blue coordinate scale value */
uint32_t gammaBlue;
} BMP4Header;
/** BMP (Windows) Header Format */
typedef struct _BMPHeader
{
/* signature, must be 4D42 hex */
uint16_t type;
/* size of BMP file in bytes (unreliable) */
uint32_t fileSize;
/* reserved, must be zero */
uint16_t reserved1;
/* reserved, must be zero */
uint16_t reserved2;
/* offset to start of image data in bytes */
uint32_t offset;
/* size of BITMAPINFOHEADER structure, must be 40 */
uint32_t headerSize;
/* image width in pixels */
uint32_t width;
/* image height in pixels */
uint32_t height;
/* number of planes in the image, must be 1 */
uint16_t planes;
/* number of bits per pixel (1, 4, 8, 16, 24, 32) */
uint16_t bits;
/* compression type (0=none, 1=RLE-8, 2=RLE-4) */
uint32_t compression;
/* size of image data in bytes (including padding) */
uint32_t imageSize;
/* horizontal resolution in pixels per meter (unreliable) */
uint32_t xresolution;
/* vertical resolution in pixels per meter (unreliable) */
uint32_t yresolution;
/* number of colors in image, or zero */
uint32_t ncolours;
/* number of important colors, or zero */
uint32_t importantcolours;
} BMPHeader ; // GCC
#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__
# pragma pack()
#endif
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint8_t BMP_IsValid(void *file);
extern uint32_t BMP_GetFileSize(void *file);
extern uint8_t BMP_Decode(
void *file,
uint8_t*buffer,
uint32_t width,
uint32_t height,
unsigned char bpp);
extern void WriteBMPheader(uint32_t* pAddressHeader,
uint32_t bmpHSize,
uint32_t bmpVSize,
uint8_t bmpRgb,
uint8_t nbByte_Pixels);
extern void BMP_displayHeader(uint32_t* pAddressHeader);
extern void RGB565toBGR555(
uint8_t *fileSource,
uint8_t *fileDestination,
uint32_t width,
uint32_t height,
uint8_t bpp);
#endif //#ifndef BMP_H

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for the low-level initialization function.
*
*/
#ifndef BOARD_LOWLEVEL_H
#define BOARD_LOWLEVEL_H
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void defaultSpuriousHandler( void );
extern void defaultFiqHandler( void );
extern void defaultIrqHandler( void );
extern void LowLevelInit( void ) ;
#endif /* BOARD_LOWLEVEL_H */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for memories configuration on board.
*
*/
#ifndef BOARD_MEMORIES_H
#define BOARD_MEMORIES_H
// Micron MT47H128M16 ?16 Meg x 16 x 8 banks = 256 MBytes
// => 2 chips used => 512 MBytes
// data bus = 32 bits => 16 Meg x 32 x 8 Banks => 256 Meg * 16 available
#define DDR2_MEM8SIZE 0x20000000
#define DDR2_MEM16SIZE 0x10000000
#define DDR2_MEM32SIZE 0x8000000
#define EXT_32_LPDDR2_8BANK_16_32_SOD200_SIZE 0x20000000
//void LPDDR2_AC_TIMING(LPDDR2 * st_ddr2, unsigned int f_base);
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void BOARD_RemapRom( void );
extern void BOARD_RemapRam( void );
extern void BOARD_ConfigureVddMemSel(uint8_t VddMemSel) ;
extern void BOARD_ConfigureDdram( uint8_t device );
extern void BOARD_ConfigureSdram( void );
extern void BOARD_ConfigureNandFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureNorFlash( uint8_t busWidth ) ;
extern void BOARD_ConfigureLpDdram(void);
#endif /* #ifndef BOARD_MEMORIES_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup lib_board
* \addtogroup cand_module CAN Driver
*
* \section Purpose
*
* Implement driver functions for CAN operations.
*
* \section cand_usage Usage
*
* Uses following functions for CAN operations.
* -# Uses CAND_Handler() as peripheral interrupt handler.
* -# Uses CAND_Init() to initialize the driver and peripheral.
* -# Uses CAND_Activate() to enable the CAN interface. Then check
* CAND_IsReady() to find when CAN is synchronized for data transfer.
* -# To send a CAN message you can:
* -# Initialize mailbox with CAND_ResetMailbox()
* -# Start data transfer with CAND_Transfer()
* -# You can also start CAN message by:
* -# Initialize transfer with CAND_ConfigureTransfer(). Several
* transfers linked to different mailbox can be initialized.
* -# After configuration, transfers can be enabled by
* CAND_StartTransfers() at one time.
* -# To check if the transfer is done, CAND_IsTransferDone() is used.
*
* The following structs should be instanced for driver operations.
* -# \ref sCand : Driver instance struct.
* -# \ref sCandMbCfg : Mailbox configuration parameters list.
* -# \ref sCandTransfer : Message transfer operation parameters list.
*
*/
#ifndef _CAND_H_
#define _CAND_H_
/**@{*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <chip.h>
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** \addtogroup cand_rc CAN Driver Status (Return Codes)
* @{*/
/** Operation success */
#define CAND_OK 0
/** The driver/mailbox is busy */
#define CAND_BUSY 1
/** General error */
#define CAND_ERROR 0x10
/** Bad operation because of wrong state */
#define CAND_ERR_STATE 0x11
/** Bad operation for parameter error */
#define CAND_ERR_PARAM 0xFE
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/* CAN Driver General callback */
//typedef void(*CandCallback)(uint8_t bEvent, void* pArg);
/** CAN Driver Mailbox settings */
typedef struct _CandMbCfg {
uint32_t dwMsgMask; /**< Message ID Mask _MAMx */
uint8_t bMsgType; /**< Message type */
uint8_t bTxPriority; /**< Priority for TX */
} sCandMbCfg;
/** CAN Driver Transfer Parameters */
typedef struct _CandTransfer {
//void* fCallback; /**< Callback function when transfer finished */
//void* pArg; /**< Callback arguments */
uint32_t dwMsgID; /**< Message ID _MIDx */
uint32_t msgData[2]; /**< Message data */
uint8_t bMailbox; /**< Mailbox used */
uint8_t bMsgLen; /**< Message length */
uint8_t bState; /**< Transfer state */
uint8_t bRC; /**< Transfer return code */
} sCandTransfer;
/** CAN Driver Transfer callback */
typedef void(*CandTransferCallback)(sCandTransfer* pXfr);
/**
* CAN Driver instance struct.
*/
typedef struct _Cand {
Can* pHw; /**< Pointer to HW register base */
//CandCallback fCallback; /**< Pointer to Callback function */
//void* pArg; /**< Pointer to Callback argument */
sCandTransfer *pMbs[CAN_NUM_MAILBOX]; /**< Pointer list to mailboxes */
uint32_t dwMck; /**< MCK for baudrate calculating */
uint16_t wBaudrate; /**< Current working baudrate */
uint8_t bID; /**< Peripheral ID */
uint8_t bState; /**< CAN states */
} sCand;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t CAND_Init(sCand * pCand,
Can * pHw,uint8_t bID,
uint16_t wBaudrate,uint32_t dwMck);
extern void CAND_Activate(sCand * pCand);
extern void CAND_Sleep(sCand * pCand);
extern uint8_t CAND_IsReady(sCand * pCand);
extern void CAND_Handler(sCand * pCand);
extern uint8_t CAND_IsMailboxReady(sCand * pCand,uint8_t bMb);
extern void CAND_ResetMailbox(sCand * pCand,uint8_t bMb,sCandMbCfg * pCfg);
extern uint8_t CAND_ConfigureTransfer(sCand * pCand,
sCandMbCfg * pCfg,
sCandTransfer * pXfr);
extern uint8_t CAND_Transfer(sCand * pCand,sCandTransfer * pXfr);
extern void CAND_StartTransfers(sCand * pCand,uint32_t bmMbs);
extern uint8_t CAND_IsTransferDone(sCandTransfer * pXfr);
/**@}*/
#endif /* #ifndef _CAN_H_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _CLOCK_
#define _CLOCK_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void CLOCK_SetConfig( uint8_t configuration ) ;
extern void CLOCK_DisplayMenu( void ) ;
extern void CLOCK_UserChangeConfig( void ) ;
extern uint16_t CLOCK_GetCurrMCK( void ) ;
extern uint16_t CLOCK_GetCurrPCK( void ) ;
#endif /* #ifndef _CLOCK_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Implements DBG utility that uses DBGU and System tick to get byte or binary
* stream from DBGU console.
*/
#ifndef _DBG_UTIL_
#define _DBG_UTIL_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint8_t DbgReceiveByte(uint8_t * pByte,uint32_t timeOut);
extern uint32_t DbgReceiveBinary(uint8_t start,
uint32_t address,
uint32_t maxSize);
extern uint32_t DbgReceive1KXModem(uint8_t * pktBuffer,
uint32_t address,
uint32_t maxSize);
#endif /* _DBG_UTIL_ */

55
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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _DBGU_CONSOLE_
#define _DBGU_CONSOLE_
#include <stdint.h>
/** Console baudrate always using 115200. */
#define CONSOLE_BAUDRATE 115200
extern void DBGU_ConsoleUseDBGU(void);
extern void DBGU_ConsoleUseUSART0(void);
extern void DBGU_ConsoleUseUSART1(void);
extern void DBGU_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ;
extern void DBGU_PutChar( uint8_t uc ) ;
extern uint32_t DBGU_GetChar( void ) ;
extern uint32_t DBGU_IsRxReady( void ) ;
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ;
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ;
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue ) ;
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax ) ;
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue ) ;
#endif /* _DBGU_CONSOLE_ */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _DMAD_IF_H
#define _DMAD_IF_H
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** DMA hardware interface */
typedef struct _DmaHardwareInterface {
uint8_t bDmac; /**< DMA Controller number */
uint32_t bPeriphID; /**< Peripheral ID */
uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/
uint8_t bIfID; /**< DMA Interface ID */
} DmaHardwareInterface;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t DMAIF_IsValidatedPeripherOnDma( uint8_t bDmac, uint8_t bPeriphID);
extern uint8_t DMAIF_Get_ChannelNumber (uint8_t bDmac, uint8_t bPeriphID, uint8_t bTransfer);
#endif //#ifndef _DMAD_IF_H

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _DMAD_H
#define _DMAD_H
/** \addtogroup dmad_module
*@{
*/
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
/** \addtogroup dmad_defines DMA Driver Defines
@{*/
/*----------------------------------------------------------------------------
* Consts
*----------------------------------------------------------------------------*/
#define DMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */
#define DMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */
#define DMAD_TRANSFER_TX 0
#define DMAD_TRANSFER_RX 1
/*----------------------------------------------------------------------------
* MACRO
*----------------------------------------------------------------------------*/
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_structs DMA Driver Structs
@{*/
/** DMA status or return code */
typedef enum _DmadStatus {
DMAD_OK = 0, /**< Operation is sucessful */
DMAD_BUSY, /**< Channel occupied or transfer not finished */
DMAD_PARTIAL_DONE, /**< Partial of LLI finished (on each buffer done) */
DMAD_ERROR, /**< Operation failed */
DMAD_CANCELED /**< Operation canceled */
} eDmadStatus, eDmadRC;
/** DMA state for channel */
typedef enum _DmadState {
DMAD_FREE = 0, /**< Free channel */
DMAD_IN_USE, /**< Allocated to some peripheral */
DMAD_IN_XFR, /**< Transferring something */
DMAD_STALL /**< Error stall */
} eDmadState;
/** DMA transfer callback */
typedef void (*DmadTransferCallback)(uint32_t status, void* pArg);
/** DMA driver channel */
typedef struct _DmadChannel {
DmadTransferCallback fCallback; /**< Callback */
void* pArg; /**< Callback argument */
uint8_t bIrqOwner; /**< Uses DMA handler or external one */
uint8_t bSrcPeriphID; /**< HW ID for source */
uint8_t bDstPeriphID; /**< HW ID for destination */
uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */
uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */
uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */
uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */
volatile uint8_t state; /**< DMA channel state */
} sDmadChannel;
#if 0
/** DMA driver controller */
typedef struct _DmadController {
Dmac *pHw; /**< Pointer to controler HW base */
sDmadChannel* dmadChannels; /**< Pointer to driver channels list */
uint8_t* dmadIfUsage; /**< AHB Interface usage counting */
uint8_t bHwID; /**< ID for DMAC */
uint8_t bNumChannels; /**< Number of channels for this controller */
uint8_t bNumAHBIf; /**< Number of AHB Interface */
uint8_t reserved;
} sDmadController;
#endif
/** DMA driver instance */
typedef struct _Dmad {
Dmac *pDmacs[2];
sDmadChannel dmaChannels[2][8];
uint8_t numControllers;
uint8_t numChannels;
uint8_t pollingMode;
uint8_t pollingTimeout;
} sDmad;
/** DMA driver channel ID */
typedef struct _DmadChannelID {
uint8_t bDmac; /**< DMA Controller number */
uint8_t bChannel; /**< Channel number */
} sDmadChannelID;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup dmad_functions DMA Driver Functionos
@{*/
extern void DMAD_Initialize( sDmad *pDmad,
uint8_t bPollingMode );
extern void DMAD_Handler( sDmad *pDmad );
extern uint32_t DMAD_AllocateChannel( sDmad *pDmad,
uint8_t bSrcID, uint8_t bDstID);
extern eDmadRC DMAD_FreeChannel( sDmad *pDmad, uint32_t dwChannel );
extern eDmadRC DMAD_SetCallback( sDmad *pDmad, uint32_t dwChannel,
DmadTransferCallback fCallback, void* pArg );
extern eDmadRC DMAD_ConfigurePIP( sDmad *pDmad, uint32_t dwChannel,
uint32_t dwSrcPIP, uint32_t dwDstPIP );
extern eDmadRC DMAD_PrepareChannel( sDmad *pDmad, uint32_t dwChannel,
uint32_t dwCfg );
extern eDmadRC DMAD_IsTransferDone( sDmad *pDmad, uint32_t dwChannel );
extern eDmadRC DMAD_StartTransfer( sDmad *pDmad, uint32_t dwChannel );
extern eDmadRC DMAD_StartTransfers( sDmad *pDmad,
uint8_t bDmac, uint32_t bmChannels );
extern eDmadRC DMAD_StopTransfer( sDmad *pDmad, uint32_t dwChannel );
extern void DMAD_ClearAuto( sDmad *pDmad, uint32_t _dwChannel );
extern eDmadRC DMAD_PrepareSingleTransfer( sDmad *pDmad, uint32_t dwChannel,
sDmaTransferDescriptor *pXfrDesc );
extern eDmadRC DMAD_PrepareMultiTransfer( sDmad *pDmad, uint32_t dwChannel,
sDmaTransferDescriptor *pXfrDesc );
/** @}*/
/**@}*/
#endif //#ifndef _DMAD_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup emacd_module
* @{
* Implement EMAC data transfer and PHY management functions.
*
* \section Usage
* -# Implement EMAC interrupt handler, which must invoke EMACD_Handler()
* to handle EMAC interrupt events.
* -# Implement sEmacd instance in application.
* -# Initialize the instance with EMACD_Init() and EMACD_InitTransfer(),
* so that EMAC data can be transmitted/received.
* -# Some management callbacks can be set by EMACD_SetRxCallback()
* and EMACD_SetTxWakeupCallback().
* -# Send ethernet packets using EMACD_Send(), EMACD_TxLoad() is used
* to check the free space in TX queue.
* -# Check and obtain received ethernet packets via EMACD_Poll().
*
* \sa \ref macb_module, \ref emac_module
*
* Related files:\n
* \ref emacd.c\n
* \ref emacd.h.\n
*
* \defgroup emacd_defines EMAC Driver Defines
* \defgroup emacd_types EMAC Driver Types
* \defgroup emacd_functions EMAC Driver Functions
*/
/**@}*/
#ifndef _EMACD_H_
#define _EMACD_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup emacd_defines
@{*/
/** \addtogroup emacd_buf_size EMACD Default Buffer Size
@{*/
#define EMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */
#define EMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */
/** @}*/
/** \addtogroup emacd_rc EMACD Return Codes
@{*/
#define EMACD_OK 0 /**< Operation OK */
#define EMACD_TX_BUSY 1 /**< TX in progress */
#define EMACD_RX_NULL 1 /**< No data received */
/** Buffer size not enough */
#define EMACD_SIZE_TOO_SMALL 2
/** Parameter error, TX packet invalid or RX size too small */
#define EMACD_PARAM 3
/** Transter is not initialized */
#define EMACD_NOT_INITIALIZED 4
/** @}*/
/** @}*/
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** \addtogroup emacd_types
@{*/
/** RX callback */
typedef void (*fEmacdTransferCallback)(uint32_t status);
/** Wakeup callback */
typedef void (*fEmacdWakeupCallback)(void);
/**
* EMAC driver struct.
*/
typedef struct _EmacDriver {
/** Pointer to HW register base */
Emac *pHw;
/** Pointer to allocated TX buffer
Section 3.6 of AMBA 2.0 spec states that burst should not cross
1K Boundaries.
Receive buffer manager writes are burst of 2 words => 3 lsb bits
of the address shall be set to 0
*/
uint8_t *pTxBuffer;
/** Pointer to allocated RX buffer */
uint8_t *pRxBuffer;
/** Pointer to Rx TDs (must be 8-byte aligned) */
sEmacRxDescriptor *pRxD;
/** Pointer to Tx TDs (must be 8-byte aligned) */
sEmacTxDescriptor *pTxD;
/** Optional callback to be invoked once a frame has been received */
fEmacdTransferCallback fRxCb;
/** Optional callback to be invoked once several TD have been released */
fEmacdWakeupCallback fWakupCb;
/** Optional callback list to be invoked once TD has been processed */
fEmacdTransferCallback *fTxCbList;
/** RX TD list size */
uint16_t wRxListSize;
/** RX index for current processing TD */
uint16_t wRxI;
/** TX TD list size */
uint16_t wTxListSize;
/** Circular buffer head pointer by upper layer (buffer to be sent) */
uint16_t wTxHead;
/** Circular buffer tail pointer incremented by handlers (buffer sent) */
uint16_t wTxTail;
/** Number of free TD before wakeup callback is invoked */
uint8_t bWakeupThreshold;
/** HW ID */
uint8_t bId;
} sEmacd;
/** @}*/
/** \addtogroup emacd_functions
@{*/
/*---------------------------------------------------------------------------
* PHY Exported functions
*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------
* EMAC Exported functions
*---------------------------------------------------------------------------*/
extern void EMACD_Init( sEmacd *pEmacd,
Emac *pHw, uint8_t bID,
uint8_t bCAF, uint8_t bNBC);
extern uint8_t EMACD_InitTransfer( sEmacd *pEmacd,
uint8_t *pRxBuffer, sEmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sEmacTxDescriptor *pTxD, fEmacdTransferCallback *pTxCb,
uint16_t wTxSize);
extern void EMACD_SetRxCallback( sEmacd *pEmacd, fEmacdTransferCallback fRxCb);
extern uint8_t EMACD_SetTxWakeupCallback( sEmacd *pEmacd,
fEmacdWakeupCallback fWakeup,
uint8_t bThreshold );
extern void EMACD_Handler( sEmacd *pEmacd );
extern void EMACD_Reset( sEmacd * pEmacd );
extern uint8_t EMACD_Send(sEmacd * pEmacd,
void *pBuffer,
uint32_t size,
fEmacdTransferCallback fTxCallback);
extern uint32_t EMACD_TxLoad( sEmacd *pEmacd );
extern uint8_t EMACD_Poll(sEmacd * pEmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize);
/** @}*/
#endif // #ifndef _EMACD_H_

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacb_module Ethernet GMACB Driver
*@{
* Implement GEMAC PHY driver, that initialize the PHY to prepare for
* ethernet transfer.
*
* \section Usage
* -# EMAC related pins and Driver should be initialized at first.
* -# Initialize GMACB Driver instance by invoking GMACB_Init().
* -# Initialize PHY connected via GMACB_InitPhy(), PHY address is
* automatically adjusted by attempt to read.
* -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so
* connection established.
*
*
* Related files:\n
* \ref gmacb.h\n
* \ref gmacb.c\n
* \ref gmii.h.\n
*
*/
/**@}*/
#ifndef _GMACB_H
#define _GMACB_H
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** The reset length setting for external reset configuration */
#define GMACB_RESET_LENGTH 0xD
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** The DM9161 instance */
typedef struct _GMacb {
sGmacd *pGmacd; /**< Driver */
/** The retry & timeout settings */
uint32_t retryMax;
/** PHY address ( pre-defined by pins on reset ) */
uint8_t phyAddress;
} GMacb;
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax);
extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress);
extern uint8_t GMACB_InitPhy(GMacb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins);
extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb);
extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings);
extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size);
extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size);
extern void GMACB_DumpRegisters(GMacb *pMacb);
extern uint8_t GMACB_ResetPhy(GMacb *pMacb);
#endif // #ifndef _GMACB_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup gmacd_module
* @{
* Implement GMAC data transfer and PHY management functions.
*
* \section Usage
* -# Implement GMAC interrupt handler, which must invoke GMACD_Handler()
* to handle GMAC interrupt events.
* -# Implement sGmacd instance in application.
* -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(),
* so that GMAC data can be transmitted/received.
* -# Some management callbacks can be set by GMACD_SetRxCallback()
* and GMACD_SetTxWakeupCallback().
* -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used
* to check the free space in TX queue.
* -# Check and obtain received ethernet packets via GMACD_Poll().
*
* \sa \ref gmacb_module, \ref gmac_module
*
* Related files:\n
* \ref gmacd.c\n
* \ref gmacd.h.\n
*
* \defgroup gmacd_defines GMAC Driver Defines
* \defgroup gmacd_types GMAC Driver Types
* \defgroup gmacd_functions GMAC Driver Functions
*/
/**@}*/
#ifndef _GMACD_H_
#define _GMACD_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_defines
@{*/
/** \addtogroup gmacd_buf_size GMACD Default Buffer Size
@{*/
#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */
#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */
/** @}*/
/** \addtogroup gmacd_rc GMACD Return Codes
@{*/
#define GMACD_OK 0 /**< Operation OK */
#define GMACD_TX_BUSY 1 /**< TX in progress */
#define GMACD_RX_NULL 1 /**< No data received */
/** Buffer size not enough */
#define GMACD_SIZE_TOO_SMALL 2
/** Parameter error, TX packet invalid or RX size too small */
#define GMACD_PARAM 3
/** Transter is not initialized */
#define GMACD_NOT_INITIALIZED 4
/** @}*/
/** @}*/
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** \addtogroup gmacd_types
@{*/
/** RX callback */
typedef void (*fGmacdTransferCallback)(uint32_t status);
/** Wakeup callback */
typedef void (*fGmacdWakeupCallback)(void);
/**
* GMAC driver struct.
*/
typedef struct _GmacDriver {
/** Pointer to HW register base */
Gmac *pHw;
uint8_t *pTxBuffer;
/** Pointer to allocated RX buffer */
uint8_t *pRxBuffer;
/** Pointer to Rx TDs (must be 8-byte aligned) */
sGmacRxDescriptor *pRxD;
/** Pointer to Tx TDs (must be 8-byte aligned) */
sGmacTxDescriptor *pTxD;
/** Optional callback to be invoked once a frame has been received */
fGmacdTransferCallback fRxCb;
/** Optional callback to be invoked once several TD have been released */
fGmacdWakeupCallback fWakupCb;
/** Optional callback list to be invoked once TD has been processed */
fGmacdTransferCallback *fTxCbList;
/** RX TD list size */
uint16_t wRxListSize;
/** RX index for current processing TD */
uint16_t wRxI;
/** TX TD list size */
uint16_t wTxListSize;
/** Circular buffer head pointer by upper layer (buffer to be sent) */
uint16_t wTxHead;
/** Circular buffer tail pointer incremented by handlers (buffer sent) */
uint16_t wTxTail;
/** Number of free TD before wakeup callback is invoked */
uint8_t bWakeupThreshold;
/** HW ID */
uint8_t bId;
} sGmacd;
/** @}*/
/** \addtogroup gmacd_functions
@{*/
/*---------------------------------------------------------------------------
* GMAC Exported functions
*---------------------------------------------------------------------------*/
extern void GMACD_Handler(sGmacd *pGmacd );
extern void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC );
extern uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer,
sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer,
sGmacTxDescriptor *pTxD,
fGmacdTransferCallback *pTxCb,
uint16_t wTxSize);
extern void GMACD_Reset(sGmacd *pGmacd);
extern uint8_t GMACD_Send(sGmacd *pGmacd,
void *pBuffer,
uint32_t size,
fGmacdTransferCallback fTxCb );
extern uint32_t GMACD_TxLoad(sGmacd *pGmacd);
extern uint8_t GMACD_Poll(sGmacd * pGmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize);
extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb);
extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,
fGmacdWakeupCallback fWakeup,
uint8_t bThreshold);
/** @}*/
#endif // #ifndef _GMACD_H_

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GMII_DEFINE_H
#define _GMII_DEFINE_H
//-----------------------------------------------------------------------------
/// Definitions
//-----------------------------------------------------------------------------
//IEEE defined Registers
#define GMII_BMCR 0 // Basic Mode Control Register
#define GMII_BMSR 1 // Basic Mode Status Register
#define GMII_PHYID1 2 // PHY Idendifier Register 1
#define GMII_PHYID2 3 // PHY Idendifier Register 2
#define GMII_ANAR 4 // Auto_Negotiation Advertisement Register
#define GMII_ANLPAR 5 // Auto_negotiation Link Partner Ability Register
#define GMII_ANER 6 // Auto-negotiation Expansion Register
#define GMII_ANNPR 7 // Auto-negotiation Next Page Register
#define GMII_ANLPNPAR 8 // Auto_negotiation Link Partner Next Page Ability Register
#define GMII_1000BTCR 9 // 1000Base-T Control
#define GMII_1000BTSR 10 // 1000Base-T Status
#define GMII_ERCR 11 // Extend Register - Control Register
#define GMII_ERDWR 12 // Extend Register - Data Write Register
#define GMII_ERDRR 13 // Extend Register - Data Read Register
//14 reserved
#define GMII_EMSR 15 // Extend MII Status Register
//Vender Specific Register
//16 reserved
#define GMII_RLLMR 17 // Remote Loopback, LED Mode Register
#define GMII_LMDCDR 18 // LinkND - Cable Diagnostic Register
#define GMII_DPPSR 19 // Digital PMA/PCS Status
//20 reserved
#define GMII_RXERCR 21 // RXER Counter Register
//22-26 reserved
#define GMII_ICSR 27 // Interrupt Control/Status Register
#define GMII_DDC1R 28 // Digital Debug Control 1 Register
//29-30 reserved
#define GMII_PHYCR 31 // PHY Control Register
//Extend Registers
#define GMII_CCR 256 // Common Control Register
#define GMII_SSR 257 // Strap Status Register
#define GMII_OMSOR 258 // Operation Mode Strap Override Register
#define GMII_OMSSR 259 // Operation Mode Strap Status Register
#define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register
#define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register
#define GMII_ATR 263 // Analog Test Register
// Basic Mode Control Register (BMCR)
// Bit definitions: MII_BMCR
#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps
#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
// Reserved 7 // Read as 0, ignore on write
#define GMII_SPEED_SELECT_MSB (1 << 6) //
// Reserved 5 to 0 // Read as 0, ignore on write
// Basic Mode Status Register (BMSR)
// Bit definitions: MII_BMSR
#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
// Reserved 10 to 9 // Read as 0, ignore on write
#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
// Reserved 7
#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
#define GMII_LINK_STATUS (1 << 2) // Link Status
#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
// PHY ID Identifier Register
// definitions: MII_PHYID1
#define GMII_LSB_MASK 0x3F
#define GMII_OUI_MSB 0x0022
#define GMII_OUI_LSB 0x05
// Auto-negotiation Advertisement Register (ANAR)
// Auto-negotiation Link Partner Ability Register (ANLPAR)
// Bit definitions: MII_ANAR, MII_ANLPAR
#define GMII_NP (1 << 15) // Next page Indication
// Reserved 7
#define GMII_RF (1 << 13) // Remote Fault
// Reserved 12 // Write as 0, ignore on read
#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
// 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
#define GMII_T4 (1 << 9) // 100BASE-T4 Support
#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support
#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
#define GMII_10_HDX (1 << 5) // 10BASE-T Support
// Selector 4 to 0 // Protocol Selection Bits
#define GMII_AN_IEEE_802_3 0x0001
// Auto-negotiation Expansion Register (ANER)
// Bit definitions: MII_ANER
// Reserved 15 to 5 // Read as 0, ignore on write
#define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault
#define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able
#define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able
#define GMII_PAGE_RX (1 << 1) // New Page Received
#define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able
// GMII_1000BTCR
#define GMII_1000BaseT_HALF_DUPLEX (1 << 8)
#define GMII_1000BaseT_FULL_DUPLEX (1 << 9)
#define GMII_MARSTER_SLAVE_ENABLE (1 << 12)
#define GMII_MARSTER_SLAVE_CONFIG (1 << 11)
#define GMII_PORT_TYPE (1 << 10)
// GMII_1000BTSR
#define GMII_LINKP_1000BaseT_HALF_DUPLEX (1 << 10)
#define GMII_LINKP_1000BaseT_FULL_DUPLEX (1 << 11)
// 1 master 0 slave
#endif // #ifndef _MII_DEFINE_H

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _HAMMING_
#define _HAMMING_
/*------------------------------------------------------------------------------
* Defines
*------------------------------------------------------------------------------*/
/**
* These are the possible errors when trying to verify a block of data encoded
* using a Hamming code:
*
* \section Errors
* - Hamming_ERROR_SINGLEBIT
* - Hamming_ERROR_ECC
* - Hamming_ERROR_MULTIPLEBITS
*/
/** A single bit was incorrect but has been recovered. */
#define Hamming_ERROR_SINGLEBIT 1
/** The original code has been corrupted. */
#define Hamming_ERROR_ECC 2
/** Multiple bits are incorrect in the data and they cannot be corrected. */
#define Hamming_ERROR_MULTIPLEBITS 3
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern void Hamming_Compute256x( const uint8_t* pucData, uint32_t dwSize, uint8_t* pucCode ) ;
extern uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) ;
#endif /* _HAMMING_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
/** \page
*
* \section Purpose
*
* Definition of methods for ISO7816 driver.
*
* \section Usage
*
* -# ISO7816_Init
* -# ISO7816_IccPowerOff
* -# ISO7816_XfrBlockTPDU_T0
* -# ISO7816_Escape
* -# ISO7816_RestartClock
* -# ISO7816_StopClock
* -# ISO7816_toAPDU
* -# ISO7816_Datablock_ATR
* -# ISO7816_SetDataRateandClockFrequency
* -# ISO7816_StatusReset
* -# ISO7816_cold_reset
* -# ISO7816_warm_reset
* -# ISO7816_Decode_ATR
*----------------------------------------------------------------------------*/
#ifndef ISO7816_4_H
#define ISO7816_4_H
/*------------------------------------------------------------------------------
* Constants Definition
*----------------------------------------------------------------------------*/
/** Size max of Answer To Reset */
#define ATR_SIZE_MAX 55
/** NULL byte to restart byte procedure */
#define ISO_NULL_VAL 0x60
/*------------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ISO7816_Init( const Pin pPinIso7816RstMC );
extern void ISO7816_IccPowerOff(void);
extern uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU,
uint8_t *pMessage,
uint16_t wLength );
extern void ISO7816_Escape( void );
extern void ISO7816_RestartClock(void);
extern void ISO7816_StopClock( void );
extern void ISO7816_toAPDU( void );
extern void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength );
extern void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate );
extern uint8_t ISO7816_StatusReset( void );
extern void ISO7816_cold_reset( void );
extern void ISO7816_warm_reset( void );
extern void ISO7816_Decode_ATR( uint8_t* pAtr );
#endif /* ISO7816_4_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef COLOR_H
#define COLOR_H
/**
* \file
*
* RGB 24-bits color table definition.
*
*/
/*
* RGB 24 Bpp
* RGB 888
* R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0
*/
#define COLOR_BLACK 0x000000
#define COLOR_WHITE 0xFFFFFF
#define COLOR_BLUE 0x0000FF
#define COLOR_GREEN 0x00FF00
#define COLOR_RED 0xFF0000
#define COLOR_NAVY 0x000080
#define COLOR_DARKBLUE 0x00008B
#define COLOR_DARKGREEN 0x006400
#define COLOR_DARKCYAN 0x008B8B
#define COLOR_CYAN 0x00FFFF
#define COLOR_TURQUOISE 0x40E0D0
#define COLOR_INDIGO 0x4B0082
#define COLOR_DARKRED 0x800000
#define COLOR_OLIVE 0x808000
#define COLOR_GRAY 0x808080
#define COLOR_SKYBLUE 0x87CEEB
#define COLOR_BLUEVIOLET 0x8A2BE2
#define COLOR_LIGHTGREEN 0x90EE90
#define COLOR_DARKVIOLET 0x9400D3
#define COLOR_YELLOWGREEN 0x9ACD32
#define COLOR_BROWN 0xA52A2A
#define COLOR_DARKGRAY 0xA9A9A9
#define COLOR_SIENNA 0xA0522D
#define COLOR_LIGHTBLUE 0xADD8E6
#define COLOR_GREENYELLOW 0xADFF2F
#define COLOR_SILVER 0xC0C0C0
#define COLOR_LIGHTGREY 0xD3D3D3
#define COLOR_LIGHTCYAN 0xE0FFFF
#define COLOR_VIOLET 0xEE82EE
#define COLOR_AZUR 0xF0FFFF
#define COLOR_BEIGE 0xF5F5DC
#define COLOR_MAGENTA 0xFF00FF
#define COLOR_TOMATO 0xFF6347
#define COLOR_GOLD 0xFFD700
#define COLOR_ORANGE 0xFFA500
#define COLOR_SNOW 0xFFFAFA
#define COLOR_YELLOW 0xFFFF00
#endif /* #define COLOR_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_draw Drawing On LCD
*
* Interface for drawing function on LCD.
*
* \note Before drawing, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* Following functions can use:
* - Simple drawing:
* - LCDD_Fill()
* - LCDD_DrawPixel()
* - LCDD_ReadPixel()
* - LCDD_DrawLine()
* - LCDD_DrawRectangle(), LCDD_DrawFilledRectangle()
* - LCDD_DrawCircle(), LCDD_DrawFilledCircle()
* - LCDD_DrawImage()
* - String related:
* - LCDD_DrawString()
* - LCDD_GetStringSize()
*
* \sa \ref lcdd_module, \ref lcdd_font
*/
#ifndef DRAW_H
#define DRAW_H
/** \addtogroup lcdd_draw
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
#include "lcd_gimp_image.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_draw_func LCD Drawing Functions */
/** @{*/
extern void LCDD_Fill0( void ) ;
extern void LCDD_Fill( uint32_t color ) ;
extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t c ) ;
extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) ;
extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color ) ;
extern void LCDD_DrawRectangle( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2, uint32_t dwColor ) ;
extern void LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color ) ;
extern void LCDD_DrawFilledCircle(uint32_t dwX,uint32_t dwY,uint32_t dwR,uint32_t dwColor);
extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color ) ;
extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) ;
extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight ) ;
extern void LCDD_DrawImage( uint32_t x, uint32_t y, const uint8_t *pImage, uint32_t width, uint32_t height ) ;
void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage, uint32_t dwWidth, uint32_t dwHeight ) ;
extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ;
/** @}*/
/**@}*/
#endif /* #ifndef DRAW_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Interface for draw font on LCD.
*
*/
/**
* \addtogroup lcdd_font LCD Font Drawing
*
* \section Purpose
*
* The lcd_font.h files declares a font structure and a LCDD_DrawChar() function
* that must be implemented by a font definition file to be used with the
* LCDD_DrawString() method of draw.h.
*
* The font10x14.c implements the necessary variable and function for a 10x14
* font.
*
* \note Before drawing fonts, <b>canvas</b> should be selected via
* LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().
*
* \section Usage
*
* -# Declare a gFont global variable with the necessary Font information.
* -# Implement an LCDD_DrawChar() function which displays the specified
* character on the LCD.
* -# Select or create canvas via LCDD_SelectCanvas() or LCDD_CreateCanvas().
* -# Use the LCDD_DrawString() method defined in draw.h to display a complete
* string.
*
* \sa \ref lcdd_module, \ref lcdd_draw.
*/
#ifndef _LCD_FONT_
#define _LCD_FONT_
/** \addtogroup lcdd_font
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \brief Describes the font (width, height, supported characters, etc.) used by
* the LCD driver draw API.
*/
typedef struct _Font {
/* Font width in pixels. */
uint8_t width;
/* Font height in pixels. */
uint8_t height;
} Font;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
extern const Font gFont;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_font_func Font Functions */
/** @{*/
extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) ;
extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor );
/** @}*/
/**@}*/
#endif /* #ifndef LCD_FONT_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup lcdd_font
* @{
* \addtogroup font_10x14 Font 10x14
*/
/**@}*/
#ifndef _LCD_FONT_10x14_
#define _LCD_FONT_10x14_
/** \addtogroup font_10x14
* @{
*/
#include <stdint.h>
extern const uint8_t pCharset10x14[] ;
/** @}*/
#endif /* #ifdef _LCD_FONT_10x14_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _GIMP_IMAGE_
#define _GIMP_IMAGE_
#include <stdint.h>
typedef struct _SGIMPImage
{
uint32_t dwWidth;
uint32_t dwHeight;
uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */
uint8_t* pucPixel_data ;
} SGIMPImage ;
#endif // _GIMP_IMAGE_

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup lib_board
* \addtogroup lcdd_module LCD Driver
*
* \section Purpose
*
* Implement driver functions for LCD control and image display.
* - Implement basic LCD controler configuration.
* - Implement display functions for LCD layers.
* - Implement simple drawing functions.
* - Implement string display functions.
*
* \section lcdd_base_usage Usage
*
* Uses following functions for LCD basic configuration and displaying:
* -# Uses LCDD_Initialize() to initialize the controller and LCD.
* -# LCDD_On() and LCDD_Off() is used to turn LCD ON/OFF.
* -# LCDD_SetBacklight() is used to change LCD backlight level.
* -# To display a image (BMP format) on LCD, LCDD_ShowBMPRotated()
* LCDD_ShowBMPScaled() and LCDD_ShowBMP() can be used.
* -# To change configuration for an overlay layer, the following functions
* can use:
* -# LCDD_EnableLayer(), LCDD_IsLayerOn(): Turn ON/OFF layer, check status.
* -# LCDD_SetPosition(), LCDD_SetPrioty(), LCDD_EnableAlpha(),
* LCDD_SetAlpha(), LCDD_SetColorKeying(): Change display options.
* -# Shortcuts for layer display are as following:
* -# LCDD_ShowBase(), LCDD_StopBase()
* -# LCDD_ShowOvr1(), LCDD_StopOvr1()
* -# LCDD_ShowHeo(), LCDD_StopHeo()
* -# LCDD_ShowHcr(), LCDD_StopHcr()
* -# Drawing supporting fucntions, for drawing canvas:
* -# LCDD_CreateCanvas(): Create blank canvas on specified layer for
* drawing on
* -# LCDD_SelectCanvas(): Select a displayer as canvas to drawing on
* -# LCDD_GetCanvas(): Get current selected canvas layer
*
* For LCD drawing functions, refer to \ref lcdd_draw.
*
* For LCD string display, refer to \ref lcdd_font.
*
* @{
* \defgroup lcdd_base LCD Driver General Operations
* @{
* Implementation of LCD driver, Include LCD initialization,
* LCD on/off and LCD backlight control.
*
* \sa \ref lcdd_base_usage "LCD Driver General Usage"
* @}
* \defgroup lcdd_draw LCD Driver Simple Drawing
* @{
* @}
* \defgroup lcdd_font LCD Driver Font Display
* @{
* @}
* @}
*/
#ifndef LCDD_H
#define LCDD_H
/** \addtogroup lcdd_base
* @{
*/
/*----------------------------------------------------------------------------
* Defines
*----------------------------------------------------------------------------*/
/** \addtogroup lcdd_disp_id LCD display layers IDs
* @{
*/
/** LCD controller ID, no display, configuration ONLY */
#define LCDD_CONTROLLER 0
/** LCD base layer, display fixed size image */
#define LCDD_BASE 1
/** LCD Overlay 1 */
#define LCDD_OVR1 2
/** LCD Overlay 2 */
#define LCDD_OVR2 4
/** LCD HighEndOverlay, support resize */
#define LCDD_HEO 3
/** LCD Cursor, max size 128x128 */
#define LCDD_CUR 6
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** LCD display layer information */
typedef struct _LcddLayer {
void* pBuffer; /**< Display image buffer */
uint16_t wImgW; /**< Display image width */
uint16_t wImgH; /**< Display image height */
uint8_t bMode; /**< Image bpp (16,24,32) for RGB mode */
uint8_t bLayer; /**< Layer ID */
} sLCDDLayer;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void LCDD_Initialize(void);
extern void LCDD_On(void);
extern void LCDD_Off(void);
extern void LCDD_SetBacklight (uint32_t step);
extern void LCDD_EnableLayer(uint8_t bLayer,uint8_t bEnDis);
extern uint8_t LCDD_IsLayerOn(uint8_t bLayer);
extern void LCDD_SetPosition(uint8_t bLayer,uint32_t x,uint32_t y);
extern void LCDD_SetPrioty(uint8_t bLayer,uint8_t bPri);
extern uint8_t LCDD_GetPrioty(uint8_t bLayer);
extern void LCDD_EnableAlpha(uint8_t bLayer,uint8_t bEnDisLA,uint8_t bEnDisGA);
extern void LCDD_SetAlpha(uint8_t bLayer, uint8_t bReverse, uint8_t bAlpha);
extern uint8_t LCDD_GetAlpha(uint8_t bLayer);
extern void LCDD_SetColorKeying(uint8_t bLayer,
uint8_t bDstSrc,
uint32_t dwColor,uint32_t dwMask);
extern void LCDD_DisableColorKeying(uint8_t bLayer);
extern void LCDD_SetCLUT(uint8_t bLayer,
uint32_t * pCLUT,
uint8_t bpp,uint8_t nbColors);
extern void LCDD_Refresh(uint8_t bLayer);
extern void *LCDD_ShowBMPRotated(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH,
int16_t wRotate);
extern void *LCDD_ShowBMPScaled(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t imgW,uint32_t imgH);
extern void *LCDD_ShowBMP(uint8_t bLayer,
void * pBuffer,uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void *LCDD_ShowBase(void * pBuffer, uint8_t bpp, uint8_t bScanBottomUp);
extern void LCDD_StopBase(void);
extern void *LCDD_ShowOvr1(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopOvr1(void);
extern void *LCDD_ShowHeo(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h,
uint32_t memW,uint32_t memH);
extern void LCDD_StopHeo(void);
extern void *LCDD_ShowHcr(void * pBuffer, uint8_t bpp,
uint32_t x,uint32_t y,int32_t w,int32_t h);
extern void LCDD_StopHcr(void);
extern sLCDDLayer *LCDD_GetCanvas(void);
extern uint8_t LCDD_SelectCanvas(uint8_t bLayer);
extern void *LCDD_CreateCanvas(uint8_t bLayer,
void * pBuffer,uint8_t bBPP,
uint16_t wX,uint16_t wY,uint16_t wW,uint16_t wH);
extern void LCDD_Flush_CurrentCanvas(void);
/** @}*/
#endif /* #ifndef LCDD_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Small set of functions for simple and portable LED usage.
*
* \section Usage
*
* -# Configure one or more LEDs using LED_Configure and
* LED_ConfigureAll.
* -# Set, clear and toggle LEDs using LED_Set, LED_Clear and
* LED_Toggle.
*
* LEDs are numbered starting from 0; the number of LEDs depend on the
* board being used. All the functions defined here will compile properly
* regardless of whether the LED is defined or not; they will simply
* return 0 when a LED which does not exist is given as an argument.
* Also, these functions take into account how each LED is connected on to
* board; thus, \ref LED_Set might change the level on the corresponding pin
* to 0 or 1, but it will always light the LED on; same thing for the other
* methods.
*/
#ifndef _LED_
#define _LED_
#include <stdint.h>
//------------------------------------------------------------------------------
// Global Functions
//------------------------------------------------------------------------------
extern uint32_t LED_Configure( uint32_t dwLed ) ;
extern uint32_t LED_Set( uint32_t dwLed ) ;
extern uint32_t LED_Clear( uint32_t dwLed ) ;
extern uint32_t LED_Toggle( uint32_t dwLed ) ;
#endif /* #ifndef LED_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup macb_module Ethernet MACB Driver
*@{
* Implement EMAC PHY driver, that initialize the PHY to prepare for
* ethernet transfer.
*
* \section Usage
* -# EMAC related pins and Driver should be initialized at first.
* -# MAC address is set via EMAC_SetAddress().
* -# Initialize MACB Driver instance by invoking MACB_Init().
* -# Initialize PHY connected via MACB_InitPhy(), PHY address is
* automatically adjusted by attempt to read.
* -# Perform PHY auto negotiate through MACB_AutoNegotiate(), so
* connection established.
* -# Setup link speed by MACB_GetLinkSpeed() so link speed and
* duplex mode is desided.
* -# Now its time to send/receive ethernet packets via EMAC Driver
* - EMACD_Poll(): Polling received packets.
* - EMACD_Send(): Send a packet.
*
* \sa \ref emacd_module
*
* Related files:\n
* \ref macb.h\n
* \ref macb.c\n
* \ref mii.h.\n
*
* \defgroup eth_phy_mii MII/RMII Mode for PHY connection
* \defgroup macb_defines MACB Defines
* \defgroup macb_structs MACB Structs
* \defgroup macb_functions MACB Functions
*/
/**@}*/
#ifndef _MACB_H
#define _MACB_H
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup macb_defines
@{*/
/** The reset length setting for external reset configuration */
#define MACB_RESET_LENGTH 0xD
/** @}*/
/*---------------------------------------------------------------------------
* Types
*---------------------------------------------------------------------------*/
/** \addtogroup macb_structs
@{*/
/** The DM9161 instance */
typedef struct _Macb {
sEmacd *pEmacd; /**< Driver */
uint32_t retryMax; /**< The retry & timeout settings */
uint8_t phyAddress; /**< PHY address ( pre-defined by pins on reset ) */
uint8_t speed; /**< 100M/10M speed */
uint8_t fullDuplex; /**< Full duplex mode */
uint8_t RMII; /**< RMII/MII mode */
} Macb;
/** @}*/
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/** \addtogroup macb_functions
@{*/
extern void MACB_SetupTimeout(Macb *pMacb, uint32_t toMax);
extern void MACB_Init(Macb *pMacb, sEmacd *pEmacd, uint8_t phyAddress);
extern uint8_t MACB_InitPhy(Macb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins);
extern uint8_t MACB_FindValidPhy(Macb * pMacb,uint8_t addrStart);
extern uint8_t MACB_ResetPhy(Macb * pMacb);
extern uint8_t MACB_AutoNegotiate(Macb *pMacb, uint8_t rmiiMode);
extern uint8_t MACB_GetLinkSpeed(Macb *pMacb,
uint8_t applySettings);
extern void MACB_DumpRegisters(Macb * pMacb);
/** @}*/
#endif // #ifndef _MACB_H

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _MATH_
#define _MATH_
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern uint32_t min( uint32_t dwA, uint32_t dwB ) ;
extern uint32_t absv( int32_t lValue ) ;
extern uint32_t power( uint32_t dwX, uint32_t dwY ) ;
#endif /* #ifndef _MATH_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \ingroup sdmmc_hal
* \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib)
*
* \section Purpose
*
* This driver implements SD(IO)/MMC command operations and MCI configuration
* routines to perform SD(IO)/MMC access. It's used for upper layer
* (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations.
*
* \section Usage
*
* -# MCID_Init(): Initializes a MCI driver instance and the underlying
* peripheral.
* -# MCID_SendCmd(): Starts a MCI transfer which described by
* \ref sSdmmcCommand.
* -# MCID_CancelCmd(): Cancel a pending command.
* -# MCID_IsCmdCompleted(): Check if MCI transfer is finished.
* -# MCID_Handler(): Interrupt handler which is called by ISR handler.
* -# MCID_IOCtrl(): IO control function to report HW attributes to upper
* layer driver and modify HW settings (such as clock
* frequency, High-speed support, etc. See
* \ref sdmmc_ioctrls).
*
* \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI",
* \ref libsdmmc_module "SD/MMC Library"
*
* Related files:\n
* \ref mcid.h\n
* \ref mcid_dma.c.\n
*/
#ifndef MCID_H
#define MCID_H
/** \addtogroup mcid_module
*@{
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#include <stdio.h>
/** \addtogroup mcid_defines MCI Driver Defines
* @{*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** MCI States */
#define MCID_IDLE 0 /**< Idle */
#define MCID_LOCKED 1 /**< Locked for specific slot */
#define MCID_CMD 2 /**< Processing the command */
#define MCID_ERROR 3 /**< Command error */
/** MCI Initialize clock 400K Hz */
#define MCI_INITIAL_SPEED 400000
/** @}*/
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_structs MCI Driver Data Structs
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief MCI Driver
*/
typedef struct _Mcid
{
/** Pointer to a MCI peripheral. */
Hsmci *pMciHw;
/** Pointer to a DMA driver */
sDmad *pDmad;
/** Pointer to currently executing command. */
void *pCmd;
/** MCK source, Hz */
uint32_t dwMck;
/** DMA transfer channel */
uint32_t dwDmaCh;
/** DMA transferred data index (bytes) */
uint32_t dwXfrNdx;
/** DMA transfer size (bytes) */
uint32_t dwXSize;
/** MCI peripheral identifier. */
uint8_t bID;
/** Polling mode */
uint8_t bPolling;
/** Reserved */
uint8_t reserved;
/** state. */
volatile uint8_t bState;
} sMcid;
/** @}*/
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/** \addtogroup mcid_functions MCI Driver Functions
@{*/
extern void MCID_Init(sMcid * pMcid,
Hsmci * pMci, uint8_t bID, uint32_t dwMck,
sDmad * pDmad,
uint8_t bPolling);
extern void MCID_Reset(sMcid * pMcid);
extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot);
extern uint32_t MCID_Release(sMcid * pMcid);
extern void MCID_Handler(sMcid * pMcid);
extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd);
extern uint32_t MCID_CancelCmd(sMcid * pMcid);
extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid);
extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param);
#ifdef __cplusplus
}
#endif
/** @}*/
/**@}*/
#endif //#ifndef HSMCID_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _MII_DEFINE_H
#define _MII_DEFINE_H
/** \addtogroup eth_phy_mii
@{*/
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** \addtogroup mii_registers PHY registers Addresses
@{*/
#define MII_BMCR 0 /**< Basic Mode Control Register */
#define MII_BMSR 1 /**< Basic Mode Status Register */
#define MII_PHYID1 2 /**< PHY Idendifier Register 1 */
#define MII_PHYID2 3 /**< PHY Idendifier Register 2 */
#define MII_ANAR 4 /**< Auto_Negotiation Advertisement Register */
#define MII_ANLPAR 5 /**< Auto_negotiation Link Partner Ability Register */
#define MII_ANER 6 /**< Auto-negotiation Expansion Register */
#define MII_DSCR 16 /**< Specified Configuration Register */
#define MII_DSCSR 17 /**< Specified Configuration and Status Register */
#define MII_10BTCSR 18 /**< 10BASE-T Configuration and Satus Register */
#define MII_PWDOR 19 /**< Power Down Control Register */
#define MII_CONFIGR 20 /**< Specified config Register */
#define MII_MDINTR 21 /**< Specified Interrupt Register */
#define MII_RECR 22 /**< Specified Receive Error Counter Register */
#define MII_DISCR 23 /**< Specified Disconnect Counter Register */
#define MII_RLSR 24 /**< Hardware Reset Latch State Register */
/** @}*/
/** \addtogroup phy_bmcr Basic Mode Control Register (BMCR, 0)
List Bit definitions: \ref MII_BMCR
@{*/
#define MII_RESET (1ul << 15) /**< 1= Software Reset; 0=Normal Operation */
#define MII_LOOPBACK (1ul << 14) /**< 1=loopback Enabled; 0=Normal Operation */
#define MII_SPEED_SELECT (1ul << 13) /**< 1=100Mbps; 0=10Mbps */
#define MII_AUTONEG (1ul << 12) /**< Auto-negotiation Enable */
#define MII_POWER_DOWN (1ul << 11) /**< 1=Power down 0=Normal operation */
#define MII_ISOLATE (1ul << 10) /**< 1 = Isolates 0 = Normal operation */
#define MII_RESTART_AUTONEG (1ul << 9) /**< 1 = Restart auto-negotiation 0 = Normal operation */
#define MII_DUPLEX_MODE (1ul << 8) /**< 1 = Full duplex operation 0 = Normal operation */
#define MII_COLLISION_TEST (1ul << 7) /**< 1 = Collision test enabled 0 = Normal operation */
/** Reserved bits: 6 to 0, Read as 0, ignore on write */
/** @}*/
/** \addtogroup phy_bmsr Basic Mode Status Register (BMSR, 1)
List Bit definitions: \ref MII_BMSR
@{*/
#define MII_100BASE_T4 (1ul << 15) /**< 100BASE-T4 Capable */
#define MII_100BASE_TX_FD (1ul << 14) /**< 100BASE-TX Full Duplex Capable */
#define MII_100BASE_T4_HD (1ul << 13) /**< 100BASE-TX Half Duplex Capable */
#define MII_10BASE_T_FD (1ul << 12) /**< 10BASE-T Full Duplex Capable */
#define MII_10BASE_T_HD (1ul << 11) /**< 10BASE-T Half Duplex Capable */
/** Reserved bits: 10 to 7, Read as 0, ignore on write */
#define MII_MF_PREAMB_SUPPR (1ul << 6) /**< MII Frame Preamble Suppression */
#define MII_AUTONEG_COMP (1ul << 5) /**< Auto-negotiation Complete */
#define MII_REMOTE_FAULT (1ul << 4) /**< Remote Fault */
#define MII_AUTONEG_ABILITY (1ul << 3) /**< Auto Configuration Ability */
#define MII_LINK_STATUS (1ul << 2) /**< Link Status */
#define MII_JABBER_DETECT (1ul << 1) /**< Jabber Detect */
#define MII_EXTEND_CAPAB (1ul << 0) /**< Extended Capability */
/** @}*/
/** \addtogroup phy_id PHY ID Identifier Register (PHYID, 2,3)
List definitions: \ref MII_PHYID1, \ref MII_PHYID2
@{*/
#define MII_LSB_MASK 0x3F /**< Mask for PHY ID LSB */
#if defined(BOARD_EMAC_PHY_COMP_DM9161)
#define MII_OUI_MSB 0x0181
#define MII_OUI_LSB 0x2E
//#define MII_PHYID1_OUI 0x606E // OUI: Organizationally Unique Identifier
//#define MII_ID 0x0181b8a0
#elif defined(BOARD_EMAC_PHY_COMP_LAN8700)
#define MII_OUI_MSB 0x0007
#define MII_OUI_LSB 0x30
#elif defined(BOARD_EMAC_PHY_COMP_KSZ8051RNL)
#define MII_OUI_MSB 0x0022
#define MII_OUI_LSB 0x05
#else
#error no PHY Ethernet component defined !
#endif
/** @}*/
/** \addtogroup phy_neg Auto-negotiation (ANAR, 4; ANLPAR, 5)
- Auto-negotiation Advertisement Register (ANAR)
- Auto-negotiation Link Partner Ability Register (ANLPAR)
Lists Bit definitions: \ref MII_ANAR, \ref MII_ANLPAR
@{*/
#define MII_NP (1ul << 15) /**< Next page Indication */
#define MII_ACK (1ul << 14) /**< Acknowledge */
#define MII_RF (1ul << 13) /**< Remote Fault */
/** Reserved: 12 to 11, Write as 0, ignore on read */
#define MII_FCS (1ul << 10) /**< Flow Control Support */
#define MII_T4 (1ul << 9) /**< 100BASE-T4 Support */
#define MII_TX_FDX (1ul << 8) /**< 100BASE-TX Full Duplex Support */
#define MII_TX_HDX (1ul << 7) /**< 100BASE-TX Support */
#define MII_10_FDX (1ul << 6) /**< 10BASE-T Full Duplex Support */
#define MII_10_HDX (1ul << 5) /**< 10BASE-T Support */
/** Selector: 4 to 0, Protocol Selection Bits */
#define MII_AN_IEEE_802_3 0x0001
/** @}*/
/** \addtogroup phy_neg_exp Auto-negotiation Expansion Register (ANER, 6)
List Bit definitions: \ref MII_ANER
@{*/
/** Reserved: 15 to 5, Read as 0, ignore on write */
#define MII_PDF (1ul << 4) /**< Local Device Parallel Detection Fault */
#define MII_LP_NP_ABLE (1ul << 3) /**< Link Partner Next Page Able */
#define MII_NP_ABLE (1ul << 2) /**< Local Device Next Page Able */
#define MII_PAGE_RX (1ul << 1) /**< New Page Received */
#define MII_LP_AN_ABLE (1ul << 0) /**< Link Partner Auto-negotiation Able */
/** @}*/
/** \addtogroup phy_dscr Specified Configuration Register (DSCR, 16)
List Bit definitions: \ref MII_DSCR
@{*/
#define MII_BP4B5B (1ul << 15) /**< Bypass 4B5B Encoding and 5B4B Decoding */
#define MII_BP_SCR (1ul << 14) /**< Bypass Scrambler/Descrambler Function */
#define MII_BP_ALIGN (1ul << 13) /**< Bypass Symbol Alignment Function */
#define MII_BP_ADPOK (1ul << 12) /**< BYPASS ADPOK */
#define MII_REPEATER (1ul << 11) /**< Repeater/Node Mode */
#define MII_TX (1ul << 10) /**< 100BASE-TX Mode Control */
#define MII_FEF (1ul << 9) /**< Far end Fault enable */
#define MII_RMII_ENABLE (1ul << 8) /**< Reduced MII Enable */
#define MII_F_LINK_100 (1ul << 7) /**< Force Good Link in 100Mbps */
#define MII_SPLED_CTL (1ul << 6) /**< Speed LED Disable */
#define MII_COLLED_CTL (1ul << 5) /**< Collision LED Enable */
#define MII_RPDCTR_EN (1ul << 4) /**< Reduced Power Down Control Enable */
#define MII_SM_RST (1ul << 3) /**< Reset State Machine */
#define MII_MFP_SC (1ul << 2) /**< MF Preamble Suppression Control */
#define MII_SLEEP (1ul << 1) /**< Sleep Mode */
#define MII_RLOUT (1ul << 0) /**< Remote Loopout Control */
/** @}*/
/** \addtogroup phy_dscsr Specified Configuration and Status Register (DSCSR, 17)
List Bit definitions: \ref MII_DSCSR
@{*/
#define MII_100FDX (1ul << 15) /**< 100M Full Duplex Operation Mode */
#define MII_100HDX (1ul << 14) /**< 100M Half Duplex Operation Mode */
#define MII_10FDX (1ul << 13) /**< 10M Full Duplex Operation Mode */
#define MII_10HDX (1ul << 12) /**< 10M Half Duplex Operation Mode */
/** @}*/
/** \addtogroup phy_10btcsr 10BASE-T Configuration/Status (10BTCSR, 18)
List Bit definitions: \ref MII_10BTCSR
@{*/
/** Reserved: 18 to 15, Read as 0, ignore on write */
#define MII_LP_EN (1ul << 14) /**< Link Pulse Enable */
#define MII_HBE (1ul << 13) /**< Heartbeat Enable */
#define MII_SQUELCH (1ul << 12) /**< Squelch Enable */
#define MII_JABEN (1ul << 11) /**< Jabber Enable */
#define MII_10BT_SER (1ul << 10) /**< 10BASE-T GPSI Mode */
/** Reserved: 9 to 1, Read as 0, ignore on write */
#define MII_POLR (1ul << 0) /**< Polarity Reversed */
/** @}*/
/** \addtogroup phy_mdintr Specified Interrupt Register (MDINTR, 21)
List Bit definitions: \ref MII_MDINTR
@{*/
#define MII_INTR_PEND (1ul << 15) /**< Interrupt Pending */
/** Reserved: 14 to 12, Reserved */
#define MII_FDX_MASK (1ul << 11) /**< Full-duplex Interrupt Mask */
#define MII_SPD_MASK (1ul << 10) /**< Speed Interrupt Mask */
#define MII_LINK_MASK (1ul << 9) /**< Link Interrupt Mask */
#define MII_INTR_MASK (1ul << 8) /**< Master Interrupt Mask */
/** Reserved: 7 to 5, Reserved */
#define MII_FDX_CHANGE (1ul << 4) /**< Duplex Status Change Interrupt */
#define MII_SPD_CHANGE (1ul << 3) /**< Speed Status Change Interrupt */
#define MII_LINK_CHANGE (1ul << 2) /**< Link Status Change Interrupt */
/** Reserved: 1, Reserved */
#define MII_INTR_STATUS (1ul << 0) /**< Interrupt Status */
/** @}*/
/**@}*/
#endif // #ifndef _MII_DEFINE_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OMNIVISION_H
#define OMNIVISION_H
/*---------------------------------------------------------------------------
* TYPE
*---------------------------------------------------------------------------*/
/** define a structure for ovxxxx register initialization values */
struct ov_reg
{
/* Register to be written */
uint16_t reg;
/* Value to be written in the register */
uint8_t val;
};
/*---------------------------------------------------------------------------
* DEFINITAION
*---------------------------------------------------------------------------*/
#define OV_2640 0x00
#define OV_2643 0x01
#define OV_5640 0x02
#define OV_7740 0x03
#define OV_9740 0x04
#define OV_UNKNOWN 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t ov_init(Twid *pTwid);
extern void ov_DumpRegisters8(Twid *pTwid);
extern void ov_DumpRegisters16(Twid *pTwid);
extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist);
extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist);
extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData);
extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData);
extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val);
extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val);
extern void isOV5640_AF_InitDone(Twid *pTwid);
extern uint32_t ov_5640_AF_single(Twid *pTwid);
extern uint32_t ov_5640_AF_continue(Twid *pTwid);
extern uint32_t ov_5640_AFPause(Twid *pTwid);
extern uint32_t ov_5640_AFrelease(Twid *pTwid);
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef OV_H
#define OV_H
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** Captor capture size */
struct capture_size {
uint32_t width;
uint32_t height;
};
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth);
extern void ov_5640Afc_Firmware(Twid *pTwid);
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _YUV_H_
#define _YUV_H_
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Exported variable
*---------------------------------------------------------------------------*/
extern const struct ov_reg ov2640_yuv_vga[];
extern const struct ov_reg ov2643_yuv_vga[];
extern const struct ov_reg ov2643_yuv_swvga[];
extern const struct ov_reg ov2643_yuv_uxga[];
extern const struct ov_reg ov5640_yuv_vga[];
extern const struct ov_reg ov5640_yuv_sxga[];
extern const struct ov_reg ov5640_afc[];
extern const struct ov_reg ov7740_yuv_vga[];
extern const struct ov_reg ov9740_yuv_sxga[];
extern const struct ov_reg ov9740_yuv_vga[];
#endif // #ifndef _YUV_H_

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation QT1070 driver.
*
*/
#ifndef QT1070_H
#define QT1070_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** Slave address */
#define QT1070_SLAVE_ADDRESS 0x1B
/** Internal Register Address Allocation */
/** Chip ID register*/
#define QT1070_CHIP_ID 0
/** Firmware version register*/
#define QT1070_REG_FIRMWARE_VERSION 1
/** Detection status*/
#define QT1070_REG_DETECTION_STATUS 2
/** Key status*/
#define QT1070_REG_KEY_STATUS 3
/** Key signal */
#define QT1070_REG_KEY0_SIGNAL_MSB 4
#define QT1070_REG_KEY0_SIGNAL_LSB 5
#define QT1070_REG_KEY1_SIGNAL_MSB 6
#define QT1070_REG_KEY1_SIGNAL_LSB 7
#define QT1070_REG_KEY2_SIGNAL_MSB 8
#define QT1070_REG_KEY2_SIGNAL_LSB 9
#define QT1070_REG_KEY3_SIGNAL_MSB 10
#define QT1070_REG_KEY3_SIGNAL_LSB 11
#define QT1070_REG_KEY4_SIGNAL_MSB 12
#define QT1070_REG_KEY4_SIGNAL_LSB 13
#define QT1070_REG_KEY5_SIGNAL_MSB 14
#define QT1070_REG_KEY5_SIGNAL_LSB 15
#define QT1070_REG_KEY6_SIGNAL_MSB 16
#define QT1070_REG_KEY6_SIGNAL_LSB 17
/** Reference date */
#define QT1070_REG_REFDATA0_MSB 18
#define QT1070_REG_REFDATA0_LSB 19
#define QT1070_REG_REFDATA1_MSB 20
#define QT1070_REG_REFDATA1_LSB 21
#define QT1070_REG_REFDATA2_MSB 22
#define QT1070_REG_REG_REFDATA2_LSB 23
#define QT1070_REG_REFDATA3_MSB 24
#define QT1070_REG_REG_REFDATA3_LSB 25
#define QT1070_REG_REFDATA4_MSB 26
#define QT1070_REG_REFDATA4_LSB 27
#define QT1070_REG_REFDATA5_MSB 28
#define QT1070_REG_REFDATA5_LSB 29
#define QT1070_REG_REFDATA6_MSB 30
#define QT1070_REG_REFDATA6_LSB 31
/** Negative threshold level */
#define QT1070_REG_NTHR_KEY0 32
#define QT1070_REG_NTHR_KEY1 33
#define QT1070_REG_NTHR_KEY2 34
#define QT1070_REG_NTHR_KEY3 35
#define QT1070_REG_NTHR_KEY4 36
#define QT1070_REG_NTHR_KEY5 37
#define QT1070_REG_NTHR_KEY6 38
/** Adjacent key suppression level */
#define QT1070_REG_AVEAKS_KEY0 39
#define QT1070_REG_AVEAKS_KEY1 40
#define QT1070_REG_AVEAKS_KEY2 41
#define QT1070_REG_AVEAKS_KEY3 42
#define QT1070_REG_AVEAKS_KEY4 43
#define QT1070_REG_AVEAKS_KEY5 44
#define QT1070_REG_AVEAKS_KEY6 45
/** Detection interator conter for key*/
#define QT1070_REG_DI_KEY0 46
#define QT1070_REG_DI_KEY1 47
#define QT1070_REG_DI_KEY2 48
#define QT1070_REG_DI_KEY3 49
#define QT1070_REG_DI_KEY4 50
#define QT1070_REG_DI_KEY5 51
#define QT1070_REG_DI_KEY6 52
/** Low power mode */
#define QT1070_REG_LOWPOWER_MODE 54
/** Maximum on duration */
#define QT1070_REG_MAX_DURATION 55
/** Calibrate */
#define QT1070_REG_CALIRATE 56
/** Reset */
#define QT1070_REG_RESET 57
/** Detection Status. */
/** This bit is set during a calibration sequence.*/
#define QT_CALIBRATE_BIT 7
/** This bit is set if the time to acquire all key signals exceeds 8 ms*/
#define QT_OVERFLOW_BIT 6
/** This bit is set if Comms mode is enabled. */
#define QT_COMMSENABLED_BIT 5
/** This bit is set if any keys are in detect. */
#define QT_TOUCH_BIT 0
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint8_t QT1070_GetChipId(Twid *pTwid);
extern uint8_t QT1070_GetFirmwareVersion(Twid *pTwid);
extern uint8_t QT1070_GetDetection_Status(Twid *pTwid);
extern uint8_t QT1070_GetKey_Status(Twid *pTwid);
extern uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key);
extern uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key);
extern void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold);
extern void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks);
extern void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di);
extern void QT1070_StartCalibrate(Twid *pTwid);
extern void QT1070_StartReset(Twid *pTwid);
#endif // QT1070_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* \file
*
* \section Purpose
* Small function for gererating random number.
*
*------------------------------------------------------------------------------*/
#ifndef _RAND_
#define _RAND_
/*------------------------------------------------------------------------------
* Global Functions
*------------------------------------------------------------------------------*/
extern void srand( uint32_t dwSeed ) ;
extern uint32_t rand( void ) ;
#endif /* #ifndef _RAND_ */

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/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file syscalls.h
*
* Implementation of newlib syscall.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdarg.h>
#include <sys/types.h>
#include <sys/stat.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern caddr_t _sbrk ( int incr ) ;
extern int link( char *old, char *new ) ;
extern int _close( int file ) ;
extern int _fstat( int file, struct stat *st ) ;
extern int _isatty( int file ) ;
extern int _lseek( int file, int ptr, int dir ) ;
extern int _read(int file, char *ptr, int len) ;
extern int _write( int file, char *ptr, int len ) ;

80
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \par Purpose
*
* Methods and definitions for Global time tick and wait functions.
*
* Defines a common and simpliest use of Time Tick, to increase tickCount
* every 1ms, the application can get this value through GetTickCount().
*
* \par Usage
*
* -# Configure the System Tick with TimeTick_Configure() when MCK changed
* \note
* Must be done before any invoke of GetTickCount(), Wait() or Sleep().
* -# Uses GetTickCount to get current tick value.
* -# Uses Wait to wait several ms.
* -# Uses Sleep to enter wait for interrupt mode to wait several ms.
*
*/
#ifndef _TIMETICK_
#define _TIMETICK_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;
extern void TimeTick_Increment( uint32_t dwInc ) ;
extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick);
extern uint32_t GetTickCount( void ) ;
extern void Wait( volatile uint32_t dwMs ) ;
extern void Sleep( volatile uint32_t dwMs ) ;
#endif /* _TIMETICK_ */

86
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup tsd_module TouchScreen Driver
*
* \section Purpose
*
* This unit provides a very powerful touchscreen driver which handles all the
* complexity. This includes touchscreen calibration, retrieving measurements,
* configuring the TSADC, etc.
*
* \section Usage
*
* -# Implement ADC interrupt handler in application, to invoke TSD_Handler()
* to handle ADC sampling events for touchscreen monitor.
* -# Call TSD_Initialize() to initialize ADC used for touchscreen.
* -# Call TSD_Calibrate() to do touchscreen calibration with LCD, and enable
* touchscreen monitor if calibration success.
* -# Call TSD_Enable() to enable or disable touchscreen monitoring.
* -# Declare a global TSD_PenPressed() function anywhere in your code. This
* function will get called every time the pen is pressed on the screen.
* -# Declare a global TSD_PenMoved() function, which will get called whenever
* the pen stays in contact with the screen but changes position.
* -# Declare a global TSD_PenReleased() function, which will be invoked as the
* pen is lifted from the screen.
*/
#ifndef TSD_H
#define TSD_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSD_Handler(uint32_t dwAdcStatus);
extern void TSD_Initialize(void);
extern void TSD_DeInitialize(void);
extern void TSD_Enable(uint8_t bEnDis);
extern uint8_t TSD_Calibrate(void);
/* calibration used functions */
extern void TSD_GetRawMeasurement(uint32_t * pData);
extern void TSD_WaitPenPressed(void);
extern void TSD_WaitPenReleased(void);
/* callbacks */
extern void TSD_PenPressed(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenMoved(uint32_t x, uint32_t y, uint32_t pressure);
extern void TSD_PenReleased(uint32_t x, uint32_t y);
#endif //#ifndef TSD_H

50
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
#ifndef TSD_COM_H
#define TSD_COM_H
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
extern void TSDCom_InterpolateMeasurement(
const uint32_t *pData,
uint32_t *pPoint);
uint8_t TSDCom_Calibrate(void);
uint8_t TSDCom_IsCalibrationOk(void);
void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size);
void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size);
#endif /* #ifndef TSD_COM_H */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef WAV_H
#define WAV_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
/* Standard WAV file header information. */
typedef struct _WavHeader
{
/* Contains the letters "RIFF" in ASCII form. */
unsigned int chunkID;
/* Size of the rest of the chunk following this number.*/
unsigned int chunkSize;
/* Contains the letters "WAVE".*/
unsigned int format;
/* Contains the letters "fmt ".*/
unsigned int subchunk1ID;
/* 16 for PCM. This is the size of the rest of the Subchunk which follows this number.*/
unsigned int subchunk1Size;
/* PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression.*/
unsigned short audioFormat;
/* Mono = 1, Stereo = 2, etc.*/
unsigned short numChannels;
/* 8000, 44100, etc.*/
unsigned int sampleRate;
/* SampleRate * NumChannels * BitsPerSample/8*/
unsigned int byteRate;
/* NumChannels * BitsPerSample/8*/
unsigned short blockAlign;
/* 8 bits = 8, 16 bits = 16, etc.*/
unsigned short bitsPerSample;
/* Contains the letters "data".*/
unsigned int subchunk2ID;
/* Number of bytes in the data.*/
unsigned int subchunk2Size;
} WavHeader;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern unsigned char WAV_IsValid(const WavHeader *header);
extern void WAV_DisplayInfo(const WavHeader *header);
#endif //#ifndef WAV_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation WM8904 driver.
*
*/
#ifndef WM8904_H
#define WM8904_H
#include "board.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
#define WM8904_CSB_STATE (0x0 << 0)
/** Slave address */
#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE
/** Reset register*/
#define WM8904_REG_RESET 0x00
/** Bias control 0 register*/
#define WM8904_REG_BIAS_CTRL0 0x04
/** VMID control 0 register*/
#define WM8904_REG_VMID_CTRL0 0x05
/** MIC Bias control 0 register*/
#define WM8904_REG_MICBIAS_CTRL0 0x06
/** Bias control 1 register*/
#define WM8904_REG_BIAS_CTRL1 0x07
/** Power management control 0 register*/
#define WM8904_REG_POWER_MANG0 0x0C
/** Power management control 2 register*/
#define WM8904_REG_POWER_MANG2 0x0E
/** Power management control 3 register*/
#define WM8904_REG_POWER_MANG3 0x0F
/** Power management control 6 register*/
#define WM8904_REG_POWER_MANG6 0x12
/** Clock rate0 register*/
#define WM8904_REG_CLOCK_RATE0 0x14
/** Clock rate1 register*/
#define WM8904_REG_CLOCK_RATE1 0x15
/** Clock rate2 register*/
#define WM8904_REG_CLOCK_RATE2 0x16
/** Audio interface0 register*/
#define WM8904_REG_AUD_INF0 0x18
/** Audio interface1 register*/
#define WM8904_REG_AUD_INF1 0x19
/** Audio interface2 register*/
#define WM8904_REG_AUD_INF2 0x1A
/** Audio interface3 register*/
#define WM8904_REG_AUD_INF3 0x1B
/** ADC digital 0 register*/
#define WM8904_REG_ADC_DIG0 0x20
/** ADC digital 1 register*/
#define WM8904_REG_ADC_DIG1 0x21
/** Analogue left input 0 register*/
#define WM8904_REG_ANALOGUE_LIN0 0x2C
/** Analogue right input 0 register*/
#define WM8904_REG_ANALOGUE_RIN0 0x2D
/** Analogue left input 1 register*/
#define WM8904_REG_ANALOGUE_LIN1 0x2E
/** Analogue right input 1 register*/
#define WM8904_REG_ANALOGUE_RIN1 0x2F
/** Analogue left output 1 register*/
#define WM8904_REG_ANALOGUE_LOUT1 0x39
/** Analogue right output 1 register*/
#define WM8904_REG_ANALOGUE_ROUT1 0x3A
/** Analogue left output 2 register*/
#define WM8904_REG_ANALOGUE_LOUT2 0x3B
/** Analogue right output 2 register*/
#define WM8904_REG_ANALOGUE_ROUT2 0x3C
/** Analogue output 12 ZC register*/
#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D
/** DC servo 0 register*/
#define WM8904_REG_DC_SERVO0 0x43
/** Analogue HP 0 register*/
#define WM8904_REG_ANALOGUE_HP0 0x5A
/** Charge pump 0 register*/
#define WM8904_REG_CHARGE_PUMP0 0x62
/** Class W 0 register*/
#define WM8904_REG_CLASS0 0x68
/** FLL control 1 register*/
#define WM8904_REG_FLL_CRTL1 0x74
/** FLL control 2 register*/
#define WM8904_REG_FLL_CRTL2 0x75
/** FLL control 3 register*/
#define WM8904_REG_FLL_CRTL3 0x76
/** FLL control 4 register*/
#define WM8904_REG_FLL_CRTL4 0x77
/** FLL control 5 register*/
#define WM8904_REG_FLL_CRTL5 0x78
/** DUMMY register*/
#define WM8904_REG_END 0xFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr);
extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data);
extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device );
extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value);
extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device);
#endif // WM8904_H

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FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-ddram.mac Normal file
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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d3x-ek-ddram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
__var REG_CKGR_MOR;
__var CKGR_MOR_MOSCXTEN;
__var CKGR_MOR_MOSCXTBY;
__var CKGR_MOR_MOSCRCEN;
__var CKGR_MOR_MOSCSEL;
__var REG_CKGR_MCFR;
__var CKGR_MCFR_MAINFRDY;
__var REG_PMC_SR;
__var PMC_SR_MCKRDY;
__var PMC_SR_LOCKA;
__var PMC_PCK_CSS_MAIN_CLK;
__var REG_CKGR_PLLAR;
__var REG_PMC_PLLICPR;
__var REG_PMC_MCKR;
__var PMC_MCKR_PLLADIV2_DIV2;
__var PMC_MCKR_PRES_Msk;
__var PMC_MCKR_PRES_CLOCK;
__var PMC_MCKR_MDIV_Msk;
__var PMC_MCKR_MDIV_PCK_DIV3;
__var PMC_MCKR_CSS_PLLA_CLK;
__var PMC_SR_MOSCSELS;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
CheckNoRemap();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
// DDR reset
//MPDDRC->MPDDRC_LPR = MPDDRC_LPR_LPCB_DEEP_PWD |MPDDRC_LPR_CLK_FR_ENABLED;
__writeMemory32(0x07,0xFFFFEA1C,"Memory");
// Disable DDR clock
//PMC->PMC_PCDR1 |= (1 << (ID_MPDDRC-32));
__tempo_var = __readMemory32(0xFFFFFD08,"Memory");
__tempo_var |= 0x00020000;
__writeMemory32(__tempo_var,0xFFFFFD04,"Memory"); // Enable MPDDR controller clock
// PMC->PMC_SCDR |= PMC_SCER_DDRCK;
__tempo_var = __readMemory32(0xFFFFFC08,"Memory");
__tempo_var |= 0x00000084;
__writeMemory32(__tempo_var,0xFFFFFC04,"Memory"); // System Clock Enable Register : Enable DDR clock
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA();
PMC_SetMckPllaDiv();
PMC_SetMckPrescaler();
PMC_SetMckDivider();
PMC_SwitchMck2Pll();
__message "------------ PLL set to 792 MHz, MCK set to 132 MHz ------------";
//#define DDRAM_MT47H64M16HR 0
//#define DDRAM_MT47H128M16RT 1
//#define BOARD_DDRAM_TYPE DDRAM_MT47H128M16RT
__initDDR2(1); //* Init DDR2 memory
__message "------------ DDR2 is initialized ------------";
CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFFFFEE40,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
__tempo_var = __readMemory32(0x00000000,"Memory");
if (__tempo_var == 0xAA55AA55)
{
__data_test = 0x55AA55AA;
}
else
{
__data_test = 0xAA55AA55;
}
__writeMemory32(__data_test,0x00000000,"Memory");
__dummy_read = __readMemory32(0x00000000,"Memory");
__writeMemory32(__tempo_var,0x00000000,"Memory");
if (__dummy_read == __data_test)
{
__message " ------------------------ The Remap is already done ------------------------";
}
else
{
__message " ------------------------ The Remap is not DONE ------------------------";
__writeMemory32(0x00000001,0xFFFFED00,"Memory");
__delay(2);
__writeMemory32(0x00000001,0x00800000,"Memory");
__delay(50);
__message "------------ The Remap was executed ------------";
}
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFFFFFE44,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}
/*********************************************************************
*
* PMC_SelectExt12M_Osc()
*
* Function description
* Select external 12MHz oscillator
*/
PMC_SelectExt12M_Osc()
{
REG_CKGR_MOR = 0xFFFFFC20;
CKGR_MOR_MOSCXTEN = (0x1 << 0); /*(CKGR_MOR) Main Crystal Oscillator Enable */
CKGR_MOR_MOSCXTBY = (0x1 << 1); /*(CKGR_MOR) Main Crystal Oscillator Bypass */
CKGR_MOR_MOSCRCEN = (0x1 << 3); /*(CKGR_MOR) Main On-Chip RC Oscillator Enable */
CKGR_MOR_MOSCSEL = (0x1 << 24); /*(CKGR_MOR) Main Oscillator Selection */
REG_CKGR_MCFR = 0xFFFFFC24; /*(PMC) Main Clock Frequency Register */
CKGR_MCFR_MAINFRDY = (0x1 << 16); /*(CKGR_MCFR) Main Clock Ready */
REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */
PMC_SR_MOSCSELS = (0x1 << 16); /*(PMC_SR) Main Oscillator Selection Status */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
/* enable external OSC 12 MHz */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCXTEN | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait Main CLK Ready */
while(!((__readMemory32(REG_CKGR_MCFR,"Memory")) & CKGR_MCFR_MAINFRDY));
/* disable external OSC 12 MHz bypass */
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var = (__tempo_var & ~CKGR_MOR_MOSCXTBY) | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* switch MAIN clock to external OSC 12 MHz*/
__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
__tempo_var |= CKGR_MOR_MOSCSEL | (0x37 << 16);
__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
/* wait MAIN clock status change for external OSC 12 MHz selection*/
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MOSCSELS));
/* in case when MCK is running on MAIN CLK */
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
/* disable internal RC 12 MHz*/
//__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");
//__tempo_var = (__tempo_var & ~CKGR_MOR_MOSCRCEN) | (0x37 << 16);
//__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");
//__mac_i=__readMemory32(REG_CKGR_MOR,"Memory");
__message " -------- PMC_SelectExt12M_Osc ---------- REG_CKGR_MOR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Main()
*
* Function description
* Switch PMC from MCK to main clock.
*/
PMC_SwitchMck2Main()
{
REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */
PMC_PCK_CSS_MAIN_CLK = (0x1 << 0); /*(PMC_PCK[3]) Main Clock is selected */
PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */
REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */
/* Select Main Oscillator as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03)| PMC_PCK_CSS_MAIN_CLK ;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Main ----------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetPllA()
*
* Function description
* Configure PLLA Registe.
*/
PMC_SetPllA()
{
REG_CKGR_PLLAR = 0xFFFFFC28; /*(PMC) PLLA Register */
REG_PMC_PLLICPR = 0xFFFFFC80; /*(PMC) PLL Charge Pump Current Register */
REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */
PMC_SR_LOCKA = (0x1 << 1); /*(PMC_SR) PLLA Lock Status */
__writeMemory32(((0x1 << 29) | (0x3F << 8) | ( 0 << 14) | (65 << 18) | 1 ), REG_CKGR_PLLAR,"Memory");
__writeMemory32((0x03<<8), REG_PMC_PLLICPR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_LOCKA));
__mac_i=__readMemory32(REG_CKGR_PLLAR,"Memory");
__message " --------- PMC_SetPllA ---------------- REG_CKGR_PLLAR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckPllaDiv()
*
* Function description
* Configure MCK PLLA divider.
*/
PMC_SetMckPllaDiv()
{
REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */
PMC_MCKR_PLLADIV2_DIV2 = (0x1 << 12); /*(PMC_MCKR) PLLA clock frequency is divided by 2. */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
if ((__tempo_var & PMC_MCKR_PLLADIV2_DIV2) != PMC_MCKR_PLLADIV2_DIV2)
{
__tempo_var |= PMC_MCKR_PLLADIV2_DIV2;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
}
}
/*********************************************************************
*
* PMC_SetMckPrescaler()
*
* Function description
* Configure MCK Prescaler.
*/
PMC_SetMckPrescaler()
{
REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */
PMC_MCKR_PRES_Msk = (0x7 << 4); /*(PMC_MCKR) Master/Processor Clock Prescaler */
PMC_MCKR_PRES_CLOCK = (0x0 << 4); /*(PMC_MCKR) Selected clock */
/* Change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLOCK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckPrescaler -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SetMckDivider()
*
* Function description
* Configure MCK Divider.
*/
PMC_SetMckDivider()
{
REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */
PMC_MCKR_MDIV_Msk = (0x3 << 8); /*(PMC_MCKR) Master Clock Division */
PMC_MCKR_MDIV_PCK_DIV3 = (0x3 << 8); /*(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
/* change MCK Prescaler divider in PMC_MCKR register */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~PMC_MCKR_MDIV_Msk) | PMC_MCKR_MDIV_PCK_DIV3;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SetMckDivider -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
/*********************************************************************
*
* PMC_SwitchMck2Pll()
*
* Function description
* Switch PMC from MCK to PLL clock.
*/
PMC_SwitchMck2Pll()
{
REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */
PMC_MCKR_CSS_PLLA_CLK = (0x2 << 0); /*(PMC_MCKR) PLLACK/PLLADIV2 is selected */
/* Select PLL as input clock for PCK and MCK */
__tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");
__tempo_var = (__tempo_var & ~0x03) | PMC_MCKR_CSS_PLLA_CLK;
__writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");
while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));
__mac_i=__readMemory32(REG_PMC_MCKR,"Memory");
__message " --------- PMC_SwitchMck2Pll -------------- REG_PMC_MCKR 0x",__mac_i:%X;
}
// ---------------------------------------------------------------------------
// Function Name : __initDDR2
// Object : Set DDR2 memory for working at 133 Mhz
// ---------------------------------------------------------------------------
__initDDR2(type)
{
// ------------------ DDR Controller Registers --------------
// 0xFFFFEA00 Mode Register MPDDRC_MR
// 0xFFFFEA04 Refresh Timer Register MPDDRC_RTR
// 0xFFFFEA08 Configuration Register MPDDRC_CR
// 0xFFFFEA0C Timing Parameter 0 Register MPDDRC_TPR0
// 0xFFFFEA10 Timing Parameter 1 Register MPDDRC_TPR1
// 0xFFFFEA14 Timing Parameter 2 Register MPDDRC_TPR2
// 0xFFFFEA1C Low-power Register MPDDRC_LPR
// 0xFFFFEA20 Memory Device Register MPDDRC_MD
// 0xFFFFEA28 LPDDR2 Low-power Register MPDDRC_LPDDR2_LPR
// 0xFFFFEA2C LPDDR2 Calibration and MR4 Register MPDDRC_LPDDR2_CAL_MR4
// 0xFFFFEA30 LPDDR2 Timing Calibration Register MPDDRC_LPDDR2_TIM_CAL
// 0xFFFFEA34 IO Calibration MPDDRC_IO_CALIBR
// 0xFFFFEA38 OCMS Register MPDDRC_OCMS
// 0xFFFFEA3C OCMS KEY1 Register MPDDRC_OCMS_KEY1 Write-only
// 0xFFFFEA40 OCMS KEY2 Register MPDDRC_OCMS_KEY2 Write-only
// 0xFFFFEA74 DLL Master Offset Register MPDDRC_DLL_MOR
// 0xFFFFEA78 DLL Slave Offset Register MPDDRC_DLL_SOR
// 0xFFFFEA7C DLL Master Status Register MPDDRC_DLL_MSR Read-only
// 0xFFFFEA80 DLL Slave 0 Status Register MPDDRC_DLL_S0SR Read-only
// 0xFFFFEA84 DLL Slave 1 Status Register MPDDRC_DLL_S1SR Read-only
// 0xFFFFEAE4 Write Protect Control Register MPDDRC_WPCR
// 0xFFFFEAE8 Write Protect Status Register MPDDRC_WPSR Read-only
// -----------------------------------------------
// ---------------- DDR2 Timings (133MHz) -----------------
// -------- Configuration Register
// n_row = 14
// n_col = 10
// n_bank = 8
// -------- Refresh Timer Register
// t_refresh = 520
// -------- Timing 0 Register
// t_tras = TRAS 6
// t_trcd = TRCD 2
// t_twr = TWR 2
// t_trc = TRC 8
// t_trp = TRP 2
// t_trrd = TRRD 2
// t_twtr = TWTR 2
// t_tmrd = TMRD 2
// -------- Timing 1 Register
// t_trfc = TRFC 26/14
// t_txsnr = TXSNR 28/16
// t_txsrd = TXSRD 208
// t_txp = TXP 2
// -------- Timing 2 Register
// t_txard = TXARD 7
// t_tards = TXARDS 7
// t_trpa = TRPA 3
// t_trtp = TRTP 2
// t_tfaw = TFAW 10
// -----------------------------------------------
if (type == 0) {
__message " --------- Configure MT47H128M16 DDR2 ";
} else {
__message " --------- Configure MT47H64M16 DDR2 ";
}
__delay(2);
__writeMemory32(0x00008000,0xFFFFFE44,"Memory"); // Disable Watchdog
__writeMemory32(0x10000,0xFFFFEA1C,"Memory");
__writeMemory32(0x00020000,0xFFFFFD00,"Memory"); // Enable MPDDR controller clock
__writeMemory32(0x00000004,0xFFFFFC00,"Memory"); // System Clock Enable Register : Enable DDR clock
// __writeMemory32(0x00000020,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register (MPDDRC_HS) : hidden option -> calibration during autorefresh
// __writeMemory32(0x00030000,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration Force DDR_DQ and DDR_DQS input buffer always on
__writeMemory32(0x01010101,0xFFFFEA78,"Memory"); // MPDDRC DLL Slave Offset Register : set DLL Slave x Delay Line Offset
__writeMemory32(0xC5011F07,0xFFFFEA74,"Memory"); // MPDDRC DLL Master Offset Register : DLL Master Delay Line Offset + DLL CLK90 Delay Line Offset + DLL Offset Selection
// __writeMemory32(0x00000028,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register : enable calibration during autorefresh
// __writeMemory32(0x00030001,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration : Force DDR_DQ and DDR_DQS input buffer always on
__writeMemory32(0x01010101,0xFFFFEA78,"Memory"); // MPDDRC DLL Slave Offset Register : set DLL Slave x Delay Line Offset
__writeMemory32(0xC5011f07,0xFFFFEA74,"Memory"); // MPDDRC DLL Master Offset Register : DLL Master Delay Line Offset + DLL CLK90 Delay Line Offset + DLL Offset Selection
__writeMemory32(0x00870303,0xFFFFEA34,"Memory"); // MPDDRC I/O Calibration Register : set Resistor Divider + IO Calibration (delay between an IO Calibration Command and any Valid commands)
__writeMemory32(0x00001100,0xFFFFEA80,"Memory");
__writeMemory32(0x00001100,0xFFFFEA84,"Memory");
__writeMemory32(0x00001100,0xFFFFEA88,"Memory");
__writeMemory32(0x00001100,0xFFFFEA8C,"Memory");
// __writeMemory32(0x00000028,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register : enable calibration during autorefresh
// __writeMemory32(0x00030001,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration : Force DDR_DQ and DDR_DQS input buffer always on
__writeMemory32(0x00000006,0xFFFFEA20,"Memory"); // Memory Device Register : 32bit mode - DDR2 mode
if (type == 0) {
__writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : row = 13, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength
} else {
__writeMemory32(0x00B0004D,0xFFFFEA08,"Memory"); // Configuration Register : row = 14, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength
}
__writeMemory32(0x22228326,0xFFFFEA0C,"Memory"); // Timing 0 Register : tras | trcd | twr | trc | trp | trrd | twtr | tmrd
__writeMemory32(0x02C81C1A,0xFFFFEA10,"Memory"); // Timing 1 Register : trfc | txsnr | txsrd | txp
__writeMemory32(0x00072278,0xFFFFEA14,"Memory"); // Timing 2 Register : txard | tards | trpa | trtp | tfaw
__writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1); // wait 1 ms
__writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xFFFFEA00,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR2 BA0=0 BA1=1
if (type == 0) {
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
} else {
__writeMemory32(0x00000000,0x28000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
}
__delay(1);
__writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR3 BA0=1 BA1=1
if (type == 0) {
__writeMemory32(0x00000000,0x26000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
} else {
__writeMemory32(0x00000000,0x2C000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
}
__delay(1);
__writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR1 BA0=1 BA1=0 ENABLE DLL
if (type == 0) {
__writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
} else {
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
}
__delay(1);
__writeMemory32(0x00B000BD,0xFFFFEA08,"Memory"); // Configuration Register : Enable DLL reset
__writeMemory32(0x00000003,0xFFFFEA00,"Memory"); // Mode register : command RESET DLL
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000002,0xFFFFEA00,"Memory"); // Mode register : command All Banks Precharge
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xFFFFEA00,"Memory"); // Mode register : 2 * command Auto-Refresh
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000004,0xFFFFEA00,"Memory"); // Mode register :
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : disable DLL reset
__writeMemory32(0x00000003,0xFFFFEA00,"Memory"); // Mode register : MRS initialize device operation (CAS latency, burst length and disable DLL reset)
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00B0703D,0xFFFFEA08,"Memory"); // Configuration Register : OCD default value
__writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : EMRS1 OCD Default values
if (type == 0) {
__writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
} else {
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
}
__delay(1);
__writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : OCD exit
__writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : EMRS1 OCD exit
if (type == 0) {
__writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
} else {
__writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
}
__delay(1);
__writeMemory32(0x00000000,0xFFFFEA00,"Memory"); // Mode register : command Normal mode
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command
__delay(1);
__writeMemory32(0x00300408,0xFFFFEA04,"Memory"); // Refresh Timer register : 520 for 133 MHz
__message "------------------------------- DDR2 memory init for 133 MHz ----------------------------------";
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d3x-ek-sram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
// __message "------------------------------ execUserReset ---------------------------------";
// CheckNoRemap();
// __message "-------------------------------Set PC Reset ----------------------------------";
// __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
// __message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
// __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
// CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
// __mac_i=__readMemory32(0xFFFFEE40,"Memory");
// __message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
__tempo_var = __readMemory32(0x00000000,"Memory");
if (__tempo_var == 0xAA55AA55)
{
__data_test = 0x55AA55AA;
}
else
{
__data_test = 0xAA55AA55;
}
__writeMemory32(__data_test,0x00000000,"Memory");
__dummy_read = __readMemory32(0x00000000,"Memory");
__writeMemory32(__tempo_var,0x00000000,"Memory");
if (__dummy_read == __data_test)
{
__message " ------------------------ The Remap is already done ------------------------";
}
else
{
__message " ------------------------ The Remap is not DONE ------------------------";
__writeMemory32(0x00000001,0xFFFFED00,"Memory");
__delay(2);
__writeMemory32(0x00000001,0x00800000,"Memory");
__delay(50);
__message "------------ The Remap was executed ------------";
}
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFFFFFE44,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: sama5d3x-ek-sram.mac
// User setup file for CSPY debugger.
//
// ---------------------------------------------------------
__var __tempo_var;
__var __dummy_read;
__var __data_test;
__var __mac_i;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
//CheckNoRemap();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
//__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
//CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFFFFEE40,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
__tempo_var = __readMemory32(0x00000000,"Memory");
if (__tempo_var == 0xAA55AA55)
{
__data_test = 0x55AA55AA;
}
else
{
__data_test = 0xAA55AA55;
}
__writeMemory32(__data_test,0x00000000,"Memory");
__dummy_read = __readMemory32(0x00000000,"Memory");
__writeMemory32(__tempo_var,0x00000000,"Memory");
if (__dummy_read == __data_test)
{
__message " ------------------------ The Remap is already done ------------------------";
}
else
{
__message " ------------------------ The Remap is not DONE ------------------------";
__writeMemory32(0x00000001,0xFFFFED00,"Memory");
__delay(2);
__writeMemory32(0x00000001,0x00800000,"Memory");
__delay(50);
__message "------------ The Remap was executed ------------";
}
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
// Watchdog Disable
__writeMemory32(0x00008000,0xFFFFFE44,"Memory");
__message " ------------------------ Watchdog Disable ------------------------";
}

53
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_DDRAM_end__ = 0x20FFFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF;
define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x23000000;
define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x23FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_startup__ = 0x200;
define symbol __ICFEDIT_size_vectors__ = 0x200;
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_sysstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x0;
/*-Exports-*/
export symbol __ICFEDIT_region_DDRAM_start__;
export symbol __ICFEDIT_region_DDRAM_end__;
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_startup__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_sysstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__];
define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_DDRAM_end__];
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { section .vectors };
do not initialize { section .noinit };
place in STA_region { section .cstartup };
place in VEC_region { section .vectors };
place in DDRAM_region { readonly };
place in DDRAM_region { readwrite };
place in DDRAM_region { zeroinit };
place in DMA_BUF_region {section region_dma_nocache };
place in DDRAM_region { block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };

45
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0;
define symbol __ICFEDIT_region_RAM_start__ = 0x70000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x73FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_svcstack__ = 0x0;
define symbol __ICFEDIT_size_irqstack__ = 0x0;
define symbol __ICFEDIT_size_fiqstack__ = 0x0;
define symbol __ICFEDIT_size_undstack__ = 0x0;
define symbol __ICFEDIT_size_abtstack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
//initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ {section .intvec };
place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}};
place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .noinit,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP}};

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/**** start of ICF editor section. ###ICF###*/
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF;
define symbol __ICFEDIT_region_SRAM0_start__ = 0x00300000;
define symbol __ICFEDIT_region_SRAM0_end__ = 0x0030FFFF;
define symbol __ICFEDIT_region_SRAM1_start__ = 0x00310000;
define symbol __ICFEDIT_region_SRAM1_end__ = 0x0031FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_svcstack__ = 0x40;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region SRAM0 = mem:[from __ICFEDIT_region_SRAM0_start__ to __ICFEDIT_region_SRAM0_end__];
define region SRAM1 = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors };
place in ROM { readonly };
place in SRAM0 { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
define exported symbol fl_ram_end = (__ICFEDIT_region_SRAM0_end__ & 0xFFFFFFF8);

38
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_sysstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x0;
/*-Exports-*/
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_sysstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing=none { readwrite };
do not initialize { readonly section .noinit };
place in VEC_region { section .vectors };
place in RAM_region { readonly };
place in RAM_region { section .cstartup };
place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <string.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
/// BMP offset for header
#define IMAGE_OFFSET 0x100
/*----------------------------------------------------------------------------
* Internal types
*----------------------------------------------------------------------------*/
/** Describe the BMP palette */
typedef struct _BMPPaletteEntry
{
/** Blue value */
uint8_t b;
/** Green value */
uint8_t g;
/** Red value */
uint8_t r;
/** Filler character value */
uint8_t filler;
} BMPPaletteEntry ;
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Test if BMP is valid.
* \param file Buffer holding the file to examinate.
* \return 1 if the header of a BMP file is valid; otherwise returns 0.
*/
uint8_t BMP_IsValid( void *file )
{
return ((BMPHeader*) file)->type == BMP_TYPE ;
}
/**
* \brief Returns the size of a BMP image given at least its header (the file does
* not have to be complete).
* \param file Pointer to the buffer which holds the BMP file.
* \return size of BMP image
*/
uint32_t BMP_GetFileSize( void *file )
{
return ((BMPHeader *) file)->fileSize ;
}
/**
* \brief Write a BMP header
* \param pAddressHeader Begin address of the BMP
* \param bmpHSize BMP heigth size
* \param bmpVSize BMP width size
* \param bmpRgb Type of BMP (YUV or RGB)
* \param nbByte_Pixels Number of byte per pixels
*/
void WriteBMPheader( uint32_t* pAddressHeader, uint32_t bmpHSize, uint32_t bmpVSize, uint8_t bmpRgb, uint8_t nbByte_Pixels )
{
uint32_t i;
uint32_t* fill;
BMPHeader *Header;
bmpRgb = bmpRgb;
fill = pAddressHeader;
for ( i=0 ; i < IMAGE_OFFSET ; i+=4 )
{
*fill++ = 0;
}
Header = (BMPHeader*) pAddressHeader;
Header->type = BMP_TYPE;
Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET;
Header->reserved1 = 0;
Header->reserved2 = 0;
Header->offset = IMAGE_OFFSET;
Header->headerSize = BITMAPINFOHEADER;
Header->width = bmpHSize;
Header->height = bmpVSize;
Header->planes = 1;
Header->bits = nbByte_Pixels * 8;
Header->compression = 0;
Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels;
Header->xresolution = 0;
Header->yresolution = 0;
Header->ncolours = 0;
Header->importantcolours = 0;
}
/**
* \brief Debug function, dislay BMP header
* \param pAddressHeader Address of the BMP
*/
void BMP_displayHeader( uint32_t* pAddressHeader )
{
#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
BMPHeader *header;
header = (BMPHeader*) pAddressHeader;
TRACE_INFO("BMP\n\r");
TRACE_INFO("type 0x%X \n\r", header->type);
TRACE_INFO("fileSize %ld \n\r", header->fileSize);
TRACE_INFO("reserved1 %d \n\r", header->reserved1);
TRACE_INFO("reserved2 %d \n\r", header->reserved2);
TRACE_INFO("offset %ld \n\r", header->offset);
TRACE_INFO("headerSize %ld \n\r", header->headerSize);
TRACE_INFO("width %ld \n\r", header->width);
TRACE_INFO("height %ld \n\r", header->height);
TRACE_INFO("planes %d \n\r", header->planes);
TRACE_INFO("bits %d \n\r", header->bits);
TRACE_INFO("compression %ld \n\r", header->compression);
TRACE_INFO("imageSize %ld \n\r", header->imageSize);
TRACE_INFO("xresolution %ld \n\r", header->xresolution);
TRACE_INFO("yresolution %ld \n\r", header->yresolution);
TRACE_INFO("ncolours %ld \n\r", header->ncolours);
TRACE_INFO("importantcolours %ld\n\r", header->importantcolours);
#else
pAddressHeader = pAddressHeader;
#endif
}
/**
* \brief Loads a BMP image located at the given address, decodes it and stores the
* resulting image inside the provided buffer. Image must have the specified
* width & height.
* If no buffer is provided, this function simply checks if it is able to
* decode the image.
* \param file Buffer which holds the BMP file.
* \param buffer Buffer in which to store the decoded image.
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
* \return 0 if the image has been loaded; otherwise returns an error code.
*/
uint8_t BMP_Decode( void *file, uint8_t *buffer, uint32_t width, uint32_t height, uint8_t bpp )
{
BMPHeader *header;
uint32_t i, j;
uint8_t r, g, b;
uint8_t *image;
// Read header information
header = (BMPHeader*) file;
// Verify that the file is valid
if ( !BMP_IsValid( file ) )
{
TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type);
return 1;
}
// Check that parameters match
if ( (header->compression != 0) || (header->width != width) || (header->height != height))
{
TRACE_ERROR("BMP_Decode: File format not supported\n\r");
TRACE_ERROR(" -> .compression = %u\n\r", (unsigned int)header->compression);
TRACE_ERROR(" -> .width = %u\n\r", (unsigned int)header->width);
TRACE_ERROR(" -> .height = %u\n\r", (unsigned int)header->height);
TRACE_ERROR(" -> .bits = %d\n\r", header->bits);
return 2;
}
// Get image data
image = (uint8_t *) ((uint32_t) file + header->offset);
// Check that the bpp resolution is supported
// Only a 24-bit output & 24- or 8-bit input are supported
if ( bpp != 24 )
{
TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r");
return 3;
}
else
{
if (header->bits == 24)
{
// Decoding is ok
if (!buffer) return 0;
// Get image data (swapping red & blue)
for ( i=0 ; i < height ; i++ )
{
for ( j=0 ; j < width; j++ )
{
r = image[((height - i - 1) * width + j) * 3 + 2];
g = image[((height - i - 1) * width + j) * 3 + 1];
b = image[((height - i - 1) * width + j) * 3];
#if defined(BOARD_LCD_RGB565)
// Interlacing
r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5);
g = (g << 1) & 0xF8;
b = b & 0xF8;
buffer[(i * width + j) * 3] = b;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = r;
#else
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
#endif //#if defined(BOARD_LCD_RGB565)
}
}
}
else
{
if ( header->bits == 8 )
{
// Decoding is ok
if (!buffer) return 0;
// Retrieve palette
BMPPaletteEntry palette[256];
memcpy( palette, (uint8_t *) ((uint32_t) file + sizeof( BMPHeader )), header->offset - sizeof( BMPHeader ) ) ;
// Decode image (reversing row order)
for ( i=0 ; i < height ; i++ )
{
for (j=0; j < width; j++)
{
r = palette[image[(height - i - 1) * width + j]].r;
g = palette[image[(height - i - 1) * width + j]].g;
b = palette[image[(height - i - 1) * width + j]].b;
buffer[(i * width + j) * 3] = r;
buffer[(i * width + j) * 3 + 1] = g;
buffer[(i * width + j) * 3 + 2] = b;
}
}
}
else
{
TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r");
TRACE_INFO("header->bits 0x%X \n\r", header->bits);
return 4 ;
}
}
}
return 0 ;
}
/**
* \brief Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD)
*
* \param fileSource Buffer which holds the RGB file
* \param fileDestination Buffer in which to store the decoded image
* \param width Buffer width in pixels.
* \param height Buffer height in pixels.
* \param bpp Number of bits per pixels that the buffer stores.
*/
void RGB565toBGR555( uint8_t *fileSource, uint8_t *fileDestination, uint32_t width, uint32_t height, uint8_t bpp )
{
uint32_t i;
uint32_t j;
uint32_t row;
for (i=0; i < height*(bpp/8); i++)
{
row = (i*width*(bpp/8));
for (j=0; j <= width*(bpp/8); j+=2)
{
fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F)
| (fileSource[row+j]&0xE0);
fileDestination[row+j+1] = (fileSource[row+j+1]&0x03)
| ((fileSource[row+j]&0x1F)<<2);
}
}
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFFFFF000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define IRQ_STACK_SIZE 8*3*4
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define I_BIT 0x80
#define F_BIT 0x40
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
.align 4
.arm
/* Exception vectors
*******************/
.section .vectors, "a", %progbits
resetVector:
ldr pc, =resetHandler /* Reset */
undefVector:
b undefVector /* Undefined instruction */
swiVector:
b swiVector /* Software interrupt */
prefetchAbortVector:
b prefetchAbortVector /* Prefetch abort */
dataAbortVector:
b dataAbortVector /* Data abort */
reservedVector:
b reservedVector /* Reserved for future use */
irqVector:
b irqHandler /* Interrupt */
fiqVector:
/* Fast interrupt */
//------------------------------------------------------------------------------
/// Handles a fast interrupt request by branching to the address defined in the
/// AIC.
//------------------------------------------------------------------------------
fiqHandler:
b fiqHandler
//------------------------------------------------------------------------------
/// Handles incoming interrupt requests by branching to the corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//------------------------------------------------------------------------------
irqHandler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SVC
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
//------------------------------------------------------------------------------
/// Initializes the chip and branches to the main() function.
//------------------------------------------------------------------------------
.section .textEntry
.global entry
entry:
resetHandler:
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0xf00000
mcr p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
/* Useless instruction for referencing the .vectors section */
ldr r0, =resetVector
/* Set pc to actual code location (i.e. not in remap zone) */
ldr pc, =1f
/* Initialize the prerelocate segment */
1:
ldr r0, =_efixed
ldr r1, =_sprerelocate
ldr r2, =_eprerelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Perform low-level initialization of the chip using LowLevelInit() */
ldr sp, =_sstack
stmfd sp!, {r0}
ldr r0, =LowLevelInit
blx r0
/* Initialize the postrelocate segment */
ldmfd sp!, {r0}
ldr r1, =_spostrelocate
ldr r2, =_epostrelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Clear the zero segment */
ldr r0, =_szero
ldr r1, =_ezero
mov r2, #0
1:
cmp r0, r1
strcc r2, [r0], #4
bcc 1b
/* Setup stacks
**************/
/* IRQ mode */
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
ldr sp, =_sstack
sub r4, sp, #IRQ_STACK_SIZE
/* Supervisor mode (interrupts enabled) */
msr CPSR_c, #ARM_MODE_SVC | F_BIT
mov sp, r4
/*Initialize the C library */
ldr r3, =__libc_init_array
mov lr, pc
bx r3
/* Branch to main()
******************/
ldr r0, =main
blx r0
/* Loop indefinitely when program is finished */
1:
b 1b

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*
IAR startup file for AT91SAMA5D3X microcontrollers.
*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
//#define __ASSEMBLY__
//#include "board.h"
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
#define AIC 0xFFFFF000
#define AIC_IVR 0x10
#define AIC_EOICR 0x38
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F
#define I_BIT 0x80
#define F_BIT 0x40
//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------
/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)
PUBLIC resetVector
PUBLIC irqHandler
EXTERN Undefined_Handler
EXTERN SWI_Handler
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN FIQ_Handler
ARM
__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done
resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR pc, =irqHandler ; IRQ
LDR pc, FIQ_Addr ; FIQ
Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
FIQ_Addr: DCD FIQ_Handler
/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
irqHandler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
LDR lr, =AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SYS
STMFD sp!, {r1-r3, r4, r12, lr}
/* Check for 8-byte alignment and save lr plus a */
/* word to indicate the stack adjustment used (0 or 4) */
AND r1, sp, #4
SUB sp, sp, r1
STMFD sp!, {r1, lr}
BLX r0
LDMIA sp!, {r1, lr}
ADD sp, sp, r1
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
/* Acknowledge interrupt */
LDR lr, =AIC
STR lr, [r14, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^
/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)
PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
ARM
resetHandler:
CPSIE A
/* Enable VFP */
/* - Enable access to CP10 and CP11 in CP15.CACR */
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0xf00000
mcr p15, 0, r0, c1, c0, 2
/* - Enable access to CP10 and CP11 in CP15.NSACR */
/* - Set FPEXC.EN (B30) */
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
/* Set pc to actual code location (i.e. not in remap zone) */
LDR pc, =label
/* Perform low-level initialization of the chip using LowLevelInit() */
label:
LDR r0, =LowLevelInit
LDR r4, =SFE(CSTACK)
MOV sp, r4
BLX r0
/* Set up the interrupt stack pointer. */
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
LDR sp, =SFE(IRQ_STACK)
/* Set up the SYS stack pointer. */
MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
LDR sp, =SFE(CSTACK)
/* Branch to main() */
LDR r0, =?main
BLX r0
/* Loop indefinitely when program is finished */
loop4:
B loop4
END

143
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Provides the low-level initialization function that called on chip startup.
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Internal functions
*----------------------------------------------------------------------------*/
/**
* \brief Default spurious interrupt handler. Infinite loop.
*/
void defaultSpuriousHandler( void )
{
while (1);
}
/**
* \brief Default handler for fast interrupt requests. Infinite loop.
*/
void defaultFiqHandler( void )
{
while (1);
}
/**
* \brief Default handler for standard interrupt requests. Infinite loop.
*/
void defaultIrqHandler( void )
{
while (1);
}
/**
* \brief Performs the low-level initialization of the chip.
* This includes EFC and master clock configuration.
* It also enable a low level on the pin NRST triggers a user reset.
*/
extern WEAK void LowLevelInit( void )
{
uint32_t i;
if ((uint32_t)LowLevelInit < DDR_CS_ADDR) /* Code not in external mem */ {
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA( CKGR_PLLAR_STUCKTO1 |
CKGR_PLLAR_PLLACOUNT(0x3F) |
CKGR_PLLAR_OUTA(0x0) |
CKGR_PLLAR_MULA(65) |
CKGR_PLLAR_DIVA(1),
0x3u << 8);
PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2);
PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK);
PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3);
PMC_SwitchMck2Pll();
}
#if 0
uint32_t abcdsr;
/* Configure PCK1 to measure MCK */
PIOD->PIO_IDR = (1<<31);
abcdsr = PIOD->PIO_ABCDSR[0];
PIOD->PIO_ABCDSR[0] = ((1<<31) | abcdsr);
abcdsr = PIOD->PIO_ABCDSR[1];
PIOD->PIO_ABCDSR[1] &= (~(1<<31) & abcdsr);
PIOD->PIO_PDR = (1<<31);
/* Disable programmable clock 1 output */
REG_PMC_SCDR = PMC_SCER_PCK1;
/* Enable the DAC master clock */
PMC->PMC_PCK[1] = PMC_PCK_CSS_MCK_CLK | PMC_PCK_PRES_CLOCK;
/* Enable programmable clock 1 output */
REG_PMC_SCER = PMC_SCER_PCK1;
/* Wait for the PCKRDY1 bit to be set in the PMC_SR register*/
while ((REG_PMC_SR & PMC_SR_PCKRDY1) == 0);
#endif
/* select FIQ */
AIC->AIC_SSR = 0;
AIC->AIC_SVR = (unsigned int) defaultFiqHandler;
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_SVR = (unsigned int) defaultIrqHandler;
}
AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
/* Disable all interrupts */
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_IDCR = 1 ;
}
/* Clear All pending interrupts flags */
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_ICCR = 1 ;
}
/* Perform 8 IT acknoledge (write any value in EOICR) */
for (i = 0; i < 8 ; i++)
{
AIC->AIC_EOICR = 0;
}
/* Remap */
BOARD_RemapRam();
}

708
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2014, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup ddrd_module
*
* The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
* four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved
* to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.
*
* \section ddr2 Configures DDR2
*
* The DDR2-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1: Program the memory device type</li>
* <li> Step 2:
* -# Program the features of DDR2-SDRAM device into the Configuration Register.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR.
* -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR. </li>
* <li> Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock. </li>
* <li> Step 4: An NOP command is issued to the DDR2-SDRAM </li>
* <li> Step 5: An all banks precharge command is issued to the DDR2-SDRAM. </li>
* <li> Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.</li>
* <li> Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. </li>
* <li> Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.</li>
* <li> Step 9: Program DLL field into the Configuration Register.</li>
* <li> Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.</li>
* <li> Step 11: An all banks precharge command is issued to the DDR2-SDRAM.</li>
* <li> Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.</li>
* <li> Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).</li>
* <li> Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.</li>
* <li> Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). </li>
* <li> Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.</li>
* <li> Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).</li>
* <li> Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.</li>
* <li> Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.</li>
* <li> Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 or 7.81. </li>
* </ul>
*/
/*@{*/
/*@}*/
/** \addtogroup sdram_module
*
* \section sdram Configures SDRAM
*
* The SDR-SDRAM devices are initialized by the following sequence:
* <ul>
* <li> EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.</li>
* <li> Step 1. Program the memory device type into the Memory Device Register</li>
* <li> Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.</li>
* <li> Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.</li>
* <li> Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
* set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command.
* Now the clock which drives SDR-SDRAM device is enabled.</li>
* <li> Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the
* Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.</li>
* <li> Step 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register.
* Once in the idle state, two AUTO REFRESH cycles must be performed.</li>
* <li> Step 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM
* devices, in particular CAS latency and burst length. </li>
* <li> Step 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The write
* address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0 </li>
* <li> Step 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and perform a write access at any location in the SDRAM to acknowledge this command.</li>
* <li> Step 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register </li>
* </ul>
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of memories configuration on board.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Definiation
*----------------------------------------------------------------------------*/
#define DDRC2_MODE_NORMAL_CMD (0x0) // (HDDRSDRC2) Normal Mode
#define DDRC2_MODE_NOP_CMD (0x1) // (HDDRSDRC2) Issue a NOP Command at every access
#define DDRC2_MODE_PRCGALL_CMD (0x2) // (HDDRSDRC2) Issue a All Banks Precharge Command at every access
#define DDRC2_MODE_LMR_CMD (0x3) // (HDDRSDRC2) Issue a Load Mode Register at every access
#define DDRC2_MODE_RFSH_CMD (0x4) // (HDDRSDRC2) Issue a Refresh
#define DDRC2_MODE_EXT_LMR_CMD (0x5) // (HDDRSDRC2) Issue an Extended Load Mode Register
#define DDRC2_MODE_DEEP_CMD (0x6) // (HDDRSDRC2) Enter Deep Power Mode
#define DDRC2_MODE_Reserved (0x7) // (HDDRSDRC2) Reserved value
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal ROM or the EBI CS0.
*/
void BOARD_RemapRom( void )
{
MATRIX->MATRIX_MRCR = MATRIX_MRCR_RCB0;
AXIMX->AXIMX_REMAP = 0;
}
/**
* \brief Changes the mapping of the chip so that the remap area mirrors the
* internal RAM.
*/
void BOARD_RemapRam( void )
{
MATRIX->MATRIX_MRCR = MATRIX_MRCR_RCB0;
AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0;
}
/**
* \brief Initialize Vdd EBI drive
* \param 0: 1.8V 1: 3.3V
*/
void BOARD_ConfigureVddMemSel( uint8_t VddMemSel )
{
( void ) VddMemSel;
}
#define DDR2_BA0(r) (1 << (25 + r))
#define DDR2_BA1(r) (1 << (26 + r))
/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x74) MPDDRC DLL Slave Offset Register -------- */
// SxOFF: DLL Slave x Delay Line Offset ([x=0..1][x=0..3])
#define MPDDRC_DLL_SOR_S0_OFF_Pos 0
#define MPDDRC_DLL_SOR_S0_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S0_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 0 Delay Line Offset */
#define MPDDRC_DLL_SOR_S0_OFF(value) ((MPDDRC_DLL_SOR_S0_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S0_OFF_Pos)))
#define MPDDRC_DLL_SOR_S1_OFF_Pos 8
#define MPDDRC_DLL_SOR_S1_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S1_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 1 Delay Line Offset */
#define MPDDRC_DLL_SOR_S1_OFF(value) ((MPDDRC_DLL_SOR_S1_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S1_OFF_Pos)))
#define MPDDRC_DLL_SOR_S2_OFF_Pos 16
#define MPDDRC_DLL_SOR_S2_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S2_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 2 Delay Line Offset */
#define MPDDRC_DLL_SOR_S2_OFF(value) ((MPDDRC_DLL_SOR_S2_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S2_OFF_Pos)))
#define MPDDRC_DLL_SOR_S3_OFF_Pos 24
#define MPDDRC_DLL_SOR_S3_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S3_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 3 Delay Line Offset */
#define MPDDRC_DLL_SOR_S3_OFF(value) ((MPDDRC_DLL_SOR_S3_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S3_OFF_Pos)))
/**
* \brief Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
MT47H64M16HR : 8 Meg x 16 x 8 banks
Refresh count: 8K
Row address: A[12:0] (8K)
Column address A[9:0] (1K)
Bank address BA[2:0] a(24,25) (8)
*/
void BOARD_ConfigureDdram( uint8_t device )
{
volatile uint8_t *pDdr = (uint8_t *) DDR_CS_ADDR;
volatile uint32_t i;
volatile uint32_t cr = 0;
volatile uint32_t dummy_value;
dummy_value = 0x00000000;
/* Enable DDR2 clock x2 in PMC */
PMC->PMC_PCER1 = (1 << (ID_MPDDRC-32));
PMC->PMC_SCER |= PMC_SCER_DDRCK;
MPDDRC->MPDDRC_LPR = 0;
MPDDRC->MPDDRC_DLL_SOR = 0x101 | MPDDRC_DLL_SOR_S1_OFF(0x0) | MPDDRC_DLL_SOR_S2_OFF(0x1) | MPDDRC_DLL_SOR_S3_OFF(0x1);
MPDDRC->MPDDRC_DLL_MOR = (0xC5000000) | MPDDRC_DLL_MOR_MOFF(7) | MPDDRC_DLL_MOR_CLK90OFF(0x1F) | MPDDRC_DLL_MOR_SELOFF; // Key = 0xc5000000
dummy_value = MPDDRC->MPDDRC_IO_CALIBR;
dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;
dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;
dummy_value |= MPDDRC_IO_CALIBR_RDIV_RZQ_48;
dummy_value |= MPDDRC_IO_CALIBR_TZQIO(3);
MPDDRC->MPDDRC_IO_CALIBR = dummy_value;
*(uint32_t *)0xFFFFEA80 = 0x1100;
*(uint32_t *)0xFFFFEA84 = 0x1100;
*(uint32_t *)0xFFFFEA88 = 0x1100;
*(uint32_t *)0xFFFFEA8C = 0x1100;
/* Step 1: Program the memory device type */
/* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM;
/* Step 2: Program the features of DDR2-SDRAM device into the Timing Register.*/
if (device == DDRAM_MT47H128M16RT)
{
MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_14 |
MPDDRC_CR_NC_10 |
MPDDRC_CR_CAS_4_DDR2 |
MPDDRC_CR_NB_8 |
MPDDRC_CR_DLL_RESET_DISABLED |
MPDDRC_CR_DQMS_NOT_SHARED |
MPDDRC_CR_ENRDM_OFF |
MPDDRC_CR_UNAL_SUPPORTED |
MPDDRC_CR_NDQS_DISABLED |
MPDDRC_CR_OCD(0x0);
}
if (device == DDRAM_MT47H64M16HR)
{
MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_13 |
MPDDRC_CR_NC_10 |
MPDDRC_CR_CAS_3_DDR2|
MPDDRC_CR_NB_8 |
MPDDRC_CR_DLL_RESET_DISABLED |
MPDDRC_CR_DQMS_NOT_SHARED |
MPDDRC_CR_ENRDM_OFF |
MPDDRC_CR_UNAL_SUPPORTED |
MPDDRC_CR_NDQS_DISABLED |
MPDDRC_CR_OCD(0x0);
}
MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(6) // 6 * 7.5 = 45 ns
| MPDDRC_TPR0_TRCD(2) // 2 * 7.5 = 15 ns
| MPDDRC_TPR0_TWR(3) // 3 * 7.5 = 22.5 ns
| MPDDRC_TPR0_TRC(8) // 8 * 7.5 = 60 ns
| MPDDRC_TPR0_TRP(2) // 2 * 7.5 = 15 ns
| MPDDRC_TPR0_TRRD(2) // 2 * 7.5 = 15 ns
| MPDDRC_TPR0_TWTR(2) // 2 clock cycle
| MPDDRC_TPR0_TMRD(2); // 2 clock cycles
MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(0x1A) // 18 * 7.5 = 135 ns (min 127.5 ns for 1Gb DDR)
| MPDDRC_TPR1_TXSNR(0x1C) // 20 * 7.5 > 142.5ns TXSNR: Exit self refresh delay to non read command
| MPDDRC_TPR1_TXSRD(0xC8) // min 200 clock cycles, TXSRD: Exit self refresh delay to Read command
| MPDDRC_TPR1_TXP(0x2); // 2 * 7.5 = 15 ns
MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8) // min 2 clock cycles
| MPDDRC_TPR2_TXARDS(7)// min 7 clock cycles
| MPDDRC_TPR2_TRPA(2) // min 18ns
| MPDDRC_TPR2_TRTP(2) // 2 * 7.5 = 15 ns (min 7.5ns)
| MPDDRC_TPR2_TFAW(7) ;
/* DDRSDRC Low-power Register */
for (i = 0; i < 13300; i++) {
asm("nop");
}
MPDDRC->MPDDRC_LPR = MPDDRC_LPR_LPCB_DISABLED |
MPDDRC_LPR_CLK_FR_DISABLED |
MPDDRC_LPR_TIMEOUT_0 |
MPDDRC_LPR_APDE_SLOW ;
/* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register, the application must set MODE to 1 in the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
*pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/
/* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */
for (i = 0; i < 13300; i++) {
asm("nop");
}
/* Step 4: An NOP command is issued to the DDR2-SDRAM */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0; /* Now CKE is driven high.*/
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
/* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
*pDdr = 0;
/* wait 400 ns min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(device))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA1(device) + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. */
/* An additional 200 cycles of clock are required for locking DLL */
for (i = 0; i < 10000; i++) {
asm("nop");
}
/* Step 9: Program DLL field into the Configuration Register.*/
cr = MPDDRC->MPDDRC_CR;
MPDDRC->MPDDRC_CR = cr | MPDDRC_CR_DLL_RESET_ENABLED;
/* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] bits are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Configure 2nd CBR. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;
*(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */
cr = MPDDRC->MPDDRC_CR;
MPDDRC->MPDDRC_CR = cr & (~MPDDRC_CR_DLL_RESET_ENABLED);
/* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;
*(pDdr) = 0; /* The write address must be chosen so that BA[1:0] are set to 0. */
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). */
cr = MPDDRC->MPDDRC_CR;
MPDDRC->MPDDRC_CR = cr | MPDDRC_CR_OCD(0x07);
/* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit). */
// cr = MPDDRC->MPDDRC_CR;
// MPDDRC->MPDDRC_CR = cr & (~ MPDDRC_CR_OCD(0x07));
/* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.*/
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;
*((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/
/* wait 2 cycles min */
for (i = 0; i < 100; i++) {
asm("nop");
}
/* Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;
*(pDdr) = 0;
/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs.
With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */
/* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average
refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */
/* ((64 x 10(^-3))/8192) x133 x (10^6) */
//MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(300); /* Set Refresh timer 7.8125 us*/
MPDDRC->MPDDRC_RTR = 0x00300408;
/* OK now we are ready to work on the DDRSDR */
/* wait for end of calibration */
for (i = 0; i < 500; i++) {
asm(" nop");
}
}
/**
* \brief Configures the EBI for Sdram (LPSDR Micron MT48H8M16) access.
*/
void BOARD_ConfigureSdram( void )
{
}
/** \brief Configures the EBI for NandFlash access at 133Mhz.
*/
void BOARD_ConfigureNandFlash( uint8_t busWidth )
{
PMC_EnablePeripheral(ID_SMC);
SMC->SMC_CS_NUMBER[3].SMC_SETUP = 0
| SMC_SETUP_NWE_SETUP(1)
| SMC_SETUP_NCS_WR_SETUP(1)
| SMC_SETUP_NRD_SETUP(2)
| SMC_SETUP_NCS_RD_SETUP(1);
SMC->SMC_CS_NUMBER[3].SMC_PULSE = 0
| SMC_PULSE_NWE_PULSE(5)
| SMC_PULSE_NCS_WR_PULSE(7)
| SMC_PULSE_NRD_PULSE(5)
| SMC_PULSE_NCS_RD_PULSE(7);
SMC->SMC_CS_NUMBER[3].SMC_CYCLE = 0
| SMC_CYCLE_NWE_CYCLE(8)
| SMC_CYCLE_NRD_CYCLE(9);
SMC->SMC_CS_NUMBER[3].SMC_TIMINGS = SMC_TIMINGS_TCLR(3)
| SMC_TIMINGS_TADL(10)
| SMC_TIMINGS_TAR(3)
| SMC_TIMINGS_TRR(4)
| SMC_TIMINGS_TWB(5)
| SMC_TIMINGS_RBNSEL(3)
|(SMC_TIMINGS_NFSEL);
SMC->SMC_CS_NUMBER[3].SMC_MODE = SMC_MODE_READ_MODE |
SMC_MODE_WRITE_MODE |
((busWidth == 8 )? SMC_MODE_DBW_BIT_8 :SMC_MODE_DBW_BIT_16) |
SMC_MODE_TDF_CYCLES(1);
}
void BOARD_ConfigureNorFlash( uint8_t busWidth )
{
uint32_t dbw;
PMC_EnablePeripheral(ID_SMC);
if (busWidth == 8)
{
dbw = SMC_MODE_DBW_BIT_8;
}
else {
dbw = SMC_MODE_DBW_BIT_16;
}
/* Configure SMC, NCS0 is assigned to a norflash */
SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0x00020001;
SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0x0B0B0A0A;
SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0x000E000B;
SMC->SMC_CS_NUMBER[0].SMC_TIMINGS = 0x00000000;
SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE_WRITE_MODE
| SMC_MODE_READ_MODE
| dbw
| SMC_MODE_EXNW_MODE_DISABLED
| SMC_MODE_TDF_CYCLES(1);
}
// -----------------------------------------------------------------------------
// Function Name : LPDDR2_Initialize
// Object :
// -----------------------------------------------------------------------------
void BOARD_ConfigureLpDdram( void)
{
volatile uint32_t i;
volatile uint32_t dummy_value;
PMC->PMC_PCER1 = (1 << (ID_MPDDRC-32));
PMC->PMC_SCER |= PMC_SCER_DDRCK;
/* -------------------- Additional DDR2 setting ------------------------ */
MPDDRC->MPDDRC_DLL_SOR = MPDDRC_DLL_SOR_S0_OFF(0x4) | MPDDRC_DLL_SOR_S1_OFF(0x3) | MPDDRC_DLL_SOR_S2_OFF(0x4) | MPDDRC_DLL_SOR_S3_OFF(0x4); // design recommendation
MPDDRC->MPDDRC_DLL_MOR = (0xC5000000) | MPDDRC_DLL_MOR_MOFF(7) | MPDDRC_DLL_MOR_CLK90OFF(0x1F) | MPDDRC_DLL_MOR_SELOFF; // Key = 0xc5000000
dummy_value = MPDDRC->MPDDRC_IO_CALIBR;
dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;
dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;
dummy_value |= (0x4 << 0);
dummy_value |= MPDDRC_IO_CALIBR_TZQIO(3);
MPDDRC->MPDDRC_IO_CALIBR = dummy_value;
/* DDRSDRC High Speed Register (MPDDRC_HS) : hidden option -> calibration during autorefresh */
*(uint32_t *)0xFFFFEA24 |= (1 << 5);
/* SFR_DDRCFG DDR Configuration Force DDR_DQ and DDR_DQS input buffer always on */
*(uint32_t *)0xF0038004 |= (0x3 << 16);
/* Initialization sequence STEP 1
Program the memory device type into the Memory Device Register */
/* Memory device = LPDDR2 => MPDDRC_MD_MD_LPDDR2_SDRAM
Data bus width = 32 bits => 0x0 (The system is in 64 bits, thus memory data bus width should be 32 bits) */
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_LPDDR2_SDRAM;
/* Initialization sequence STEP 2
Program the features of Low-power DDR2-SDRAM device into the Timing Register
(asynchronous timing, trc, tras, etc.) and into the Configuration Register (number of
columns, rows, banks, CAS latency and output drive strength) (see Section 8.3 on
page 35, Section 8.4 on page 39 and Section 80.5 on page 41). */
MPDDRC->MPDDRC_CR = MPDDRC_CR_NC_10 |
MPDDRC_CR_NR_14 |
MPDDRC_CR_CAS_5_LPDDR2 |
MPDDRC_CR_NB_8 |
MPDDRC_CR_UNAL_SUPPORTED |
MPDDRC_CR_ENRDM_ON;
MPDDRC->MPDDRC_LPDDR2_LPR |= MPDDRC_LPDDR2_LPR_DS(0x3);
MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS (6) | // 03 - TRAS tRAS Row active time
MPDDRC_TPR0_TRCD (2) | // 04 - TRC tRCD RAS-to-CAS delay
MPDDRC_TPR0_TWR (3) | // 05 - TWR tWR WRITE recovery time
MPDDRC_TPR0_TRC (8) | // 06 - TRC tRC ACTI-to-ACTIVT command period
MPDDRC_TPR0_TRP (3) | // 07 - TRP tRPpb Row precharge time
MPDDRC_TPR0_TRRD (2) | // 08 - TRRD tRRD Active bank a to active bank b
MPDDRC_TPR0_TWTR (2) | // 09 - TWTR-tWTR Internal WRITE-to-READcommand delay
MPDDRC_TPR0_TMRD (3); // 10 - TMRD-tMRD
MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC (17) | // 11 - TRFC tRFCab Refresh cycle time
MPDDRC_TPR1_TXSNR (18) | // 12 - TXSNR SELF REFRESH exit to next valid delay
MPDDRC_TPR1_TXSRD (14) | // 13 - TXSRD Exit Self Refresh
MPDDRC_TPR1_TXP (2); // 14 - TXP-tXP Exit power-down
MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD (1) | // 15 - TXARD-txARD
MPDDRC_TPR2_TXARDS (1) | // 16 - TXARDS-txARDs
MPDDRC_TPR2_TRPA (3) | // 17 - TRPA-tRPpab Row precharge time (all banks)
MPDDRC_TPR2_TRTP (2) | // 18 - TRTP-tRTP
MPDDRC_TPR2_TFAW (8); // 19 - TFAW-tFAW
/* Initialization sequence STEP 3
An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
command into the Mode Register, the application must set the MODE (MDDRC Command
Mode) field to 1 in the Mode Register (see Section 8.1 on page 32). Perform a
write access to any Low-power DDR2-SDRAM address to acknowledge this command.
Now, clocks which drive Low-power DDR2-SDRAM devices are enabled.
A minimum pause of 100 ns must be observed to precede any signal toggle. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; // NOP to ENABLE CLOCK output
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 100; i++) {
asm(" nop");
} // Delay loop (at least 100 ns)
/* Initialization sequence STEP 4
An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
command into the Mode Register, the application must set MODE to 1 in the Mode
Register (see Section 8.1 on page 32). Perform a write access to any Low-power
DDR2-SDRAM address to acknowledge this command. Now, CKE is driven high.
A minimum pause of 200 us must be satisfied before Reset Command.
*/
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; // NOP to drive CKE high
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 10000; i++) {
asm(" nop");
} // Delay loop (at least 200 us)
/* Initialization sequence STEP 5
A reset command is issued to the Low-power DDR2-SDRAM. Program
LPDDR2_CMD in the MODE (MDDRC Command Mode) and MRS (Mode Register
Select LPDDR2) field of the Mode Register, the application must set MODE to 7 and
MRS to 63. (see Section 8.1 on page 32). Perform a write access to any Low-power
DDR2-SDRAM address to acknowledge this command. Now, the reset command is issued.
A minimum pause of 1us must be satisfied before any commands. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MRS(0x3F) | MPDDRC_MR_MODE_LPDDR2_CMD;
*(unsigned int *)DDR_CS_ADDR = 0x00000000;
for (i = 0; i < 500; i++) { asm(" nop"); }
/* Initialization sequence STEP 6
A Mode Register Read command is issued to the Low-power DDR2-SDRAM. Program
LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
application must set MODE to 7 and must set MRS field to 0. (see Section 8.1 on
page 32). Perform a write access to any Low-power DDR2-SDRAM address to
acknowledge this command. Now, the Mode Register Read command is issued.
A minimum pause of 10 us must be satisfied before any commands. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x00);
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 5000; i++) {asm(" nop"); }
/* Initialization sequence STEP 7
A calibration command is issued to the Low-power DDR2-SDRAM. Program the type
of calibration into the Configuration Register, ZQ field, RESET value (see Section 8.3
”MPDDRC Configuration Register?on page 37). In the Mode Register, program the
MODE field to LPDDR2_CMD value, and the MRS field; the application must set
MODE to 7 and MRS to 10 (see Section 8.1 LPDDRC Mode Register?on page 34).
Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
this command. Now, the ZQ Calibration command is issued. Program the type of calibration
into the Configuration Register, ZQ field */
MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_RESET;
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x0A);
// Mode Register Read command. MODE = 0x7 and MRS = 0x0A
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 500; i++) {asm(" nop"); }
MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_SHORT;
/* Initialization sequence STEP 8
A Mode Register Write command is issued to the Low-power DDR2-SDRAM. Program
LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
application must set MODE to 7 and must set MRS field to 0.5 (see Section 8.1 on
page 32). The Mode Register Write command cycle is issued to program the parameters
of the Low-power DDR2-SDRAM devices, in particular burst length. Perform a
write access to any Low-power DDR2-SDRAM address to acknowledge this command.
Now, the Mode Register Write command is issued. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x01);
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 500; i++) {
asm(" nop");
}
/* Initialization sequence STEP 9
Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
application must set MODE to 7 and must set MRS field to 2. (see Section 8.1 on
page 32). The Mode Register Write command cycle is issued to program the parameters
of the Low-power DDR2-SDRAM devices, in particular CAS latency. Perform a
write access to any Low-power DDR2-SDRAM address to acknowledge this command.
Now, the Mode Register Write command is issued. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x02);
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 500; i++) {
asm(" nop");
}
/* Initialization sequence STEP 10
A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
application must set MODE to 7 and must set MRS field to 3. (see Section 8.1 on
page 32). The Mode Register Write command cycle is issued to program the parameters
of the Low-power DDR2-SDRAM devices, in particular Drive Strength and Slew
Rate. Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
this command. Now, the Mode Register Write command is issued. */
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x03); //0x00000307;
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 500; i++) {
asm(" nop");
}
/* Initialization sequence STEP 11
A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
application must set MODE to 7 and must set MRS field to 16. (see Section 8.1 on
page 32). Mode Register Write command cycle is issued to program the parameters
of the Low-power DDR2-SDRAM devices, in particular Partial Array Self Refresh
(PASR). Perform a write access to any Low-power DDR2-SDRAM address to
acknowledge this command. Now, the Mode Register Write command is issued.*/
MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x10);// 0x00001007;
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory
for (i = 0; i < 500; i++) {
asm(" nop");
}
/* Initialization sequence STEP 12
Write the refresh rate into the COUNT field in the Refresh Timer register (see page
33). (Refresh rate = delay between refresh cycles). The Low-power DDR2-SDRAM
device requires a refresh every 7.81 ìs. With a 100 MHz frequency, the refresh timer
count register must to be set with (7.81/100 MHz) = 781 i.e. 0x030d. */
MPDDRC->MPDDRC_RTR &= ~MPDDRC_RTR_COUNT_Msk;
MPDDRC->MPDDRC_RTR |= MPDDRC_RTR_COUNT(1030);
MPDDRC->MPDDRC_MR = 0x00000000; // Set Normal mode
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Perform
for (i = 0; i < 500; i++) {
asm(" nop");
}
/* Launch short ZQ calibration */
MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk; // Enable short calibration in the CR
MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_SHORT;
MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
*(unsigned int *)DDR_CS_ADDR = 0x00000000; // Perform
/* Calculate ZQS: search for tZQCS in the memory datasheet => tZQCS = 180 ns*/
MPDDRC->MPDDRC_LPDDR2_TIM_CAL = MPDDRC_LPDDR2_TIM_CAL_ZQCS(12);
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \addtogroup cand_module
*@{*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
#if defined(REG_CAN0_MR) || defined(REG_CAN_MR)
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/** \addtogroup cand_states CAN Driver states
* @{*/
#define CAND_STATE_DISABLED 0 /**< Power-up reset, controller is disabled */
#define CAND_STATE_INIT 1 /**< Initializing */
#define CAND_STATE_SLEEP 2 /**< Low-power mode */
#define CAND_STATE_SYNC 3 /**< Synchronizating */
#define CAND_STATE_ERROR 4 /**< Error halt */
#define CAND_STATE_ACTIVATED 5 /**< Bus synchronization is done */
#define CAND_STATE_XFR 6 /**< Transfer in progress */
/** @}*/
/** \addtogroup cand_xfr_states CAN Transfer states
* @{*/
#define CAND_XFR_DISABLED 0 /**< Transfer not used */
#define CAND_XFR_HALTED 1 /**< Error halt */
#define CAND_XFR_IDLE 2 /**< No transfer */
#define CAND_XFR_TX 3 /**< Transferring data */
/** @}*/
/** \addtogroup cand_reg_bits CAN Register Bitfields
* @{*/
/** CAN mailbox event statuses bits */
#define CAN_MB_EVENTS 0xFF
/** CAN errors statuses bits */
#define CAN_ERRS (0 \
/*|CAN_SR_ERRA*/ \
/*|CAN_SR_WARN*/ \
/*|CAN_SR_ERRP*/ \
/*|CAN_SR_BOFF*/ \
/*|CAN_SR_SLEEP*/ \
/*|CAN_SR_WAKEUP*/ \
/*|CAN_SR_TOVF*/ \
/*|CAN_SR_TSTP*/ \
|CAN_SR_CERR \
|CAN_SR_SERR \
|CAN_SR_AERR \
|CAN_SR_FERR \
|CAN_SR_BERR \
/*|CAN_SR_RBSY*/ \
/*|CAN_SR_TBSY*/ \
/*|CAN_SR_OVLSY*/ \
)
/** CAN mailbox ID mask */
#define CAN_ID_MASK (CAN_MID_MIDE | CAN_MID_MIDvA_Msk | CAN_MID_MIDvB_Msk)
#define CAN_MMR_MOT(x) (((x)<<CAN_MMR_MOT_Pos)&CAN_MMR_MOT_Msk)
/** @}*/
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
/**
* Check if the mailbox is ready to transfer
* \param pMb The current mailbox transfer parameters.
*/
static uint8_t CAND_IsMbReady(sCandTransfer *pMb)
{
/* MB has no transfer, OK */
if (pMb == NULL) return 1;
/* MB has transfer, NOK */
if (pMb->bState == CAND_XFR_TX) return 0;
/* MB in a state that acceps modification */
return 1;
}
/**
* Reset mailbox with specified configuration value.
* \param pCand Pointer to CAN Driver instance.
* \param pCfg Pointer to list of configurations.
*/
static void CAND_ResetMb(sCand *pCand, uint8_t bMb, sCandMbCfg *pCfg)
{
Can *pCan = pCand->pHw;
CAN_DisableIt(pCan, (1 << bMb) & CAN_MB_EVENTS);
CAN_MessageControl(pCan, bMb, 0);
CAN_ConfigureMessageMode(pCan, bMb, 0);
if (pCand->pMbs[bMb])
{
pCand->pMbs[bMb] = CAND_XFR_DISABLED;
pCand->pMbs[bMb] = NULL;
}
if (pCfg)
{
CAN_ConfigureMessageAcceptanceMask(pCan, bMb, pCfg->dwMsgMask);
CAN_ConfigureMessageMode(pCan, bMb, CAN_MMR_MOT(pCfg->bMsgType)
| CAN_MMR_PRIOR(pCfg->bTxPriority));
}
}
/**
* Initialize transfer on specific Mailbox.
* \param pCand Pointer to CAN Driver instance.
* \param pXfr Pointer to CAN Transfer instance.
* \param bStart Start transfer immediately.
*/
static void CAND_InitXfr(sCand *pCand, sCandTransfer *pXfr, uint8_t bStart)
{
Can *pCan = pCand->pHw;
uint8_t bMb = pXfr->bMailbox;
uint32_t dwMmr = CAN_GetMessageMode(pCan, bMb);
if (pXfr == NULL)
return;
/* Log tranfser */
pCand->pMbs[bMb] = pXfr;
/* Set transfer state */
if (bStart)
{
pXfr->bState = CAND_XFR_TX;
pCand->bState = CAND_STATE_XFR;
}
/* Reset transfer state */
else
pXfr->bState = CAND_XFR_IDLE;
/* Fill ID */
CAN_ConfigureMessageID(pCan, bMb, pXfr->dwMsgID);
/* Fill data registers */
CAN_SetMessage(pCan, bMb, pXfr->msgData);
/* Start TX if not RX */
if ((dwMmr & CAN_MMR_MOT_Msk) > CAN_MMR_MOT_MB_RX_OVERWRITE)
{
CAN_MessageControl(pCan, bMb,
CAN_MCR_MDLC(pXfr->bMsgLen)
| (bStart ? CAN_MCR_MTCR : 0) );
}
}
/**
* Finish transfer on specific Mailbox.
* \param pCand Pointer to CAN Driver instance.
* \param pXfr Pointer to CAN Transfer instance.
* \param bSC Status code.
*/
static void CAND_EndXfr(sCand *pCand, sCandTransfer *pXfr, uint8_t bSC)
{
if (!pCand) return;
/* Return status */
pXfr->bRC = bSC;
if (bSC >= CAND_ERROR)
pXfr->bState = CAND_XFR_HALTED;
else if(pXfr->bState == CAND_XFR_TX)
pXfr->bState = CAND_XFR_IDLE;
/* Invoke callbacks */
}
/**
* Disable all mailboxes
*/
static void CAND_ResetMailboxes(sCand *pCand)
{
uint32_t i;
/* Reset all mailboxes */
for (i = 0; i < CAN_NUM_MAILBOX; i ++)
{
CAND_ResetMb(pCand, i, NULL);
}
pCand->bState = CAND_STATE_INIT;
}
/**
* Handler for CAN errors
*/
static void CAND_ErrorHandler(sCand *pCand, uint32_t dwErrS)
{
pCand = pCand;
uint32_t ecr;
TRACE_INFO("CAN[%x]: 0x%08x\n\r", pCand->pHw, dwErrS);
#if 1
ecr = (pCand->pHw)->CAN_ECR;
ecr = ecr; /*Dummy */
if (dwErrS & CAN_SR_ERRA)
{
TRACE_ERROR_WP("-E- Active Mode: TEC %u, REC %u\n\r",
(unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos),
(unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos));
}
if (dwErrS & CAN_SR_WARN)
{
TRACE_ERROR_WP("Warning Limit: TEC %u, REC %u\n\r",
(unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos),
(unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos));
}
if (dwErrS & CAN_SR_ERRP)
{
TRACE_ERROR_WP("-E- Passive Mode: TEC %u, REC %u\n\r",
(unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos),
(unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos));
}
if (dwErrS & CAN_SR_BOFF)
{
TRACE_ERROR_WP("Bus Off Mode, TEC %u\n\r", (unsigned int)((((pCand->pHw)->CAN_ECR) & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos));
}
#endif
if (dwErrS & CAN_SR_CERR)
{
TRACE_ERROR_WP("-E- MB CRC\n\r");
}
if (dwErrS & CAN_SR_SERR)
{
TRACE_ERROR_WP("-E- MB Stuffing\n\r");
}
if (dwErrS & CAN_SR_AERR)
{
TRACE_ERROR_WP("-E- Ack\n\r");
}
if (dwErrS & CAN_SR_FERR)
{
TRACE_ERROR_WP("-E- Form\n\r");
}
if (dwErrS & CAN_SR_BERR)
{
TRACE_ERROR_WP("-E- Bit\n\r");
}
}
/**
* Handler for messages
* \param pCand Pointer to CAN Driver instance.
*/
static void CAND_MessageHandler(sCand *pCand)
{
Can *pCan = pCand->pHw;
sCandTransfer *pXfr;
uint8_t bMb;
uint32_t dwMsr;
for (bMb = 0; bMb < CAN_NUM_MAILBOX; bMb ++)
{
/* Mailbox used ? */
pXfr = pCand->pMbs[bMb];
if (pXfr == NULL)
continue;
/* Mailbox ready ? */
dwMsr = CAN_GetMessageStatus(pCan, bMb);
if ((dwMsr & CAN_MSR_MRDY) != CAN_MSR_MRDY)
continue;
/* Handle data */
switch (CAN_GetMessageMode(pCan, bMb) & CAN_MMR_MOT_Msk)
{
case CAN_MMR_MOT_MB_RX_OVERWRITE: /** Next data overwrite current */
/*pXfr->bState = CAND_XFR_RX_ONE;*/
case CAN_MMR_MOT_MB_RX:
case CAN_MMR_MOT_MB_CONSUMER: /** TX then RX message */
pXfr->bMsgLen = (dwMsr & CAN_MSR_MDLC_Msk) >> CAN_MSR_MDLC_Pos;
CAN_GetMessage(pCan, bMb, pXfr->msgData);
CAND_EndXfr(pCand, pXfr, CAND_OK);
break;
case CAN_MMR_MOT_MB_TX:
case CAN_MMR_MOT_MB_PRODUCER: /** RX then TX message */
CAND_EndXfr(pCand, pXfr, CAND_OK);
break;
default:
TRACE_ERROR("MB[%d] disabled\n\r", bMb);
CAND_EndXfr(pCand, pXfr, CAND_ERROR);
break;
}
/*if (pXfr->bState != CAND_XFR_RX_ONE)*/
{
/* Disable mailbox interrupt */
CAN_DisableIt(pCan, 1 << bMb);
/* Unlink transfer */
pCand->pMbs[bMb] = NULL;
}
}
/* All transfer finished ? */
if ((CAN_GetItMask(pCan)&CAN_MB_EVENTS) == 0)
pCand->bState = CAND_STATE_ACTIVATED;
}
/*----------------------------------------------------------------------------
* Exported Functions
*----------------------------------------------------------------------------*/
/**
* Initialize CAN Driver with specific baudrate.
* \param pCand Pointer to CAN Driver instance.
* \param pHw Pointer to CAN controller HW base address.
* \param bID ID for CAN controller.
* \param wBaudrate Expected baudrate.
* \param dwMck Current MCK used.
*/
uint8_t CAND_Init(sCand* pCand,
Can *pHw, uint8_t bID,
uint16_t wBaudrate, uint32_t dwMck)
{
pCand->pHw = pHw;
pCand->bID = bID;
PMC_EnablePeripheral(pCand->bID);
/* Reserved */
//pCand->fCallback = NULL;
//pCand->pArg = NULL;
/* Disable all interrupts */
CAN_DisableIt(pHw, 0xFFFFFFFF);
/* (Re)initialize baudrate */
if (wBaudrate)
{
pCand->dwMck = dwMck;
pCand->wBaudrate = wBaudrate;
if (!CAN_CalcBaudrate(pHw, wBaudrate, dwMck))
return CAND_ERROR;
}
/* Reset CAN mode */
CAN_ConfigureMode(pHw, 0);
/* Reset all mailboxes */
CAND_ResetMailboxes(pCand);
/* Enable the interrupts for error cases */
CAN_EnableIt(pHw, CAN_ERRS);
return CAND_OK;
}
/**
* Activate CAN.
* \param pCand Pointer to CAN Driver instance.
*/
void CAND_Activate(sCand *pCand)
{
Can *pCan = pCand->pHw;
if (pCand->bState > CAND_STATE_SYNC)
return;
/* Disable low-power mode */
CAN_EnableLowPower(pCan, 0);
/* Start sync state */
pCand->bState = CAND_STATE_SYNC;
/* Enable CAN and wait interrupt */
CAN_EnableIt(pCan, CAN_IER_WAKEUP);
CAN_Enable(pCan, 1);
}
#if 0
/**
* Find good baudrate (activated).
*/
void CAND_AutoBaudrate(sCand *pCand, uint16_t *pBuadList, uint16_t wListSize)
{
}
#endif
/**
* Put into sleep mode
* \param pCand Pointer to CAN Driver instance.
*/
void CAND_Sleep(sCand *pCand)
{
Can *pCan = pCand->pHw;
CAN_EnableIt(pCan, CAN_IER_SLEEP);
CAN_EnableLowPower(pCan, 1);
}
/**
* Check if CAN is ready to transfer messages.
* \param pCand Pointer to CAN Driver instance.
*/
uint8_t CAND_IsReady(sCand *pCand)
{
return (pCand->bState >= CAND_STATE_ACTIVATED);
}
/**
* Interrupt handler for CAN Driver.
* \param pCand Pointer to CAN Driver instance.
*/
void CAND_Handler(sCand *pCand)
{
Can *pHw = pCand->pHw;
uint32_t dwSr = CAN_GetStatus(pHw);
//uint32_t dwSm = CAN_GetItMask(pHw);
TRACE_INFO("%d:%8x\n\r", (pHw==CAN0)?0:1, dwSr);
/* Errors */
if (dwSr & CAN_ERRS)
{
pCand->bState = CAND_STATE_ERROR;
CAND_ErrorHandler(pCand, (dwSr & CAN_ERRS));
CAN_DisableIt(pHw, dwSr & CAN_ERRS);
}
else
{
/* Wakeup and bus synchronization done */
if (pCand->bState > CAND_STATE_ACTIVATED)
{
/* Mailbox events */
if (dwSr & CAN_MB_EVENTS)
{
CAND_MessageHandler(pCand);
}
}
else if (dwSr & CAN_SR_WAKEUP)
{
CAN_DisableIt(pHw, CAN_IDR_WAKEUP);
pCand->bState = CAND_STATE_ACTIVATED;
}
}
/* Low-power Mode enabled */
if (dwSr & CAN_SR_SLEEP)
{
CAN_DisableIt(pHw, CAN_IDR_SLEEP);
pCand->bState = CAND_STATE_SLEEP;
}
/* Timestamp */
if (dwSr & CAN_SR_TSTP)
{
}
/* Timer overflow */
if (dwSr & CAN_SR_TOVF)
{
}
}
/**
* Check if the mailbox is ready to configure or transfer.
* \param pCand Pointer to CAN Driver instance.
* \param bMb Mailbox number.
* \return 1 if mailbox is free.
*/
uint8_t CAND_IsMailboxReady(sCand *pCand, uint8_t bMb)
{
return (CAND_IsMbReady(pCand->pMbs[bMb]));
}
/**
* Reset the CAN Mailbox (with configuration).
* \param pCand Pointer to CAN Driver instance.
* \param bMb Mailbox number.
* \param pCfg Pointer to Mailbox configuration instance.
* NULL to reset and disable the mailbox.
*/
void CAND_ResetMailbox(sCand *pCand, uint8_t bMb, sCandMbCfg *pCfg)
{
CAND_ResetMb(pCand, bMb, pCfg);
}
/**
* Configure the CAN Mailbox for message transfer.
* \param pCand Pointer to CAN Driver instance.
* \param pCfg Pointer to Mailbox configuration instance.
* NULL to use old configuration.
* \param pXfr Pointer to transfer configuration instance.
*/
uint8_t CAND_ConfigureTransfer(sCand *pCand,
sCandMbCfg *pCfg,
sCandTransfer *pXfr)
{
uint8_t bMb = pXfr->bMailbox;
sCandTransfer *pTx = pCand->pMbs[bMb];
if (!CAND_IsMbReady(pTx))
return CAND_BUSY;
if (pCfg)
CAND_ResetMb(pCand, bMb, pCfg);
CAND_InitXfr(pCand, pXfr, 0);
return CAND_OK;
}
/**
* Transfer CAN message through a configured mailbox.
* The transfer will not start until it's started by CAND_StartTransfers().
* \note For data receiving, if there is previous pending message in
* mailbox, the RX operation will return this message data.
* \param pCand Pointer to CAN Driver instance.
* \param pXfr Pointer to transfer configuration instance.
* \param bStart 1 to start the transfer immediately.
*/
uint8_t CAND_Transfer(sCand *pCand, sCandTransfer *pXfr)
{
Can *pCan = pCand->pHw;
sCandTransfer *pTx;
uint8_t bMb = pXfr->bMailbox;
pTx = pCand->pMbs[bMb];
if (!CAND_IsMbReady(pTx)) return CAND_BUSY;
if (0 == CAN_GetMessageMode(pCan, bMb))
return CAND_ERR_STATE;
/* Configure and start transfer */
CAND_InitXfr(pCand, pXfr, 1);
/* Enable interrupts statuses */
CAN_EnableIt(pCan, (CAN_ID_MASK & (1 << bMb))|CAN_ERRS);
return CAND_OK;
}
/**
* Start configured transfers (by CAND_ConfigureTransfer()).
* \note For data receiving, if there is previous pending message in
* mailbox, the RX operation will return this message data.
* \param pCand Pointer to CAN Driver instance.
* \param bmMbs Mailbox bitmap.
*/
void CAND_StartTransfers(sCand *pCand, uint32_t bmMbs)
{
Can *pCan = pCand->pHw;
sCandTransfer *pTx;
uint8_t bMb;
uint32_t bmTx = 0;
uint32_t bmRx = 0;
uint32_t dwMMR;
/* Scan mailboxes that not started */
for (bMb = 0; bMb < CAN_NUM_MAILBOX; bMb ++)
{
if ((bmMbs & (1 << bMb)) == 0)
continue;
/* Check if the mailbox is ready to transfer */
pTx = pCand->pMbs[bMb];
if (pTx == NULL)
{
/* Ignore the mailbox */
bmMbs &= ~(1 << bMb);
continue;
}
if (pTx->bState > CAND_XFR_IDLE)
{
/* Ignore the mailbox */
bmMbs &= ~(1 << bMb);
continue;
}
dwMMR = CAN_GetMessageMode(pCan, bMb);
/* Disabled ? */
if ( 0 == dwMMR )
{
/* Ignore the mailbox */
bmMbs &= ~(1 << bMb);
continue;
}
/* RX ? */
else if ((dwMMR & CAN_MMR_MOT_Msk) <= CAN_MMR_MOT_MB_RX_OVERWRITE)
{
bmRx |= 1 << bMb;
}
/* TX ! */
else
{
bmTx |= 1 << bMb;
}
/* Change transfer state */
pTx->bState = CAND_XFR_TX;
/* Nothing to start */
if (bmMbs == 0)
return;
}
/* Change CAN state */
pCand->bState = CAND_STATE_XFR;
/* Start transfers */
CAN_Command(pCan, bmTx);
/* Enable interrupts */
CAN_EnableIt(pCan, bmMbs | CAN_ERRS);
}
/**
* Check if the transfer is finished.
* \return 1 if it's ready to transfer data.
*/
uint8_t CAND_IsTransferDone(sCandTransfer *pXfr)
{
return CAND_IsMbReady(pXfr);
}
#endif
/**@}*/

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/*
* \brief Describes a possible clock configuration (processor clock & master clock),
* including the necessary register values.
*/
typedef struct _ClockConfiguration
{
/** Processor clock frequency (in MHz). */
uint16_t pck;
/** Master clock frequency (in MHz). */
uint16_t mck;
/** CKGR_PLL reqister value. */
uint32_t pllr;
/** PMC_MCKR register value. */
uint32_t mckr;
} ClockConfiguration ;
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/* Clock configurations for the AT91SAM3S4-EK */
#define CKGR_MUL_SHIFT 16
#define CKGR_PLLCOUNT_SHIFT 8
#define CKGR_DIV_SHIFT 0
/* Clock configuration for the AT91SAM3S */
static const ClockConfiguration clockConfigurations[] = {
{133, 133, CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(199)
| CKGR_PLLAR_OUTA(0) | CKGR_PLLAR_PLLACOUNT(64) | CKGR_PLLAR_DIVA(3),
PMC_MCKR_CSS_SLOW_CLK | PMC_MCKR_PRES_CLOCK | PMC_MCKR_MDIV_PCK_DIV3
| PMC_MCKR_PLLADIV2_DIV2 | PMC_MCKR_CSS_PLLA_CLK}
};
/* Number of available clock configurations */
#define NB_CLOCK_CONFIGURATION (sizeof(clockConfigurations)/sizeof(clockConfigurations[0]))
/* Current clock configuration */
uint32_t currentConfig = 0; /* 0 have to be the default configuration */
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Sets the specified clock configuration.
*
* \param configuration Index of the configuration to set.
*/
void CLOCK_SetConfig(uint8_t configuration)
{
TRACE_DEBUG("Setting clock configuration #%d ... ", configuration);
currentConfig = configuration;
/* Switch to main oscillator in two operations */
//C->PMC_MCKR = (PMC->PMC_MCKR & (uint32_t)~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
/* Configure PLL */
PMC->CKGR_PLLAR = clockConfigurations[configuration].pllr;
while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
/* Configure master clock in two operations */
//C->PMC_MCKR = (clockConfigurations[configuration].mckr & (uint32_t)~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
PMC->PMC_MCKR = clockConfigurations[configuration].mckr;
while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
/* DBGU reconfiguration */
DBGU_Configure(115200, clockConfigurations[configuration].mck*1000000);
TRACE_DEBUG("done.\n\r");
}
/**
* \brief Display the user menu on the DBGU.
*/
void CLOCK_DisplayMenu(void)
{
uint32_t i;
printf("\n\rMenu Clock configuration:\n\r");
for (i = 0; i < NB_CLOCK_CONFIGURATION; i++) {
printf(" %u: Set PCK = %3u MHz, MCK = %3u MHz %s\n\r",
(unsigned int)i,
(unsigned int)clockConfigurations[i].pck,
(unsigned int)clockConfigurations[i].mck,
(currentConfig==i)?"(curr)":"");
}
}
/**
* \brief Get the current MCK
*/
uint16_t CLOCK_GetCurrMCK(void)
{
return clockConfigurations[currentConfig].mck;
}
/**
* \brief Get the current PCK
*/
uint16_t CLOCK_GetCurrPCK(void)
{
return clockConfigurations[currentConfig].pck;
}
/**
* \brief Change clock configuration.
*/
void CLOCK_UserChangeConfig(void)
{
uint8_t key = 0;
while (1)
{
CLOCK_DisplayMenu();
key = DBGU_GetChar();
if ((key >= '0') && (key <= ('0' + NB_CLOCK_CONFIGURATION - 1)))
{
CLOCK_SetConfig(key - '0');
break;
}
}
}

315
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbg_util.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* Implement simple DBGU usage as stream receiver.
*/
/*-------------------------------
* Headers
*-------------------------------*/
#include <board.h>
/*-------------------------------
* Defines
*-------------------------------*/
/** Data RX timeout in binary start up */
#define TIMEOUT_RX_START (1000*20)
/** Data RX timeout default value */
#define TIMEOUT_RX (200)
/* ASCII Character Codes */
#define SOH 0x01
#define STX 0x02
#define EOT 0x04
#define CTRL_D 0x04 /**< Transfer Done */
#define ACK 0x06
#define NAK 0x15
#define CAN 0x18 /**< Cancel transfer */
#define CTRL_X 0x24
/* 1K XMODEM Parameters */
#define SOH_LENGTH 128
#define STX_LENGTH 1024
#define SOH_TIMEOUT 1000
/*-------------------------------
* Local functions
*-------------------------------*/
/**
* \brief Compute the CRC
*/
static uint16_t _GetCRC(uint8_t bByte, uint16_t wCrc)
{
int32_t cnt;
uint8_t newBit;
for (cnt = 7; cnt >= 0; cnt --)
{
newBit = ((wCrc >> 15) & 0x1) ^ ((bByte >> cnt) & 0x1);
wCrc <<= 1;
if (newBit) wCrc ^= (0x1021);
}
return wCrc;
}
/*-------------------------------
* Exported functions
*-------------------------------*/
/**
* \brief Receives byte with timeout.
* \param pByte pointer to locate received byte, can be NULL
* to discard data.
* \param timeOut timeout setting, in number of ticks.
*/
uint8_t DbgReceiveByte(uint8_t* pByte, uint32_t timeOut)
{
uint32_t tick;
uint32_t delay;
tick = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
uint8_t tmp = DBGU_GetChar();
if (pByte) *pByte = tmp;
return 1;
}
if (timeOut == 0)
{ /* Never timeout */
}
else
{
delay = GetDelayInTicks(tick, GetTickCount());
if (delay > timeOut)
{
return 0;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
* \param bStart 1 to start a new data stream.
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceiveBinary(uint8_t bStart, uint32_t address, uint32_t maxSize)
{
volatile uint32_t tick0;
uint32_t delay;
uint8_t *pBuffer = (uint8_t*)address;
uint8_t xSign = 0;
uint32_t rxCnt = 0;
if (maxSize == 0) return 0;
if (bStart)
{
printf("\n\r-- Please start binary data in %d seconds:\n\r",
TIMEOUT_RX_START / 1000);
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
DBGU_PutChar(' ');
break;
}
else
{
delay = GetDelayInTicks(tick0, GetTickCount());
if ((delay % 1000) == 0)
{
if (xSign == 0)
{
DBGU_PutChar('*');
xSign = 1;
}
}
else if (xSign)
{
xSign = 0;
}
if (delay > TIMEOUT_RX_START)
{
printf("\n\rRX timeout!\n\r");
return rxCnt;
}
}
}
}
/* Get data */
while(1)
{
tick0 = GetTickCount();
while(1)
{
if (DBGU_IsRxReady())
{
pBuffer[rxCnt ++] = DBGU_GetChar();
if ((rxCnt % (10*1024)) == 0)
{
DBGU_PutChar('.');
}
if (rxCnt >= maxSize)
{
/* Wait until file transfer finished */
return rxCnt;
}
break;
}
delay = GetDelayInTicks(tick0, GetTickCount());
if (delay > TIMEOUT_RX)
{
return rxCnt;
}
}
}
}
/**
* \brief Receives raw binary file through DBGU.
*
* \note When "CCC..", uses Ctrl + D to exit.
*
* \param pktBuffer 1K size packet buffer
* \param address receiving data address
* \param maxSize max receive data size in bytes
* \return number of received bytes
*/
uint32_t DbgReceive1KXModem(uint8_t* pktBuffer,
uint32_t address,
uint32_t maxSize)
{
uint8_t inChar;
uint32_t i, index = 0, pktLen = 0;
uint8_t pktNum = 0, prevPktNum = 0;
uint32_t error = 0;
uint16_t inCrc, myCrc;
uint8_t inCheckSum = 0xFF, checkSum = 0;
uint8_t *pBuffer = (uint8_t*)address;
uint32_t totalLen = 0;
DBGU_PutChar('C');
while (1)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT))
{
DBGU_PutChar('C');
continue;
}
/* Done */
if (EOT == inChar)
{
error = 0;
DBGU_PutChar(ACK);
break;
}
else if (CAN == inChar)
{
error = 2;
}
else if (CTRL_X == inChar)
{
error = 3;
}
else if (SOH == inChar)
{
pktLen = SOH_LENGTH;
}
else if (STX == inChar)
{
pktLen = STX_LENGTH;
}
else continue;
/* Get Packet Number */
if (!DbgReceiveByte(&pktNum, SOH_TIMEOUT)) error = 4;
/* Get 1's complement of packet number */
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 5;
/* Get 1 packet of information. */
checkSum = 0; myCrc = 0; index = 0;
for (i = 0; i < pktLen; i ++)
{
if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 6;
checkSum += inChar;
myCrc = _GetCRC(inChar, myCrc);
if (pktNum != prevPktNum)
{
pktBuffer[index ++] = inChar;
}
}
/* Get CRC bytes */
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc = inCheckSum << 8;
if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7;
inCrc += inCheckSum;
/* If CRC error, NAK */
if (error || (inCrc != myCrc))
{
DBGU_PutChar(NAK);
error = 0;
}
/* Save packet, ACK and next */
else
{
prevPktNum = pktNum;
/* Buffer full? */
if (totalLen + pktLen > maxSize)
{
/* Copy until buffer full? */
/* Stop transfer */
DBGU_PutChar(CAN);
return totalLen;
}
/* Copy the packet */
for (i = 0; i < pktLen; i ++)
{
pBuffer[totalLen + i] = pktBuffer[i];
}
totalLen += pktLen;
DBGU_PutChar(ACK);
}
}
return totalLen;
}

457
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbgu_console.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implements DBGU console.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdio.h>
#include <stdint.h>
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** The Pheripheral has no HW ID */
#define ID_NOTUSED 0xFF
/** Usart Hw ID (ID_USART0) */
#define CONSOLE_ID (pDbgPort->bID)
/** Usart Hw interface used by the console (USART0). */
#define CONSOLE_DBGU ((Dbgu*)pDbgPort->pHw)
/** Pins description list */
#define CONSOLE_PINLIST (pDbgPort->pPioList)
/** Pins description list size */
#define CONSOLE_PINLISTSIZE (pDbgPort->bPioListSize)
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/**
* Debug port struct
*/
typedef struct _DbgPort {
const void* pHw;
const Pin* pPioList;
const uint8_t bPioListSize;
const uint8_t bID;
} sDbgPort;
/*----------------------------------------------------------------------------
* Variables
*----------------------------------------------------------------------------*/
/** Pins for DBGU */
static const Pin pinsDbgu[] = {PINS_DBGU};
/** Pins for USART0 */
static const Pin pinsUs0[] = {PIN_USART0_TXD, PIN_USART0_RXD};
/** Pins for USART1 */
static const Pin pinsUs1[] = {PIN_USART1_TXD, PIN_USART1_RXD};
/** Uses DBGU as debug port */
static sDbgPort dbgpDbgu =
{
DBGU,
pinsDbgu, PIO_LISTSIZE(pinsDbgu),
ID_DBGU
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs0 =
{
USART0,
pinsUs0, PIO_LISTSIZE(pinsUs0),
ID_USART0
};
/** Uses USART0 as debug port */
static sDbgPort dbgpUs1 =
{
USART1,
pinsUs1, PIO_LISTSIZE(pinsUs1),
ID_USART1
};
/** Current used debug port */
static sDbgPort *pDbgPort = &dbgpDbgu;
/** Console initialize status */
uint8_t _bConsoleIsInitialized = 0;
/**
* \brief Select USART0 as DBGU port.
*/
void DBGU_ConsoleUseUSART0(void)
{
pDbgPort = &dbgpUs0;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select USART1 as DBGU port.
*/
void DBGU_ConsoleUseUSART1(void)
{
pDbgPort = &dbgpUs1;
_bConsoleIsInitialized = 0;
}
/**
* \brief Select DBGU as DBGU port.
*/
void DBGU_ConsoleUseDBGU(void)
{
pDbgPort = &dbgpDbgu;
_bConsoleIsInitialized = 0;
}
/**
* \brief Configures an DBGU peripheral with the specified parameters.
*
* \param baudrate Baudrate at which the DBGU should operate (in Hz).
* \param masterClock Frequency of the system master clock (in Hz).
*/
extern void DBGU_Configure( uint32_t baudrate, uint32_t masterClock)
{
/* Configure PIO */
PIO_Configure(CONSOLE_PINLIST, CONSOLE_PINLISTSIZE);
if ( ID_NOTUSED != CONSOLE_ID )
{
PMC_EnablePeripheral(CONSOLE_ID);
}
/* Configure mode register */
if (CONSOLE_DBGU!= DBGU ) {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE | US_MR_CHRL_8_BIT;
}
else {
CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE;
}
/* Reset and disable receiver & transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RSTRX | DBGU_CR_RSTTX;
CONSOLE_DBGU->DBGU_IDR = 0xFFFFFFFF;
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXDIS | DBGU_CR_TXDIS;
/* Configure baudrate */
CONSOLE_DBGU->DBGU_BRGR = (masterClock / baudrate) / 16;
/* Enable receiver and transmitter */
CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXEN | DBGU_CR_TXEN;
_bConsoleIsInitialized = 1 ;
#if defined(__GNUC__)
setvbuf(stdout, (char*)NULL, _IONBF, 0);
#endif
}
/**
* \brief Outputs a character on the DBGU line.
*
* \note This function is synchronous (i.e. uses polling).
* \param c Character to send.
*/
extern void DBGU_PutChar( uint8_t c )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
/* Wait for the transmitter to be ready */
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_TXEMPTY) == 0 ) ;
/* Send character */
CONSOLE_DBGU->DBGU_THR=c ;
}
/**
* \brief Input a character from the DBGU line.
*
* \note This function is synchronous
* \return character received.
*/
extern uint32_t DBGU_GetChar( void )
{
if ( !_bConsoleIsInitialized )
{
DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
}
while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) == 0 ) ;
return CONSOLE_DBGU->DBGU_RHR ;
}
/**
* \brief Check if there is Input from DBGU line.
*
* \return true if there is Input.
*/
extern uint32_t DBGU_IsRxReady( void )
{
if ( !_bConsoleIsInitialized )
{
//DBGU_Configure( CONSOLE_BAUDRATE, BOARD_MCK ) ;
}
return (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) > 0 ;
}
/**
* Displays the content of the given frame on the DBGU.
*
* \param pucFrame Pointer to the frame to dump.
* \param dwSize Buffer size in bytes.
*/
extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize )
{
uint32_t dw ;
for ( dw=0 ; dw < dwSize ; dw++ )
{
printf( "%02X ", pucFrame[dw] ) ;
}
printf( "\n\r" ) ;
}
/**
* Displays the content of the given buffer on the DBGU.
*
* \param pucBuffer Pointer to the buffer to dump.
* \param dwSize Buffer size in bytes.
* \param dwAddress Start address to display
*/
extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress )
{
uint32_t i ;
uint32_t j ;
uint32_t dwLastLineStart ;
uint8_t* pucTmp ;
for ( i=0 ; i < (dwSize / 16) ; i++ )
{
printf( "0x%08X: ", (unsigned int )(dwAddress + ( i * 16) )) ;
pucTmp = (uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 4 ; j++ )
{
printf( "%02X%02X%02X%02X ", pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3] ) ;
pucTmp += 4 ;
}
pucTmp=(uint8_t*)&pucBuffer[i*16] ;
for ( j=0 ; j < 16 ; j++ )
{
DBGU_PutChar( *pucTmp++ ) ;
}
printf( "\n\r" ) ;
}
if ( (dwSize%16) != 0 )
{
dwLastLineStart=dwSize - (dwSize%16) ;
printf( "0x%08X: ", (unsigned int ) (dwAddress + dwLastLineStart )) ;
for ( j=dwLastLineStart ; j < dwLastLineStart+16 ; j++ )
{
if ( (j!=dwLastLineStart) && (j%4 == 0) )
{
printf( " " ) ;
}
if ( j < dwSize )
{
printf( "%02X", pucBuffer[j] ) ;
}
else
{
printf(" ") ;
}
}
printf( " " ) ;
for ( j=dwLastLineStart ; j < dwSize ; j++ )
{
DBGU_PutChar( pucBuffer[j] ) ;
}
printf( "\n\r" ) ;
}
}
/**
* Reads an integer
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetInteger( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint8_t ucNbNb=0 ;
uint32_t dwValue=0 ;
while ( 1 )
{
ucKey=DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 10) + (ucKey - '0');
ucNbNb++ ;
}
else
{
if ( ucKey == 0x0D || ucKey == ' ' )
{
if ( ucNbNb == 0 )
{
printf( "\n\rWrite a number and press ENTER or SPACE!\n\r" ) ;
return 0 ;
}
else
{
printf( "\n\r" ) ;
*pdwValue=dwValue ;
return 1 ;
}
}
else
{
printf( "\n\r'%c' not a number!\n\r", ucKey ) ;
return 0 ;
}
}
}
}
/**
* Reads an integer and check the value
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
* \param dwMin Minimum value
* \param dwMax Maximum value
*/
extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax )
{
uint32_t dwValue=0 ;
if ( DBGU_GetInteger( &dwValue ) == 0 )
{
return 0 ;
}
if ( dwValue < dwMin || dwValue > dwMax )
{
printf( "\n\rThe number have to be between %u and %u\n\r", (unsigned int)dwMin, (unsigned int)dwMax ) ;
return 0 ;
}
printf( "\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
/**
* Reads an hexadecimal number
*
* \param pdwValue Pointer to the uint32_t variable to contain the input value.
*/
extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue )
{
uint8_t ucKey ;
uint32_t dw = 0 ;
uint32_t dwValue = 0 ;
for ( dw=0 ; dw < 8 ; dw++ )
{
ucKey = DBGU_GetChar() ;
DBGU_PutChar( ucKey ) ;
if ( ucKey >= '0' && ucKey <= '9' )
{
dwValue = (dwValue * 16) + (ucKey - '0') ;
}
else
{
if ( ucKey >= 'A' && ucKey <= 'F' )
{
dwValue = (dwValue * 16) + (ucKey - 'A' + 10) ;
}
else
{
if ( ucKey >= 'a' && ucKey <= 'f' )
{
dwValue = (dwValue * 16) + (ucKey - 'a' + 10) ;
}
else
{
printf( "\n\rIt is not a hexa character!\n\r" ) ;
return 0 ;
}
}
}
}
printf("\n\r" ) ;
*pdwValue = dwValue ;
return 1 ;
}
#if defined __ICCARM__ /* IAR Ewarm 5.41+ */
/**
* \brief Outputs a character on the DBGU.
*
* \param c Character to output.
*
* \return The character that was output.
*/
extern WEAK signed int putchar( signed int c )
{
DBGU_PutChar( c ) ;
return c ;
}
#endif // defined __ICCARM__

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup dmad_module
*
* \section DmaHw Dma Hardware Interface Usage
* <ul>
* <li> The DMA controller can handle the transfer between peripherals and memory
* and so receives the triggers from the peripherals. The hardware interface number
* are getting from DMAIF_Get_ChannelNumber().</li>
* <li> DMAIF_IsValidatedPeripherOnDma() helps to check if the given DMAC has associated
* peripheral identifier coded by the given peripheral.</li>
*
* </ul>
*/
/*@{*/
/*@}*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <board.h>
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Array of DMA Channel definition for SAMA5 chip*/
static const DmaHardwareInterface dmaHwIf[] = {
/* dmac, peripheral, T/R, Channel Number*/
{0, ID_HSMCI0, 0, 0},
{0, ID_HSMCI0, 1, 0},
{0, ID_SPI0, 0, 1},
{0, ID_SPI0, 1, 2},
{0, ID_USART0, 0, 3},
{0, ID_USART0, 1, 4},
{0, ID_USART1, 0, 5},
{0, ID_USART1, 1, 6},
{0, ID_TWI0, 0, 7},
{0, ID_TWI0, 1, 8},
{0, ID_TWI1, 0, 9},
{0, ID_TWI1, 1, 10},
{0, ID_UART0, 0, 11},
{0, ID_UART0, 1, 12},
{0, ID_SSC0, 0, 13},
{0, ID_SSC0, 1, 14},
/* dmac 1 */
{1, ID_HSMCI1, 0, 0},
{1, ID_HSMCI1, 1, 0},
{1, ID_HSMCI2, 0, 1},
{1, ID_HSMCI2, 1, 1},
{1, ID_ADC, 1, 2},
{1, ID_SSC1, 0, 3},
{1, ID_SSC1, 1, 4},
{1, ID_UART1, 0, 5},
{1, ID_UART1, 1, 6},
{1, ID_USART2, 0, 7},
{1, ID_USART2, 1, 8},
{1, ID_USART3, 0, 9},
{1, ID_USART3, 1, 10},
{1, ID_TWI2, 0, 11},
{1, ID_TWI2, 1, 12},
{1, ID_DBGU, 0, 13},
{1, ID_DBGU, 1, 14},
{1, ID_SPI1, 0, 15},
{1, ID_SPI1, 1, 16},
{1, ID_SHA, 0, 17},
{1, ID_AES, 0, 18},
{1, ID_AES, 1, 19},
{1, ID_TDES, 0, 20},
{1, ID_TDES, 1, 21}
};
/*----------------------------------------------------------------------------
* Consts
*----------------------------------------------------------------------------*/
/** Number of recognized peripheral identifier code for DMA0/1. */
#define NUMPERIPHERAL (sizeof(dmaHwIf) / sizeof (DmaHardwareInterface))
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Get peripheral identifier coded for hardware handshaking interface
*
* \param bDmac DMA Controller number.
* \param bPeriphID Peripheral ID.
* \param bTransfer Transfer type 0: Tx, 1 :Rx.
* \return 0-15 peripheral identifier coded.
* 0xff : no associated peripheral identifier coded.
*/
uint8_t DMAIF_Get_ChannelNumber (uint8_t bDmac,
uint8_t bPeriphID,
uint8_t bTransfer)
{
uint8_t i;
for (i = 0; i < NUMPERIPHERAL; i++)
{
if ((dmaHwIf[i].bDmac == bDmac) && (dmaHwIf[i].bPeriphID == bPeriphID) && (dmaHwIf[i].bTransfer == bTransfer))
{
return dmaHwIf[i].bIfID;
}
}
return 0xff;
}
/**
* \brief Check if the given DMAC has associated peripheral identifier coded by
* the given peripheral.
*
* \param bDmac DMA Controller number.
* \param bPeriphID Peripheral ID (0xff : memory only).
* \return 1: Is a validated peripher. 0: no associated peripheral identifier coded.
*/
uint8_t DMAIF_IsValidatedPeripherOnDma( uint8_t bDmac, uint8_t bPeriphID)
{
uint8_t i;
/* It is always validated when transfer to memory */
if (bPeriphID == 0xFF) {
return 1;
}
for (i = 0; i < NUMPERIPHERAL; i++)
{
if ((dmaHwIf[i].bDmac == bDmac) && (dmaHwIf[i].bPeriphID == bPeriphID))
{
return 1;
}
}
return 0;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup dmad_module
*
* \section DmaConfig Dma Configuration Usage
*
* To configure a DMA channel, the user has to follow these few steps :
* <ul>
* <li> Initialize a DMA driver instance by DMAD_Initialize().</li>
* <li> choose an available (disabled) channel using DMAD_AllocateChannel().</li>
* <li> After the DMAC selected channel has been programmed, DMAD_PrepareChannel() is to enable
* clock and dma peripheral of the DMA, and set Configuration register to set up the transfer type
* (memory or non-memory peripheral for source and destination) and flow control device.</li>
* <li> Configure DMA multi-buffer transfers using DMAD_PrepareMultiTransfer() to set up the chain of Linked List Items,
* single-buffer transfers using DMAD_PrepareSingleTransfer().</li>
* <li> Invoke DMAD_StartTransfer() to start DMA transfer, or DMAD_StopTransfer() to force stop DMA transfer.</li>
* <li> If picture-in-picture mode is enabled, DMAD_ConfigurePIP() helps to configure PIP mode.</li>
* <li> Once the buffer of data is transferred, DMAD_IsTransferDone() checks if DMA transfer is finished.</li>
* <li> DMAD_Handler() handles DMA interrupt, and invoking DMAD_SetCallback() if provided.</li>
* </ul>
*
* Related files:\n
* \ref dmad.h\n
* \ref dmad.c.\n
*/
/** \file */
/** \addtogroup dmad_functions
@{*/
/*----------------------------------------------------------------------------
* Includes
*----------------------------------------------------------------------------*/
#include "board.h"
#include <assert.h>
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* \brief Try to allocate a DMA channel for on given controller.
* \param pDmad Pointer to DMA driver instance.
* \param bDmac DMA controller ID (0 ~ 1).
* \param bSrcID Source peripheral ID, 0xFF for memory.
* \param bDstID Destination peripheral ID, 0xFF for memory.
* \return Channel number if allocation sucessful, return
* DMAD_ALLOC_FAILED if allocation failed.
*/
static uint32_t DMAD_AllocateDmacChannel( sDmad *pDmad,
uint8_t bDmac,
uint8_t bSrcID,
uint8_t bDstID)
{
uint32_t i;
/* Can't support peripheral to peripheral */
if ((( bSrcID != DMAD_TRANSFER_MEMORY ) && ( bDstID != DMAD_TRANSFER_MEMORY )))
{
return DMAD_ALLOC_FAILED;
}
/* dma transfer from peripheral to memory */
if ( bDstID == DMAD_TRANSFER_MEMORY)
{
if( (!DMAIF_IsValidatedPeripherOnDma(bDmac, bSrcID)) )
{
return DMAD_ALLOC_FAILED;
}
}
/* dma transfer from memory to peripheral */
if ( bSrcID == DMAD_TRANSFER_MEMORY )
{
if( (!DMAIF_IsValidatedPeripherOnDma(bDmac, bDstID)) )
{
return DMAD_ALLOC_FAILED;
}
}
for (i = 0; i < pDmad->numChannels; i ++)
{
if ( pDmad->dmaChannels[bDmac][i].state == DMAD_FREE )
{
/* Allocate the channel */
pDmad->dmaChannels[bDmac][i].state = DMAD_IN_USE;
/* Get general informations */
pDmad->dmaChannels[bDmac][i].bSrcPeriphID = bSrcID;
pDmad->dmaChannels[bDmac][i].bDstPeriphID = bDstID;
pDmad->dmaChannels[bDmac][i].bSrcTxIfID =
DMAIF_Get_ChannelNumber(bDmac, bSrcID, 0);
pDmad->dmaChannels[bDmac][i].bSrcRxIfID =
DMAIF_Get_ChannelNumber(bDmac, bSrcID, 1);
pDmad->dmaChannels[bDmac][i].bDstTxIfID =
DMAIF_Get_ChannelNumber(bDmac, bDstID, 0);
pDmad->dmaChannels[bDmac][i].bDstTxIfID =
DMAIF_Get_ChannelNumber(bDmac, bDstID, 1);
return ((bDmac << 8)) | ((i) & 0xFF);
}
}
return DMAD_ALLOC_FAILED;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Initialize DMA driver instance.
* \param pDmad Pointer to DMA driver instance.
* \param bPollingMode Polling DMA transfer:
* 1. Via DMAD_IsTransferDone(); or
* 2. Via DMAD_Handler().
*/
void DMAD_Initialize( sDmad *pDmad,
uint8_t bPollingMode )
{
uint32_t i, j;
assert( pDmad != NULL ) ;
pDmad->pDmacs[0] = DMAC0;
pDmad->pDmacs[1] = DMAC1;
pDmad->pollingMode = bPollingMode;
pDmad->numControllers = 2;
pDmad->numChannels = 8;
for (i = 0; i < pDmad->numControllers; i ++)
{
for (j = 0; j < pDmad->numChannels; j ++)
{
pDmad->dmaChannels[i][j].fCallback = 0;
pDmad->dmaChannels[i][j].pArg = 0;
pDmad->dmaChannels[i][j].bIrqOwner = 0;
pDmad->dmaChannels[i][j].bSrcPeriphID = 0;
pDmad->dmaChannels[i][j].bDstPeriphID = 0;
pDmad->dmaChannels[i][j].bSrcTxIfID = 0;
pDmad->dmaChannels[i][j].bSrcRxIfID = 0;
pDmad->dmaChannels[i][j].bDstTxIfID = 0;
pDmad->dmaChannels[i][j].bDstRxIfID = 0;
pDmad->dmaChannels[i][j].state = DMAD_FREE;
}
}
}
/**
* \brief DMA interrupt handler
* \param pDmad Pointer to DMA driver instance.
*/
void DMAD_Handler( sDmad *pDmad )
{
Dmac *pDmac;
sDmadChannel *pCh;
uint32_t _iController, iChannel;
uint32_t dmaSr, chSr;
uint32_t dmaRc = DMAD_OK;
assert( pDmad != NULL ) ;
for (_iController = 0; _iController < pDmad->numControllers; _iController ++)
{
pDmac = pDmad->pDmacs[_iController];
/* Check raw status but not masked one for polling mode support */
dmaSr = DMAC_GetStatus( pDmac );
if ((dmaSr & 0x00FFFFFF) == 0) continue;
chSr = DMAC_GetChannelStatus( pDmac );
//printf("iDma(%x,%x)\n\r", dmaSr, chSr);
for (iChannel = 0; iChannel < pDmad->numChannels; iChannel ++)
{
uint8_t bExec = 1;
pCh = &pDmad->dmaChannels[_iController][iChannel];
/* Error */
if (dmaSr & (DMAC_EBCIDR_ERR0 << iChannel))
{
DMAC_DisableChannel( pDmac, iChannel );
if (pCh->state > DMAD_IN_USE) pCh->state = DMAD_STALL;
dmaRc = DMAD_ERROR;
}
/* Chained buffer complete */
else if (dmaSr & (DMAC_EBCIDR_CBTC0 << iChannel))
{
DMAC_DisableChannel( pDmac, iChannel );
if (pCh->state > DMAD_IN_USE) pCh->state = DMAD_IN_USE;
dmaRc = DMAD_OK;
}
/* Buffer complete */
else if (dmaSr & (DMAC_EBCIDR_BTC0 << iChannel))
{
dmaRc = DMAD_PARTIAL_DONE;
/* Re-enable */
if ((chSr & (DMAC_CHSR_ENA0 << iChannel)) == 0)
{
DMAC_EnableChannel( pDmac, iChannel );
}
}
else
{
bExec = 0;
}
/* Execute callback */
if (bExec && pCh->fCallback)
{
pCh->fCallback(dmaRc, pCh->pArg);
}
}
}
}
/**
* \brief Allocate a DMA channel for upper layer.
* \param pDmad Pointer to DMA driver instance.
* \param bSrcID Source peripheral ID, 0xFF for memory.
* \param bDstID Destination peripheral ID, 0xFF for memory.
* \return Channel number if allocation sucessful, return
* DMAD_ALLOC_FAILED if allocation failed.
*/
uint32_t DMAD_AllocateChannel( sDmad *pDmad,
uint8_t bSrcID,
uint8_t bDstID)
{
uint32_t _iController;
uint32_t _dwChannel = DMAD_ALLOC_FAILED;
for ( _iController = 0; _iController < pDmad->numControllers; _iController ++)
{
_dwChannel = DMAD_AllocateDmacChannel( pDmad, _iController,
bSrcID, bDstID );
if (_dwChannel != DMAD_ALLOC_FAILED)
break;
}
return _dwChannel;
}
/**
* \brief Free the specified DMA channel.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eDmadRC DMAD_FreeChannel( sDmad *pDmad, uint32_t _dwChannel )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
switch ( pDmad->dmaChannels[_iController][iChannel].state )
{
case DMAD_IN_XFR:
return DMAD_BUSY;
case DMAD_IN_USE:
pDmad->dmaChannels[_iController][iChannel].state = DMAD_FREE;
break;
}
return DMAD_OK;
}
/**
* \brief Set the callback function for DMA channel transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
* \param fCallback Pointer to callback function.
* \param pArg Pointer to optional argument for callback.
*/
eDmadRC DMAD_SetCallback( sDmad *pDmad, uint32_t _dwChannel,
DmadTransferCallback fCallback, void* pArg )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
pDmad->dmaChannels[_iController][iChannel].fCallback = fCallback;
pDmad->dmaChannels[_iController][iChannel].pArg = pArg;
return DMAD_OK;
}
/**
* \brief Configure Picture-in-Picture mode for DMA transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
* \param srcPIP Source PIP setting.
* \param dstPIP Destination PIP setting.
*/
eDmadRC DMAD_ConfigurePIP( sDmad *pDmad,
uint32_t _dwChannel,
uint32_t dwSrcPIP,
uint32_t dwDstPIP )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[_iController];
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
DMAC_SetPipMode(pDmac, iChannel, dwSrcPIP, dwDstPIP);
return DMAD_OK;
}
/**
* \brief Enable clock of the DMA peripheral, Enable the dma peripheral,
* configure configuration register for DMA transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
* \param dwCfg Configuration value.
*/
eDmadRC DMAD_PrepareChannel( sDmad *pDmad,
uint32_t _dwChannel,
uint32_t dwCfg )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
uint32_t _dwdmaId;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[_iController];
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
DMAC_SetCFG( pDmac, iChannel, dwCfg );
_dwdmaId = (_iController == 0) ? ID_DMAC0 : ID_DMAC1;
/* Enable clock of the DMA peripheral */
if (!PMC_IsPeriphEnabled( _dwdmaId ))
{
PMC_EnablePeripheral( _dwdmaId );
}
/* Enables the DMAC peripheral. */
DMAC_Enable( pDmac );
/* Disables DMAC interrupt for the given channel. */
DMAC_DisableIt (pDmac,
(DMAC_EBCIDR_BTC0 << iChannel)
|(DMAC_EBCIDR_CBTC0 << iChannel)
|(DMAC_EBCIDR_ERR0 << iChannel) );
/* Disable the given dma channel. */
DMAC_DisableChannel( pDmac, iChannel );
/* Clear dummy status */
DMAC_GetChannelStatus( pDmac );
DMAC_GetStatus (pDmac);
return DMAD_OK;
}
/**
* \brief Check if DMA transfer is finished.
* In polling mode DMAD_Handler() is polled.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eDmadRC DMAD_IsTransferDone( sDmad *pDmad, uint32_t _dwChannel )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
{
if ( pDmad->pollingMode ) DMAD_Handler( pDmad );
return DMAD_BUSY;
}
return DMAD_OK;
}
/**
* \brief Clear the automatic mode that services the next-to-last
buffer transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
void DMAD_ClearAuto( sDmad *pDmad, uint32_t _dwChannel )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
Dmac *pDmac;
assert( pDmad != NULL ) ;
pDmac = pDmad->pDmacs[_iController];
DMAC_DisableAutoMode( pDmac, iChannel );
}
/**
* \brief Start DMA transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eDmadRC DMAD_StartTransfer( sDmad *pDmad, uint32_t _dwChannel )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[_iController];
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
/* Change state to transferring */
pDmad->dmaChannels[_iController][iChannel].state = DMAD_IN_XFR;
if ( pDmad->pollingMode == 0 )
{
/* Monitor status in interrupt handler */
DMAC_EnableIt(pDmac, (DMAC_EBCIDR_BTC0 << iChannel)
|(DMAC_EBCIDR_CBTC0 << iChannel)
|(DMAC_EBCIDR_ERR0 << iChannel) );
}
DMAC_EnableChannel(pDmac, iChannel);
return DMAD_OK;
}
/**
* \brief Start DMA transfers on the same controller.
* \param pDmad Pointer to DMA driver instance.
* \param bDmac DMA Controller number.
* \param bmChannels Channels bitmap.
*/
eDmadRC DMAD_StartTransfers( sDmad *pDmad, uint8_t bDmac, uint32_t bmChannels )
{
uint32_t iChannel;
uint32_t bmChs = 0, bmIts = 0;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[bDmac];
for (iChannel = 0; iChannel < pDmad->numChannels; iChannel ++)
{
uint32_t bmChBit = 1 << iChannel;
/* Skipped channels */
if ( pDmad->dmaChannels[bDmac][iChannel].state == DMAD_FREE )
continue;
else if ( pDmad->dmaChannels[bDmac][iChannel].state == DMAD_IN_XFR )
continue;
/* Log to start bit map */
if (bmChannels & bmChBit)
{
bmChs |= bmChBit;
bmIts |= ( (DMAC_EBCIDR_BTC0 << iChannel)
|(DMAC_EBCIDR_CBTC0 << iChannel)
|(DMAC_EBCIDR_ERR0 << iChannel) );
/* Change state */
pDmad->dmaChannels[bDmac][iChannel].state = DMAD_IN_XFR;
}
}
DMAC_EnableChannels(pDmac, bmChs);
if ( pDmad->pollingMode == 0 )
{
/* Monitor status in interrupt handler */
DMAC_EnableIt( pDmac, bmIts );
}
return DMAD_OK;
}
/**
* \brief Stop DMA transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eDmadRC DMAD_StopTransfer( sDmad *pDmad, uint32_t _dwChannel )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[_iController];
sDmadChannel *pCh = &pDmad->dmaChannels[_iController][iChannel];
uint32_t to = 0x1000;
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
if ( pDmad->dmaChannels[_iController][iChannel].state != DMAD_IN_XFR )
return DMAD_OK;
/* Suspend */
DMAC_SuspendChannel(pDmac, iChannel);
/* Poll empty */
for (;to; to --)
{
if (DMAC_GetChannelStatus(pDmac) & (DMAC_CHSR_EMPT0 << iChannel))
{
break;
}
}
/* Disable channel */
DMAC_DisableChannel(pDmac, iChannel);
/* Disable interrupts */
DMAC_DisableIt(pDmac, (DMAC_EBCIDR_BTC0 << iChannel)
|(DMAC_EBCIDR_CBTC0 << iChannel)
|(DMAC_EBCIDR_ERR0 << iChannel) );
/* Clear pending status */
DMAC_GetChannelStatus(pDmac);
DMAC_GetStatus(pDmac);
/* Resume */
DMAC_RestoreChannel(pDmac, iChannel);
/* Change state */
pDmad->dmaChannels[_iController][iChannel].state = DMAD_IN_USE;
/* Invoke callback */
if (pCh->fCallback) pCh->fCallback(DMAD_CANCELED, pCh->pArg);
return DMAD_OK;
}
/**
* \brief Configure DMA for a single transfer.
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
*/
eDmadRC DMAD_PrepareSingleTransfer( sDmad *pDmad,
uint32_t _dwChannel,
sDmaTransferDescriptor *pXfrDesc )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
Dmac *pDmac = pDmad->pDmacs[_iController];
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
DMAC_SetSourceAddr(pDmac, iChannel, pXfrDesc->dwSrcAddr);
DMAC_SetDestinationAddr(pDmac, iChannel, pXfrDesc->dwDstAddr);
DMAC_SetDescriptorAddr(pDmac, iChannel, 0, 0);
DMAC_SetControlA(pDmac, iChannel, pXfrDesc->dwCtrlA);
DMAC_SetControlB(pDmac, iChannel, pXfrDesc->dwCtrlB);
return DMAD_OK;
}
/**
* \brief Configure DMA multi-buffer transfers using linked lists
* \param pDmad Pointer to DMA driver instance.
* \param _dwChannel ControllerNumber << 8 | ChannelNumber.
* \param pXfrDesc Pointer to DMA Linked List.
*/
eDmadRC DMAD_PrepareMultiTransfer( sDmad *pDmad,
uint32_t _dwChannel,
sDmaTransferDescriptor *pXfrDesc )
{
uint8_t _iController = (_dwChannel >> 8);
uint8_t iChannel = (_dwChannel) & 0xFF;
assert( pDmad != NULL ) ;
Dmac *pDmac = pDmad->pDmacs[_iController];
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE )
return DMAD_ERROR;
if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR )
return DMAD_BUSY;
DMAC_SetDescriptorAddr( pDmac, iChannel, (uint32_t)pXfrDesc, 0 );
DMAC_SetControlB( pDmac, iChannel, 0);
return DMAD_OK;
}
/**@}*/

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FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/emacd.c Normal file
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@ -0,0 +1,712 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
#include <string.h>
/** \addtogroup EMACD_defines
@{*/
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
/** Error bits for TX */
#define EMAC_TX_ERR_BITS \
(EMAC_TXD_bmERROR | EMAC_TXD_bmUNDERRUN | EMAC_TXD_bmEXHAUSTED)
/*---------------------------------------------------------------------------
* Circular buffer management
*---------------------------------------------------------------------------*/
/** Return count in buffer */
#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size))
/** Return space available, 0..size-1. always leave one free char as a completely full buffer
has head == tail, which is the same as empty */
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once,
so they can change underneath us without returning inconsistent results */
#define CIRC_CNT_TO_END(head,tail,size) \
({int end = (size) - (tail); \
int n = ((head) + end) % (size); \
n < end ? n : end;})
/** Return space available up to the end of the buffer */
#define CIRC_SPACE_TO_END(head,tail,size) \
({int end = (size) - 1 - (head); \
int n = (end + (tail)) % (size); \
n <= end ? n : end+1;})
/** Increment head or tail */
#define CIRC_INC(headortail,size) \
headortail++; \
if(headortail >= size) { \
headortail = 0; \
}
/** Circular buffer is empty ? */
#define CIRC_EMPTY(head, tail) (head == tail)
/** Clear circular buffer */
#define CIRC_CLEAR(head, tail) (head = tail = 0)
/** @}*/
/*----------------------------------------------------------------------------
* Internal variables
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Internal functions
*----------------------------------------------------------------------------*/
/**
* Disable TX & reset registers and descriptor list
* \param pDrv Pointer to EMAC Driver instance.
*/
static void EMACD_ResetTx(sEmacd *pDrv)
{
Emac *pHw = pDrv->pHw;
uint8_t *pTxBuffer = pDrv->pTxBuffer;
sEmacTxDescriptor *pTd = pDrv->pTxD;
uint32_t Index;
uint32_t Address;
/* Disable TX */
EMAC_TransmitEnable(pHw, 0);
/* Setup the TX descriptors. */
CIRC_CLEAR(pDrv->wTxHead, pDrv->wTxTail);
for(Index = 0; Index < pDrv->wTxListSize; Index++)
{
Address = (uint32_t)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE]));
pTd[Index].addr = Address;
pTd[Index].status.val = EMAC_TXD_bmUSED;
}
pTd[pDrv->wTxListSize - 1].status.val = EMAC_TXD_bmUSED | EMAC_TXD_bmWRAP;
/* Transmit Buffer Queue Pointer Register */
EMAC_SetTxQueue(pHw, (uint32_t)pTd);
}
/**
* Disable RX & reset registers and descriptor list
* \param pDrv Pointer to EMAC Driver instance.
*/
static void EMACD_ResetRx(sEmacd *pDrv)
{
Emac *pHw = pDrv->pHw;
uint8_t *pRxBuffer = pDrv->pRxBuffer;
sEmacRxDescriptor *pRd = pDrv->pRxD;
uint32_t Index;
uint32_t Address;
/* Disable RX */
EMAC_ReceiveEnable(pHw, 0);
/* Setup the RX descriptors. */
pDrv->wRxI = 0;
for(Index = 0; Index < pDrv->wRxListSize; Index++)
{
Address = (uint32_t)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE]));
/* Remove EMAC_RXD_bmOWNERSHIP and EMAC_RXD_bmWRAP */
pRd[Index].addr.val = Address & EMAC_RXD_ADDR_MASK;
pRd[Index].status.val = 0;
}
pRd[pDrv->wRxListSize - 1].addr.val |= EMAC_RXD_bmWRAP;
/* Receive Buffer Queue Pointer Register */
EMAC_SetRxQueue(pHw, (uint32_t) pRd);
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* EMAC Interrupt handler
*/
void EMACD_Handler( sEmacd *pEmacd )
{
Emac *pHw = pEmacd->pHw;
uint32_t isr;
uint32_t rsr;
uint32_t tsr;
sEmacTxDescriptor *pTxTd;
fEmacdTransferCallback *pTxCb = NULL;
uint32_t rxStatusFlag;
uint32_t txStatusFlag;
isr = EMAC_GetItStatus(pHw);
rsr = EMAC_GetRxStatus(pHw);
tsr = EMAC_GetTxStatus(pHw);
isr &= ~(EMAC_GetItMask(pHw) | 0xFFC300);
/* RX packet */
if ((isr & EMAC_ISR_RCOMP) || (rsr & EMAC_RSR_REC))
{
asm("nop");
rxStatusFlag = EMAC_RSR_REC;
/* Check OVR */
if (rsr & EMAC_RSR_OVR)
{
rxStatusFlag |= EMAC_RSR_OVR;
}
/* Check BNA */
if (rsr & EMAC_RSR_BNA)
{
rxStatusFlag |= EMAC_RSR_BNA;
}
/* Clear status */
EMAC_ClearRxStatus(pHw, rxStatusFlag);
/* Invoke callbacks */
if (pEmacd->fRxCb)
{
pEmacd->fRxCb(rxStatusFlag);
}
}
/* TX packet */
if ((isr & EMAC_ISR_TCOMP) || (tsr & EMAC_TSR_COMP)) {
asm("nop");
txStatusFlag = EMAC_TSR_COMP;
/* A frame transmitted */
/* Check RLE */
if (tsr & EMAC_TSR_RLES)
{
/* Status RLE & Number of discarded buffers */
txStatusFlag = EMAC_TSR_RLES
| CIRC_CNT(pEmacd->wTxHead,
pEmacd->wTxTail,
pEmacd->wTxListSize)
;
pTxCb = &pEmacd->fTxCbList[pEmacd->wTxTail];
EMACD_ResetTx(pEmacd);
TRACE_INFO("Tx RLE!!\n\r");
EMAC_TransmitEnable(pHw, 1);
}
/* Check COL */
if (tsr & EMAC_TSR_COL)
{
txStatusFlag |= EMAC_TSR_COL;
}
/* Check BEX */
if (tsr & EMAC_TSR_BEX)
{
txStatusFlag |= EMAC_TSR_BEX;
}
/* Check UND */
if (tsr & EMAC_TSR_UND)
{
txStatusFlag |= EMAC_TSR_UND;
}
/* Clear status */
EMAC_ClearTxStatus(pHw, txStatusFlag);
if (!CIRC_EMPTY(pEmacd->wTxHead, pEmacd->wTxTail))
{
// Check the buffers
do {
pTxTd = &pEmacd->pTxD[pEmacd->wTxTail];
pTxCb = &pEmacd->fTxCbList[pEmacd->wTxTail];
/* Any error?
Exit if buffer has not been sent yet */
if ((pTxTd->status.val & EMAC_TXD_bmUSED) == 0)
{
break;
}
/* Notify upper layer that a packet has been sent */
if (*pTxCb)
{
(*pTxCb)(txStatusFlag);
}
CIRC_INC( pEmacd->wTxTail, pEmacd->wTxListSize );
} while (CIRC_CNT(pEmacd->wTxHead, pEmacd->wTxTail, pEmacd->wTxListSize));
}
if (tsr & EMAC_TSR_RLES)
{
/* Notify upper layer RLE */
if (*pTxCb)
{
(*pTxCb)(txStatusFlag);
}
}
/* If a wakeup has been scheduled, notify upper layer that it can
send other packets, send will be successfull. */
if( (CIRC_SPACE(pEmacd->wTxHead,
pEmacd->wTxTail,
pEmacd->wTxListSize) >= pEmacd->bWakeupThreshold)
&& pEmacd->fWakupCb)
{
pEmacd->fWakupCb();
}
}
/* PAUSE Frame */
if (isr & EMAC_ISR_PFRE)
{
TRACE_INFO("Pause!\n\r");
}
if (isr & EMAC_ISR_PTZ)
{
TRACE_INFO("Pause TO!\n\r");
}
}
/**
* Initialize the EMAC Driver with HW settings.
* \param pEmacd Pointer to EMAC Driver instance.
* \param pHw Pointer to HW address for registers.
* \param bID HW ID for power management.
* \param bCAF Enable/Disable CopyAllFrame.
* \param bNBC Enable/Disable NoBroadCast.
*/
void EMACD_Init(sEmacd *pEmacd,
Emac *pHw, uint8_t bID,
uint8_t bCAF, uint8_t bNBC )
{
TRACE_DEBUG("EMACD_Init\n\r");
/* Initialize struct */
pEmacd->pHw = pHw;
pEmacd->bId = bID;
/* Power ON */
PMC_EnablePeripheral(bID);
/* Disable TX & RX and more */
EMAC_NetworkControl(pHw, 0);
EMAC_DisableIt(pHw, ~0u);
EMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
EMAC_ClearRxStatus(pHw, EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA);
/* Clear all status bits in the transmit status register */
EMAC_ClearTxStatus(pHw, EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLES
| EMAC_TSR_BEX | EMAC_TSR_COMP | EMAC_TSR_UND);
/* Clear interrupts */
EMAC_GetItStatus(pHw);
/* Enable the copy of data into the buffers
ignore broadcasts, and don't copy FCS. */
EMAC_Configure(pHw, EMAC_GetConfigure(pHw) | EMAC_NCFGR_DRFCS | EMAC_NCFGR_PAE);
EMAC_CpyAllEnable(pHw, bCAF);
EMAC_BroadcastDisable(pHw, bNBC);
}
/**
* Initialize necessary allocated buffer lists for EMAC Driver to transfer data.
* Must be invoked after EMACD_Init() but before RX/TX start.
* \param pEmacd Pointer to EMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* EMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* EMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return EMACD_OK or EMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
extern uint8_t EMACD_InitTransfer( sEmacd *pEmacd,
uint8_t *pRxBuffer, sEmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sEmacTxDescriptor *pTxD, fEmacdTransferCallback *pTxCb,
uint16_t wTxSize)
{
Emac *pHw = pEmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return EMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) )
{
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pEmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pEmacd->pRxD = (sEmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pEmacd->wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) )
{
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pEmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pEmacd->pTxD = (sEmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pEmacd->wTxListSize = wTxSize;
pEmacd->fTxCbList = pTxCb;
/* Reset TX & RX */
EMACD_ResetRx(pEmacd);
EMACD_ResetTx(pEmacd);
/* Enable Rx and Tx, plus the stats register. */
EMAC_TransmitEnable(pHw, 1);
EMAC_ReceiveEnable(pHw, 1);
EMAC_StatisticsWriteEnable(pHw, 1);
/* Setup the interrupts for TX (and errors) */
EMAC_EnableIt(pHw, EMAC_IER_RXUBR
| EMAC_IER_TUND
| EMAC_IER_RLE
| EMAC_IER_TXERR
| EMAC_IER_TCOMP
| EMAC_IER_ROVR
| EMAC_IER_HRESP
| EMAC_IER_PFR
| EMAC_IER_PTZ);
return EMACD_OK;
}
/**
* Reset TX & RX queue & statistics
* \param pEmacd Pointer to EMAC Driver instance.
*/
void EMACD_Reset(sEmacd *pEmacd)
{
Emac *pHw = pEmacd->pHw;
EMACD_ResetRx(pEmacd);
EMACD_ResetTx(pEmacd);
EMAC_NetworkControl(pHw, EMAC_NCR_TE | EMAC_NCR_RE
| EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT);
}
/**
* Send a packet with EMAC.
* If the packet size is larger than transfer buffer size error returned.
* If packet transfer status is monitored, specify callback for each packet.
* \param pEmacd Pointer to EMAC Driver instance.
* \param buffer The buffer to be send
* \param size The size of buffer to be send
* \param fTxCb TX callback.
* \return EMACD_OK, EMACD_PARAM or EMACD_TX_BUSY.
*/
uint8_t EMACD_Send( sEmacd *pEmacd,
void *pBuffer,
uint32_t size,
fEmacdTransferCallback fTxCb )
{
Emac *pHw = pEmacd->pHw;
volatile sEmacTxDescriptor *pTxTd;
volatile fEmacdTransferCallback *pfTxCb;
TRACE_DEBUG("EMAC_Send\n\r");
/* Check parameter */
if (size > EMAC_TX_UNITSIZE) {
TRACE_ERROR("EMAC driver does not split send packets.");
TRACE_ERROR("%d bytes max in one packet (%u bytes requested)\n\r",
EMAC_TX_UNITSIZE, (unsigned int)size);
return EMACD_PARAM;
}
/* Pointers to the current TxTd */
pTxTd = &pEmacd->pTxD[pEmacd->wTxHead];
/* If no free TxTd, buffer can't be sent, schedule the wakeup callback */
if( CIRC_SPACE(pEmacd->wTxHead, pEmacd->wTxTail, pEmacd->wTxListSize) == 0)
{
//if ((pTxTd->status & EMAC_TXD_bmUSED) != 0)
{
//EMAC_ResetTx();
//TRACE_WARNING("Circ Full but FREE TD found\n\r");
//AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE;
}
//else
{
return EMACD_TX_BUSY;
}
}
/* Pointers to the current Tx Callback */
pfTxCb = &pEmacd->fTxCbList[pEmacd->wTxHead];
/* Setup/Copy data to transmition buffer */
if (pBuffer && size)
{
/* Driver manage the ring buffer */
memcpy((void *)pTxTd->addr, pBuffer, size);
}
/* Tx Callback */
*pfTxCb = fTxCb;
/* Update TD status */
/* The buffer size defined is length of ethernet frame
so it's always the last buffer of the frame. */
if (pEmacd->wTxHead == pEmacd->wTxListSize-1)
{
pTxTd->status.val =
(size & EMAC_TXD_LEN_MASK) | EMAC_TXD_bmLAST | EMAC_TXD_bmWRAP;
}
else
{
pTxTd->status.val = (size & EMAC_TXD_LEN_MASK) | EMAC_TXD_bmLAST;
}
CIRC_INC(pEmacd->wTxHead, pEmacd->wTxListSize);
/* Now start to transmit if it is not already done */
EMAC_TransmissionStart(pHw);
return EMACD_OK;
}
/**
* Return current load of TX.
* \param pEmacd Pointer to EMAC Driver instance.
*/
uint32_t EMACD_TxLoad(sEmacd *pEmacd)
{
uint16_t head = pEmacd->wTxHead;
uint16_t tail = pEmacd->wTxTail;
return CIRC_CNT(head, tail, pEmacd->wTxListSize);
}
/**
* Receive a packet with EMAC
* If not enough buffer for the packet, the remaining data is lost but right
* frame length is returned.
* \param pEmacd Pointer to EMAC Driver instance.
* \param pFrame Buffer to store the frame
* \param frameSize Size of the frame
* \param pRcvSize Received size
* \return OK, no data, or frame too small
*/
uint8_t EMACD_Poll( sEmacd * pEmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize)
{
uint16_t bufferLength;
uint32_t tmpFrameSize=0;
uint8_t *pTmpFrame=0;
uint32_t tmpIdx = pEmacd->wRxI;
volatile sEmacRxDescriptor *pRxTd = &pEmacd->pRxD[pEmacd->wRxI];
char isFrame = 0;
if (pFrame == NULL) return EMACD_PARAM;
/* Set the default return value */
*pRcvSize = 0;
/* Process received RxTd */
while ((pRxTd->addr.val & EMAC_RXD_bmOWNERSHIP) == EMAC_RXD_bmOWNERSHIP)
{
/* A start of frame has been received, discard previous fragments */
if ((pRxTd->status.val & EMAC_RXD_bmSOF) == EMAC_RXD_bmSOF)
{
/* Skip previous fragment */
while (tmpIdx != pEmacd->wRxI)
{
pRxTd = &pEmacd->pRxD[pEmacd->wRxI];
pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP);
CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize);
}
/* Reset the temporary frame pointer */
pTmpFrame = pFrame;
tmpFrameSize = 0;
/* Start to gather buffers in a frame */
isFrame = 1;
}
/* Increment the pointer */
CIRC_INC(tmpIdx, pEmacd->wRxListSize);
asm("nop");
/* Copy data in the frame buffer */
if (isFrame)
{
if (tmpIdx == pEmacd->wRxI)
{
TRACE_INFO("no EOF (Invalid of buffers too small)\n\r");
do
{
pRxTd = &pEmacd->pRxD[pEmacd->wRxI];
pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP);
CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize);
} while(tmpIdx != pEmacd->wRxI);
return EMACD_RX_NULL;
}
/* Copy the buffer into the application frame */
bufferLength = EMAC_RX_UNITSIZE;
if ((tmpFrameSize + bufferLength) > frameSize)
{
bufferLength = frameSize - tmpFrameSize;
}
memcpy(pTmpFrame, (void*)(pRxTd->addr.val & EMAC_RXD_ADDR_MASK), bufferLength);
pTmpFrame += bufferLength;
tmpFrameSize += bufferLength;
/* An end of frame has been received, return the data */
if ((pRxTd->status.val & EMAC_RXD_bmEOF) == EMAC_RXD_bmEOF)
{
/* Frame size from the EMAC */
*pRcvSize = (pRxTd->status.val & EMAC_RXD_LEN_MASK);
TRACE_INFO("packet %d-%d (%d)\n\r", pEmacd->wRxI, tmpIdx, *pRcvSize);
/* All data have been copied in the application frame buffer => release TD */
while (pEmacd->wRxI != tmpIdx)
{
pRxTd = &pEmacd->pRxD[pEmacd->wRxI];
pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP);
CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize);
}
/* Application frame buffer is too small all data have not been copied */
if (tmpFrameSize < *pRcvSize)
{
TRACE_INFO("size req %u size allocated %u\n\r", (unsigned int)(*pRcvSize), (unsigned int)frameSize);
return EMACD_SIZE_TOO_SMALL;
}
return EMACD_OK;
}
}
/* SOF has not been detected, skip the fragment */
else
{
pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP);
pEmacd->wRxI = tmpIdx;
}
/* Process the next buffer */
pRxTd = &pEmacd->pRxD[tmpIdx];
}
return EMACD_RX_NULL;
}
/**
* Register/Clear RX callback. Callback will be invoked after the next received
* frame.
*
* When EMACD_Poll() returns EMACD_RX_NULL the application task call
* EMACD_SetRxCallback() to register fRxCb() callback and enters suspend state.
* The callback is in charge to resume the task once a new frame has been
* received. The next time EMACD_Poll() is called, it will be successfull.
*
* This function is usually invoked from the RX callback itself with NULL
* callback, to unregister. Once the callback has resumed the application task,
* there is no need to invoke the callback again.
*
* \param pEmacd Pointer to EMAC Driver instance.
* \param fRxCb RX callback.
*/
void EMACD_SetRxCallback(sEmacd * pEmacd, fEmacdTransferCallback fRxCb)
{
Emac *pHw = pEmacd->pHw;
if (fRxCb == NULL)
{
EMAC_DisableIt(pHw, EMAC_IDR_RCOMP);
pEmacd->fRxCb = NULL;
}
else
{
pEmacd->fRxCb = fRxCb;
EMAC_EnableIt(pHw, EMAC_IER_RCOMP);
}
}
/**
* Register/Clear TX wakeup callback.
*
* When EMACD_Send() returns EMACD_TX_BUSY (all TD busy) the application
* task calls EMACD_SetTxWakeupCallback() to register fWakeup() callback and
* enters suspend state. The callback is in charge to resume the task once
* several TD have been released. The next time EMACD_Send() will be called,
* it shall be successfull.
*
* This function is usually invoked with NULL callback from the TX wakeup
* callback itself, to unregister. Once the callback has resumed the
* application task, there is no need to invoke the callback again.
*
* \param pEmacd Pointer to EMAC Driver instance.
* \param fWakeup Wakeup callback.
* \param bThreshould Number of free TD before wakeup callback invoked.
* \return EMACD_OK, EMACD_PARAM on parameter error.
*/
uint8_t EMACD_SetTxWakeupCallback(sEmacd * pEmacd,
fEmacdWakeupCallback fWakeup,
uint8_t bThreshold)
{
if (fWakeup == NULL)
{
pEmacd->fWakupCb = NULL;
}
else
{
if (bThreshold <= pEmacd->wTxListSize)
{
pEmacd->fWakupCb = fWakeup;
pEmacd->bWakeupThreshold = bThreshold;
}
else
{
return EMACD_PARAM;
}
}
return EMACD_OK;
}

618
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacb.c Normal file
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@ -0,0 +1,618 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** Default max retry count */
#define GMACB_RETRY_MAX 300000
/** Default max retry count */
#define GACB_RETRY_MAX 1000000
/*---------------------------------------------------------------------------
* Local functions
*---------------------------------------------------------------------------*/
/**
* Wait PHY operation complete.
* Return 1 if the operation completed successfully.
* May be need to re-implemented to reduce CPU load.
* \param retry: the retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_WaitPhy( Gmac *pHw, uint32_t retry )
{
volatile uint32_t retry_count = 0;
while (!GMAC_IsIdle(pHw))
{
if(retry == 0) continue;
retry_count ++;
if (retry_count >= retry)
{
return 0;
}
}
return 1;
}
/**
* Read PHY register.
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param pValue Pointer to a 32 bit location to store read data
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_ReadPhy(Gmac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t *pValue,
uint32_t retry)
{
GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0);
if ( GMACB_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut GMACB_ReadPhy\n\r");
return 0;
}
*pValue = GMAC_PHYData(pHw);
return 1;
}
/**
* Write PHY register
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param Value Data to write ( Actually 16 bit data )
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t GMACB_WritePhy(Gmac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t Value,
uint32_t retry)
{
GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value);
if ( GMACB_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut GMACB_WritePhy\n\r");
return 0;
}
return 1;
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* \brief Find a valid PHY Address ( from 0 to 31 ).
* \param pMacb Pointer to the MACB instance
* \return 0xFF when no valid PHY Address found.
*/
static uint8_t GMACB_FindValidPhy(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value=0;
uint8_t rc;
uint8_t phyAddress;
uint8_t cnt;
TRACE_DEBUG("GMACB_FindValidPhy\n\r");
GMAC_EnableMdio(pHw);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
/* Check current phyAddress */
rc = phyAddress;
if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1, &value, retryMax) == 0 ) {
TRACE_ERROR("GMACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
/* Find another one */
if (value != GMII_OUI_MSB) {
rc = 0xFF;
for(cnt = 0; cnt < 32; cnt ++) {
phyAddress = (phyAddress + 1) & 0x1F;
if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1, &value, retryMax) == 0 ) {
TRACE_ERROR("MACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
if (value == GMII_OUI_MSB) {
rc = phyAddress;
break;
}
}
}
GMAC_DisableMdio(pHw);
if (rc != 0xFF) {
TRACE_INFO("** Valid PHY Found: %d\n\r", rc);
GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);
TRACE_DEBUG("_BMSR : 0x%X, addr: %d\n\r", value, phyAddress);
GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &value, retryMax);
TRACE_DEBUG("_1000BTSR : 0x%X, addr: %d\n\r", value, phyAddress);
GMACB_ReadPhy(pHw, phyAddress, GMII_EMSR, &value, retryMax);
TRACE_DEBUG("_EMSR : 0x%X, addr: %d\n\r", value, phyAddress);
}
return rc;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Dump all the useful registers.
* \param pMacb Pointer to the MACB instance
*/
void GMACB_DumpRegisters(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint8_t phyAddress;
uint32_t retryMax;
uint32_t value;
TRACE_INFO("GMACB_DumpRegisters\n\r");
GMAC_EnableMdio(pHw);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
TRACE_INFO("GMII MACB @%d) Registers:\n\r", phyAddress);
GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);
TRACE_INFO(" _BMCR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);
TRACE_INFO(" _BMSR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &value, retryMax);
TRACE_INFO(" _ANAR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &value, retryMax);
TRACE_INFO(" _ANLPAR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANER, &value, retryMax);
TRACE_INFO(" _ANER : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANNPR, &value, retryMax);
TRACE_INFO(" _ANNPR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPNPAR, &value, retryMax);
TRACE_INFO(" _ANLPNPAR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTCR, &value, retryMax);
TRACE_INFO(" _1000BTCR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &value, retryMax);
TRACE_INFO(" _1000BTSR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_EMSR, &value, retryMax);
TRACE_INFO(" _EMSR : 0x%X\n\r", value);
TRACE_INFO(" \n\r");
GMACB_ReadPhy(pHw, phyAddress, GMII_RLLMR, &value, retryMax);
TRACE_INFO(" _RLLMR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_LMDCDR, &value, retryMax);
TRACE_INFO(" _LMDCDR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_DPPSR, &value, retryMax);
TRACE_INFO(" _DPPSR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_RXERCR, &value, retryMax);
TRACE_INFO(" _RXERCR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_ICSR, &value, retryMax);
TRACE_INFO(" _ICSR : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_DDC1R, &value, retryMax);
TRACE_INFO(" _DDC1R : 0x%X\n\r", value);
GMACB_ReadPhy(pHw, phyAddress, GMII_PHYCR, &value, retryMax);
TRACE_INFO(" _PHYCR : 0x%X\n\r", value);
TRACE_INFO(" \n\r");
value = GMII_CCR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _CCR : 0x%X\n\r", value);
value = GMII_SSR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _SSR : 0x%X\n\r", value);
value = GMII_OMSOR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _OMSOR : 0x%X\n\r", value);
value = GMII_OMSSR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _OMSSR : 0x%X\n\r", value);
value = GMII_RCCPSR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _RCCPSR : 0x%X\n\r", value);
value = GMII_RRDPSR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _RCCPSR : 0x%X\n\r", value);
value = GMII_ATR;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax);
TRACE_INFO(" _ATR : 0x%X\n\r", value);
GMAC_DisableMdio(pHw);
}
/**
* \brief Setup the maximum timeout count of the driver.
* \param pMacb Pointer to the MACB instance
* \param toMax Timeout maxmum count.
*/
void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax)
{
pMacb->retryMax = toMax;
}
/**
* \brief Initialize the MACB instance.
* \param pMacb Pointer to the MACB instance
* \param phyAddress The PHY address used to access the PHY
*/
void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress)
{
pMacb->pGmacd = pGmacd;
pMacb->phyAddress = phyAddress;
/* Initialize timeout by default */
pMacb->retryMax = GMACB_RETRY_MAX;
}
/**
* \brief Issue a SW reset to reset all registers of the PHY.
* \param pMacb Pointer to the MACB instance
* \return 1 if successfully, 0 if timeout.
*/
uint8_t GMACB_ResetPhy(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t bmcr = GMII_RESET;
uint8_t phyAddress;
uint32_t timeout = 10;
uint8_t ret = 1;
TRACE_INFO(" GMACB_ResetPhy\n\r");
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
GMAC_EnableMdio(pHw);
bmcr = GMII_RESET;
GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, bmcr, retryMax);
do {
GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &bmcr, retryMax);
timeout--;
} while ((bmcr & GMII_RESET) && timeout);
GMAC_DisableMdio(pHw);
if (!timeout) {
ret = 0;
}
return( ret );
}
/**
* \brief Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs
* This should be called only once to initialize the PHY pre-settings.
* The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups).
* The COL pin is used to select MII mode on reset (pulled up for Reduced MII)
* The RXDV pin is used to select test mode on reset (pulled up for test mode)
* The above pins should be predefined for corresponding settings in resetPins
* The GMAC peripheral pins are configured after the reset done.
* \param pMacb Pointer to the MACB instance
* \param mck Main clock setting to initialize clock
* \param resetPins Pointer to list of PIOs to configure before HW RESET
* (for PHY power on reset configuration latch)
* \param nbResetPins Number of PIO items that should be configured
* \param emacPins Pointer to list of PIOs for the EMAC interface
* \param nbEmacPins Number of PIO items that should be configured
* \return 1 if RESET OK, 0 if timeout.
*/
uint8_t GMACB_InitPhy(GMacb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint8_t rc = 1;
uint8_t phy;
/* Perform RESET */
TRACE_DEBUG("RESET PHY\n\r");
if (pResetPins) {
/* Configure PINS */
PIO_Configure(pResetPins, nbResetPins);
}
/* Configure EMAC runtime pins */
if (rc) {
PIO_Configure(pEmacPins, nbEmacPins);
rc = GMAC_SetMdcClock(pHw, mck );
if (!rc) {
TRACE_ERROR("No Valid MDC clock\n\r");
return 0;
}
/* Check PHY Address */
phy = GMACB_FindValidPhy(pMacb);
if (phy == 0xFF) {
TRACE_ERROR("PHY Access fail\n\r");
return 0;
}
if(phy != pMacb->phyAddress) {
pMacb->phyAddress = phy;
GMACB_ResetPhy(pMacb);
}
}
else {
TRACE_ERROR("PHY Reset Timeout\n\r");
}
return rc;
}
/**
* \brief Issue a Auto Negotiation of the PHY
* \param pMacb Pointer to the MACB instance
* \return 1 if successfully, 0 if timeout.
*/
uint8_t GMACB_AutoNegotiate(GMacb *pMacb)
{
sGmacd *pDrv = pMacb->pGmacd;
Gmac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value;
uint32_t phyAnar;
uint32_t phyAnalpar;
uint32_t gbaseTC;
uint32_t gbaseTS;
uint32_t retryCount= 0;
uint8_t phyAddress;
uint8_t rc = 1;
uint32_t duplex, speed;
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
GMAC_EnableMdio(pHw);
if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID1, &value, retryMax))
{
TRACE_ERROR("Pb GEMAC_ReadPhy Id1\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress);
if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID2, &phyAnar, retryMax))
{
TRACE_ERROR("Pb GMACB_ReadPhy Id2\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar);
if( ( value == GMII_OUI_MSB )
&& ( ((phyAnar>>10)&GMII_LSB_MASK) == GMII_OUI_LSB ) )
{
TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F));
TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0x7));
}
else
{
TRACE_ERROR("Problem OUI value\n\r");
}
value = GMII_RCCPSR | 0x8000;
GMACB_WritePhy(pHw,phyAddress, GMII_ERCR, value, retryMax);
//value = 0xF0F4;
value = 0xF2F4;
GMACB_WritePhy(pHw,phyAddress, GMII_ERDWR, value, retryMax);
value = GMII_RRDPSR | 0x8000;
GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax);
//value = 0x3028;
value = 0x2222;
GMACB_WritePhy(pHw,phyAddress, GMII_ERDWR, value, retryMax);
value = 0xFF00;
rc = GMACB_WritePhy(pHw,phyAddress, GMII_ICSR, value, retryMax);
/* Set the Auto_negotiation Advertisement Register, MII advertising for Next page
100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &phyAnar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
phyAnar = GMII_TX_FDX | GMII_TX_HDX |
GMII_10_FDX | GMII_10_HDX | GMII_AN_IEEE_802_3;
rc = GMACB_WritePhy(pHw,phyAddress, GMII_ANAR, phyAnar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Read & modify 1000Base-T control register */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTCR, &gbaseTC, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
gbaseTC |= GMII_1000BaseT_HALF_DUPLEX |GMII_1000BaseT_FULL_DUPLEX;
rc = GMACB_WritePhy(pHw, phyAddress, GMII_1000BTCR, gbaseTC, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Read & modify control register */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Restart Auto_negotiation */
value |= GMII_RESTART_AUTONEG;
rc = GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
TRACE_DEBUG(" _BMCR: 0x%X\n\r", value);
/* Check AutoNegotiate complete */
while (1)
{
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax);
if (rc == 0)
{
TRACE_ERROR("rc==0\n\r");
goto AutoNegotiateExit;
}
/* Done successfully */
if (value & GMII_AUTONEG_COMP)
{
printf("AutoNegotiate complete\n\r");
break;
}
/* Timeout check */
if (retryMax)
{
if (++ retryCount >= retryMax)
{
GMACB_DumpRegisters(pMacb);
TRACE_ERROR("TimeOut\n\r");
rc = 0;
goto AutoNegotiateExit;
}
}
}
/*Set local link mode */
while(1)
{
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &gbaseTS, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Setup the EMAC link speed */
if ((gbaseTS & GMII_LINKP_1000BaseT_FULL_DUPLEX) &&
(gbaseTC & GMII_1000BaseT_FULL_DUPLEX))
{
/* set RGMII for 1000BaseTX and Full Duplex */
duplex = GMAC_DUPLEX_FULL;
speed = GMAC_SPEED_1000M;
break;
}
else if ((gbaseTS & GMII_LINKP_1000BaseT_HALF_DUPLEX) &&
(gbaseTC & GMII_1000BaseT_HALF_DUPLEX))
{
/* set RGMII for 1000BaseT and Half Duplex*/
duplex = GMAC_DUPLEX_HALF;
speed = GMAC_SPEED_1000M;
break;
}
/* Get the AutoNeg Link partner base page */
rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &phyAnalpar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Setup the EMAC link speed */
if ((phyAnar & phyAnalpar) & GMII_TX_FDX)
{
/* set RGMII for 100BaseTX and Full Duplex */
duplex = GMAC_DUPLEX_FULL;
speed = GMAC_SPEED_100M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_10_FDX)
{
/* set RGMII for 10BaseT and Full Duplex */
duplex = GMAC_DUPLEX_FULL;
speed = GMAC_SPEED_10M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_TX_HDX)
{
/* set RGMII for 100BaseTX and half Duplex */
duplex = GMAC_DUPLEX_HALF;
speed = GMAC_SPEED_100M;
break;
}
else if ((phyAnar & phyAnalpar) & GMII_10_HDX)
{
/* set RGMII for 10BaseT and half Duplex */
duplex = GMAC_DUPLEX_HALF;
speed = GMAC_SPEED_10M;
break;
}
}
/* Setup GMAC mode */
GMAC_EnableRGMII(pHw, duplex, speed);
AutoNegotiateExit:
GMAC_DisableMdio(pHw);
return rc;
}

715
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacd.c Normal file
View file

@ -0,0 +1,715 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
#include <string.h>
/** \addtogroup gmacd_defines
@{*/
/*----------------------------------------------------------------------------
* Macro
*----------------------------------------------------------------------------*/
/** Return count in buffer */
#define GCIRC_CNT(head,tail,size) (((head) - (tail)) % (size))
/** Return space available, 0..size-1. always leave one free char as a completely full buffer
has head == tail, which is the same as empty */
#define GCIRC_SPACE(head,tail,size) GCIRC_CNT((tail),((head)+1),(size))
/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once,
so they can change underneath us without returning inconsistent results */
#define GCIRC_CNT_TO_END(head,tail,size) \
({int end = (size) - (tail); \
int n = ((head) + end) % (size); \
n < end ? n : end;})
/** Return space available up to the end of the buffer */
#define GCIRC_SPACE_TO_END(head,tail,size) \
({int end = (size) - 1 - (head); \
int n = (end + (tail)) % (size); \
n <= end ? n : end+1;})
/** Increment head or tail */
#define GCIRC_INC(headortail,size) \
headortail++; \
if(headortail >= size) { \
headortail = 0; \
}
/** Circular buffer is empty ? */
#define GCIRC_EMPTY(head, tail) (head == tail)
/** Clear circular buffer */
#define GCIRC_CLEAR(head, tail) (head = tail = 0)
//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------
/// The buffer addresses written into the descriptors must be aligned so the
/// last few bits are zero. These bits have special meaning for the GMAC
/// peripheral and cannot be used as part of the address.
#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)
#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask
// receive buffer descriptor bits
#define GMAC_RX_OWNERSHIP_BIT (1 << 0)
#define GMAC_RX_WRAP_BIT (1 << 1)
#define GMAC_RX_SOF_BIT (1 << 14)
#define GMAC_RX_EOF_BIT (1 << 15)
// Transmit buffer descriptor bits
#define GMAC_TX_LAST_BUFFER_BIT (1 << 15)
#define GMAC_TX_WRAP_BIT (1 << 30)
#define GMAC_TX_USED_BIT (1 << 31)
#define GMAC_TX_RLE_BIT (1 << 29) /// Retry Limit Exceeded
#define GMAC_TX_UND_BIT (1 << 28) /// Tx Buffer Underrun
#define GMAC_TX_ERR_BIT (1 << 27) /// Exhausted in mid-frame
#define GMAC_TX_ERR_BITS \
(GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
/*---------------------------------------------------------------------------
* Local functions
*---------------------------------------------------------------------------*/
/**
* \brief Disable TX & reset registers and descriptor list
* \param pDrv Pointer to GMAC Driver instance.
*/
static void GMACD_ResetTx(sGmacd *pDrv )
{
Gmac *pHw = pDrv->pHw;
uint8_t *pTxBuffer = pDrv->pTxBuffer;
sGmacTxDescriptor *pTd = pDrv->pTxD;
uint32_t Index;
uint32_t Address;
/* Disable TX */
GMAC_TransmitEnable(pHw, 0);
/* Setup the TX descriptors. */
GCIRC_CLEAR(pDrv->wTxHead, pDrv->wTxTail);
for(Index = 0; Index < pDrv->wTxListSize; Index++) {
Address = (uint32_t)(&(pTxBuffer[Index * GMAC_TX_UNITSIZE]));
pTd[Index].addr = Address;
pTd[Index].status.val = (uint32_t)GMAC_TX_USED_BIT;
}
pTd[pDrv->wTxListSize - 1].status.val = GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT;
/* Transmit Buffer Queue Pointer Register */
GMAC_SetTxQueue(pHw, (uint32_t)pTd);
}
/**
* \brief Disable RX & reset registers and descriptor list
* \param pDrv Pointer to GMAC Driver instance.
*/
static void GMACD_ResetRx(sGmacd *pDrv )
{
Gmac *pHw = pDrv->pHw;
uint8_t *pRxBuffer = pDrv->pRxBuffer;
sGmacRxDescriptor *pRd = pDrv->pRxD;
uint32_t Index;
uint32_t Address;
/* Disable RX */
GMAC_ReceiveEnable(pHw, 0);
/* Setup the RX descriptors. */
pDrv->wRxI = 0;
for(Index = 0; Index < pDrv->wRxListSize; Index++)
{
Address = (uint32_t)(&(pRxBuffer[Index * GMAC_RX_UNITSIZE]));
/* Remove GMAC_RXD_bmOWNERSHIP and GMAC_RXD_bmWRAP */
pRd[Index].addr.val = Address & GMAC_ADDRESS_MASK;
pRd[Index].status.val = 0;
}
pRd[pDrv->wRxListSize - 1].addr.val |= GMAC_RX_WRAP_BIT;
/* Receive Buffer Queue Pointer Register */
GMAC_SetRxQueue(pHw, (uint32_t) pRd);
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* \brief GMAC Interrupt handler
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Handler(sGmacd *pGmacd )
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
fGmacdTransferCallback *pTxCb = NULL;
uint32_t isr;
uint32_t rsr;
uint32_t tsr;
uint32_t rxStatusFlag;
uint32_t txStatusFlag;
isr = GMAC_GetItStatus(pHw);
rsr = GMAC_GetRxStatus(pHw);
tsr = GMAC_GetTxStatus(pHw);
isr &= ~(GMAC_GetItMask(pHw)| 0xF8030300);
/* RX packet */
if ((isr & GMAC_ISR_RCOMP) || (rsr & GMAC_RSR_REC)) {
asm("nop");
rxStatusFlag = GMAC_RSR_REC;
/* Frame received */
/* Check OVR */
if (rsr & GMAC_RSR_RXOVR) {
rxStatusFlag |= GMAC_RSR_RXOVR;
}
/* Check BNA */
if (rsr & GMAC_RSR_BNA) {
rxStatusFlag |= GMAC_RSR_BNA;
}
/* Check HNO */
if (rsr & GMAC_RSR_HNO) {
rxStatusFlag |= GMAC_RSR_HNO;
}
/* Clear status */
GMAC_ClearRxStatus(pHw, rxStatusFlag);
/* Invoke callbacks */
if (pGmacd->fRxCb)
{
pGmacd->fRxCb(rxStatusFlag);
}
}
/* TX packet */
if ((isr & GMAC_ISR_TCOMP) || (tsr & GMAC_TSR_TXCOMP)) {
asm("nop");
txStatusFlag = GMAC_TSR_TXCOMP;
/* A frame transmitted Check RLE */
if (tsr & GMAC_TSR_RLE) {
/* Status RLE & Number of discarded buffers */
txStatusFlag = GMAC_TSR_RLE
| GCIRC_CNT(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize);
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
GMACD_ResetTx(pGmacd);
TRACE_INFO("Tx RLE!!\n\r");
GMAC_TransmitEnable(pHw, 1);
}
/* Check COL */
if (tsr & GMAC_TSR_COL) {
txStatusFlag |= GMAC_TSR_COL;
}
/* Check TFC */
if (tsr & GMAC_TSR_TFC) {
txStatusFlag |= GMAC_TSR_TFC;
}
/* Check UND */
if (tsr & GMAC_TSR_UND) {
txStatusFlag |= GMAC_TSR_UND;
}
/* Check HRESP */
if (tsr & GMAC_TSR_HRESP) {
txStatusFlag |= GMAC_TSR_HRESP;
}
/* Check LCO */
if (tsr & GMAC_TSR_LCO) {
txStatusFlag |= GMAC_TSR_LCO;
}
/* Clear status */
GMAC_ClearTxStatus(pHw, txStatusFlag);
if (!GCIRC_EMPTY(pGmacd->wTxHead, pGmacd->wTxTail))
{
/* Check the buffers */
do {
pTxTd = &pGmacd->pTxD[pGmacd->wTxTail];
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
/* Exit if buffer has not been sent yet */
if ((pTxTd->status.val & (uint32_t)GMAC_TX_USED_BIT) == 0) {
break;
}
/* Notify upper layer that a packet has been sent */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
GCIRC_INC( pGmacd->wTxTail, pGmacd->wTxListSize );
} while (GCIRC_CNT(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize));
}
if (tsr & GMAC_TSR_RLE) {
/* Notify upper layer RLE */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
}
/* If a wakeup has been scheduled, notify upper layer that it can
send other packets, send will be successfull. */
if((GCIRC_SPACE(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize) >= pGmacd->bWakeupThreshold) && pGmacd->fWakupCb)
{
pGmacd->fWakupCb();
}
}
/* PAUSE Frame */
if (isr & GMAC_ISR_PFNZ) TRACE_INFO("Pause!\n\r");
if (isr & GMAC_ISR_PTZ) TRACE_INFO("Pause TO!\n\r");
}
/**
* \brief Initialize the GMAC with the Gmac controller address
* \param pGmacd Pointer to GMAC Driver instance.
* \param pHw Pointer to HW address for registers.
* \param bID HW ID for power management
* \param enableCAF Enable/Disable CopyAllFrame.
* \param enableNBC Enable/Disable NoBroadCast.
*/
void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC )
{
uint32_t dwNcfgr;
/* Check parameters */
assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);
TRACE_DEBUG("GMAC_Init\n\r");
/* Initialize struct */
pGmacd->pHw = pHw;
pGmacd->bId = bID;
/* Power ON */
PMC_EnablePeripheral(bID);
/* Disable TX & RX and more */
GMAC_NetworkControl(pHw, 0);
GMAC_DisableIt(pHw, ~0u);
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_UND | GMAC_TSR_HRESP | GMAC_TSR_LCO);
/* Clear interrupts */
GMAC_GetItStatus(pHw);
/* Enable the copy of data into the buffers
ignore broadcasts, and don't copy FCS. */
dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_GBE | GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_64;
if( enableCAF ) {
dwNcfgr |= GMAC_NCFGR_CAF;
}
if( enableNBC ) {
dwNcfgr |= GMAC_NCFGR_NBC;
}
GMAC_Configure(pHw, dwNcfgr);
}
/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* GMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* GMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,
uint16_t wTxSize)
{
Gmac *pHw = pGmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) )
{
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pGmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pGmacd->pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pGmacd->wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) )
{
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pGmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pGmacd->pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pGmacd->wTxListSize = wTxSize;
pGmacd->fTxCbList = pTxCb;
/* Reset TX & RX */
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
/* Enable Rx and Tx, plus the stats register. */
GMAC_TransmitEnable(pHw, 1);
GMAC_ReceiveEnable(pHw, 1);
GMAC_StatisticsWriteEnable(pHw, 1);
/* Setup the interrupts for TX (and errors) */
GMAC_EnableIt(pHw, GMAC_IER_MFS
|GMAC_IER_RCOMP
|GMAC_IER_RXUBR
|GMAC_IER_TXUBR
|GMAC_IER_TUR
|GMAC_IER_RLEX
|GMAC_IER_TFC
|GMAC_IER_TCOMP
|GMAC_IER_ROVR
|GMAC_IER_HRESP
|GMAC_IER_PFNZ
|GMAC_IER_PTZ
|GMAC_IER_PFTR
|GMAC_IER_EXINT
|GMAC_IER_DRQFR
|GMAC_IER_SFR
|GMAC_IER_DRQFT
|GMAC_IER_SFT
|GMAC_IER_PDRQFR
|GMAC_IER_PDRSFR
|GMAC_IER_PDRQFT
|GMAC_IER_PDRSFT);
//0x03FCFCFF
return GMACD_OK;
}
/**
* Reset TX & RX queue & statistics
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Reset(sGmacd *pGmacd)
{
Gmac *pHw = pGmacd->pHw;
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
//memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats));
GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN
| GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
}
/**
* \brief Send a packet with GMAC. If the packet size is larger than transfer buffer size
* error returned. If packet transfer status is monitored, specify callback for each packet.
* \param pGmacd Pointer to GMAC Driver instance.
* \param buffer The buffer to be send
* \param size The size of buffer to be send
* \param fGMAC_TxCallback Threshold Wakeup callback
* \param fWakeUpCb TX Wakeup
* \return OK, Busy or invalid packet
*/
uint8_t GMACD_Send(sGmacd *pGmacd,
void *pBuffer,
uint32_t size,
fGmacdTransferCallback fTxCb )
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
volatile fGmacdTransferCallback *pfTxCb;
TRACE_DEBUG("GMAC_Send\n\r");
/* Check parameter */
if (size > GMAC_TX_UNITSIZE) {
TRACE_ERROR("GMAC driver does not split send packets.");
return GMACD_PARAM;
}
/* Pointers to the current TxTd */
pTxTd = &pGmacd->pTxD[pGmacd->wTxHead];
/* If no free TxTd, buffer can't be sent */
if( GCIRC_SPACE(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize) == 0)
return GMACD_TX_BUSY;
/* Pointers to the current Tx Callback */
pfTxCb = &pGmacd->fTxCbList[pGmacd->wTxHead];
/* Sanity check */
/* Setup/Copy data to transmition buffer */
if (pBuffer && size) {
// Driver manage the ring buffer
memcpy((void *)pTxTd->addr, pBuffer, size);
}
/* Tx Callback */
*pfTxCb = fTxCb;
/* Update TD status. The buffer size defined is length of ethernet frame
so it's always the last buffer of the frame. */
if (pGmacd->wTxHead == pGmacd->wTxListSize-1) {
pTxTd->status.val =
(size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT | GMAC_TX_WRAP_BIT;
}
else {
pTxTd->status.val = (size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT;
}
GCIRC_INC(pGmacd->wTxHead, pGmacd->wTxListSize);
//CP15_flush_dcache_for_dma ((uint32_t)(pTxTd), ((uint32_t)(pTxTd) + sizeof(pTxTd)));
/* Tx packets count */
/* Now start to transmit if it is not already done */
GMAC_TransmissionStart(pHw);
return GMACD_OK;
}
/**
* Return current load of TX.
* \param pGmacd Pointer to GMAC Driver instance.
*/
uint32_t GMACD_TxLoad(sGmacd *pGmacd)
{
uint16_t head = pGmacd->wTxHead;
uint16_t tail = pGmacd->wTxTail;
return GCIRC_CNT(head, tail, pGmacd->wTxListSize);
}
/**
* \brief Receive a packet with GMAC.
* If not enough buffer for the packet, the remaining data is lost but right
* frame length is returned.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pFrame Buffer to store the frame
* \param frameSize Size of the frame
* \param pRcvSize Received size
* \return OK, no data, or frame too small
*/
uint8_t GMACD_Poll(sGmacd * pGmacd,
uint8_t *pFrame,
uint32_t frameSize,
uint32_t *pRcvSize)
{
uint16_t bufferLength;
uint32_t tmpFrameSize = 0;
uint8_t *pTmpFrame = 0;
uint32_t tmpIdx = pGmacd->wRxI;
volatile sGmacRxDescriptor *pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
uint8_t isFrame = 0;
if (pFrame == NULL) return GMACD_PARAM;
/* Set the default return value */
*pRcvSize = 0;
/* Process received RxTd */
while ((pRxTd->addr.val & GMAC_RX_OWNERSHIP_BIT) == GMAC_RX_OWNERSHIP_BIT)
{
/* A start of frame has been received, discard previous fragments */
if ((pRxTd->status.val & GMAC_RX_SOF_BIT) == GMAC_RX_SOF_BIT)
{
/* Skip previous fragment */
while (tmpIdx != pGmacd->wRxI)
{
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
}
pTmpFrame = pFrame;
tmpFrameSize = 0;
/* Start to gather buffers in a frame */
isFrame = 1;
}
/* Increment the pointer */
GCIRC_INC(tmpIdx, pGmacd->wRxListSize);
asm("nop");
/* Copy data in the frame buffer */
if (isFrame) {
if (tmpIdx == pGmacd->wRxI)
{
TRACE_INFO("no EOF (Invalid of buffers too small)\n\r");
do {
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
} while(tmpIdx != pGmacd->wRxI);
return GMACD_RX_NULL;
}
/* Copy the buffer into the application frame */
bufferLength = GMAC_RX_UNITSIZE;
if ((tmpFrameSize + bufferLength) > frameSize)
{
bufferLength = frameSize - tmpFrameSize;
}
memcpy(pTmpFrame, (void*)(pRxTd->addr.val & GMAC_ADDRESS_MASK), bufferLength);
pTmpFrame += bufferLength;
tmpFrameSize += bufferLength;
/* An end of frame has been received, return the data */
if ((pRxTd->status.val & GMAC_RX_EOF_BIT) == GMAC_RX_EOF_BIT)
{
/* Frame size from the GMAC */
*pRcvSize = (pRxTd->status.val & GMAC_LENGTH_FRAME);
/* Application frame buffer is too small all data have not been copied */
if (tmpFrameSize < *pRcvSize) {
return GMACD_SIZE_TOO_SMALL;
}
TRACE_DEBUG("packet %d-%d (%d)\n\r", pGmacd->wRxI, tmpIdx, *pRcvSize);
/* All data have been copied in the application frame buffer => release TD */
while (pGmacd->wRxI != tmpIdx)
{
pRxTd = &pGmacd->pRxD[pGmacd->wRxI];
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize);
}
return GMACD_OK;
}
}
/* SOF has not been detected, skip the fragment */
else {
pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT);
pGmacd->wRxI = tmpIdx;
}
/* Process the next buffer */
pRxTd = &pGmacd->pRxD[tmpIdx];
}
return GMACD_RX_NULL;
}
/**
* \brief Registers pRxCb callback. Callback will be invoked after the next received
* frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task call GMAC_Set_RxCb()
* to register pRxCb() callback and enters suspend state. The callback is in charge
* to resume the task once a new frame has been received. The next time GMAC_Poll()
* is called, it will be successfull.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxCb Pointer to callback function
* \return OK, no data, or frame too small
*/
void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb)
{
Gmac *pHw = pGmacd->pHw;
if (fRxCb == NULL)
{
GMAC_DisableIt(pHw, GMAC_IDR_RCOMP);
pGmacd->fRxCb = NULL;
}
else
{
pGmacd->fRxCb = fRxCb;
GMAC_EnableIt(pHw, GMAC_IER_RCOMP);
}
}
/**
* Register/Clear TX wakeup callback.
*
* When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application
* task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and
* enters suspend state. The callback is in charge to resume the task once
* several TD have been released. The next time GMACD_Send() will be called,
* it shall be successfull.
*
* This function is usually invoked with NULL callback from the TX wakeup
* callback itself, to unregister. Once the callback has resumed the
* application task, there is no need to invoke the callback again.
*
* \param pGmacd Pointer to GMAC Driver instance.
* \param fWakeup Wakeup callback.
* \param bThreshould Number of free TD before wakeup callback invoked.
* \return GMACD_OK, GMACD_PARAM on parameter error.
*/
uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd,
fGmacdWakeupCallback fWakeup,
uint8_t bThreshold)
{
if (fWakeup == NULL)
{
pGmacd->fWakupCb = NULL;
}
else
{
if (bThreshold <= pGmacd->wTxListSize)
{
pGmacd->fWakupCb = fWakeup;
pGmacd->bWakeupThreshold = bThreshold;
}
else
{
return GMACD_PARAM;
}
}
return GMACD_OK;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Internal function
*----------------------------------------------------------------------------*/
/**
* Counts and return the number of bits set to '1' in the given byte.
* \param byte Byte to count.
*/
static uint8_t CountBitsInByte(uint8_t byte)
{
uint8_t count = 0;
while (byte > 0)
{
if (byte & 1)
{
count++;
}
byte >>= 1;
}
return count;
}
/**
* Counts and return the number of bits set to '1' in the given hamming code.
* \param code Hamming code.
*/
static uint8_t CountBitsInCode256(uint8_t *code)
{
return CountBitsInByte(code[0]) + CountBitsInByte(code[1]) + CountBitsInByte(code[2]);
}
/**
* Calculates the 22-bit hamming code for a 256-bytes block of data.
* \param data Data buffer to calculate code for.
* \param code Pointer to a buffer where the code should be stored.
*/
static void Compute256(const uint8_t *data, uint8_t *code)
{
uint32_t i;
uint8_t columnSum = 0;
uint8_t evenLineCode = 0;
uint8_t oddLineCode = 0;
uint8_t evenColumnCode = 0;
uint8_t oddColumnCode = 0;
// Xor all bytes together to get the column sum;
// At the same time, calculate the even and odd line codes
for (i=0; i < 256; i++)
{
columnSum ^= data[i];
// If the xor sum of the byte is 0, then this byte has no incidence on
// the computed code; so check if the sum is 1.
if ((CountBitsInByte(data[i]) & 1) == 1)
{
// Parity groups are formed by forcing a particular index bit to 0
// (even) or 1 (odd).
// Example on one byte:
//
// bits (dec) 7 6 5 4 3 2 1 0
// (bin) 111 110 101 100 011 010 001 000
// '---'---'---'----------.
// |
// groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |
// P2' ooooooo eeeeeee ooooooo eeeeeee P2 |
// P1' ooo eee ooo eee ooo eee ooo eee P1 |
// |
// We can see that: |
// - P4 -> bit 2 of index is 0 --------------------'
// - P4' -> bit 2 of index is 1.
// - P2 -> bit 1 of index if 0.
// - etc...
// We deduce that a bit position has an impact on all even Px if
// the log2(x)nth bit of its index is 0
// ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
// and on all odd Px' if the log2(x)nth bit of its index is 1
// ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
//
// As such, we calculate all the possible Px and Px' values at the
// same time in two variables, evenLineCode and oddLineCode, such as
// evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1
// oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1'
//
evenLineCode ^= (255 - i);
oddLineCode ^= i;
}
}
// At this point, we have the line parities, and the column sum. First, We
// must caculate the parity group values on the column sum.
for (i=0; i < 8; i++)
{
if (columnSum & 1)
{
evenColumnCode ^= (7 - i);
oddColumnCode ^= i;
}
columnSum >>= 1;
}
// Now, we must interleave the parity values, to obtain the following layout:
// Code[0] = Line1
// Code[1] = Line2
// Code[2] = Column
// Line = Px' Px P(x-1)- P(x-1) ...
// Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
code[0] = 0;
code[1] = 0;
code[2] = 0;
for (i=0; i < 4; i++)
{
code[0] <<= 2;
code[1] <<= 2;
code[2] <<= 2;
// Line 1
if ((oddLineCode & 0x80) != 0)
{
code[0] |= 2;
}
if ((evenLineCode & 0x80) != 0)
{
code[0] |= 1;
}
// Line 2
if ((oddLineCode & 0x08) != 0)
{
code[1] |= 2;
}
if ((evenLineCode & 0x08) != 0)
{
code[1] |= 1;
}
// Column
if ((oddColumnCode & 0x04) != 0)
{
code[2] |= 2;
}
if ((evenColumnCode & 0x04) != 0)
{
code[2] |= 1;
}
oddLineCode <<= 1;
evenLineCode <<= 1;
oddColumnCode <<= 1;
evenColumnCode <<= 1;
}
// Invert codes (linux compatibility)
code[0] = (~(uint32_t)code[0]);
code[1] = (~(uint32_t)code[1]);
code[2] = (~(uint32_t)code[2]);
TRACE_DEBUG("Computed code = %02X %02X %02X\n\r",
code[0], code[1], code[2]);
}
/**
* Verifies and corrects a 256-bytes block of data using the given 22-bits
* hamming code.
*
* \param data Data buffer to check.
* \param originalCode Hamming code to use for verifying the data.
*
* \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.
*/
static uint8_t Verify256( uint8_t* pucData, const uint8_t* pucOriginalCode )
{
/* Calculate new code */
uint8_t computedCode[3] ;
uint8_t correctionCode[3] ;
Compute256( pucData, computedCode ) ;
/* Xor both codes together */
correctionCode[0] = computedCode[0] ^ pucOriginalCode[0] ;
correctionCode[1] = computedCode[1] ^ pucOriginalCode[1] ;
correctionCode[2] = computedCode[2] ^ pucOriginalCode[2] ;
TRACE_DEBUG( "Correction code = %02X %02X %02X\n\r", correctionCode[0], correctionCode[1], correctionCode[2] ) ;
// If all bytes are 0, there is no error
if ( (correctionCode[0] == 0) && (correctionCode[1] == 0) && (correctionCode[2] == 0) )
{
return 0 ;
}
/* If there is a single bit error, there are 11 bits set to 1 */
if ( CountBitsInCode256( correctionCode ) == 11 )
{
// Get byte and bit indexes
uint8_t byte = correctionCode[0] & 0x80;
byte |= (correctionCode[0] << 1) & 0x40;
byte |= (correctionCode[0] << 2) & 0x20;
byte |= (correctionCode[0] << 3) & 0x10;
byte |= (correctionCode[1] >> 4) & 0x08;
byte |= (correctionCode[1] >> 3) & 0x04;
byte |= (correctionCode[1] >> 2) & 0x02;
byte |= (correctionCode[1] >> 1) & 0x01;
uint8_t bit = (correctionCode[2] >> 5) & 0x04;
bit |= (correctionCode[2] >> 4) & 0x02;
bit |= (correctionCode[2] >> 3) & 0x01;
/* Correct bit */
printf("Correcting byte #%d at bit %d\n\r", byte, bit ) ;
pucData[byte] ^= (1 << bit) ;
return Hamming_ERROR_SINGLEBIT ;
}
/* Check if ECC has been corrupted */
if ( CountBitsInCode256( correctionCode ) == 1 )
{
return Hamming_ERROR_ECC ;
}
/* Otherwise, this is a multi-bit error */
else
{
return Hamming_ERROR_MULTIPLEBITS ;
}
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Computes 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256 bytes block gets its own code.
* \param data Data to compute code for.
* \param size Data size in bytes.
* \param code Codes buffer.
*/
void Hamming_Compute256x( const uint8_t *pucData, uint32_t dwSize, uint8_t* puCode )
{
TRACE_DEBUG("Hamming_Compute256x()\n\r");
while ( dwSize > 0 )
{
Compute256( pucData, puCode ) ;
pucData += 256;
puCode += 3;
dwSize -= 256;
}
}
/**
* Verifies 3-bytes hamming codes for a data block whose size is multiple of
* 256 bytes. Each 256-bytes block is verified with its own code.
*
* \return 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more
* block(s) have had a single bit corrected, or either Hamming_ERROR_ECC
* or Hamming_ERROR_MULTIPLEBITS.
*
* \param data Data buffer to verify.
* \param size Size of the data in bytes.
* \param code Original codes.
*/
uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode )
{
uint8_t error ;
uint8_t result = 0 ;
TRACE_DEBUG( "Hamming_Verify256x()\n\r" ) ;
while ( dwSize > 0 )
{
error = Verify256( pucData, pucCode ) ;
if ( error == Hamming_ERROR_SINGLEBIT )
{
result = Hamming_ERROR_SINGLEBIT ;
}
else
{
if ( error )
{
return error ;
}
}
pucData += 256;
pucCode += 3;
dwSize -= 256;
}
return result ;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* ISO 7816 driver
*
* \section Usage
*
* Explanation on the usage of the code made available through the header file.
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Definitions
*------------------------------------------------------------------------------*/
/** Case for APDU commands*/
#define CASE1 1
#define CASE2 2
#define CASE3 3
/** Flip flop for send and receive char */
#define USART_SEND 0
#define USART_RCV 1
#if !defined(BOARD_ISO7816_BASE_USART)
#define BOARD_ISO7816_BASE_USART USART1
#define BOARD_ISO7816_ID_USART ID_USART1
#endif
/*-----------------------------------------------------------------------------
* Internal variables
*-----------------------------------------------------------------------------*/
/** Variable for state of send and receive froom USART */
static uint8_t StateUsartGlobal = USART_RCV;
/** Pin reset master card */
static Pin st_pinIso7816RstMC;
/*----------------------------------------------------------------------------
* Internal functions
*----------------------------------------------------------------------------*/
/**
* Get a character from ISO7816
* \param pCharToReceive Pointer for store the received char
* \return 0: if timeout else status of US_CSR
*/
static uint32_t ISO7816_GetChar( uint8_t *pCharToReceive )
{
uint32_t status;
uint32_t timeout=0;
if( StateUsartGlobal == USART_SEND ) {
while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXEMPTY) == 0) {}
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
StateUsartGlobal = USART_RCV;
}
/* Wait USART ready for reception */
while( ((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_RXRDY) == 0) ) {
if(timeout++ > 12000 * (BOARD_MCK/1000000)) {
TRACE_DEBUG("TimeOut\n\r");
return( 0 );
}
}
TRACE_DEBUG("T: %u\n\r", timeout);
/* At least one complete character has been received and US_RHR has not yet been read. */
/* Get a char */
*pCharToReceive = ((BOARD_ISO7816_BASE_USART->US_RHR) & 0xFF);
status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME|
US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK|
(1<<10)));
if (status != 0 ) {
/* TRACE_DEBUG("R:0x%X\n\r", status); */
TRACE_DEBUG("R:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR);
TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER );
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA;
}
/* Return status */
return( status );
}
/**
* Send a char to ISO7816
* \param CharToSend char to be send
* \return status of US_CSR
*/
static uint32_t ISO7816_SendChar( uint8_t CharToSend )
{
uint32_t status;
if( StateUsartGlobal == USART_RCV ) {
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
StateUsartGlobal = USART_SEND;
}
/* Wait USART ready for transmit */
while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXRDY) == 0) {}
/* There is no character in the US_THR */
/* Transmit a char */
BOARD_ISO7816_BASE_USART->US_THR = CharToSend;
status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME|
US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK|
(1<<10)));
if (status != 0 ) {
TRACE_DEBUG("E:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR);
TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER );
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA;
}
/* Return status */
return( status );
}
/**
* Iso 7816 ICC power on
*/
static void ISO7816_IccPowerOn( void )
{
/* Set RESET Master Card */
PIO_Set(&st_pinIso7816RstMC);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Iso 7816 ICC power off
*/
void ISO7816_IccPowerOff( void )
{
/* Clear RESET Master Card */
PIO_Clear(&st_pinIso7816RstMC);
}
/**
* Transfert Block TPDU T=0
* \param pAPDU APDU buffer
* \param pMessage Message buffer
* \param wLength Block length
* \return Message index
*/
uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU,
uint8_t *pMessage,
uint16_t wLength )
{
uint16_t NeNc;
uint16_t indexApdu = 4;
uint16_t indexMessage = 0;
uint8_t SW1 = 0;
uint8_t procByte;
uint8_t cmdCase;
uint8_t ins;
TRACE_DEBUG("pAPDU[0]=0x%X\n\r",pAPDU[0]);
TRACE_DEBUG("pAPDU[1]=0x%X\n\r",pAPDU[1]);
TRACE_DEBUG("pAPDU[2]=0x%X\n\r",pAPDU[2]);
TRACE_DEBUG("pAPDU[3]=0x%X\n\r",pAPDU[3]);
TRACE_DEBUG("pAPDU[4]=0x%X\n\r",pAPDU[4]);
TRACE_DEBUG("pAPDU[5]=0x%X\n\r",pAPDU[5]);
TRACE_DEBUG("wlength=%d\n\r",wLength);
ISO7816_SendChar( pAPDU[0] ); /* CLA */
ISO7816_SendChar( pAPDU[1] ); /* INS */
ISO7816_SendChar( pAPDU[2] ); /* P1 */
ISO7816_SendChar( pAPDU[3] ); /* P2 */
ISO7816_SendChar( pAPDU[4] ); /* P3 */
/* Handle the four structures of command APDU */
indexApdu = 4;
if( wLength == 4 ) {
cmdCase = CASE1;
NeNc = 0;
}
else if( wLength == 5) {
cmdCase = CASE2;
NeNc = pAPDU[4]; /* C5 */
if (NeNc == 0) {
NeNc = 256;
}
}
else if( wLength == 6) {
NeNc = pAPDU[4]; /* C5 */
cmdCase = CASE3;
}
else if( wLength == 7) {
NeNc = pAPDU[4]; /* C5 */
if( NeNc == 0 ) {
cmdCase = CASE2;
NeNc = (pAPDU[5]<<8)+pAPDU[6];
}
else {
cmdCase = CASE3;
}
}
else {
NeNc = pAPDU[4]; /* C5 */
if( NeNc == 0 ) {
cmdCase = CASE3;
NeNc = (pAPDU[5]<<8)+pAPDU[6];
}
else {
cmdCase = CASE3;
}
}
TRACE_DEBUG("CASE=0x%X NeNc=0x%X\n\r", cmdCase, NeNc);
/* Handle Procedure Bytes */
do {
ISO7816_GetChar(&procByte);
ins = procByte ^ 0xff;
/* Handle NULL */
if ( procByte == ISO_NULL_VAL ) {
TRACE_DEBUG("INS\n\r");
continue;
}
/* Handle SW1 */
else if ( ((procByte & 0xF0) ==0x60) || ((procByte & 0xF0) ==0x90) ) {
TRACE_DEBUG("SW1\n\r");
SW1 = 1;
}
/* Handle INS */
else if ( pAPDU[1] == procByte) {
TRACE_DEBUG("HdlINS\n\r");
if (cmdCase == CASE2) {
/* receive data from card */
do {
ISO7816_GetChar(&pMessage[indexMessage++]);
} while( 0 != --NeNc );
}
else {
/* Send data */
do {
ISO7816_SendChar(pAPDU[indexApdu++]);
} while( 0 != --NeNc );
}
}
/* Handle INS ^ 0xff */
else if ( pAPDU[1] == ins) {
TRACE_DEBUG("HdlINS+\n\r");
if (cmdCase == CASE2) {
/* receive data from card */
ISO7816_GetChar(&pMessage[indexMessage++]);
}
else {
ISO7816_SendChar(pAPDU[indexApdu++]);
}
NeNc--;
}
else {
/* ?? */
TRACE_DEBUG("procByte=0x%X\n\r", procByte);
break;
}
} while (NeNc != 0);
/* Status Bytes */
if (SW1 == 0) {
ISO7816_GetChar(&pMessage[indexMessage++]); /* SW1 */
}
else {
pMessage[indexMessage++] = procByte;
}
ISO7816_GetChar(&pMessage[indexMessage++]); /* SW2 */
return( indexMessage );
}
/**
* Escape ISO7816
*/
void ISO7816_Escape( void )
{
TRACE_DEBUG("For user, if needed\n\r");
}
/**
* Restart clock ISO7816
*/
void ISO7816_RestartClock( void )
{
TRACE_DEBUG("ISO7816_RestartClock\n\r");
BOARD_ISO7816_BASE_USART->US_BRGR = 13;
}
/**
* Stop clock ISO7816
*/
void ISO7816_StopClock( void )
{
TRACE_DEBUG("ISO7816_StopClock\n\r");
BOARD_ISO7816_BASE_USART->US_BRGR = 0;
}
/**
* T0 APDU
*/
void ISO7816_toAPDU( void )
{
TRACE_DEBUG("ISO7816_toAPDU\n\r");
TRACE_DEBUG("Not supported at this time\n\r");
}
/**
* Answer To Reset (ATR)
* \param pAtr ATR buffer
* \param pLength Pointer for store the ATR length
*/
void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength )
{
uint32_t i;
uint32_t j;
uint32_t y;
*pLength = 0;
/* Read ATR TS */
ISO7816_GetChar(&pAtr[0]);
/* Read ATR T0 */
ISO7816_GetChar(&pAtr[1]);
y = pAtr[1] & 0xF0;
i = 2;
/* Read ATR Ti */
while (y) {
if (y & 0x10) { /* TA[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x20) { /* TB[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x40) { /* TC[i] */
ISO7816_GetChar(&pAtr[i++]);
}
if (y & 0x80) { /* TD[i] */
ISO7816_GetChar(&pAtr[i]);
y = pAtr[i++] & 0xF0;
}
else {
y = 0;
}
}
/* Historical Bytes */
y = pAtr[1] & 0x0F;
for( j=0; j < y; j++ ) {
ISO7816_GetChar(&pAtr[i++]);
}
*pLength = i;
}
/**
* Set data rate and clock frequency
* \param dwClockFrequency ICC clock frequency in KHz.
* \param dwDataRate ICC data rate in bpd
*/
void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate )
{
uint8_t ClockFrequency;
/* Define the baud rate divisor register */
/* CD = MCK / SCK */
/* SCK = FIDI x BAUD = 372 x 9600 */
/* BOARD_MCK */
/* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */
BOARD_ISO7816_BASE_USART->US_BRGR = BOARD_MCK / (dwClockFrequency*1000);
ClockFrequency = BOARD_MCK / BOARD_ISO7816_BASE_USART->US_BRGR;
BOARD_ISO7816_BASE_USART->US_FIDI = (ClockFrequency)/dwDataRate;
}
/**
* Pin status for ISO7816 RESET
* \return 1 if the Pin RstMC is high; otherwise 0.
*/
uint8_t ISO7816_StatusReset( void )
{
return PIO_Get(&st_pinIso7816RstMC);
}
/**
* cold reset
*/
void ISO7816_cold_reset( void )
{
volatile uint32_t i;
/* tb: wait 400 cycles*/
for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) {
}
BOARD_ISO7816_BASE_USART->US_RHR;
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
ISO7816_IccPowerOn();
}
/**
* Warm reset
*/
void ISO7816_warm_reset( void )
{
volatile uint32_t i;
ISO7816_IccPowerOff();
/* tb: wait 400 cycles */
for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) {
}
BOARD_ISO7816_BASE_USART->US_RHR;
BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;
ISO7816_IccPowerOn();
}
/**
* Decode ATR trace
* \param pAtr pointer on ATR buffer
*/
void ISO7816_Decode_ATR( uint8_t* pAtr )
{
uint32_t i;
uint32_t j;
uint32_t y;
uint8_t offset;
printf("\n\r");
printf("ATR: Answer To Reset:\n\r");
printf("TS = 0x%X Initial character ",pAtr[0]);
if( pAtr[0] == 0x3B ) {
printf("Direct Convention\n\r");
}
else {
if( pAtr[0] == 0x3F ) {
printf("Inverse Convention\n\r");
}
else {
printf("BAD Convention\n\r");
}
}
printf("T0 = 0x%X Format caracter\n\r",pAtr[1]);
printf(" Number of historical bytes: K = %d\n\r", pAtr[1]&0x0F);
printf(" Presence further interface byte:\n\r");
if( pAtr[1]&0x80 ) {
printf("TA ");
}
if( pAtr[1]&0x40 ) {
printf("TB ");
}
if( pAtr[1]&0x20 ) {
printf("TC ");
}
if( pAtr[1]&0x10 ) {
printf("TD ");
}
if( pAtr[1] != 0 ) {
printf(" present\n\r");
}
i = 2;
y = pAtr[1] & 0xF0;
/* Read ATR Ti */
offset = 1;
while (y) {
if (y & 0x10) { /* TA[i] */
printf("TA[%d] = 0x%X ", offset, pAtr[i]);
if( offset == 1 ) {
printf("FI = %d ", (pAtr[i]>>8));
printf("DI = %d", (pAtr[i]&0x0F));
}
printf("\n\r");
i++;
}
if (y & 0x20) { /* TB[i] */
printf("TB[%d] = 0x%X\n\r", offset, pAtr[i]);
i++;
}
if (y & 0x40) { /* TC[i] */
printf("TC[%d] = 0x%X ", offset, pAtr[i]);
if( offset == 1 ) {
printf("Extra Guard Time: N = %d", pAtr[i]);
}
printf("\n\r");
i++;
}
if (y & 0x80) { /* TD[i] */
printf("TD[%d] = 0x%X\n\r", offset, pAtr[i]);
y = pAtr[i++] & 0xF0;
}
else {
y = 0;
}
offset++;
}
/* Historical Bytes */
printf("Historical bytes:\n\r");
y = pAtr[1] & 0x0F;
for( j=0; j < y; j++ ) {
printf(" 0x%X", pAtr[i]);
if( (pAtr[i] > 0x21) && (pAtr[i] < 0x7D) ) { /* ASCII */
printf("(%c) ", pAtr[i]);
}
i++;
}
printf("\n\r\n\r");
}
/** Initializes a ISO driver
* \param pPinIso7816RstMC Pin ISO 7816 Rst MC
*/
void ISO7816_Init( const Pin pPinIso7816RstMC )
{
TRACE_DEBUG("ISO_Init\n\r");
/* Pin ISO7816 initialize */
st_pinIso7816RstMC = pPinIso7816RstMC;
USART_Configure( BOARD_ISO7816_BASE_USART,
US_MR_USART_MODE_IS07816_T_0
| US_MR_USCLKS_MCK
| US_MR_NBSTOP_1_BIT
| US_MR_PAR_EVEN
| US_MR_CHRL_8_BIT
| US_MR_CLKO
| (3<<24), /* MAX_ITERATION */
1,
0);
/* Configure USART */
PMC_EnablePeripheral(BOARD_ISO7816_ID_USART);
/* Disable interrupts */
BOARD_ISO7816_BASE_USART->US_IDR = (uint32_t) -1;
BOARD_ISO7816_BASE_USART->US_FIDI = 372; /* by default */
/* Define the baud rate divisor register */
/* CD = MCK / SCK */
/* SCK = FIDI x BAUD = 372 x 9600 */
/* BOARD_MCK */
/* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */
BOARD_ISO7816_BASE_USART->US_BRGR = BOARD_MCK / (372*9600);
/* Write the Timeguard Register */
BOARD_ISO7816_BASE_USART->US_TTGR = 5;
USART_SetTransmitterEnabled(BOARD_ISO7816_BASE_USART, 1);
USART_SetReceiverEnabled(BOARD_ISO7816_BASE_USART, 1);
}

635
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_draw.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup lcdd_draw
*
* Implementation of draw function on LCD, Include draw text, image
* and basic shapes (line, rectangle, circle).
*
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
#include <string.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Local variable
*----------------------------------------------------------------------------*/
/** Front color cache */
static uint32_t dwFrontColor;
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* Hide canvas layer
*/
static void _HideCanvas(void)
{
//LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 0);
}
/**
* Update canvas
*/
static void _ShowCanvas(void)
{
//LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 1);
}
/**
* Set front color
* \param dwColor Pixel color.
*/
static void _SetFrontColor(uint32_t dwColor)
{
dwFrontColor = dwColor;
}
/**
* \brief Draw a pixel on LCD of front color.
*
* \param dwX X-coordinate of pixel.
* \param dwY Y-coordinate of pixel.
*/
static void _DrawPixel( uint32_t dwX, uint32_t dwY )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint8_t* buffer = pDisp->pBuffer;
uint16_t w = pDisp->wImgW;
//uint16_t h = pDisp->wImgH;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
//uint8_t r, g, b;
uint8_t *pPix;
if (buffer == NULL)
return;
if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */
pPix = &buffer[dwY * rw + cw * dwX];
switch (pDisp->bMode)
{
case 16: /* TRGB 1555 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
break;
case 24: /* RGB 888 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
pPix[2] = (dwFrontColor >> 16) & 0xFF;
break;
case 32: /* ARGB 8888 */
pPix[0] = (dwFrontColor ) & 0xFF;
pPix[1] = (dwFrontColor >> 8) & 0xFF;
pPix[2] = (dwFrontColor >> 16) & 0xFF;
pPix[3] = (dwFrontColor >> 24) & 0xFF;
break;
}
}
/**
* \brief Fill rectangle with front color.
* \param dwX1 X-coordinate of top left.
* \param dwY1 Y-coordinate of top left.
* \param dwX2 X-coordinate of bottom right.
* \param dwY1 Y-coordinate of bottom right.
*/
static void _FillRect( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint16_t w = pDisp->wImgW;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
uint8_t *base = pDisp->pBuffer;
uint8_t *buffer = pDisp->pBuffer;
uint32_t fillStart, fillEnd;
uint32_t i;
if (buffer == NULL) return;
/* 4-byte aligned rows */
if (rw & 0x3) rw = (rw | 0x3) + 1;
/* Buffer address for the starting row */
base = &buffer[dwY1*rw];
fillStart = dwX1 * cw;
fillEnd = dwX2 * cw;
#if 1 /* Memcopy pixel */
buffer = base;
for (; dwY1 <= dwY2; dwY1 ++)
{
for (i = fillStart; i <= fillEnd; i += cw)
{
memcpy(&buffer[i], &dwFrontColor, cw);
}
buffer = &buffer[rw];
}
#endif
#if 0 /* Pixel by pixel */
for (; dwY1 <= dwY2; dwY1 ++)
{
for (i = dwX1; i <= dwX2; i ++)
{
_DrawPixel(i, dwY1);
}
}
#endif
#if 0 /* Optimized */
/* First row */
for (i = fillStart; i <= fillEnd; i += cw)
{
memcpy(&base[i], &dwFrontColor, cw);
}
/* Next rows, copy first */
buffer = &base[rw + fillStart];
for (i = dwY1 + 1; i <= dwY2; i ++)
{
memcpy(buffer, &base[fillStart], fillEnd - fillStart + cw);
buffer = &buffer[rw];
}
#endif
}
/**
* \brief Draw a line on LCD, which is not horizontal or vertical.
*
* \param dwX1 X-coordinate of line start.
* \param dwY1 Y-coordinate of line start.
* \param dwX2 X-coordinate of line end.
* \param dwY2 Y-coordinate of line end.
*/
static uint32_t _DrawLineBresenham( uint32_t dwX1, uint32_t dwY1,
uint32_t dwX2, uint32_t dwY2 )
{
int dx, dy ;
int i ;
int xinc, yinc, cumul ;
int x, y ;
x = dwX1 ;
y = dwY1 ;
dx = dwX2 - dwX1 ;
dy = dwY2 - dwY1 ;
xinc = ( dx > 0 ) ? 1 : -1 ;
yinc = ( dy > 0 ) ? 1 : -1 ;
dx = ( dx > 0 ) ? dx : -dx ;
dy = ( dy > 0 ) ? dy : -dy ;
_DrawPixel( x, y ) ;
if ( dx > dy )
{
cumul = dx / 2 ;
for ( i = 1 ; i <= dx ; i++ )
{
x += xinc ;
cumul += dy ;
if ( cumul >= dx )
{
cumul -= dx ;
y += yinc ;
}
_DrawPixel( x, y ) ;
}
}
else
{
cumul = dy / 2 ;
for ( i = 1 ; i <= dy ; i++ )
{
y += yinc ;
cumul += dx ;
if ( cumul >= dy )
{
cumul -= dy ;
x += xinc ;
}
_DrawPixel( x, y ) ;
}
}
return 0 ;
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Fills the given LCD buffer with a particular color.
*
* \param color Fill color.
*/
void LCDD_Fill( uint32_t dwColor )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect( 0, 0, pDisp->wImgW, pDisp->wImgH );
_ShowCanvas();
}
void LCDD_Fill0(void)
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
_HideCanvas();
_SetFrontColor(0xFF0000);
_FillRect( 0, 0, pDisp->wImgW/3, pDisp->wImgH );
_SetFrontColor(0x00FF00);
_FillRect( pDisp->wImgW/3, 0, pDisp->wImgW/3+pDisp->wImgW/3, pDisp->wImgH );
_SetFrontColor(0x0000FF);
_FillRect( pDisp->wImgW/3+pDisp->wImgW/3, 0, pDisp->wImgW, pDisp->wImgH );
_ShowCanvas();
}
/**
* \brief Draw a pixel on LCD of given color.
*
* \param x X-coordinate of pixel.
* \param y Y-coordinate of pixel.
* \param color Pixel color.
*/
extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t color )
{
_SetFrontColor(color);
_HideCanvas();
_DrawPixel(x, y);
_ShowCanvas();
}
/**
* \brief Read a pixel from LCD.
*
* \param x X-coordinate of pixel.
* \param y Y-coordinate of pixel.
*
* \return color Readed pixel color.
*/
extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint8_t* buffer = pDisp->pBuffer;
uint16_t w = pDisp->wImgW;
//uint16_t h = pDisp->wImgH;
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = w * cw; /* row width in bytes */
uint8_t *pPix;
uint32_t color = 0;
if (buffer == NULL) return 0;
if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */
pPix = &buffer[x * rw + cw * y];
switch (pDisp->bMode)
{
case 16: /* TRGB 1555 */
color = pPix[0] | (pPix[1] << 8);
break;
case 24: /* RGB 888 */
color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16);
break;
case 32: /* ARGB 8888 */
color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16) | (pPix[3] << 24);
break;
}
return color;
}
/**
* \brief Draw a line on LCD, horizontal and vertical line are supported.
*
* \param x1 X-coordinate of line start.
* \param y1 Y-coordinate of line start.
* \param x2 X-coordinate of line end.
* \param y2 Y-coordinate of line end.
* \param color Pixel color.
*/
extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color )
{
_SetFrontColor(color);
if ( (x1 == x2) || (y1 == y2) )
{
LCDD_DrawFilledRectangle(x1, y1, x2, y2, color);
}
else
{
_HideCanvas();
_DrawLineBresenham(x1, y1, x2, y2);
_ShowCanvas();
}
}
/**
* \brief Draws a rectangle on LCD, at the given coordinates.
*
* \param x X-coordinate of upper-left rectangle corner.
* \param y Y-coordinate of upper-left rectangle corner.
* \param width Rectangle width in pixels.
* \param height Rectangle height in pixels.
* \param color Rectangle color.
*/
extern void LCDD_DrawRectangle( uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t color )
{
uint32_t x1 = x + width - 1;
uint32_t y1 = y + height - 1;
_SetFrontColor(color);
_HideCanvas();
_FillRect(x , y , x1, y );
_FillRect(x1, y , x1, y1);
_FillRect(x , y , x , y1);
_FillRect(x , y1, x1, y1);
_ShowCanvas();
}
/**
* \brief Draws a rectangle with fill inside on LCD, at the given coordinates.
*
* \param dwX1 X-coordinate of upper-left rectangle corner.
* \param dwY1 Y-coordinate of upper-left rectangle corner.
* \param dwX2 X-coordinate of down-right rectangle corner.
* \param dwY2 Y-coordinate of down-right rectangle corner.
* \param color Rectangle color.
*/
extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1,
uint32_t dwX2, uint32_t dwY2,
uint32_t dwColor )
{
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect(dwX1, dwY1, dwX2, dwY2);
_ShowCanvas();
}
/**
* \brief Draws a circle on LCD, at the given coordinates.
*
* \param dwX X-coordinate of circle center.
* \param dwY Y-coordinate of circle center.
* \param dwR circle radius.
* \param dwColor circle color.
*/
extern void LCDD_DrawCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor )
{
int32_t d; /* Decision Variable */
uint32_t curX; /* Current X Value */
uint32_t curY; /* Current Y Value */
if (dwR == 0) return;
_SetFrontColor(dwColor);
d = 3 - (dwR << 1);
curX = 0;
curY = dwR;
_HideCanvas();
while (curX <= curY)
{
_DrawPixel(dwX + curX, dwY + curY);
_DrawPixel(dwX + curX, dwY - curY);
_DrawPixel(dwX - curX, dwY + curY);
_DrawPixel(dwX - curX, dwY - curY);
_DrawPixel(dwX + curY, dwY + curX);
_DrawPixel(dwX + curY, dwY - curX);
_DrawPixel(dwX - curY, dwY + curX);
_DrawPixel(dwX - curY, dwY - curX);
if (d < 0) {
d += (curX << 2) + 6;
}
else {
d += ((curX - curY) << 2) + 10;
curY--;
}
curX++;
}
_ShowCanvas();
}
/**
* \brief Draws a filled circle on LCD, at the given coordinates.
*
* \param dwX X-coordinate of circle center.
* \param dwY Y-coordinate of circle center.
* \param dwR circle radius.
* \param dwColor circle color.
*/
void LCDD_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor )
{
signed int d ; // Decision Variable
uint32_t dwCurX ; // Current X Value
uint32_t dwCurY ; // Current Y Value
uint32_t dwXmin, dwYmin;
if (dwR == 0) return;
_SetFrontColor(dwColor);
d = 3 - (dwR << 1) ;
dwCurX = 0 ;
dwCurY = dwR ;
_HideCanvas();
while ( dwCurX <= dwCurY )
{
dwXmin = (dwCurX > dwX) ? 0 : dwX-dwCurX;
dwYmin = (dwCurY > dwY) ? 0 : dwY-dwCurY;
_FillRect( dwXmin, dwYmin, dwX+dwCurX, dwYmin ) ;
_FillRect( dwXmin, dwY+dwCurY, dwX+dwCurX, dwY+dwCurY ) ;
dwXmin = (dwCurY > dwX) ? 0 : dwX-dwCurY;
dwYmin = (dwCurX > dwY) ? 0 : dwY-dwCurX;
_FillRect( dwXmin, dwYmin, dwX+dwCurY, dwYmin ) ;
_FillRect( dwXmin, dwY+dwCurX, dwX+dwCurY, dwY+dwCurX ) ;
if ( d < 0 )
{
d += (dwCurX << 2) + 6 ;
}
else
{
d += ((dwCurX - dwCurY) << 2) + 10;
dwCurY-- ;
}
dwCurX++ ;
}
_ShowCanvas();
}
/**
* \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks
* will be honored.
*
* \param x X-coordinate of string top-left corner.
* \param y Y-coordinate of string top-left corner.
* \param pString String to display.
* \param color String color.
*/
extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color )
{
uint32_t xorg = x;
while (*pString)
{
if (*pString == '\n')
{
y += gFont.height + 2; x = xorg;
}
else
{
LCDD_DrawChar(x, y, *pString, color);
x += gFont.width + 2;
}
pString ++;
}
}
/**
* \brief Draws a string inside a LCD buffer, at the given coordinates
* with given background color. Line breaks will be honored.
*
* \param x X-coordinate of string top-left corner.
* \param y Y-coordinate of string top-left corner.
* \param pString String to display.
* \param fontColor String color.
* \param bgColor Background color.
*/
extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor )
{
uint32_t xorg = x;
while (*pString)
{
if (*pString == '\n')
{
y += gFont.height + 2; x = xorg;
}
else
{
LCDD_DrawCharWithBGColor(x, y, *pString, fontColor, bgColor);
x += gFont.width + 2;
}
pString ++;
}
}
/**
* \brief Returns the width & height in pixels that a string will occupy on the screen
* if drawn using LCDD_DrawString.
*
* \param pString String.
* \param pWidth Pointer for storing the string width (optional).
* \param pHeight Pointer for storing the string height (optional).
*
* \return String width in pixels.
*/
extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight )
{
uint32_t width = 0;
uint32_t height = gFont.height;
while (*pString)
{
if (*pString == '\n') height += gFont.height + 2;
else width += gFont.height + 2;
pString ++;
}
if (width > 0) width -= 2;
if (pWidth) *pWidth = width;
if (pHeight)*pHeight = height;
}
/**
* \brief Draw a raw image at given position on LCD.
*
* \param x X-coordinate of image start.
* \param y Y-coordinate of image start.
* \param pImage Image buffer.
* \param width Image width.
* \param height Image height.
*/
void LCDD_DrawImage( uint32_t dwX, uint32_t dwY, const uint8_t *pImage, uint32_t dwWidth, uint32_t dwHeight )
{
sLCDDLayer *pDisp = LCDD_GetCanvas();
uint16_t cw = pDisp->bMode/8; /* color width */
uint32_t rw = pDisp->wImgW * cw; /* Row width in bytes */
uint32_t rws = dwWidth * cw; /* Source Row Width */
uint32_t rl = (rw & 0x3) ? ((rw | 0x3) + 1) : rw; /* Aligned length*/
uint32_t rls = (rws & 0x3) ? ((rws | 0x3) + 1) : rws; /* Aligned length */
uint8_t *pSrc, *pDst;
uint32_t i;
pSrc = (uint8_t*)pImage;
pDst = pDisp->pBuffer;
pDst = &pDst[dwX*cw + dwY*rl];
for (i = 0; i < dwHeight; i ++)
{
memcpy(pDst, pSrc, rws);
pSrc = &pSrc[rls];
pDst = &pDst[rl];
}
}
/**
* \brief Clear a window with an color.
*
* \param dwX X-coordinate of the window.
* \param dwY Y-coordinate of the window.
* \param dwWidth window width.
* \param dwHeight window height.
* \param dwColor background color
*/
extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor )
{
_SetFrontColor(dwColor);
_HideCanvas();
_FillRect(0, 0, dwX + dwWidth - 1, dwY + dwHeight - 1);
_ShowCanvas();
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file
*
* Implementation of draw font on LCD.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdint.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Global variable describing the font being instancied. */
const Font gFont = {10, 14};
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Draws an ASCII character on LCD.
*
* \param x X-coordinate of character upper-left corner.
* \param y Y-coordinate of character upper-left corner.
* \param c Character to output.
* \param color Character color.
*/
extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color )
{
uint32_t row, col ;
assert( (c >= 0x20) && (c <= 0x7F) ) ;
for ( col = 0 ; col < 10 ; col++ )
{
for ( row = 0 ; row < 8 ; row++ )
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row, color ) ;
}
}
for (row = 0; row < 6; row++ )
{
if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1)
{
LCDD_DrawPixel( x+col, y+row+8, color ) ;
}
}
}
}
/**
* \brief Draws an ASCII character on LCD with given background color.
*
* \param x X-coordinate of character upper-left corner.
* \param y Y-coordinate of character upper-left corner.
* \param c Character to output.
* \param fontColor Character color.
* \param bgColor Background color.
*/
extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor )
{
uint32_t row, col ;
assert( (c >= 0x20) && (c <= 0x7F) ) ;
for (col = 0; col < 10; col++)
{
for (row = 0 ; row < 8 ; row++)
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row, fontColor ) ;
}
else
{
LCDD_DrawPixel( x+col, y+row, bgColor ) ;
}
}
for ( row = 0 ; row < 6 ; row++ )
{
if ( (pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1 )
{
LCDD_DrawPixel( x+col, y+row+8, fontColor ) ;
}
else
{
LCDD_DrawPixel( x+col, y+row+8, bgColor ) ;
}
}
}
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Font 10x14 table definition.
*
*/
/** \addtogroup font_10x14
*@{
*/
#include "board.h"
/** Char set of font 10x14 */
const uint8_t pCharset10x14[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,
0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,
0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,
0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,
0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,
0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,
0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,
0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,
0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,
0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,
0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,
0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,
0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,
0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,
0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,
0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,
0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,
0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,
0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,
0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,
0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,
0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,
0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,
0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,
0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,
0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,
0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,
0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,
0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,
0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,
0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,
0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,
0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,
0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,
0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,
0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,
0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,
0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,
0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,
0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,
0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,
0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,
0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,
0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,
0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,
0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,
0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,
0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,
0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,
0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,
0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,
0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,
0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,
0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,
0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,
0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,
0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,
0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,
0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,
0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,
0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,
0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,
0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,
0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,
0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,
0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,
0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,
0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,
0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,
0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,
0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,
0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,
0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,
0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,
0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,
0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,
0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,
0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,
0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,
0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,
0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,
0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,
0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,
0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,
0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,
0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,
0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,
0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,
0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC
} ;
/**@}*/

1640
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcdd.c Normal file
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168
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/led.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
#ifdef PINS_LEDS
static const Pin pinsLeds[] = { PINS_LEDS } ;
static const uint32_t numLeds = PIO_LISTSIZE( pinsLeds ) ;
#endif
/*------------------------------------------------------------------------------
* Global Functions
*------------------------------------------------------------------------------*/
/**
* Configures the pin associated with the given LED number. If the LED does
* not exist on the board, the function does nothing.
* \param led Number of the LED to configure.
* \return 1 if the LED exists and has been configured; otherwise 0.
*/
extern uint32_t LED_Configure( uint32_t dwLed )
{
#ifdef PINS_LEDS
// Check that LED exists
if ( dwLed >= numLeds)
{
return 0;
}
// Configure LED
return ( PIO_Configure( &pinsLeds[dwLed], 1 ) ) ;
#else
return 0 ;
#endif
}
/**
* Turns the given LED on if it exists; otherwise does nothing.
* \param led Number of the LED to turn on.
* \return 1 if the LED has been turned on; 0 otherwise.
*/
extern uint32_t LED_Set( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Turn LED on */
if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}
/**
* Turns a LED off.
*
* \param led Number of the LED to turn off.
* \return 1 if the LED has been turned off; 0 otherwise.
*/
extern uint32_t LED_Clear( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Turn LED off */
if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 )
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}
/**
* Toggles the current state of a LED.
*
* \param led Number of the LED to toggle.
* \return 1 if the LED has been toggled; otherwise 0.
*/
extern uint32_t LED_Toggle( uint32_t dwLed )
{
#ifdef PINS_LEDS
/* Check if LED exists */
if ( dwLed >= numLeds )
{
return 0 ;
}
/* Toggle LED */
if ( PIO_GetOutputDataStatus( &pinsLeds[dwLed] ) )
{
PIO_Clear( &pinsLeds[dwLed] ) ;
}
else
{
PIO_Set( &pinsLeds[dwLed] ) ;
}
return 1 ;
#else
return 0 ;
#endif
}

648
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/macb.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*---------------------------------------------------------------------------
* Headers
*---------------------------------------------------------------------------*/
#include <board.h>
/*---------------------------------------------------------------------------
* Definitions
*---------------------------------------------------------------------------*/
/** Default max retry count */
#define MACB_RETRY_MAX 1000000
/*---------------------------------------------------------------------------
* Local functions
*---------------------------------------------------------------------------*/
/**
* Wait PHY operation complete.
* Return 1 if the operation completed successfully.
* May be need to re-implemented to reduce CPU load.
* \param retry: the retry times, 0 to wait forever until complete.
*/
static uint8_t EMAC_WaitPhy( Emac *pHw, uint32_t retry )
{
volatile uint32_t retry_count = 0;
while (!EMAC_IsIdle(pHw))
{
if(retry == 0) continue;
retry_count ++;
if (retry_count >= retry)
{
return 0;
}
}
return 1;
}
/**
* Read PHY register.
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param pValue Pointer to a 32 bit location to store read data
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t EMAC_ReadPhy(Emac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t *pValue,
uint32_t retry)
{
EMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0);
if ( EMAC_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut EMAC_ReadPhy\n\r");
return 0;
}
*pValue = EMAC_PHYData(pHw);
return 1;
}
/**
* Write PHY register
* Return 1 if successfully, 0 if timeout.
* \param pHw HW controller address
* \param PhyAddress PHY Address
* \param Address Register Address
* \param Value Data to write ( Actually 16 bit data )
* \param retry The retry times, 0 to wait forever until complete.
*/
static uint8_t EMAC_WritePhy(Emac *pHw,
uint8_t PhyAddress,
uint8_t Address,
uint32_t Value,
uint32_t retry)
{
EMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value);
if ( EMAC_WaitPhy(pHw, retry) == 0 )
{
TRACE_ERROR("TimeOut EMAC_WritePhy\n\r");
return 0;
}
return 1;
}
/*---------------------------------------------------------------------------
* Exported functions
*---------------------------------------------------------------------------*/
/**
* Find a valid PHY Address ( from addrStart to 31 ).
* Check BMSR register ( not 0 nor 0xFFFF )
* Return 0xFF when no valid PHY Address found.
* \param pMacb Pointer to the MACB instance
*/
uint8_t MACB_FindValidPhy(Macb *pMacb, uint8_t addrStart)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value=0;
uint8_t rc;
uint8_t phyAddress;
uint8_t cnt;
TRACE_DEBUG("MACB_FindValidPhy\n\r");
EMAC_ManagementEnable(pHw, 1);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
/* Check current phyAddress */
rc = phyAddress;
if( EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax) == 0 )
{
TRACE_ERROR("MACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
/* Find another one */
if (value != MII_OUI_MSB)
{
rc = 0xFF;
for(cnt = 0; cnt < 32; cnt ++)
{
phyAddress = (phyAddress + 1) & 0x1F;
if( EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax) == 0 )
{
TRACE_ERROR("MACB PROBLEM\n\r");
}
TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
if (value == MII_OUI_MSB)
{
rc = phyAddress;
break;
}
}
}
EMAC_ManagementEnable(pHw, 0);
if (rc != 0xFF)
{
printf("** Valid PHY Found: %d\n\r", rc);
EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &value, retryMax);
TRACE_DEBUG("_DSCSR : 0x%X, addr: %d\n\r", value, phyAddress);
}
return rc;
}
/**
* Dump all the useful registers
* \param pMacb Pointer to the MACB instance
*/
void MACB_DumpRegisters(Macb *pMacb)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint8_t phyAddress;
uint32_t retryMax;
uint32_t value;
TRACE_INFO("MACB_DumpRegisters\n\r");
EMAC_ManagementEnable(pHw, 1);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
TRACE_INFO("%cMII MACB (@%d) Registers:\n\r",
pMacb->RMII ? 'R' : ' ',
phyAddress);
EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax);
TRACE_INFO(" _BMCR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &value, retryMax);
TRACE_INFO(" _BMSR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_ANAR, &value, retryMax);
TRACE_INFO(" _ANAR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_ANLPAR, &value, retryMax);
TRACE_INFO(" _ANLPAR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_ANER, &value, retryMax);
TRACE_INFO(" _ANER : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_DSCR, &value, retryMax);
TRACE_INFO(" _DSCR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &value, retryMax);
TRACE_INFO(" _DSCSR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_10BTCSR, &value, retryMax);
TRACE_INFO(" _10BTCSR: 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_PWDOR, &value, retryMax);
TRACE_INFO(" _PWDOR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_CONFIGR, &value, retryMax);
TRACE_INFO(" _CONFIGR: 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_MDINTR, &value, retryMax);
TRACE_INFO(" _MDINTR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_RECR, &value, retryMax);
TRACE_INFO(" _RECR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_DISCR, &value, retryMax);
TRACE_INFO(" _DISCR : 0x%X\n\r", value);
EMAC_ReadPhy(pHw, phyAddress, MII_RLSR, &value, retryMax);
TRACE_INFO(" _RLSR : 0x%X\n\r", value);
EMAC_ManagementEnable(pHw, 0);
}
/**
* Setup the maximum timeout count of the driver.
* \param pMacb Pointer to the MACB instance
* \param toMax Timeout maxmum count.
*/
void MACB_SetupTimeout(Macb *pMacb, uint32_t toMax)
{
pMacb->retryMax = toMax;
}
/**
* Initialize the MACB instance
* \param pMacb Pointer to the MACB instance
* \param pEmac Pointer to the Emac instance for the MACB
* \param phyAddress The PHY address used to access the PHY
* ( pre-defined by pin status on PHY reset )
*/
void MACB_Init(Macb *pMacb, sEmacd *pEmacd, uint8_t phyAddress)
{
pMacb->pEmacd = pEmacd;
pMacb->phyAddress = phyAddress;
/* Initialize timeout by default */
pMacb->retryMax = MACB_RETRY_MAX;
}
/**
* Issue a SW reset to reset all registers of the PHY
* Return 1 if successfully, 0 if timeout.
* \param pMacb Pointer to the MACB instance
*/
uint8_t MACB_ResetPhy(Macb *pMacb)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t bmcr = MII_RESET;
uint8_t phyAddress;
uint32_t timeout = 10;
uint8_t ret = 1;
TRACE_INFO(" MACB_ResetPhy\n\r");
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
EMAC_ManagementEnable(pHw, 1);
bmcr = MII_RESET;
EMAC_WritePhy(pHw, phyAddress, MII_BMCR, bmcr, retryMax);
do
{
EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &bmcr, retryMax);
timeout--;
} while ((bmcr & MII_RESET) && timeout);
EMAC_ManagementEnable(pHw, 0);
if (!timeout)
{
ret = 0;
}
return( ret );
}
/**
* Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs
* This should be called only once to initialize the PHY pre-settings.
* The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups).
* The COL pin is used to select MII mode on reset (pulled up for Reduced MII)
* The RXDV pin is used to select test mode on reset (pulled up for test mode)
* The above pins should be predefined for corresponding settings in resetPins
* The EMAC peripheral pins are configured after the reset done.
* Return 1 if RESET OK, 0 if timeout.
* \param pMacb Pointer to the MACB instance
* \param mck Main clock setting to initialize clock
* \param resetPins Pointer to list of PIOs to configure before HW RESET
* (for PHY power on reset configuration latch)
* \param nbResetPins Number of PIO items that should be configured
* \param emacPins Pointer to list of PIOs for the EMAC interface
* \param nbEmacPins Number of PIO items that should be configured
*/
uint8_t MACB_InitPhy(Macb *pMacb,
uint32_t mck,
const Pin *pResetPins,
uint32_t nbResetPins,
const Pin *pEmacPins,
uint32_t nbEmacPins)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint8_t rc = 1;
uint8_t phy;
/* Perform RESET */
TRACE_DEBUG("RESET PHY\n\r");
if (pResetPins)
{
/* Configure PINS */
PIO_Configure(pResetPins, nbResetPins);
/* Execute reset */
RSTC_SetExtResetLength(MACB_RESET_LENGTH);
RSTC_ExtReset();
/* Get NRST level */
/* Wait for end hardware reset */
while (!RSTC_GetNrstLevel());
}
/* Configure EMAC runtime pins */
if (rc)
{
PIO_Configure(pEmacPins, nbEmacPins);
rc = EMAC_SetClock( pHw, mck );
if (!rc)
{
TRACE_ERROR("No Valid MDC clock\n\r");
return 0;
}
/* Check PHY Address */
phy = MACB_FindValidPhy(pMacb, 0);
if (phy == 0xFF)
{
TRACE_ERROR("PHY Access fail\n\r");
return 0;
}
if(phy != pMacb->phyAddress)
{
pMacb->phyAddress = phy;
MACB_ResetPhy(pMacb);
}
}
else
{
TRACE_ERROR("PHY Reset Timeout\n\r");
}
return rc;
}
/**
* Issue a Auto Negotiation of the PHY
* Return 1 if successfully, 0 if timeout.
* \param pMacb Pointer to the MACB instance
*/
uint8_t MACB_AutoNegotiate(Macb *pMacb, uint8_t rmiiMode)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t value;
uint32_t phyAnar;
uint32_t phyAnalpar;
uint32_t retryCount= 0;
uint8_t phyAddress;
uint8_t bFD = 0;
uint8_t bSP = 0;
uint8_t rc = 1;
pMacb->RMII = rmiiMode;
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
EMAC_ManagementEnable(pHw, 1);
if (!EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax))
{
TRACE_ERROR("Pb EMAC_ReadPhy Id1\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress);
if (!EMAC_ReadPhy(pHw, phyAddress, MII_PHYID2, &phyAnar, retryMax))
{
TRACE_ERROR("Pb EMAC_ReadPhy Id2\n\r");
rc = 0;
goto AutoNegotiateExit;
}
TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar);
if( ( value == MII_OUI_MSB )
&& ( ((phyAnar>>10)&MII_LSB_MASK) == MII_OUI_LSB ) )
{
TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F));
TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0x7));
}
else
{
TRACE_ERROR("Problem OUI value\n\r");
}
/* Setup control register */
rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
value &= ~MII_AUTONEG; /* Remove autonegotiation enable */
value &= ~(MII_LOOPBACK|MII_POWER_DOWN);
value |= MII_ISOLATE; /* Electrically isolate PHY */
rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Set the Auto_negotiation Advertisement Register
MII advertising for Next page
100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
phyAnar = MII_TX_FDX | MII_TX_HDX |
MII_10_FDX | MII_10_HDX | MII_AN_IEEE_802_3;
rc = EMAC_WritePhy(pHw, phyAddress, MII_ANAR, phyAnar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Read & modify control register */
rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE;
rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Restart Auto_negotiation */
value |= MII_RESTART_AUTONEG;
value &= ~MII_ISOLATE;
rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
TRACE_DEBUG(" _BMCR: 0x%X\n\r", value);
/* Check AutoNegotiate complete */
while (1)
{
rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &value, retryMax);
if (rc == 0)
{
TRACE_ERROR("_BMSR Rd err\n\r");
goto AutoNegotiateExit;
}
/* Done successfully */
if (value & MII_AUTONEG_COMP)
{
printf("AutoNegotiate complete\n\r");
break;
}
/* Timeout check */
if (retryMax)
{
if (++ retryCount >= retryMax)
{
MACB_DumpRegisters(pMacb);
TRACE_ERROR("TimeOut\n\r");
rc = 0;
goto AutoNegotiateExit;
}
}
}
/* Get the AutoNeg Link partner base page */
rc = EMAC_ReadPhy(pHw, phyAddress, MII_ANLPAR, &phyAnalpar, retryMax);
if (rc == 0)
{
goto AutoNegotiateExit;
}
/* Setup the EMAC link speed */
if ((phyAnar & phyAnalpar) & MII_TX_FDX)
{
/* set MII for 100BaseTX and Full Duplex */
bSP = 1; bFD = 1;
}
else if ((phyAnar & phyAnalpar) & MII_10_FDX)
{
/* set MII for 10BaseT and Full Duplex */
bSP = 0; bFD = 1;
}
else if ((phyAnar & phyAnalpar) & MII_TX_HDX)
{
// set MII for 100BaseTX and half Duplex
bSP = 1; bFD = 0;
}
else if ((phyAnar & phyAnalpar) & MII_10_HDX)
{
// set MII for 10BaseT and half Duplex
bSP = 0; bFD = 0;
}
EMAC_SetSpeed(pHw, bSP);
EMAC_FullDuplexEnable(pHw, bFD);
EMAC_RMIIEnable(pHw, rmiiMode);
EMAC_TransceiverClockEnable(pHw, 1);
AutoNegotiateExit:
EMAC_ManagementEnable(pHw, 0);
return rc;
}
/**
* Get the Link & speed settings, and automatically setup the EMAC with the
* settings.
* Return 1 if link found, 0 if no ethernet link.
* \param pMacb Pointer to the MACB instance
* \param applySetting Apply the settings to EMAC interface
*/
uint8_t MACB_GetLinkSpeed(Macb *pMacb, uint8_t applySetting)
{
sEmacd *pDrv = pMacb->pEmacd;
Emac *pHw = pDrv->pHw;
uint32_t retryMax;
uint32_t stat1;
uint32_t stat2;
uint8_t phyAddress, bSP, bFD;
uint8_t rc = 1;
TRACE_DEBUG("MACB_GetLinkSpeed\n\r");
bSP = 0; bFD = 0;
EMAC_ManagementEnable(pHw, 1);
phyAddress = pMacb->phyAddress;
retryMax = pMacb->retryMax;
rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &stat1, retryMax);
if (rc == 0)
{
goto GetLinkSpeedExit;
}
if ((stat1 & MII_LINK_STATUS) == 0)
{
TRACE_ERROR("Pb: LinkStat: 0x%x\n\r", (unsigned int)stat1);
rc = 0;
goto GetLinkSpeedExit;
}
if (applySetting == 0)
{
TRACE_WARNING("Speed #%d not applied\n\r", applySetting);
bSP = 0; bFD = 0;
goto GetLinkSpeedExit;
}
/* Re-configure Link speed */
rc = EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &stat2, retryMax);
if (rc == 0)
{
TRACE_ERROR("Pb _DSCSR: rc 0x%x\n\r", rc);
goto GetLinkSpeedExit;
}
if ((stat1 & MII_100BASE_TX_FD) && (stat2 & MII_100FDX))
{
/* set Emac for 100BaseTX and Full Duplex */
bSP = 1; bFD = 1;
}
if ((stat1 & MII_10BASE_T_FD) && (stat2 & MII_10FDX))
{
/* set MII for 10BaseT and Full Duplex */
bSP= 0; bFD = 1;
}
if ((stat1 & MII_100BASE_T4_HD) && (stat2 & MII_100HDX))
{
/* set MII for 100BaseTX and Half Duplex */
bSP = 1; bFD = 0;
}
if ((stat1 & MII_10BASE_T_HD) && (stat2 & MII_10HDX))
{
/* set MII for 10BaseT and Half Duplex */
bSP = 0; bFD = 0;
}
EMAC_SetSpeed(pHw, bSP);
EMAC_FullDuplexEnable(pHw, bFD);
/* Start the EMAC transfers */
TRACE_DEBUG("MACB_GetLinkSpeed passed\n\r");
GetLinkSpeedExit:
EMAC_ManagementEnable(pHw, 0);
return rc;
}

97
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/math.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
/**
* Returns the minimum value between two integers.
*
* \param a First integer to compare.
* \param b Second integer to compare.
*/
extern uint32_t min( uint32_t dwA, uint32_t dwB )
{
if ( dwA < dwB )
{
return dwA ;
}
else
{
return dwB ;
}
}
/*------------------------------------------------------------------------------
* Returns the absolute value of an integer.
*
* \param value Integer value.
*
* \note Do not call this function "abs", problem with gcc !
*/
extern uint32_t absv( int32_t lValue )
{
if ( lValue < 0 )
{
return -lValue ;
}
else
{
return lValue ;
}
}
/*------------------------------------------------------------------------------
* Computes and returns x power of y.
*
* \param x Value.
* \param y Power.
*/
extern uint32_t power( uint32_t dwX, uint32_t dwY )
{
uint32_t dwResult = 1 ;
while ( dwY > 0 )
{
dwResult *= dwX ;
dwY-- ;
}
return dwResult ;
}

1027
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/mcid_dma.c Normal file
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421
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/omnivision.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** Slave address of OMNIVISION chips. */
#define OV_CAPTOR_ADDRESS_1 0x30
#define OV_CAPTOR_ADDRESS_2 0x21
#define OV_CAPTOR_ADDRESS_3 0x3c
#define OV_CAPTOR_ADDRESS_4 0x10
/** terminating list entry for register in configuration file */
#define OV_REG_TERM 0xFF
#define OV_REG_DELAY 0xFFFF
/** terminating list entry for value in configuration file */
#define OV_VAL_TERM 0xFF
static const Pin pin_ISI_RST= PIN_ISI_RST;
static uint8_t twiSlaveAddr = OV_CAPTOR_ADDRESS_1;
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
static void ov_reset(void)
{
volatile uint32_t i;
PIO_Configure(&pin_ISI_RST, 1);
PIO_Clear(&pin_ISI_RST);
for(i = 0; i < 6000; i++ );
PIO_Set(&pin_ISI_RST);
for(i = 0; i<6000; i++ );
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id8(Twid *pTwid)
{
uint8_t id, ver;
uint8_t status;
// OV_PID
status = ov_read_reg8(pTwid, 0x0A, &id);
if( status != 0 ) return 0;
TRACE_INFO("PID = 0x%X\n\r", id);
// OV_VER
status = ov_read_reg8(pTwid, 0x0B, &ver);
if( status != 0 ) return 0;
TRACE_INFO("VER = 0x%X\n\r", ver);
return((uint16_t)(id <<8) | ver);
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id16(Twid *pTwid)
{
uint8_t id, ver;
// OV_PID
ov_read_reg16(pTwid, 0x300A, &id);
TRACE_INFO("PID = 0x%X\n\r", id);
// OV_VER
ov_read_reg16(pTwid, 0x300B, &ver);
TRACE_INFO("VER = 0x%X\n\r", ver);
return((uint16_t)(id <<8) | ver);
}
/**
* \brief Read PID and VER
* \param pTwid TWI interface
* \return VER | (PID<<8)
*/
static uint16_t ov_id(Twid *pTwid)
{
uint16_t id;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
twiSlaveAddr = OV_CAPTOR_ADDRESS_1;
id = ov_id8(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_2;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id8(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_3;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id16(pTwid);
if (id == 0) {
twiSlaveAddr = OV_CAPTOR_ADDRESS_4;
printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr);
id = ov_id16(pTwid);
}
}
}
return id;
}
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/**
* \brief Read a value from a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be read
* \param isize Internal address size in bytes.
* \param pData Data read
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData)
{
uint8_t status;
status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, &reg, 1, 0);
status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_read_reg pb\n\r");
}
return status;
}
/**
* \brief Read a value from a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be read
* \param pData Data read
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData)
{
uint8_t status;
uint8_t reg8[2];
reg8[0] = reg>>8;
reg8[1] = reg & 0xff;
status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, reg8, 2, 0);
status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_read_reg pb\n\r");
}
return status;
}
/**
* \brief Write a value to a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be writen
* \param pData Data written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val)
{
uint8_t status;
status = TWID_Write(pTwid, twiSlaveAddr, reg, 1, &val, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_write_reg pb\n\r");
}
return status;
}
/**
* \brief Write a value to a register in an OV sensor device.
* \param pTwid TWI interface
* \param reg Register to be writen
* \param pData Data written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val)
{
uint8_t status;
status = TWID_Write(pTwid, twiSlaveAddr, reg, 2, &val, 1, 0);
if( status != 0 ) {
TRACE_ERROR("ov_write_reg pb\n\r");
}
return status;
}
/**
* \brief Initialize a list of OV registers.
* The list of registers is terminated by the pair of values
* \param pTwid TWI interface
* \param pReglist Register list to be written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist)
{
uint32_t err;
uint32_t size=0;
const struct ov_reg *pNext = pReglist;
volatile uint32_t delay;
TRACE_DEBUG("ov_write_regs:");
while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {
err = ov_write_reg8(pTwid, pNext->reg, pNext->val);
size++;
for(delay=0;delay<=10000;delay++);
if (err == TWID_ERROR_BUSY){
TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");
return err;
}
//printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);
pNext++;
}
TRACE_DEBUG_WP("\n\r");
return 0;
}
/**
* \brief Initialize a list of OV registers.
* The list of registers is terminated by the pair of values
* \param pTwid TWI interface
* \param pReglist Register list to be written
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist)
{
uint32_t err = 0;
uint32_t size = 0;
const struct ov_reg *pNext = pReglist;
volatile uint32_t delay;
TRACE_DEBUG("ov_write_regs:");
while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) {
err = ov_write_reg16(pTwid, pNext->reg, pNext->val);
size++;
for(delay = 0;delay <= 10000; delay++);
if (err == TWID_ERROR_BUSY){
TRACE_ERROR("ov_write_regs: TWI ERROR\n\r");
return err;
}
//printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val);
pNext++;
}
TRACE_DEBUG_WP("\n\r");
return 0;
}
void isOV5640_AF_InitDone(Twid *pTwid)
{
uint8_t value = 0;
while(1){
ov_read_reg16(pTwid, 0x3029, &value);
if (value == 0x70) break;
}
}
/**
* \brief AF for OV 5640
* \param pTwid TWI interface
* \return 0 if no error; otherwize TWID_ERROR_BUSY
*/
uint32_t ov_5640_AF_single(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 3);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AF_continue(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3024, 1);
ov_write_reg16(pTwid, 0x3022, 4);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AFPause(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 6);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
uint32_t ov_5640_AFrelease(Twid *pTwid)
{
uint8_t value;
ov_write_reg16(pTwid, 0x3023, 1);
ov_write_reg16(pTwid, 0x3022, 8);
value =1;
while(1){
ov_read_reg16(pTwid, 0x3023, &value);
if (value == 0) break;
}
return 0;
}
/**
* \brief Dump all register
* \param pTwid TWI interface
*/
void ov_DumpRegisters8(Twid *pTwid)
{
uint32_t i;
uint8_t value;
TRACE_INFO_WP("Dump all camera register\n\r");
for(i = 0; i <= 0x5C; i++) {
value = 0;
ov_read_reg8(pTwid, i, &value);
TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);
if( ((i+1)%5) == 0 ) {
TRACE_INFO_WP("\n\r");
}
}
TRACE_INFO_WP("\n\r");
}
/**
* \brief Dump all register
* \param pTwid TWI interface
*/
void ov_DumpRegisters16(Twid *pTwid)
{
uint32_t i;
uint8_t value;
TRACE_INFO_WP("Dump all camera register\n\r");
for(i = 3000; i <= 0x305C; i++) {
value = 0;
ov_read_reg16(pTwid, i, &value);
TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value);
if( ((i+1)%5) == 0 ) {
TRACE_INFO_WP("\n\r");
}
}
TRACE_INFO_WP("\n\r");
}
/**
* \brief Sequence For correct operation of the sensor
* \param pTwid TWI interface
* \return OV type
*/
uint8_t ov_init(Twid *pTwid)
{
uint16_t id = 0;
uint8_t ovType;
ov_reset();
id = ov_id(pTwid);
switch (id) {
case 0x7740: case 0x7742:
ovType = OV_7740;
break;
case 0x9740: case 0x9742:
ovType = OV_9740;
break;
case 0x2642: case 0x2640:
ovType = OV_2640;
break;
case 0x2643:
ovType = OV_2643;
break;
case 0x5640:
ovType = OV_5640;
break;
default:
ovType = OV_UNKNOWN;
TRACE_ERROR("Can not support product ID %x \n\r", id);
break;
}
return ovType;
}

189
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
const static struct capture_size ov_sizes[] = {
// {width, height}
/// VGA
{ 640, 360 },
{ 640, 480 },
// SWVGA
{ 800, 600 },
/// SXGA
{1280, 960 },
{1280, 720 },
/// UXGA
{1600, 1200 },
};
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/**
* \brief Configure the OV for a specified image size, pixel format,
* and frame period.
*/
void ov_configure(Twid *pTwid, uint8_t ovType, uint32_t width, uint32_t heigth)
{
const struct ov_reg *reg_conf;
uint8_t goodCaptureSize = 0;
uint8_t i;
reg_conf = ov5640_yuv_vga;
TRACE_DEBUG("ovxxx_configure\n\r");
for( i = 0; i< sizeof(ov_sizes); i++ ) {
if( ov_sizes[i].width == width ) {
if( ov_sizes[i].height != heigth ) {
TRACE_INFO("ov configure vsize not define\n\r");
}
else {
goodCaptureSize = 1;
break;
}
}
}
if( goodCaptureSize == 0 ) {
TRACE_ERROR("Problem size\n\r");
while(1);
}
switch (ovType){
case OV_2640: {
// Default value
reg_conf = ov2640_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov2640_yuv_vga;
break;
default:
TRACE_DEBUG("ov2640_configure problem\n\r");
break;
}
break;
}
case OV_7740: {
// Default value
reg_conf = ov7740_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov7740_yuv_vga;
break;
default:
TRACE_DEBUG("ov7740_configure problem\n\r");
break;
}
break;
}
case OV_9740: {
// Default value
reg_conf = ov9740_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 360\n\r");
reg_conf = ov9740_yuv_vga;
break;
case 1280: //VGA
printf("-I- VGA 1280 x 720\n\r");
reg_conf = ov9740_yuv_sxga;
break;
default:
TRACE_DEBUG("ov9740_configure problem\n\r");
break;
}
break;
}
case OV_2643: {
// Default value
reg_conf = ov2643_yuv_vga;
// common register initialization
switch(width) {
case 1600: //UXGA
printf("-I- UXGA 1600 x 1200 \n\r");
reg_conf = ov2643_yuv_uxga;
break;
case 800: //SWVGA
printf("-I- SWVGA 800 x 600\n\r");
reg_conf = ov2643_yuv_swvga;
break;
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov2643_yuv_vga;
break;
default:
TRACE_DEBUG("ov2643_configure problem\n\r");
break;
}
break;
}
case OV_5640: {
// Default value
reg_conf = ov5640_yuv_vga;
// common register initialization
switch(width) {
case 640: //VGA
printf("-I- VGA 640 x 480\n\r");
reg_conf = ov5640_yuv_vga;
break;
case 1280: //SXGA
printf("-I- SXGA 1280 x 720\n\r");
reg_conf = ov5640_yuv_sxga;
break;
default:
TRACE_DEBUG("ov5640_configure problem\n\r");
break;
}
break;
}
}
if ((ovType == OV_5640) || (ovType == OV_9740))
ov_write_regs16(pTwid, reg_conf);
else
ov_write_regs8(pTwid, reg_conf);
}
/**
* \brief Configure the OV 5640 afc fireware.
*/
void ov_5640Afc_Firmware(Twid *pTwid)
{
const struct ov_reg *reg_conf;
reg_conf = ov5640_afc;
ov_write_regs16(pTwid, reg_conf);
}

286
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov2640_yuv_vga[]= {
{0xff, 0x01}, //dsp
{0x12, 0x80}, //reset
{0xff, 0x00}, //sensor
{0x2c, 0xff}, //?
{0x2e, 0xdf}, //ADDVSH, VSYNC msb=223
{0xff, 0x01}, //dsp
{0x3c, 0x32}, //?
{0x11, 0x00}, //clock rate off
{0x09, 0x02}, //2 capablity + standby mode
{0x04, 0x28}, //? ??????????????????????????????????
{0x13, 0xe5}, //
{0x14, 0x48}, //Auto agc
{0x2c, 0x0c}, //?
{0x33, 0x78}, //?
{0x3a, 0x33}, //?
{0x3b, 0xfb}, //?
{0x3e, 0x00}, //?
{0x43, 0x11}, //?
{0x16, 0x10}, //?
{0x39, 0x02}, //?
{0x35, 0x88}, //?
{0x22, 0x0a}, //?
{0x37, 0x40}, //?
{0x23, 0x00}, //?
{0x34, 0xa0}, //startpoint 0
{0x36, 0x1a}, //? XXXXXXXXXXXXXXXX
{0x06, 0x02}, //?
{0x07, 0xc0}, //?
{0x0d, 0xb7}, //?
{0x0e, 0x01}, //?
{0x4c, 0x00}, //?
{0x4a, 0x81}, //?
{0x21, 0x99}, //?
{0x24, 0x3a}, // Luminance high
{0x25, 0x32}, // Luminance low
//{0x24, 0x10}, // Luminance high
//{0x25, 0x03}, // Luminance low
{0x26, 0xF3}, // Fast mode large Step Range Threshold
{0x5c, 0x00}, //?
{0x63, 0x00}, //?
{0x5d, 0x55}, //zone
{0x5e, 0x7d}, //zone
{0x5f, 0x7d}, //zone
{0x60, 0x55}, //zone
{0x61, 0x70}, //Histogram low
{0x62, 0x80}, //Histogram high
{0x7c, 0x05}, //?
{0x20, 0x80}, //?
{0x28, 0x30}, //?
{0x6c, 0x00}, //?
{0x6d, 0x80}, //?
{0x6e, 0x00}, //?
{0x70, 0x02}, //?
{0x71, 0x94}, //?
{0x73, 0xc1}, //?
{0x3d, 0x34}, //?
{0x5a, 0x57}, //?
{0x4f, 0xbb}, //50Hz
{0x50, 0x9c}, //60Hz
{0xff, 0x00}, //dsp
{0xe5, 0x7f}, //?
{0xf9, 0xc0}, //MicroC reset,Boot
{0x41, 0x24}, //?
{0xe0, 0x14}, //JPEG,DVP reset
{0x76, 0xff}, //?
{0x33, 0xa0}, //?
{0x42, 0x20}, //?
{0x43, 0x18}, //?
{0x4c, 0x00}, //?
{0x87, 0xd0}, //Module Enable BPC+WPC 11010000
{0x88, 0x3f}, //?
{0xd7, 0x03}, //?
{0xd9, 0x10}, //?
{0xd3, 0x82}, //Auto mode
{0xc8, 0x08}, //?
{0xc9, 0x80}, //?
{0x7c, 0x00}, //SDE indirect register access: address
{0x7d, 0x02}, //SDE indirect register data
{0x7c, 0x03}, //
{0x7d, 0x48}, //
{0x7d, 0x48}, //
{0x7c, 0x08}, //
{0x7d, 0x20}, //
{0x7d, 0x10}, //
{0x7d, 0x0e}, //
{0x90, 0x00}, //?
{0x91, 0x0e}, //?
{0x91, 0x1a}, //?
{0x91, 0x31}, //?
{0x91, 0x5a}, //?
{0x91, 0x69}, //?
{0x91, 0x75}, //?
{0x91, 0x7e}, //?
{0x91, 0x88}, //?
{0x91, 0x8f}, //?
{0x91, 0x96}, //?
{0x91, 0xa3}, //?
{0x91, 0xaf}, //?
{0x91, 0xc4}, //?
{0x91, 0xd7}, //?
{0x91, 0xe8}, //?
{0x91, 0x20}, //?
{0x92, 0x00}, //?
{0x93, 0x06}, //?
{0x93, 0xe3}, //?
{0x93, 0x05}, //?
{0x93, 0x05}, //?
{0x93, 0x00}, //?
{0x93, 0x02}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x93, 0x00}, //?
{0x96, 0x00}, //?
{0x97, 0x08}, //?
{0x97, 0x19}, //?
{0x97, 0x02}, //?
{0x97, 0x0c}, //?
{0x97, 0x24}, //?
{0x97, 0x30}, //?
{0x97, 0x28}, //?
{0x97, 0x26}, //?
{0x97, 0x02}, //?
{0x97, 0x98}, //?
{0x97, 0x80}, //?
{0x97, 0x00}, //?
{0x97, 0x00}, //?
{0xc3, 0xed}, //Module enable
{0xa4, 0x00}, //?
{0xa8, 0x00}, //?
{0xc5, 0x11}, //?
{0xc6, 0x51}, //?
{0xbf, 0x80}, //?
{0xc7, 0x10}, //?
{0xb6, 0x66}, //?
{0xb8, 0xa5}, //?
{0xb7, 0x64}, //?
{0xb9, 0x7c}, //?
{0xb3, 0xaf}, //?
{0xb4, 0x97}, //?
{0xb5, 0xff}, //?
{0xb0, 0xc5}, //?
{0xb1, 0x94}, //?
{0xb2, 0x0f}, //?
{0xc4, 0x5c}, //?
{0xc0, 0xc8}, // HSIZE8[7:0] 1600
{0xc1, 0x96}, // VSIZE8[7:0] 1200
{0x86, 0x1d}, //Module enable
{0x50, 0x00}, //?
{0x51, 0x90}, //H_SIZE[7:0] (real/4) 1600
{0x52, 0x18}, //V_SIZE[7:0] (real/4) 1120
{0x53, 0x00}, //OFFSET_X[7:0]
{0x54, 0x00}, //OFFSET_Y[7:0]
{0x55, 0x88}, //V_SIZE[8]=1 H_SIZE[8]
{0x57, 0x00}, //?
{0x5a, 0x90}, //OUTW
{0x5b, 0x18}, //OUTH
{0x5c, 0x05}, //OUTW8 ,OUTH8
{0xc3, 0xed}, //
{0x7f, 0x00}, //?
{0xda, 0x04}, //Image output format select ------ RAW
{0xe5, 0x1f}, //?
{0xe1, 0x67}, //?
{0xe0, 0x00}, //Reset
{0xdd, 0xff}, //?
{0x05, 0x00}, //Bypass DSP no
{0xC2, 0x08 | 0x04 | 0x02 },
{0xff, 0x01}, //Sensor
{0x11, 0x01}, //?
{0xff, 0x01}, //Sensor
{0x12, 0x40}, //Preview mode
{0x17, 0x11}, //?
{0x18, 0x43}, //?
{0x19, 0x00}, //?
{0x1a, 0x4b}, //?
{0x32, 0x09}, //?
{0x4f, 0xca}, //?
{0x50, 0xa8}, //10 101 000 V_DIVDER = 5
{0x5a, 0x23}, // OUTW 23
{0x6d, 0x00}, //?
{0x3d, 0x38}, //?
{0x39, 0x12}, //?
{0x35, 0xda}, //?
{0x22, 0x1a}, //?
{0x37, 0xc3}, //?
{0x23, 0x00}, //?
{0x34, 0xc0}, //?
{0x36, 0x1a}, //?
{0x06, 0x88}, //?
{0x07, 0xc0}, //?
{0x0d, 0x87}, //?
{0x0e, 0x41}, //?
{0x4c, 0x00}, //?
{0x48, 0x00}, //?
{0x5B, 0x00}, //OUTH
{0x42, 0x03}, //?
{0xff, 0x00}, //DSP
{0xe0, 0x04}, //Reset DVP
{0xc0, 0x64}, // HSIZE8[7:0] 400
{0xc1, 0x4B}, // VSIZE8[7:0] 300
{0x8c, 0x00}, //?
{0x86, 0x1D}, //Modle enable
{0xd3, 0x82}, //Auto mode DVP PCLK=2
{0xe0, 0x00}, //Reset
{0xff, 0x00}, //DSP
{0xc0, 0x64}, // HSIZE8[7:0] 400
{0xc1, 0x4B}, // VSIZE8[7:0] 300
{0x8c, 0x00}, //?
{0x86, 0x3D}, //?
{0x50, 0x00}, //?
{0x51, 0xC8}, //H_SIZE[7:0] (real/4) 800
{0x52, 0x96}, //V_SIZE[7:0] (real/4) 600
{0x53, 0x00}, //OFFSET
{0x54, 0x00}, //OFFSET
{0x55, 0x00}, //H_SIZE[8],V_SIZE[8]
{0x5a, 0xA0}, //OUTW[0-7] 160?
{0x5b, 0x78}, //OUTH[0-7] 120?
{0x5c, 0x00}, //OUTW8,OUTH8
{0xd3, 0x04}, //?
{0xFF, 0x00},
{0xE0, 0x04},
{0xE1, 0x67},
{0xD7, 0x01},
{0xDA, 0x00}, //Image output format select ------ YUV422
{0xD3, 0x82},
{0xE0, 0x00},
{0xFF, 0xFF}
};

676
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
#define MANUFACTURER_ID 0x7FA2
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov2643_yuv_uxga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0xFF, 0xFF}
};
const struct ov_reg ov2643_yuv_swvga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x3d, 0x48},
{0x0e, 0xb8},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x20, 0x01},
{0x21, 0x98},
{0x22, 0x00},
{0x23, 0x06},
{0x24, 0x32},
{0x25, 0x04},
{0x26, 0x25},
{0x27, 0x84},
{0x28, 0x40},
{0x29, 0x04},
{0x2a, 0xce},
{0x2b, 0x02},
{0x2c, 0x8a},
{0x12, 0x09},
{0x39, 0xd0},
{0xcd, 0x13},
{0xde, 0x7c},
{0x3d, 0x08},
{0x15, 0x42},
{0xde, 0x7c},
{0x0f, 0x24},
{0xFF, 0xFF}
};
const struct ov_reg ov2643_yuv_vga[]= {
{0x12, 0x80},
{0xc3, 0x1f},
{0xc4, 0xff},
{0x3d, 0x48},
{0xdd, 0xa5},
{0x0e, 0xb4},
{0x10, 0x0a},
{0x11, 0x00},
{0x0f, 0x14},
{0x21, 0x25},
{0x23, 0x0c},
{0x12, 0x08},
{0x39, 0x10},
{0xcd, 0x12},
{0x13, 0xff},
{0x14, 0xa7},
{0x15, 0x42},
{0x3c, 0xa4},
{0x18, 0x60},
{0x19, 0x50},
{0x1a, 0xe2},
{0x37, 0xe8},
{0x16, 0x90},
{0x43, 0x00},
{0x40, 0xfb},
{0xa9, 0x44},
{0x2f, 0xec},
{0x35, 0x10},
{0x36, 0x10},
{0x0c, 0x00},
{0x0d, 0x00},
{0xd0, 0x93},
{0xdc, 0x2b},
{0xd9, 0x41},
{0xd3, 0x02},
{0x3d, 0x08},
{0x0c, 0x00},
{0x18, 0x2c},
{0x19, 0x24},
{0x1a, 0x71},
{0x9b, 0x69},
{0x9c, 0x7d},
{0x9d, 0x7d},
{0x9e, 0x69},
{0x35, 0x04},
{0x36, 0x04},
{0x65, 0x12},
{0x66, 0x20},
{0x67, 0x39},
{0x68, 0x4e},
{0x69, 0x62},
{0x6a, 0x74},
{0x6b, 0x85},
{0x6c, 0x92},
{0x6d, 0x9e},
{0x6e, 0xb2},
{0x6f, 0xc0},
{0x70, 0xcc},
{0x71, 0xe0},
{0x72, 0xee},
{0x73, 0xf6},
{0x74, 0x11},
{0xab, 0x20},
{0xac, 0x5b},
{0xad, 0x05},
{0xae, 0x1b},
{0xaf, 0x76},
{0xb0, 0x90},
{0xb1, 0x90},
{0xb2, 0x8c},
{0xb3, 0x04},
{0xb4, 0x98},
{0x4c, 0x03},
{0x4d, 0x30},
{0x4e, 0x02},
{0x4f, 0x5c},
{0x50, 0x56},
{0x51, 0x00},
{0x52, 0x66},
{0x53, 0x03},
{0x54, 0x30},
{0x55, 0x02},
{0x56, 0x5c},
{0x57, 0x40},
{0x58, 0x00},
{0x59, 0x66},
{0x5a, 0x03},
{0x5b, 0x20},
{0x5c, 0x02},
{0x5d, 0x5c},
{0x5e, 0x3a},
{0x5f, 0x00},
{0x60, 0x66},
{0x41, 0x1f},
{0xb5, 0x01},
{0xb6, 0x02},
{0xb9, 0x40},
{0xba, 0x28},
{0xbf, 0x0c},
{0xc0, 0x3e},
{0xa3, 0x0a},
{0xa4, 0x0f},
{0xa5, 0x09},
{0xa6, 0x16},
{0x9f, 0x0a},
{0xa0, 0x0f},
{0xa7, 0x0a},
{0xa8, 0x0f},
{0xa1, 0x10},
{0xa2, 0x04},
{0xa9, 0x04},
{0xaa, 0xa6},
{0x75, 0x6a},
{0x76, 0x11},
{0x77, 0x92},
{0x78, 0x21},
{0x79, 0xe1},
{0x7a, 0x02},
{0x7c, 0x05},
{0x7d, 0x08},
{0x7e, 0x08},
{0x7f, 0x7c},
{0x80, 0x58},
{0x81, 0x2a},
{0x82, 0xc5},
{0x83, 0x46},
{0x84, 0x3a},
{0x85, 0x54},
{0x86, 0x44},
{0x87, 0xf8},
{0x88, 0x08},
{0x89, 0x70},
{0x8a, 0xf0},
{0x8b, 0xf0},
{0x90, 0xe3},
{0x93, 0x10},
{0x94, 0x20},
{0x95, 0x10},
{0x96, 0x18},
{0x0f, 0x34},
{0x13, 0x00},
{0x3d, 0x48},
{0x0e, 0xb8},
{0x20, 0x02},
{0x21, 0x18},
{0x22, 0x00},
{0x23, 0x42},
{0x24, 0x28},
{0x25, 0x04},
{0x26, 0x1e},
{0x27, 0x04},
{0x28, 0x40},
{0x29, 0x04},
{0x2a, 0xce},
{0x2b, 0x02},
{0x2c, 0x8a},
{0x12, 0x09},
{0x39, 0xd0},
{0xcd, 0x13},
{0xde, 0x7c},
{0x3d, 0x08},
{0x13, 0xff},
{0x15, 0x42},
{0xFF, 0xFF}
};

4799
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FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov7740_config.c Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*
* ID
*/
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov7740_yuv_vga[]= {
{0x12 ,0x80},
//{0x11 ,0x07},
{0x55 ,0x40},
{0x11 ,0x02},
{0x12 ,0x00},
{0xd5 ,0x10},
{0x0c ,0x12},
{0x0d ,0x34},
{0x17 ,0x25},
{0x18 ,0xa0},
{0x19 ,0x03},
{0x1a ,0xf0},
{0x1b ,0x89}, //;was 81
{0x22 ,0x03}, //;new
{0x29 ,0x18}, //;was 17
{0x2b ,0xf8},
{0x2c ,0x01},
{0x31 ,0xa0},
{0x32 ,0xf0},
{0x33 ,0xc4}, //;was44
{0x35 ,0x05}, //;new
{0x36 ,0x3f},
{0x04 ,0x60},
{0x27 ,0x80}, //;delete "42 3a b4"
{0x3d ,0x0f},
{0x3e ,0x80},
{0x3f ,0x40},
{0x40 ,0x7f},
{0x41 ,0x6a},
{0x42 ,0x29},
{0x44 ,0x22}, //;was 11
{0x45 ,0x41},
{0x47 ,0x02},
{0x49 ,0x64},
{0x4a ,0xa1},
{0x4b ,0x40},
{0x4c ,0x1a},
{0x4d ,0x50},
{0x4e ,0x13},
{0x64 ,0x00},
{0x67 ,0x88},
{0x68 ,0x1a},
{0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling
{0x24 ,0x3c},
{0x25 ,0x30},
{0x26 ,0x72},
{0x50 ,0x97},
{0x51 ,0x1f}, //;0fc/7e/3f/1f for 60/30/15/7.5fps, 60Hz
{0x52 ,0x00}, //;[7:6]/[5:4] 2 msb for 60/50Hz
{0x53 ,0x00},
{0x20 ,0x00},
{0x21 ,0xcf}, //;01/23/57/cf for 60/30/15/7.5fps
{0x50, 0x4b}, // ;12e/97/4b/25 for 60/30/15/7.5fps, 50Hz
{0x38 ,0x14},
{0xe9 ,0x00},
{0x56 ,0x55},
{0x57 ,0xff},
{0x58 ,0xff},
{0x59 ,0xff},
{0x5f ,0x04},
{0xec ,0x00},
{0x13 ,0xff},
{0x80 ,0x7f}, //;[6]/[5] for BPC/WPC
{0x81 ,0x3f},
{0x82 ,0x32},
{0x83 ,0x01},
{0x38 ,0x11},
{0x84 ,0x70},
{0x85 ,0x00},
{0x86 ,0x03},
{0x87 ,0x01},
{0x88 ,0x05},
{0x89 ,0x30},
{0x8d ,0x30},
{0x8f ,0x85},
{0x93 ,0x30},
{0x95 ,0x85},
{0x99 ,0x30},
{0x9b ,0x85},
{0x9c ,0x08},
{0x9d ,0x12},
{0x9e ,0x23},
{0x9f ,0x45},
{0xa0 ,0x55},
{0xa1 ,0x64},
{0xa2 ,0x72},
{0xa3 ,0x7f},
{0xa4 ,0x8b},
{0xa5 ,0x95},
{0xa6 ,0xa7},
{0xa7 ,0xb5},
{0xa8 ,0xcb},
{0xa9 ,0xdd},
{0xaa ,0xec},
{0xab ,0x1a},
{0xce ,0x78},
{0xcf ,0x6e},
{0xd0 ,0x0a},
{0xd1 ,0x0c},
{0xd2 ,0x84},
{0xd3 ,0x90},
{0xd4 ,0x1e},
{0x5a ,0x24},
{0x5b ,0x1f},
{0x5c ,0x88},
{0x5d ,0x60},
{0xac ,0x6e},
{0xbe ,0xff},
{0xbf ,0x00},
{0x0f ,0x1d},
{0x0f ,0x1f},
{0xFF, 0xFF}
};

602
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*/
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Local Variables
*------------------------------------------------------------------------------*/
const struct ov_reg ov9740_yuv_vga[]= {
//@@ VGA 640x360 bin YUV DVP 60FPS (Full speed)
{0x0103,0x01},
{0x3026,0x00},
{0x3027,0x00},
{0x3002,0xe8},
{0x3004,0x03},
{0x3005,0xff},
{0x3703,0x42},
{0x3704,0x10},
{0x3705,0x45},
{0x3603,0xaa},
{0x3632,0x27},
{0x3620,0x66},
{0x3621,0xc0},
{0x0202,0x03},
{0x0203,0x43},
{0x3833,0x04},
{0x3835,0x02},
{0x4702,0x04},
{0x4704,0x00},
{0x4706,0x08},
{0x3819,0x6e},
{0x3817,0x94},
{0x3a18,0x00},
{0x3a19,0x7f},
{0x5003,0xa7},
{0x3631,0x5e},
{0x3633,0x50},
{0x3630,0xd2},
{0x3604,0x0c},
{0x3601,0x40},
{0x3602,0x16},
{0x3610,0xa1},
{0x3612,0x24},
{0x034a,0x02},
{0x034b,0xd3},
{0x034c,0x02},
{0x034d,0x80},
{0x034e,0x01},
{0x034f,0x68},
{0x0202,0x01},
{0x0203,0x9e},
{0x381a,0x44},
{0x3707,0x14},
{0x3622,0x9f},
{0x5841,0x04},
{0x4002,0x45},
{0x5000,0x01},
{0x5001,0x00},
{0x3406,0x00},
{0x5000,0xff},
{0x5001,0xef},
{0x5003,0xff},
{0x4005,0x18},
{0x3503,0x10},
{0x3a11,0xa0},
{0x3a1b,0x50},
{0x3a0f,0x50},
{0x3a10,0x4c},
{0x3a1e,0x4c},
{0x3a1f,0x26},
{0x3104,0x20},
{0x0305,0x03},
{0x0307,0x5f},
{0x0303,0x01},
{0x0301,0x0a},
{0x3010,0x01},
{0x300c,0x02},
{0x0340,0x02},
{0x0341,0x08},
{0x0342,0x04},
{0x0343,0xc0},
{0x0101,0x01},
{0x3a08,0x01},
{0x3a09,0x38},
{0x3a0e,0x01},
{0x3a14,0x09},
{0x3a15,0xc0},
{0x3a0a,0x01},
{0x3a0b,0x02},
{0x3a0d,0x02},
{0x3a02,0x10},
{0x3a03,0x30},
{0x3c0a,0x9c},
{0x3c0b,0x3f},
{0x529a,0x1 },
{0x529b,0x2 },
{0x529c,0x3 },
{0x529d,0x5 },
{0x529e,0x5 },
{0x529f,0x28},
{0x52a0,0x32},
{0x52a2,0x0 },
{0x52a3,0x2 },
{0x52a4,0x0 },
{0x52a5,0x4 },
{0x52a6,0x0 },
{0x52a7,0x8 },
{0x52a8,0x0 },
{0x52a9,0x10},
{0x52aa,0x0 },
{0x52ab,0x38},
{0x52ac,0x0 },
{0x52ad,0x3c},
{0x52ae,0x0 },
{0x52af,0x4c},
{0x5842,0x02},
{0x5843,0x5e},
{0x5844,0x04},
{0x5845,0x32},
{0x5846,0x03},
{0x5847,0x29},
{0x5848,0x02},
{0x5849,0xcc},
{0x5800,0x22},
{0x5801,0x1e},
{0x5802,0x1a},
{0x5803,0x1a},
{0x5804,0x1f},
{0x5805,0x26},
{0x5806,0xe },
{0x5807,0x9 },
{0x5808,0x7 },
{0x5809,0x8 },
{0x580a,0xb },
{0x580b,0x11},
{0x580c,0x5 },
{0x580d,0x2 },
{0x580e,0x0 },
{0x580f,0x0 },
{0x5810,0x3 },
{0x5811,0x7 },
{0x5812,0x4 },
{0x5813,0x1 },
{0x5814,0x0 },
{0x5815,0x0 },
{0x5816,0x3 },
{0x5817,0x7 },
{0x5818,0xc },
{0x5819,0x8 },
{0x581a,0x6 },
{0x581b,0x6 },
{0x581c,0x9 },
{0x581d,0x10},
{0x581e,0x20},
{0x581f,0x1b},
{0x5820,0x17},
{0x5821,0x18},
{0x5822,0x1d},
{0x5823,0x23},
{0x5824,0x5b},
{0x5825,0x6e},
{0x5826,0x6e},
{0x5827,0x7e},
{0x5828,0xab},
{0x5829,0x5e},
{0x582a,0x8a},
{0x582b,0x8a},
{0x582c,0x8a},
{0x582d,0x9d},
{0x582e,0x5b},
{0x582f,0x88},
{0x5830,0x88},
{0x5831,0x98},
{0x5832,0x9a},
{0x5833,0x4e},
{0x5834,0x8a},
{0x5835,0x79},
{0x5836,0x7a},
{0x5837,0xad},
{0x5838,0x9b},
{0x5839,0x9d},
{0x583a,0xad},
{0x583b,0x8e},
{0x583c,0x5c},
{0x583e,0x08},
{0x583f,0x04},
{0x5840,0x10},
{0x5480,0x07},
{0x5481,0x16},
{0x5482,0x2c},
{0x5483,0x4d},
{0x5484,0x59},
{0x5485,0x64},
{0x5486,0x6e},
{0x5487,0x76},
{0x5488,0x7f},
{0x5489,0x86},
{0x548a,0x94},
{0x548b,0xa3},
{0x548c,0xba},
{0x548d,0xd2},
{0x548e,0xe9},
{0x548f,0x1e},
{0x5490,0x0f},
{0x5491,0xff},
{0x5492,0x0e},
{0x5493,0x34},
{0x5494,0x07},
{0x5495,0x1a},
{0x5496,0x04},
{0x5497,0x0e},
{0x5498,0x03},
{0x5499,0x82},
{0x549a,0x03},
{0x549b,0x20},
{0x549c,0x02},
{0x549d,0xd7},
{0x549e,0x02},
{0x549f,0xa5},
{0x54a0,0x02},
{0x54a1,0x75},
{0x54a2,0x02},
{0x54a3,0x55},
{0x54a4,0x02},
{0x54a5,0x1c},
{0x54a6,0x01},
{0x54a7,0xea},
{0x54a8,0x01},
{0x54a9,0xae},
{0x54aa,0x01},
{0x54ab,0x7c},
{0x54ac,0x01},
{0x54ad,0x57},
{0x5180,0xf0},
{0x5181,0x00},
{0x5182,0x41},
{0x5183,0x42},
{0x5184,0x8f},
{0x5185,0x63},
{0x5186,0xce},
{0x5187,0xa8},
{0x5188,0x17},
{0x5189,0x1f},
{0x518a,0x27},
{0x518b,0x41},
{0x518c,0x34},
{0x518d,0xf0},
{0x518e,0x10},
{0x518f,0xff},
{0x5190,0x00},
{0x5191,0xff},
{0x5192,0x00},
{0x5193,0xff},
{0x5194,0x00},
{0x5380,0x1 },
{0x5381,0x0 },
{0x5382,0x0 },
{0x5383,0x17},
{0x5384,0x0 },
{0x5385,0x1 },
{0x5386,0x0 },
{0x5387,0x0 },
{0x5388,0x0 },
{0x5389,0xad},
{0x538a,0x0 },
{0x538b,0x11},
{0x538c,0x0 },
{0x538d,0x0 },
{0x538e,0x0 },
{0x538f,0x7 },
{0x5390,0x0 },
{0x5391,0x80},
{0x5392,0x0 },
{0x5393,0xa0},
{0x5394,0x18},
{0x3c0a,0x9c},
{0x3c0b,0x3f},
{0x5501,0x14},
{0x5502,0x00},
{0x5503,0x40},
{0x5504,0x00},
{0x5505,0x80},
{0x0100,0x01},
{0xFF, 0xFF}
};
const struct ov_reg ov9740_yuv_sxga[]= {
//@@ WXGA 1280x720 YUV DVP 15FPS for card reader
{0x0103, 0x01},
{0x3026, 0x00},
{0x3027, 0x00},
{0x3002, 0xe8},
{0x3004, 0x03},
{0x3005, 0xff},
{0x3406, 0x00},
{0x3603, 0xaa},
{0x3632, 0x27},
{0x3620, 0x66},
{0x3621, 0xc0},
{0x3631, 0x5e},
{0x3633, 0x50},
{0x3630, 0xd2},
{0x3604, 0x0c},
{0x3601, 0x40},
{0x3602, 0x16},
{0x3610, 0xa1},
{0x3612, 0x24},
{0x3622, 0x9f},
{0x3703, 0x42},
{0x3704, 0x10},
{0x3705, 0x45},
{0x3707, 0x14},
{0x3833, 0x04},
{0x3835, 0x03},
{0x3819, 0x6e},
{0x3817, 0x94},
{0x3503, 0x10},
{0x3a18, 0x00},
{0x3a19, 0x7f},
{0x3a11, 0xa0},
{0x3a1a, 0x05},
{0x3a1b, 0x50},
{0x3a0f, 0x50},
{0x3a10, 0x4c},
{0x3a1e, 0x4c},
{0x3a1f, 0x26},
{0x4002, 0x45},
{0x4005, 0x18},
{0x4702, 0x04},
{0x4704, 0x00},
{0x4706, 0x08},
{0x5000, 0xff},
{0x5001, 0xef},
{0x5003, 0xff},
{0x3104,0x20},
{0x0305,0x03},
{0x0307,0x70},
{0x0303,0x01},
{0x0301,0x0a},
{0x3010,0x01},
{0x300c,0x02},
{0x0340, 0x03},
{0x0341, 0x07},
{0x0342, 0x06},
{0x0343, 0x62},
{0x034b, 0xd1},
{0x034c, 0x05},
{0x034d, 0x00},
{0x034e, 0x02},
{0x034f, 0xd0},
{0x0101, 0x01},
{0x3a08, 0x00},
{0x3a09, 0xe8},
{0x3a0e, 0x03},
{0x3a14, 0x15},
{0x3a15, 0xc6},
{0x3a0a, 0x00},
{0x3a0b, 0xc0},
{0x3a0d, 0x04},
{0x3a02, 0x18},
{0x3a03, 0x20},
{0x3c0a, 0x9c},
{0x3c0b, 0x3f},
{0x529a, 0x1 },
{0x529b, 0x2 },
{0x529c, 0x3 },
{0x529d, 0x5 },
{0x529e, 0x5 },
{0x529f, 0x28},
{0x52a0, 0x32},
{0x52a2, 0x0 },
{0x52a3, 0x2 },
{0x52a4, 0x0 },
{0x52a5, 0x4 },
{0x52a6, 0x0 },
{0x52a7, 0x8 },
{0x52a8, 0x0 },
{0x52a9, 0x10},
{0x52aa, 0x0 },
{0x52ab, 0x38},
{0x52ac, 0x0 },
{0x52ad, 0x3c},
{0x52ae, 0x0 },
{0x52af, 0x4c},
{0x5842, 0x02},
{0x5843, 0x5e},
{0x5844, 0x04},
{0x5845, 0x32},
{0x5846, 0x03},
{0x5847, 0x29},
{0x5848, 0x02},
{0x5849, 0xcc},
{0x5800, 0x22},
{0x5801, 0x1e},
{0x5802, 0x1a},
{0x5803, 0x1a},
{0x5804, 0x1f},
{0x5805, 0x26},
{0x5806, 0xe },
{0x5807, 0x9 },
{0x5808, 0x7 },
{0x5809, 0x8 },
{0x580a, 0xb },
{0x580b, 0x11},
{0x580c, 0x5 },
{0x580d, 0x2 },
{0x580e, 0x0 },
{0x580f, 0x0 },
{0x5810, 0x3 },
{0x5811, 0x7 },
{0x5812, 0x4 },
{0x5813, 0x1 },
{0x5814, 0x0 },
{0x5815, 0x0 },
{0x5816, 0x3 },
{0x5817, 0x7 },
{0x5818, 0xc },
{0x5819, 0x8 },
{0x581a, 0x6 },
{0x581b, 0x6 },
{0x581c, 0x9 },
{0x581d, 0x10},
{0x581e, 0x20},
{0x581f, 0x1b},
{0x5820, 0x17},
{0x5821, 0x18},
{0x5822, 0x1d},
{0x5823, 0x23},
{0x5824, 0x5b},
{0x5825, 0x6e},
{0x5826, 0x6e},
{0x5827, 0x7e},
{0x5828, 0xab},
{0x5829, 0x5e},
{0x582a, 0x8a},
{0x582b, 0x8a},
{0x582c, 0x8a},
{0x582d, 0x9d},
{0x582e, 0x5b},
{0x582f, 0x88},
{0x5830, 0x88},
{0x5831, 0x98},
{0x5832, 0x9a},
{0x5833, 0x4e},
{0x5834, 0x8a},
{0x5835, 0x79},
{0x5836, 0x7a},
{0x5837, 0xad},
{0x5838, 0x9b},
{0x5839, 0x9d},
{0x583a, 0xad},
{0x583b, 0x8e},
{0x583c, 0x5c},
{0x583e, 0x08},
{0x583f, 0x04},
{0x5840, 0x10},
{0x5480, 0x07},
{0x5481, 0x16},
{0x5482, 0x2c},
{0x5483, 0x4d},
{0x5484, 0x59},
{0x5485, 0x64},
{0x5486, 0x6e},
{0x5487, 0x76},
{0x5488, 0x7f},
{0x5489, 0x86},
{0x548a, 0x94},
{0x548b, 0xa3},
{0x548c, 0xba},
{0x548d, 0xd2},
{0x548e, 0xe9},
{0x548f, 0x1e},
{0x5490, 0x0f},
{0x5491, 0xff},
{0x5492, 0x0e},
{0x5493, 0x34},
{0x5494, 0x07},
{0x5495, 0x1a},
{0x5496, 0x04},
{0x5497, 0x0e},
{0x5498, 0x03},
{0x5499, 0x82},
{0x549a, 0x03},
{0x549b, 0x20},
{0x549c, 0x02},
{0x549d, 0xd7},
{0x549e, 0x02},
{0x549f, 0xa5},
{0x54a0, 0x02},
{0x54a1, 0x75},
{0x54a2, 0x02},
{0x54a3, 0x55},
{0x54a4, 0x02},
{0x54a5, 0x1c},
{0x54a6, 0x01},
{0x54a7, 0xea},
{0x54a8, 0x01},
{0x54a9, 0xae},
{0x54aa, 0x01},
{0x54ab, 0x7c},
{0x54ac, 0x01},
{0x54ad, 0x57},
{0x5180, 0xf0},
{0x5181, 0x00},
{0x5182, 0x41},
{0x5183, 0x42},
{0x5184, 0x8f},
{0x5185, 0x63},
{0x5186, 0xce},
{0x5187, 0xa8},
{0x5188, 0x17},
{0x5189, 0x1f},
{0x518a, 0x27},
{0x518b, 0x41},
{0x518c, 0x34},
{0x518d, 0xf0},
{0x518e, 0x10},
{0x518f, 0xff},
{0x5190, 0x00},
{0x5191, 0xff},
{0x5192, 0x00},
{0x5193, 0xff},
{0x5194, 0x00},
{0x5380, 0x1 },
{0x5381, 0x0 },
{0x5382, 0x0 },
{0x5383, 0x17},
{0x5384, 0x0 },
{0x5385, 0x1 },
{0x5386, 0x0 },
{0x5387, 0x0 },
{0x5388, 0x0 },
{0x5389, 0xad},
{0x538a, 0x0 },
{0x538b, 0x11},
{0x538c, 0x0 },
{0x538d, 0x0 },
{0x538e, 0x0 },
{0x538f, 0x7 },
{0x5390, 0x0 },
{0x5391, 0x80},
{0x5392, 0x0 },
{0x5393, 0xa0},
{0x5394, 0x18},
{0x3c0a, 0x9c},
{0x3c0b, 0x3f},
{0x5501, 0x14},
{0x5502, 0x00},
{0x5503, 0x40},
{0x5504, 0x00},
{0x5505, 0x80},
{0x5308, 0x40},
{0x5309, 0x60},
{0x3a11, 0xd0},
{0x3a1b, 0x78},
{0x3a0f, 0x78},
{0x3a10, 0x68},
{0x3a1e, 0x68},
{0x3a1f, 0x40},
{0x0100, 0x01},
{0xFF, 0xFF}
};

224
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/qt1070.c Normal file
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@ -0,0 +1,224 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation QT1070 driver.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* \brief Read one byte of data from QT1070 Register.
*
* \param pTwid Pointer to twi driver structure.
* \param regAddr Register address to read.
* \return value in the given register.
*/
static uint8_t QT1070_ReadReg(Twid *pTwid, uint8_t regAddr)
{
uint8_t data;
TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, &regAddr, 1, 0);
TWID_Read(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, &data, 1, 0);
return data;
}
/**
* \brief Write one byte of data to QT1070 Register.
*
* \param pTwid Pointer to twi driver structure.
* \param regAddr Register address to write.
* \param data Data to write.
*/
static void QT1070_WriteReg(Twid *pTwid, uint32_t regAddr, uint8_t data)
{
TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, regAddr, 1, &data, 1, 0);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Get qt1070 chip ID.
*
* \param pTwid Pointer to twi driver structure.
* \return Chip Id
*/
uint8_t QT1070_GetChipId(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_CHIP_ID);
}
/**
* \brief Get qt1070 firmware version number.
*
* \param pTwid Pointer to twi driver structure.
* \return Firmware version number.
*/
uint8_t QT1070_GetFirmwareVersion(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_FIRMWARE_VERSION);
}
/**
* \brief Get qt1070 detection status.
*
* \param pTwid Pointer to twi driver structure.
* \return Dectection status.
*/
uint8_t QT1070_GetDetection_Status(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_DETECTION_STATUS);
}
/**
* \brief Get qt1070 Key status.
*
* \param pTwid Pointer to twi driver structure.
* \return Key status.
*/
uint8_t QT1070_GetKey_Status(Twid *pTwid)
{
return QT1070_ReadReg( pTwid, QT1070_REG_KEY_STATUS);
}
/**
* \brief Get qt1070 key signal value in the given Key. These are the key's
* of 16-bit key signals which are accessed as two 8-bit bytes,stored MSB first
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \return Key signal value.
*/
uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key)
{
uint8_t data[2];
data[0] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_MSB + key * 2);
data[1] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_LSB + key * 2);
return (data[0] << 8) | data[1];
}
/**
* \brief Get qt1070 key reference data in the given Key. These are the key's
* of 16-bit key reference data which are accessed as two 8-bit bytes, stored MSB first
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \return Key reference data.
*/
uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key)
{
uint8_t data[2];
data[0] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_MSB + key * 2);
data[1] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_LSB + key * 2);
return (data[0] << 8) | data[1];
}
/**
* \brief Set the threshold value for the given Key.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param threshold Threshold value.
*/
void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold)
{
// Do not use a setting of 0 as this causes a key to go into detection
// when its signal is equal to its reference.
if ( threshold )
{
QT1070_WriteReg(pTwid, QT1070_REG_NTHR_KEY0 + key, threshold);
}
}
/**
* \brief Set Averaging factor and adjacent key suppression for the given Key.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param Ave Averaging factor.
* \param Aks AKS group index.
*/
void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks)
{
QT1070_WriteReg(pTwid, QT1070_REG_AVEAKS_KEY0 + key, (Ave << 3) | Aks );
}
/**
* \brief Set DI level for the given Key. This 8-bit value controls the number
* of consecutive measurement that must be confirmed as having passed the key threshold
* before that key is registered as being in detect.
*
* \param pTwid Pointer to twi driver structure.
* \param key Key index.
* \param di DI level.
*/
void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di)
{
QT1070_WriteReg(pTwid, QT1070_REG_DI_KEY0 + key, di);
}
/**
* \brief Start a calibration cycle, the CALIBTATE flag in the detection status
* register is set when the calibration begins and clears when the calibration
* has finished.
*
* \param pTwid Pointer to twi driver structure.
*/
void QT1070_StartCalibrate(Twid *pTwid)
{
QT1070_WriteReg(pTwid, QT1070_REG_CALIRATE , 1);
}
/**
* \brief Reset the qt1070 device.
*
* \param pTwid Pointer to twi driver structure.
*/
void QT1070_StartReset(Twid *pTwid)
{
QT1070_WriteReg(pTwid, QT1070_REG_RESET , 1);
}

67
FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/rand.c Normal file
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@ -0,0 +1,67 @@
/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Header
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Global Variables
*------------------------------------------------------------------------------*/
static uint32_t _dwRandNext=1 ;
/*------------------------------------------------------------------------------
* Exported Functions
*------------------------------------------------------------------------------*/
/**
* Initialize the seed for rand generator.
*
* \param seed rand initiation seed
*/
extern void srand( uint32_t dwSeed )
{
_dwRandNext = dwSeed ;
}
/**
* Return a random number, maxinum assumed to be 65536
*/
extern uint32_t rand( void )
{
_dwRandNext = _dwRandNext * 1103515245 + 12345 ;
return (uint32_t)(_dwRandNext/131072) % 65536 ;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
* Implement simple PIT usage as system tick.
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Tick Counter united by ms */
static volatile uint32_t _dwTickCount = 0 ;
/*----------------------------------------------------------------------------
* Exported Functions
*----------------------------------------------------------------------------*/
/**
* \brief Handler for Sytem Tick interrupt.
*/
extern void TimeTick_Increment( uint32_t dwInc )
{
_dwTickCount += dwInc;
}
/**
* \brief Configures the PIT & reset tickCount.
* Systick interrupt handler will generates 1ms interrupt and increase a
* tickCount.
* \note IRQ handler must be configured before invoking this function.
* \note PIT is enabled automatically in this function.
* \param new_mck Current master clock.
*/
extern uint32_t TimeTick_Configure( uint32_t new_mck )
{
_dwTickCount = 0 ;
PIT_Init( 1000, new_mck / 1000000 );
PIT_EnableIT();
PIT_Enable();
return 0;
}
/**
* Get Delayed number of tick
* \param startTick Start tick point.
* \param endTick End tick point.
*/
extern uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick)
{
if (endTick >= startTick) return (endTick - startTick);
return (endTick + (0xFFFFFFFF - startTick) + 1);
}
/**
* \brief Get current Tick Count, in ms.
*/
extern uint32_t GetTickCount( void )
{
return _dwTickCount ;
}
/**
* \brief Sync Wait for several ms
*/
extern void Wait( volatile uint32_t dwMs )
{
uint32_t dwStart ;
uint32_t dwCurrent ;
dwStart = _dwTickCount ;
do
{
dwCurrent = _dwTickCount ;
} while ( dwCurrent - dwStart < dwMs ) ;
}
/**
* \brief Sync Sleep for several ms
*/
extern void Sleep( volatile uint32_t dwMs )
{
uint32_t dwStart ;
uint32_t dwCurrent ;
__ASM("CPSIE I");
dwStart = _dwTickCount ;
do
{
dwCurrent = _dwTickCount ;
if ( dwCurrent - dwStart > dwMs )
{
break ;
}
__ASM("WFI");
} while( 1 ) ;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "board.h"
/*------------------------------------------------------------------------------
* Internal variables
*------------------------------------------------------------------------------*/
/** Trace level can be set at applet initialization */
#if !defined(NOTRACE) && (DYN_TRACES == 1)
uint32_t dwTraceLevel = TRACE_LEVEL ;
#endif
/**
* Initializes the DBGU Console
*
* \param dwBaudRate U(S)ART baudrate.
* \param dwMCk Master clock frequency.
*/
extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk )
{
const Pin pinsDBUG[] = { PINS_DBGU } ;
PIO_Configure( pinsDBUG, PIO_LISTSIZE( pinsDBUG ) ) ;
DBGU_Configure( dwBaudRate, dwMCk ) ;
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
/** \addtogroup tsd_module
*@{
*/
#include <board.h>
#include <string.h>
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/** Size in pixels of calibration points. */
#define POINTS_SIZE 4
/** Maximum difference in pixels between the test point and the measured point.
*/
#define POINTS_MAX_XERROR 10
/** Maximum difference in pixels between the test point and the measured point.
*/
#define POINTS_MAX_YERROR 8
/** Delay at the end of calibartion for result display (positive or negative) */
#define DELAY_RESULT_DISPLAY 4000000
/** Clear Strings on LCD */
#if 1
#define CLEAR_STRING() LCDD_Fill(COLOR_WHITE)
#else
#define CLEAR_STRING() \
LCDD_DrawFilledRectangle(strX - 3*strW, strY, \
strX + 20*strW, strY + 6*strH, COLOR_WHITE)
#endif
/*----------------------------------------------------------------------------
* Local types
*----------------------------------------------------------------------------*/
/**
* Point used during the touchscreen calibration process.
*/
typedef struct _CalibrationPoint {
/** Coordinate of point along the X-axis of the screen. */
uint32_t x;
/** Coordinate of point along the Y-axis of the screen. */
uint32_t y;
/** Calibration data of point. */
uint32_t data[2];
} CalibrationPoint;
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Calibration display title */
static const char* strTitle = "LCD Calibration";
/** indicates if the touch screen has been calibrated.
If not, Callback functions are not called */
static volatile uint8_t bCalibrationOk = 0;
/** Slope for interpoling touchscreen measurements along the X-axis. */
static int32_t xSlope;
/** Slope for interpoling touchscreen measurements along the Y-axis. */
static int32_t ySlope;
/** Calibration points */
static CalibrationPoint calibrationPoints[] = {
/* Top-left corner calibration point */
{
BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Top-right corner calibration point */
{
BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Bottom-right corner calibration point */
{
BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
{0, 0}
},
/* Bottom-left corner calibration point */
{
BOARD_LCD_WIDTH / 10,
BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
{0, 0}
}
};
/** Test point */
static const CalibrationPoint testPoint = {
BOARD_LCD_WIDTH / 2,
BOARD_LCD_HEIGHT / 2,
{0, 0}
};
/*----------------------------------------------------------------------------
* External functions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Local functions
*----------------------------------------------------------------------------*/
/**
* Display a calibration point on the given buffer.
* \param pPoint Calibration point to display.
*/
static void DrawCalibrationPoint(
const CalibrationPoint *pPoint)
{
LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE / 2,
pPoint->y - POINTS_SIZE / 2,
pPoint->x + POINTS_SIZE,
pPoint->y + POINTS_SIZE,
COLOR_RED);
}
/**
* Clears a calibration point from the given buffer.
* \param pLcdBuffer LCD buffer to draw on.
* \param pPoint Calibration point to clear.
*/
static void ClearCalibrationPoint(
const CalibrationPoint *pPoint)
{
LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE,
pPoint->y - POINTS_SIZE,
pPoint->x + POINTS_SIZE,
pPoint->y + POINTS_SIZE,
COLOR_WHITE);
}
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* Indicates if the calibration of the touch screen is Ok
* \return 1 calibration Ok, 0 if not
*/
uint8_t TSDCom_IsCalibrationOk(void)
{
return bCalibrationOk;
}
/**
* Interpolates the provided raw measurements using the previously calculated
* slope. The resulting x and y coordinates are stored in an array.
* \param pData Raw measurement data, as returned by TSD_GetRawMeasurement().
* \param pPoint Array in which x and y will be stored.
*/
void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint)
{
pPoint[0] = calibrationPoints[0].x
- (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024)
/ xSlope;
pPoint[1] = calibrationPoints[0].y
- (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024)
/ ySlope;
/* Is pPoint[0] negative ? */
if(pPoint[0] & 0x80000000) pPoint[0] = 0;
/* Is pPoint[0] bigger than the LCD width ? */
if(pPoint[0] > BOARD_LCD_WIDTH) pPoint[0] = BOARD_LCD_WIDTH;
/* Is pPoint[1] negative ? */
if(pPoint[1] & 0x80000000) pPoint[1] = 0;
/* Is pPoint[1] bigger than the LCD width ? */
if(pPoint[1] > BOARD_LCD_HEIGHT) pPoint[1] = BOARD_LCD_HEIGHT;
}
/**
* Performs the calibration process using the provided buffer to display
* information.
* \param pLcdBuffer LCD buffer to display.
* \return True if calibration was successful; otherwise false.
*/
uint8_t TSDCom_Calibrate(void)
{
uint32_t i; // to keep the tempo with gcc code optimisation
int32_t slope1, slope2;
CalibrationPoint measuredPoint;
uint8_t xOk, yOk;
int32_t xDiff, yDiff;
uint32_t strX = BOARD_LCD_WIDTH / 2 - 75, strY = 60;
uint32_t strW, strH;
LCDD_GetStringSize("P", &strW, &strH);
/* Calibration setup */
LCDD_Fill(COLOR_WHITE);
LCDD_Flush_CurrentCanvas();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_Flush_CurrentCanvas();
LCDD_DrawString(strX - 2*strW, strY + 3*strH,
" Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE);
LCDD_Flush_CurrentCanvas();
/* Calibration points */
for (i = 0; i < 4; i++) {
DrawCalibrationPoint(&calibrationPoints[i]);
LCDD_Flush_CurrentCanvas();
/* Wait for touch & end of conversion */
TSD_WaitPenPressed();
TSD_GetRawMeasurement(calibrationPoints[i].data);
ClearCalibrationPoint(&calibrationPoints[i]);
LCDD_Flush_CurrentCanvas();
/* Wait for contact loss */
TSD_WaitPenReleased();
printf("P%d: (%d,%d)\n\r", (unsigned int)i, (unsigned int)calibrationPoints[i].data[0], (unsigned int)calibrationPoints[i].data[1]);
}
/* Calculate slopes using the calibration data
* Theory behind those calculations:
* - We suppose the touchscreen measurements are linear, so the following equations are true (simple
* linear regression) for any two 'a' and 'b' points of the screen:
* dx = (a.data[0] - b.data[0]) / (a.x - b.x)
* dy = (a.data[1] - b.data[1]) / (a.y - b.y)
*
* - We calculate dx and dy (called xslope and yslope here) using the calibration points.
*
* - We can then use dx and dy to infer the position of a point 'p' given the measurements performed
* by the touchscreen ('c' is any of the calibration points):
* dx = (p.data[0] - c.data[0]) / (p.x - c.x)
* dy = (p.data[1] - c.data[1]) / (p.y - c.y)
* Thus:
* p.x = c.x - (p.data[0] - c.data[0]) / dx
* p.y = c.y - (p.data[1] - c.data[1]) / dy
*
* - Since there are four calibration points, dx and dy can be calculated twice, so we average
* the two values.
*/
slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]);
slope1 *= 1024;
slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x);
slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]);
slope2 *= 1024;
slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x);
xSlope = (slope1 + slope2) / 2;
slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]);
slope1 *= 1024;
slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y);
slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]);
slope2 *= 1024;
slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y);
ySlope = (slope1 + slope2) / 2;
printf("Slope: %d, %d\n\r", (unsigned int)xSlope, (unsigned int)ySlope);
/* Test point */
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX - 2*strW, strY + 3*strH,
" Touch the point to\nvalidate calibration", COLOR_DARKBLUE);
LCDD_Flush_CurrentCanvas();
DrawCalibrationPoint(&testPoint);
LCDD_Flush_CurrentCanvas();
/* Wait for touch & end of conversion */
TSD_WaitPenPressed();
TSD_GetRawMeasurement(measuredPoint.data);
TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint);
DrawCalibrationPoint(&measuredPoint);
LCDD_Flush_CurrentCanvas();
/* Check resulting x and y */
xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x;
yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y;
xOk = (xDiff >= -POINTS_MAX_XERROR) && (xDiff <= POINTS_MAX_XERROR);
yOk = (yDiff >= -POINTS_MAX_YERROR) && (yDiff <= POINTS_MAX_YERROR);
/* Wait for contact loss */
TSD_WaitPenReleased();
printf("TP: %d, %d -> %d, %d\n\r",
(unsigned int)measuredPoint.data[0], (unsigned int)measuredPoint.data[1],
(unsigned int)measuredPoint.x, (unsigned int)measuredPoint.y);
/* Check calibration result */
if (xOk && yOk) {
bCalibrationOk = 1;
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX + 3*strW, strY + 2*strH, "Success !", COLOR_GREEN);
LCDD_Flush_CurrentCanvas();
}
else {
bCalibrationOk = 0;
CLEAR_STRING();
LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK);
LCDD_DrawString(strX + strW, strY + 2*strH, "Error too big", COLOR_RED);
LCDD_Flush_CurrentCanvas();
TRACE_WARNING("X %u, Y %u; Diff %d, %d\n\r",
(unsigned int)(measuredPoint.x), (unsigned int)(measuredPoint.y), (unsigned int)xDiff, (unsigned int)yDiff);
}
/* Slight delay */
for (i = 0; i < DELAY_RESULT_DISPLAY; i++);
LCDD_Flush_CurrentCanvas();
return (xOk && yOk);
}
/**
* Read calibrate data to buffer.
* \param pBuffer Data buffer.
* \param size Size of data buffer in bytes.
*/
void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size)
{
uint8_t *pDest = (uint8_t *)pBuffer;
memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk));
pDest += sizeof(bCalibrationOk);
memcpy(pDest, &xSlope, sizeof(xSlope));
pDest += sizeof(xSlope);
memcpy(pDest, &ySlope, sizeof(ySlope));
pDest += sizeof(ySlope);
memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data));
pDest += sizeof(calibrationPoints[0].data);
}
/**
* Restore calibrate data with buffer data.
* \param pBuffer Data buffer.
* \param size Size of data buffer in bytes.
*/
void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size)
{
uint8_t *pSrc = (uint8_t *)pBuffer;
memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk));
pSrc += sizeof(bCalibrationOk);
memcpy(&xSlope, pSrc, sizeof(xSlope));
pSrc += sizeof(xSlope);
memcpy(&ySlope, pSrc, sizeof(ySlope));
pSrc += sizeof(ySlope);
memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data));
pSrc += sizeof(calibrationPoints[0].data);
}
/**@}*/

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <board.h>
#include <string.h>
#ifdef REG_ADC_TSMR
/** \addtogroup tsd_module
*@{
*/
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/** SWAP X & Y */
#define TS_XY_SWAP
/** Status that used for touchscreen */
#define TS_STATUSES ( ADC_ISR_PENS | ADC_ISR_PEN | ADC_ISR_NOPEN \
| ADC_ISR_XRDY | ADC_ISR_YRDY | ADC_ISR_PRDY )
/*----------------------------------------------------------------------------
* Local types
*----------------------------------------------------------------------------*/
/** X value is ready */
#define TS_X_RDY (1 << 0)
/** Y value is ready */
#define TS_Y_RDY (1 << 1)
/** Pressure value is ready */
#define TS_P_RDY (1 << 2)
/** Pen status */
#define TS_PEN_STAT (1 << 7)
/** All data is ready (X,Y & P) */
#define TS_DATA_RDY (TS_X_RDY|TS_Y_RDY|TS_P_RDY)
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
/** Raw register value */
static uint32_t dwRaw[3];
/** Touchscreen data sampling results */
static uint32_t dwTsData[3];
/** Last Touchscreen sampling results */
static uint32_t dwLastTsData[3];
/** Touchscreen data ready */
static uint8_t bTsFlags = 0;
/*----------------------------------------------------------------------------
* External functions
*----------------------------------------------------------------------------*/
extern uint32_t TSD_GetRaw(uint32_t i);
/**
* Return raw register value.
*/
uint32_t TSD_GetRaw(uint32_t i)
{
return dwRaw[i];
}
/*----------------------------------------------------------------------------
* Local definitions
*----------------------------------------------------------------------------*/
/**
* Interrupt handler for the TouchScreen.
* Handles pen press, pen move and pen release events
* by invoking three callback functions.
*/
void TSD_Handler(uint32_t dwAdcStatus)
{
Adc *pAdc = ADC;
uint32_t status;
/* TSADC status */
status = dwAdcStatus;
status &= /*ADC_GetItMask(pAdc) &*/ TS_STATUSES;
if (status == 0) return;
/* Pen released */
if (status & ADC_ISR_NOPEN)
{
if ((bTsFlags & TS_PEN_STAT) == 0)
{
/* Register last data */
memcpy(dwLastTsData, dwTsData, sizeof(dwTsData));
/* Invoke PenReleased callback */
if (TSDCom_IsCalibrationOk())
TSD_PenReleased(dwTsData[0], dwTsData[1]);
}
bTsFlags = 0;
/* Stop periodic trigger & enable pen */
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE);
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
/* Disable pen release detect */
ADC_DisableIt(pAdc, ADC_IDR_NOPEN);
/* Enable pen press detect */
ADC_EnableIt(pAdc, ADC_IER_PEN);
}
/* Pen pressed */
else if (status & ADC_ISR_PEN)
{
bTsFlags |= TS_PEN_STAT;
/* Configure for peripdic trigger */
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_AVG8CONV);
ADC_SetTsDebounce(pAdc, 300); /* 300ns */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PERIOD_TRIG);
/* Disable pen press detect */
ADC_DisableIt(pAdc, ADC_IDR_PEN);
/* Enable pen release detect */
ADC_EnableIt(pAdc, ADC_IER_NOPEN|ADC_IER_XRDY|ADC_IER_YRDY|ADC_IER_PRDY);
}
else if (status & ADC_ISR_PENS)
{
/* X */
if (status & ADC_ISR_XRDY)
{
bTsFlags |= TS_X_RDY;
}
/* Y */
if (status & ADC_ISR_YRDY)
{
bTsFlags |= TS_Y_RDY;
}
/* P: (X/1024)*[(Z2/Z1)-1] */
if (status & ADC_ISR_PRDY)
{
bTsFlags |= TS_P_RDY;
}
}
/* X,Y,P are ready */
if ((bTsFlags & TS_DATA_RDY) == TS_DATA_RDY)
{
uint32_t xpos, z2, z1;
bTsFlags &= ~TS_DATA_RDY;
/* Get X,Y */
TSD_GetRawMeasurement(dwRaw);
/* Interprate X,Y */
TSDCom_InterpolateMeasurement(dwRaw, dwTsData);
/* Get P: Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1] */
dwRaw[2] = ADC_GetTsPressure(pAdc);
#ifdef TS_XY_SWAP
xpos = (dwRaw[1]);
#else
xpos = (dwRaw[0]);
#endif
xpos = (xpos & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos;
z2 = (dwRaw[2] & ADC_PRESSR_Z2_Msk) >> ADC_PRESSR_Z2_Pos;
z1 = (dwRaw[2] & ADC_PRESSR_Z1_Msk) >> ADC_PRESSR_Z1_Pos;
dwTsData[2] = (xpos) * (z2 - z1) / z1;
/* PenPress */
if (bTsFlags & TS_PEN_STAT)
{
bTsFlags &= ~TS_PEN_STAT;
/* Invoke PenPress callback */
if (TSDCom_IsCalibrationOk())
TSD_PenPressed(dwTsData[0], dwTsData[1], dwTsData[2]);
}
/* Periodic if data change invoke callback */
if (dwTsData[0] != dwLastTsData[0]
|| dwTsData[1] != dwLastTsData[1]
|| dwTsData[2] != dwLastTsData[2] )
{
/* Register last data */
memcpy(dwLastTsData, dwTsData, sizeof(dwTsData));
/* Invoke PenMoved callback */
if (TSDCom_IsCalibrationOk())
TSD_PenMoved(dwTsData[0], dwTsData[1], dwTsData[2]);
}
}
}
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* Reads and store a touchscreen measurement in the provided array.
* The value stored are:
* - data[0] = XPOS * 1024 / XSCALE
* - data[1] = YPOS * 1024 / YSCALE
* \param pData Array where the measurements will be stored
*/
void TSD_GetRawMeasurement(uint32_t *pData)
{
Adc *pAdc = ADC;
uint32_t xr, yr;
#ifdef TS_XY_SWAP
yr = ADC_GetTsXPosition(pAdc);
xr = ADC_GetTsYPosition(pAdc);
#else
xr = ADC_GetTsXPosition(pAdc);
yr = ADC_GetTsYPosition(pAdc);
#endif
pData[0] = ((xr & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos) * 1024 * 4;
pData[0] /= ((xr & ADC_XPOSR_XSCALE_Msk) >> ADC_XPOSR_XSCALE_Pos);
pData[1] = ((yr & ADC_YPOSR_YPOS_Msk) >> ADC_YPOSR_YPOS_Pos) * 1024 * 4;
pData[1] /= ((yr & ADC_YPOSR_YSCALE_Msk) >> ADC_YPOSR_YSCALE_Pos);
}
/**
* Wait pen pressed
*/
void TSD_WaitPenPressed(void)
{
Adc *pAdc = ADC;
uint8_t bFlags = 0;
uint32_t dwStatus;
/* Wait for touch & end of conversion */
while (1)
{
dwStatus = ADC_GetStatus(pAdc);
if (dwStatus & ADC_ISR_PEN) bFlags |= 8;
if (dwStatus & ADC_ISR_XRDY)bFlags |= 1;
if (dwStatus & ADC_ISR_YRDY)bFlags |= 2;
if (dwStatus & ADC_ISR_PRDY)bFlags |= 4;
if (bFlags == 0xF) break;
}
}
/**
* Wait pen released
*/
void TSD_WaitPenReleased(void)
{
Adc *pAdc = ADC;
/* Wait for contact loss */
while((ADC_GetStatus(pAdc) & ADC_ISR_NOPEN) == 0);
}
/**
* Initializes the touchscreen driver and starts the calibration process. When
* finished, the touchscreen is operational.
* The configuration is taken from the board.h of the device being compiled.
* Important: the LCD driver must have been initialized prior to calling this
* function.
*/
void TSD_Initialize(void)
{
Adc *pAdc = ADC;
bTsFlags = 0;
/* Configuration */
PMC_EnablePeripheral(ID_ADC);
ADC_SetClock(pAdc, BOARD_TOUCHSCREEN_ADCCLK, BOARD_MCK);
ADC_SetStartupTime(pAdc, BOARD_TOUCHSCREEN_STARTUP);
ADC_SetTrackingTime(pAdc, BOARD_TOUCHSCREEN_SHTIM);
ADC_SetTriggerPeriod(pAdc, 20000000); /* 20ms */
ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_4_WIRE);
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_SetTsPenDetect(pAdc, 1);
ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE);
pAdc->ADC_MR &= ~(3<<28);
pAdc->ADC_ACR = 0x102;
}
/**
* Enable/Disable TSD capturing
*/
void TSD_Enable(uint8_t bEnDis)
{
Adc *pAdc = ADC;
if (bEnDis)
{
ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER);
ADC_TsCalibration(pAdc);
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
ADC_EnableIt(pAdc, ADC_IER_PEN);
}
else
{
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER);
ADC_DisableIt(pAdc, TS_STATUSES);
ADC_GetStatus(pAdc);
ADC_GetTsXPosition(pAdc);
ADC_GetTsYPosition(pAdc);
ADC_GetTsPressure(pAdc);
}
}
/**
* Do touchscreen calibration
* \param pLcdBuffer LCD buffer to use for displaying the calibration info.
* \return 1 if calibration is Ok, 0 else
*/
uint8_t TSD_Calibrate(void)
{
Adc *pAdc = ADC;
uint8_t ret = 0;
/* Calibration is done only once */
if(TSDCom_IsCalibrationOk()) return 1;
/* Disable touch */
TSD_Enable(0);
/* Enable capturing */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG);
/* Do calibration */
ret = TSDCom_Calibrate();
/* Configure interrupt generation
Do it only if the calibration is Ok. */
//TSD_Enable(ret);
return ret;
}
/**
* Reset/stop the touchscreen
*/
void TSD_DeInitialize(void)
{
Adc *pAdc = ADC;
/* Disable TS related interrupts */
ADC_DisableIt(pAdc, TS_STATUSES);
/* Disable Trigger */
ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER);
/* Disable TS mode */
ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_NONE);
bTsFlags = 0;
}
/**@}*/
#endif /* #ifdef REG_ADC_TSMR */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
#include <stdio.h>
/*----------------------------------------------------------------------------
* Definiation
*----------------------------------------------------------------------------*/
/* WAV letters "RIFF" */
#define WAV_CHUNKID 0x46464952
/* WAV letters "WAVE"*/
#define WAV_FORMAT 0x45564157
/* WAV letters "fmt "*/
#define WAV_SUBCHUNKID 0x20746D66
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Check if the header of a Wav file is valid ot not.
*
* \param file Buffer holding the file to examinate.
* \return 1 if the header of a Wav file is valid; otherwise returns 0.
*/
unsigned char WAV_IsValid(const WavHeader *header)
{
return ((header->chunkID == WAV_CHUNKID)
&& (header->format == WAV_FORMAT)
&& (header->subchunk1Size == 0x10));
}
/**
* \brief Display the information of the WAV file (sample rate, stereo/mono
* and frame size).
*
* \param header Wav head information.
*/
void WAV_DisplayInfo(const WavHeader *header)
{
printf( "Wave file header information\n\r");
printf( "--------------------------------\n\r");
printf( " - Chunk ID = 0x%08X\n\r", header->chunkID);
printf( " - Chunk Size = %u\n\r", header->chunkSize);
printf( " - Format = 0x%08X\n\r", header->format);
printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID);
printf( " - Subchunk1 Size = %u\n\r", header->subchunk1Size);
printf( " - Audio Format = 0x%04X\n\r", header->audioFormat);
printf( " - Num. Channels = %d\n\r", header->numChannels);
printf( " - Sample Rate = %u\n\r", header->sampleRate);
printf( " - Byte Rate = %u\n\r", header->byteRate);
printf( " - Block Align = %d\n\r", header->blockAlign);
printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample);
printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID);
printf( " - Subchunk2 Size = %u\n\r", header->subchunk2Size);
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Implementation WM8904 driver.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Read data from WM8904 Register.
*
* \param pTwid Pointer to twi driver structure
* \param device Twi slave address.
* \param regAddr Register address to read.
* \return value in the given register.
*/
uint16_t WM8904_Read(Twid *pTwid,
uint32_t device,
uint32_t regAddr)
{
uint16_t bitsDataRegister;
uint8_t Tdata[2]={0,0};
TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0);
bitsDataRegister = (Tdata[0] << 8) | Tdata[1];
return bitsDataRegister;
}
/**
* \brief Write data to WM8904 Register.
*
* \param pTwid Pointer to twi driver structure
* \param device Twi slave address.
* \param regAddr Register address to read.
* \param data Data to write
*/
void WM8904_Write(Twid *pTwid,
uint32_t device,
uint32_t regAddr,
uint16_t data)
{
uint8_t tmpData[2];
tmpData[0] = (data & 0xff00) >> 8;
tmpData[1] = data & 0xff;
TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0);
}
/**
* \brief Init WM8904 to DAC mode.
*
* \param pTwid Pointer to twi driver structure
* \param device Twi slave address.
* \return 0.
*/
uint8_t WM8904_Init(Twid *pTwid,
uint32_t device)
{
/* Software reset */
WM8904_Write(pTwid, device, WM8904_REG_RESET, 0x0000);
/* POBCTRL=1, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_BIAS_CTRL0, 0x0019);
/* VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_VMID_CTRL0, 0x0043);
/* MICDET_ENA=1, MICBIAS_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_MICBIAS_CTRL0, 0x0003);
/* ? */
WM8904_Write(pTwid, device, WM8904_REG_BIAS_CTRL1, 0xC000);
/* INL_ENA=1, INR_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG0, 0x0003);
/* HPL_PGA_ENA=1, HPR_PGA_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG2, 0x0003);
/* DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG6, 0x000F);
/* TOCLK_RATE_DIV16=0,TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 */
WM8904_Write(pTwid, device, WM8904_REG_CLOCK_RATE0, 0x845E);
/* SYSCLK_SRC=1, CLK_SYS_ENA=1, CLK_DSP_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_CLOCK_RATE2, 0x4006);
/* AIFADC_TCM=0, AIFADC_TCM_CHAN=0, BCLK_DIR=1 */
WM8904_Write(pTwid, device, WM8904_REG_AUD_INF1, 0x404A);
/* LRCLK=1, LRCLK_RATE=0x40 */
WM8904_Write(pTwid, device, WM8904_REG_AUD_INF3, 0x0840);
/* DAC_MCNO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_MUTE=0 */
WM8904_Write(pTwid, device, WM8904_REG_ADC_DIG1, 0x0000);
/* LINMUTE=0, LIN_VOL= 0 db */
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_LIN0, 0x0005);
/* RINMUTE=0, RIN_VOL= 0 db */
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_RIN0, 0x0005);
/* IN2L */
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_LIN1, 0x0010);
/* IN2R*/
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_RIN1, 0x0010);
/* HPOUTR_MUTE=1, HPOUTRZC=1, HPOUTR_VOL=0x1D */
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_ROUT1, 0x00AD);
/* DCS_ENA_CHAN_1=1, DCS_ENA_CHAN_0=1 */
WM8904_Write(pTwid, device, WM8904_REG_DC_SERVO0, 0x0003);
/* HPL_RMV_SHORT=1, HPL_ENA_OUTp=1, HPL_ENA_DLY=1, HPL_ENA=1
HPR_RMV_SHORT=1, HPR_ENA_OUTp=1, HPR_ENA_DLY=1, HPR_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_HP0, 0x00FF);
/* CP_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_CHARGE_PUMP0, 0x0001);
/* CP_DYN_PWR=1 */
WM8904_Write(pTwid, device, WM8904_REG_CLASS0, 0x0005);
/* FLL_FRACN_ENA=0, FLL_ENA=0 */
WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL1, 0x0000);
/* FLL_FRACN_ENA=1, FLL_ENA=1 */
WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL1, 0x0005);
/* FLL_FRATIO=4, FLL_OUTDIV= 7 */
WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL2, 0x0704);
/* Fractional multiply for Fref = 0x8000 */
WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL3, 0x8000);
/* FLL_GAIN=0, FLL_N=0x176 */
WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL4, 0x1760);
WM8904_Write(pTwid, device, WM8904_REG_END, 0x55AA);
return 0;
}
void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device)
{
//{ 0x0005, 44}, /** R44 - Analogue Left Input 0 */
//{ 0x0005, 45}, /** R45 - Analogue Right Input 0 */
//{ 0x0000, 46}, /** R46 - Analogue Left Input 1 */
//{ 0x0010, 47}, /** R47 - Analogue Right Input 1 */
WM8904_Write(pTwid, device, 0x2C, 0x0008);
WM8904_Write(pTwid, device, 0x2D, 0x0005);
WM8904_Write(pTwid, device, 0x2E, 0x0000);
WM8904_Write(pTwid, device, 0x2F, 0x0010);
}

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#ifndef _LIB_CHIP_SAMA5D3X_
#define _LIB_CHIP_SAMA5D3X_
/*
* Peripherals registers definitions
*/
#if defined sama5d3x
#include "include/SAMA5D3X.h"
#else
#warning Library does not support the specified chip, specifying ata5miura.
#define sama5d3x
#include "include/SAMA5D3X.h"
#endif
/* Define attribute */
#if defined ( __CC_ARM ) /* Keil µVision 4 */
#define WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
#define WEAK __weak
#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
#define WEAK __attribute__ ((weak))
#endif
/* Define NO_INIT attribute and compiler specific symbols */
#if defined ( __CC_ARM )
#define NO_INIT
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define NO_INIT __no_init
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define NO_INIT
#endif
#define CP15_PRESENT
/*
* Peripherals
*/
#include "include/mmu.h"
#include "cp15/cp15.h"
#include "include/rstc.h"
#include "include/adc.h"
#include "include/async.h"
#include "include/emac.h"
#include "include/gmac.h"
#include "include/hsmci.h"
#include "include/irq.h"
#include "include/fuse.h"
#include "include/pio.h"
#include "include/pio_it.h"
#include "include/pmc.h"
#include "include/pwmc.h"
#include "include/rtc.h"
#include "include/smcNfc.h"
#include "include/spi.h"
#include "include/ssc.h"
#include "include/tc.h"
#include "include/twi.h"
#include "include/twid.h"
#include "include/usart.h"
#include "include/pit.h"
#include "include/dmac.h"
#include "include/udphs.h"
#include "include/emac.h"
#include "include/can.h"
#include "include/trace.h"
#include "include/wdt.h"
#include "include/video.h"
#include "include/isi.h"
#include "include/aes.h"
#include "include/sha.h"
#include "include/tdes.h"
#include "include/trng.h"
#endif /* _LIB_CHIP_SAMA5D3X_ */

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
// core list
//-------------------
// arm7tdmi
// arm926ej_s
// arm1176jzf_s
// cortexm3
#ifndef _CORE_H
#define _CORE_H
#define cortex_a5
#endif // #ifndef _CORE_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
//-----------------------------------------------------------------------------
// Reg Reads Writes
//----------------------------------------------------------------------------
// 0 ID code Unpredictable
// 0 cache type Unpredictable
// 0 TCM status Unpredictable
// 1 Control Control
// 2 Translation table base Translation table base
// 3 Domain access control Domain access control
// 4 (Reserved)
// 5 Data fault status Data fault status
// 5 Instruction fault status Instruction fault status
// 6 Fault address Fault address
// 7 cache operations cache operations
// 8 Unpredictable TLB operations
// 9 cache lockdown cache lockdown
// 9 TCM region TCM region
// 10 TLB lockdown TLB lockdown
// 11 (Reserved)
// 12 (Reserved)
// 13 FCSE PID FCSE PID
// 13 Context ID Context ID
// 14 (Reserved)
// 15 Test configuration Test configuration
//-----------------------------------------------------------------------------
/** \page cp15_f CP15 Functions.
*
* \section CP15 function Usage
*
* Methods to manage the Coprocessor 15. Coprocessor 15, or System Control
* Coprocessor CP15, is used to configure and control all the items in the
* list below:
* <ul>
* <li> ARM core
* <li> caches (Icache, Dcache and write buffer)
* <li> TCM
* <li> MMU
* <li> Other system options
* </ul>
* \section Usage
*
* -# Enable or disable D cache with Enable_D_cache and Disable_D_cache
* -# Enable or disable I cache with Enable_I_cache and Disable_I_cache
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15.c.\n
*/
/** \file */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#if defined(__ICCARM__)
#include <intrinsics.h>
#endif
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Check Instruction cache
* \return 0 if I_cache disable, 1 if I_cache enable
*/
unsigned int CP15_IsIcacheEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & (1 << CP15_I_BIT)) != 0);
}
/**
* \brief Enable Instruction cache
*/
void CP15_EnableIcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is disabled
if ((control & (1 << CP15_I_BIT)) == 0) {
control |= (1 << CP15_I_BIT);
CP15_WriteControl(control);
TRACE_INFO("I cache enabled.\n\r");
}
#if !defined(OP_BOOTSTRAP_on)
else {
TRACE_INFO("I cache is already enabled.\n\r");
}
#endif
}
/**
* \brief Disable Instruction cache
*/
void CP15_DisableIcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is enabled
if ((control & (1 << CP15_I_BIT)) != 0) {
control &= ~(1ul << CP15_I_BIT);
CP15_WriteControl(control);
TRACE_INFO("I cache disabled.\n\r");
}
else {
TRACE_INFO("I cache is already disabled.\n\r");
}
}
/**
* \brief Check MMU
* \return 0 if MMU disable, 1 if MMU enable
*/
unsigned int CP15_IsMMUEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & (1 << CP15_M_BIT)) != 0);
}
/**
* \brief Enable MMU
*/
void CP15_EnableMMU(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if MMU is disabled
if ((control & (1 << CP15_M_BIT)) == 0) {
control |= (1 << CP15_M_BIT);
CP15_WriteControl(control);
TRACE_INFO("MMU enabled.\n\r");
}
else {
TRACE_INFO("MMU is already enabled.\n\r");
}
}
/**
* \brief Disable MMU
*/
void CP15_DisableMMU(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if MMU is enabled
if ((control & (1 << CP15_M_BIT)) != 0) {
control &= ~(1ul << CP15_M_BIT);
control &= ~(1ul << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("MMU disabled.\n\r");
}
else {
TRACE_INFO("MMU is already disabled.\n\r");
}
}
/**
* \brief Check D_cache
* \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course)
*/
unsigned int CP15_IsDcacheEnabled(void)
{
unsigned int control;
control = CP15_ReadControl();
return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);
}
/**
* \brief Enable Data cache
*/
void CP15_EnableDcache(void)
{
unsigned int control;
control = CP15_ReadControl();
if( !CP15_IsMMUEnabled() ) {
TRACE_ERROR("Do nothing: MMU not enabled\n\r");
}
else {
// Check if cache is disabled
if ((control & (1 << CP15_C_BIT)) == 0) {
control |= (1 << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("D cache enabled.\n\r");
}
else {
TRACE_INFO("D cache is already enabled.\n\r");
}
}
}
/**
* \brief Disable Data cache
*/
void CP15_DisableDcache(void)
{
unsigned int control;
control = CP15_ReadControl();
// Check if cache is enabled
if ((control & (1 << CP15_C_BIT)) != 0) {
control &= ~(1ul << CP15_C_BIT);
CP15_WriteControl(control);
TRACE_INFO("D cache disabled.\n\r");
}
else {
TRACE_INFO("D cache is already disabled.\n\r");
}
}

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _CP15_H
#define _CP15_H
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions
// change the PC:
// 0 = loads to PC set the T bit
// 1 = loads to PC do not set T bit
#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache:
// 0 = Random replacement
// 1 = Round-robin replacement.
#define CP15_V_BIT 13 // V bit Location of exception vectors:
// 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C
// 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C
#define CP15_I_BIT 12 // I bit Icache enable/disable:
// 0 = Icache disabled
// 1 = Icache enabled
#define CP15_R_BIT 9 // R bit ROM protection
#define CP15_S_BIT 8 // S bit System protection
#define CP15_B_BIT 7 // B bit Endianness:
// 0 = Little-endian operation
// 1 = Big-endian operation.
#define CP15_C_BIT 2 // C bit Dcache enable/disable:
// 0 = cache disabled
// 1 = cache enabled
#define CP15_A_BIT 1 // A bit Alignment fault enable/disable:
// 0 = Data address alignment fault checking disabled
// 1 = Data address alignment fault checking enabled
#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.
// 0 = disabled
// 1 = enabled
/** No access Any access generates a domain fault. */
#define CP15_DOMAIN_NO_ACCESS 0x00
/** Client Accesses are checked against the access permission bits in the section or page descriptor. */
#define CP15_DOMAIN_CLIENT_ACCESS 0x01
/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */
#define CP15_DOMAIN_MANAGER_ACCESS 0x03
/*------------------------------------------------------------------------------ */
/* Exported functions */
/*------------------------------------------------------------------------------ */
extern unsigned int CP15_ReadID(void);
extern unsigned int CP15_ReadControl(void);
extern void CP15_WriteControl(unsigned int value);
extern void CP15_WriteTTB(unsigned int value);
extern void CP15_WriteDomainAccessControl(unsigned int value);
extern void CP15_InvalidateIcacheInnerSharable(void);
extern void CP15_InvalidateBTBinnerSharable(void);
extern void CP15_InvalidateIcache(void);
extern void CP15_InvalidateIcacheByMva(void);
extern void CP15_FlushBTB(void);
extern void CP15_FlushBTBbyMva(void);
extern void CP15_InvalidateDcacheLineByMva(void);
extern void CP15_InvalidateDcacheLineBySetWay(void);
extern void CP15_CleanDCacheByMva(void);
extern void CP15_CleanDCacheBySetWay(void);
extern void CP15_CleanDCacheMva(void);
extern void CP15_CleanInvalidateDcacheLineByMva(void);
extern void CP15_CleanInvalidateDcacheLine(void);
extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size );
/*------------------------------------------------------------------------------ */
/* Exported functions from CP15.c */
/*------------------------------------------------------------------------------ */
/** MMU (Status/Enable/Disable) */
extern unsigned int CP15_IsMMUEnabled(void);
extern void CP15_EnableMMU(void);
extern void CP15_DisableMMU(void);
/** I cache (Status/Enable/Disable) */
extern unsigned int CP15_IsIcacheEnabled(void);
extern void CP15_EnableIcache(void);
extern void CP15_DisableIcache(void);
/** D cache (Status/Enable/Disable) */
extern unsigned int CP15_IsDcacheEnabled(void);
extern void CP15_EnableDcache(void);
extern void CP15_DisableDcache(void);
#endif // #ifndef _CP15_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA,
* OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/**
* \addtogroup cp15_cache Cache Operations
*
* \section Usage
*
* They are performed as MCR instructions and only operate on a level 1 cache associated with
* ATM v7 processor.
* The supported operations are:
* <ul>
* <li> Any of these operations can be applied to
* -# any data cache
* -# any unified cache.
* <li> Invalidate by MVA
* Performs an invalidate of a data or unified cache line based on the address it contains.
* <li> Invalidate by set/way
* Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean by MVA
* Performs a clean of a data or unified cache line based on the address it contains.
* <li> Clean by set/way
* Performs a clean of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean and Invalidate by MVA
* Performs a clean and invalidate of a data or unified cache line based on the address it contains.
* <li> Clean and Invalidate by set/way
* Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy.
* </ul>
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15_arm_gnu.S \n
*/
/*----------------------------------------------------------------------------
* Functions to access CP15 coprocessor register
*----------------------------------------------------------------------------*/
.global CP15_ReadID
.global CP15_ReadControl
.global CP15_WriteControl
.global CP15_WriteDomainAccessControl
.global CP15_WriteTTB
.global CP15_InvalidateIcacheInnerSharable
.global CP15_InvalidateBTBinnerSharable
.global CP15_InvalidateIcache
.global CP15_InvalidateIcacheByMva
.global CP15_FlushBTB
.global CP15_FlushBTBbyMva
.global CP15_InvalidateDcacheLineByMva
.global CP15_InvalidateDcacheLineBySetWay
.global CP15_CleanDCacheByMva
.global CP15_CleanDCacheBySetWay
.global CP15_CleanDCacheMva
.global CP15_CleanInvalidateDcacheLineByMva
.global CP15_CleanInvalidateDcacheLine
.global CP15_coherent_dcache_for_dma
.global CP15_invalidate_dcache_for_dma
.global CP15_clean_dcache_for_dma
.global CP15_flush_dcache_for_dma
.global CP15_flush_kern_dcache_for_dma
/**
* \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
* Reading from this register returns the device ID, the cache type, or the TCM status
* depending on the value of Opcode_2 used.
*/
.section .CP15_ReadID
.global CP15_ReadID
CP15_ReadID:
mov r0, #0
mrc p15, 0, r0, c0, c0, 0
bx lr
/**
* \brief Register c1 is the Control Register for the ARM926EJ-S processor.
* This register specifies the configuration used to enable and disable the
* caches and MMU. It is recommended that you access this register using a
* read-modify-write sequence
*/
.section .CP15_ReadControl
.global CP15_ReadControl
CP15_ReadControl:
mov r0, #0
mrc p15, 0, r0, c1, c0, 0
bx lr
.section .CP15_WriteControl
.global CP15_WriteControl
CP15_WriteControl:
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
.section .CP15_WriteDomainAccessControl
.global CP15_WriteDomainAccessControl
CP15_WriteDomainAccessControl:
mcr p15, 0, r0, c3, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief ARMv7A architecture supports two translation tables
* Configure translation table base (TTB) control register cp15,c2
* to a value of all zeros, indicates we are using TTB register 0.
* write the address of our page table base to TTB register 0.
*/
.section .CP15_WriteTTB
.global CP15_WriteTTB
CP15_WriteTTB:
mcr p15, 0, r0, c2, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief Invalidate I cache predictor array inner Sharable
*/
.section .CP15_InvalidateIcacheInnerSharable
.global CP15_InvalidateIcacheInnerSharable
CP15_InvalidateIcacheInnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 0
bx lr
/**
* \brief Invalidate entire branch predictor array inner Sharable
*/
.section .CP15_InvalidateBTBinnerSharable
.global CP15_InvalidateBTBinnerSharable
CP15_InvalidateBTBinnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
bx lr
/**
* \brief Invalidate all instruction caches to PoU, also flushes branch target cache
*/
.section .CP15_InvalidateIcache
.global CP15_InvalidateIcache
CP15_InvalidateIcache:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
bx lr
/**
* \brief Invalidate instruction caches by VA to PoU
*/
.section .CP15_InvalidateIcacheByMva
.global CP15_InvalidateIcacheByMva
CP15_InvalidateIcacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 1
bx lr
/**
* \brief Flush entire branch predictor array
*/
.section .CP15_FlushBTB
.global CP15_FlushBTB
CP15_FlushBTB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 6
bx lr
/**
* \brief Flush branch predictor array entry by MVA
*/
.section .CP15_FlushBTBbyMva
.global CP15_FlushBTBbyMva
CP15_FlushBTBbyMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 7
bx lr
/**
* \brief Invalidate data cache line by VA to Poc
*/
.section .CP15_InvalidateDcacheLineByMva
.global CP15_InvalidateDcacheLineByMva
CP15_InvalidateDcacheLineByMva:
mov r0, #0
mcr p15, 0, r0, c7, c6, 1
bx lr
/**
* \brief Invalidate data cache line by set/way
*/
.section .CP15_InvalidateDcacheLineBySetWay
.global CP15_InvalidateDcacheLineBySetWay
CP15_InvalidateDcacheLineBySetWay:
mov r0, #0
mcr p15, 0, r0, c7, c6, 2
bx lr
/**
* \brief Clean data cache line by MVA
*/
.section .CP15_CleanDCacheByMva
.global CP15_CleanDCacheByMva
CP15_CleanDCacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c10, 1
bx lr
/**
* \brief Clean data cache line by Set/way
*/
.section .CP15_CleanDCacheBySetWay
.global CP15_CleanDCacheBySetWay
CP15_CleanDCacheBySetWay:
mov r0, #0
mcr p15, 0, r0, c7, c10, 2
bx lr
/**
* \brief Clean unified cache line by MVA
*/
.section .CP15_CleanDCacheMva
.global CP15_CleanDCacheMva
CP15_CleanDCacheMva:
mov r0, #0
mcr p15, 0, r0, c7, c11, 1
bx lr
/**
* \brief Clean and invalidate data cache line by VA to PoC
*/
.section .CP15_CleanInvalidateDcacheLineByMva
.global CP15_CleanInvalidateDcacheLineByMva
CP15_CleanInvalidateDcacheLineByMva:
mov r0, #0
mcr p15, 0, r0, c7, c14, 1
bx lr
/**
* \brief Clean and Incalidate data cache line by Set/Way
*/
.section .CP15_CleanInvalidateDcacheLine
.global CP15_CleanInvalidateDcacheLine
CP15_CleanInvalidateDcacheLine:
mov r0, #0
mcr p15, 0, r0, c7, c14, 2
bx lr
/**
* \brief Ensure that the I and D caches are coherent within specified
* region. This is typically used when code has been written to
* a memory region, and will be executed.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_coherent_dcache_for_dma
.global CP15_coherent_dcache_for_dma
CP15_coherent_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r12, r0, r3
1:
mcr p15, 0, r12, c7, c11, 1
add r12, r12, r2
cmp r12, r1
blo 1b
dsb
mrc p15, 0, r3, c0, c0, 1
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r12, r0, r3
2:
mcr p15, 0, r12, c7, c5, 1
add r12, r12, r2
cmp r12, r1
blo 2b
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
mcr p15, 0, r0, c7, c5, 6
dsb
isb
bx lr
/**
* \brief Invalidate the data cache within the specified region; we will
* be performing a DMA operation in this region and we want to
* purge old data in the cache.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_invalidate_dcache_for_dma
.global CP15_invalidate_dcache_for_dma
CP15_invalidate_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
tst r0, r3
bic r0, r0, r3
mcrne p15, 0, r0, c7, c14, 1
tst r1, r3
bic r1, r1, r3
mcrne p15, 0, r1, c7, c14, 1
3:
mcr p15, 0, r0, c7, c6, 1
add r0, r0, r2
cmp r0, r1
blo 3b
dsb
bx lr
/**
* \brief Clean the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_clean_dcache_for_dma
.global CP15_clean_dcache_for_dma
CP15_clean_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r0, r0, r3
4:
mcr p15, 0, r0, c7, c10, 1
add r0, r0, r2
cmp r0, r1
blo 4b
dsb
bx lr
/**
* \brief Flush the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_flush_dcache_for_dma
.global CP15_flush_dcache_for_dma
CP15_flush_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
sub r3, r2, #1
bic r0, r0, r3
5:
mcr p15, 0, r0, c7, c14, 1
add r0, r0, r2
cmp r0, r1
blo 5b
dsb
bx lr
/**
* \brief CP15_flush_kern_dcache_for_dma
* Ensure that the data held in the page kaddr is written back to the page in question.
* \param start virtual start address of region
* \param end virtual end address of region
*/
.section .CP15_flush_kern_dcache_for_dma
.global CP15_flush_kern_dcache_for_dma
CP15_flush_kern_dcache_for_dma:
mrc p15, 0, r3, c0, c0, 1
lsr r3, r3, #16
and r3, r3, #0xf
mov r2, #4
mov r2, r2, lsl r3
add r1, r0, r1
sub r3, r2, #1
bic r0, r0, r3
mcr p15, 0, r0, c7, c14, 1
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
bx lr

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA,
* OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \file */
/** \file */
/**
* \addtogroup cp15_cache Cache Operations
*
* \section Usage
*
* They are performed as MCR instructions and only operate on a level 1 cache associated with
* ATM v7 processor.
* The supported operations are:
* <ul>
* <li> Any of these operations can be applied to
* -# any data cache
* -# any unified cache.
* <li> Invalidate by MVA
* Performs an invalidate of a data or unified cache line based on the address it contains.
* <li> Invalidate by set/way
* Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean by MVA
* Performs a clean of a data or unified cache line based on the address it contains.
* <li> Clean by set/way
* Performs a clean of a data or unified cache line based on its location in the cache hierarchy.
* <li> Clean and Invalidate by MVA
* Performs a clean and invalidate of a data or unified cache line based on the address it contains.
* <li> Clean and Invalidate by set/way
* Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy.
* </ul>
*
* Related files:\n
* \ref cp15.h\n
* \ref cp15_arm_iar.s \n
*/
MODULE ?cp15
//// Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#define __ASSEMBLY__
/*----------------------------------------------------------------------------
* Functions to access CP15 coprocessor register
*----------------------------------------------------------------------------*/
PUBLIC CP15_ReadID
PUBLIC CP15_ReadControl
PUBLIC CP15_WriteControl
PUBLIC CP15_WriteDomainAccessControl
PUBLIC CP15_WriteTTB
PUBLIC CP15_InvalidateIcacheInnerSharable
PUBLIC CP15_InvalidateBTBinnerSharable
PUBLIC CP15_InvalidateIcache
PUBLIC CP15_InvalidateIcacheByMva
PUBLIC CP15_FlushBTB
PUBLIC CP15_FlushBTBbyMva
PUBLIC CP15_InvalidateDcacheLineByMva
PUBLIC CP15_InvalidateDcacheLineBySetWay
PUBLIC CP15_CleanDCacheByMva
PUBLIC CP15_CleanDCacheBySetWay
PUBLIC CP15_CleanDCacheMva
PUBLIC CP15_CleanInvalidateDcacheLineByMva
PUBLIC CP15_CleanInvalidateDcacheLine
PUBLIC CP15_coherent_dcache_for_dma
PUBLIC CP15_invalidate_dcache_for_dma
PUBLIC CP15_clean_dcache_for_dma
PUBLIC CP15_flush_dcache_for_dma
PUBLIC CP15_flush_kern_dcache_for_dma
/**
* \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
* Reading from this register returns the device ID, the cache type, or the TCM status
* depending on the value of Opcode_2 used.
*/
SECTION .CP15_ReadID:DATA:NOROOT(2)
PUBLIC CP15_ReadID
CP15_ReadID:
mov r0, #0
mrc p15, 0, r0, c0, c0, 0
bx lr
/**
* \brief Register c1 is the Control Register for the ARM926EJ-S processor.
* This register specifies the configuration used to enable and disable the
* caches and MMU. It is recommended that you access this register using a
* read-modify-write sequence
*/
SECTION .CP15_ReadControl:CODE:NOROOT(2)
PUBLIC CP15_ReadControl
CP15_ReadControl:
mov r0, #0
mrc p15, 0, r0, c1, c0, 0
bx lr
SECTION .CP15_WriteControl:CODE:NOROOT(2)
PUBLIC CP15_WriteControl
CP15_WriteControl:
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
SECTION .CP15_WriteDomainAccessControl:CODE:NOROOT(2)
PUBLIC CP15_WriteDomainAccessControl
CP15_WriteDomainAccessControl:
mcr p15, 0, r0, c3, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief ARMv7A architecture supports two translation tables
* Configure translation table base (TTB) control register cp15,c2
* to a value of all zeros, indicates we are using TTB register 0.
* write the address of our page table base to TTB register 0.
*/
SECTION .CP15_WriteTTB:CODE:NOROOT(2)
PUBLIC CP15_WriteTTB
CP15_WriteTTB:
mcr p15, 0, r0, c2, c0, 0
nop
nop
nop
nop
nop
nop
nop
nop
bx lr
/**
* \brief Invalidate I cache predictor array inner Sharable
*/
SECTION .CP15_InvalidateIcacheInnerSharable:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcacheInnerSharable
CP15_InvalidateIcacheInnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 0
bx lr
/**
* \brief Invalidate entire branch predictor array inner Sharable
*/
SECTION .CP15_InvalidateBTBinnerSharable:CODE:NOROOT(2)
PUBLIC CP15_InvalidateBTBinnerSharable
CP15_InvalidateBTBinnerSharable:
mov r0, #0
mcr p15, 0, r0, c7, c1, 6
bx lr
/**
* \brief Invalidate all instruction caches to PoU, also flushes branch target cache
*/
SECTION .CP15_InvalidateIcache:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcache
CP15_InvalidateIcache:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
bx lr
/**
* \brief Invalidate instruction caches by VA to PoU
*/
SECTION .CP15_InvalidateIcacheByMva:CODE:NOROOT(2)
PUBLIC CP15_InvalidateIcacheByMva
CP15_InvalidateIcacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 1
bx lr
/**
* \brief Flush entire branch predictor array
*/
SECTION .CP15_FlushBTB:CODE:NOROOT(2)
PUBLIC CP15_FlushBTB
CP15_FlushBTB:
mov r0, #0
mcr p15, 0, r0, c7, c5, 6
bx lr
/**
* \brief Flush branch predictor array entry by MVA
*/
SECTION .CP15_FlushBTBbyMva:CODE:NOROOT(2)
PUBLIC CP15_FlushBTBbyMva
CP15_FlushBTBbyMva:
mov r0, #0
mcr p15, 0, r0, c7, c5, 7
bx lr
/**
* \brief Invalidate data cache line by VA to Poc
*/
SECTION .CP15_InvalidateDcacheLineByMva:CODE:NOROOT(2)
PUBLIC CP15_InvalidateDcacheLineByMva
CP15_InvalidateDcacheLineByMva:
mov r0, #0
mcr p15, 0, r0, c7, c6, 1
bx lr
/**
* \brief Invalidate data cache line by set/way
*/
SECTION .CP15_InvalidateDcacheLineBySetWay:CODE:NOROOT(2)
PUBLIC CP15_InvalidateDcacheLineBySetWay
CP15_InvalidateDcacheLineBySetWay:
mov r0, #0
mcr p15, 0, r0, c7, c6, 2
bx lr
/**
* \brief Clean data cache line by MVA
*/
SECTION .CP15_CleanDCacheByMva:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheByMva
CP15_CleanDCacheByMva:
mov r0, #0
mcr p15, 0, r0, c7, c10, 1
bx lr
/**
* \brief Clean data cache line by Set/way
*/
SECTION .CP15_CleanDCacheBySetWay:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheBySetWay
CP15_CleanDCacheBySetWay:
mov r0, #0
mcr p15, 0, r0, c7, c10, 2
bx lr
/**
* \brief Clean unified cache line by MVA
*/
SECTION .CP15_CleanDCacheMva:CODE:NOROOT(2)
PUBLIC CP15_CleanDCacheMva
CP15_CleanDCacheMva:
mov r0, #0
mcr p15, 0, r0, c7, c11, 1
bx lr
/**
* \brief Clean and invalidate data cache line by VA to PoC
*/
SECTION .CP15_CleanInvalidateDcacheLineByMva:CODE:NOROOT(2)
PUBLIC CP15_CleanInvalidateDcacheLineByMva
CP15_CleanInvalidateDcacheLineByMva:
mov r0, #0
mcr p15, 0, r0, c7, c14, 1
bx lr
/**
* \brief Clean and Incalidate data cache line by Set/Way
*/
SECTION .CP15_CleanInvalidateDcacheLine:CODE:NOROOT(2)
PUBLIC CP15_CleanInvalidateDcacheLine
CP15_CleanInvalidateDcacheLine:
mov r0, #0
mcr p15, 0, r0, c7, c14, 2
bx lr
/**
* \brief Ensure that the I and D caches are coherent within specified
* region. This is typically used when code has been written to
* a memory region, and will be executed.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_coherent_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_coherent_dcache_for_dma
CP15_coherent_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r12, r0, r3
loop1:
mcr p15, 0, r12, c7, c11, 1 // clean D line to the point of unification
add r12, r12, r2
cmp r12, r1
blo loop1
dsb
// .macro icache_line_size, reg, tmp
mrc p15, 0, r3, c0, c0, 1 // read ctr
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r12, r0, r3
loop2:
mcr p15, 0, r12, c7, c5, 1 // invalidate I line
add r12, r12, r2
cmp r12, r1
blo loop2
mov r0, #0
mcr p15, 0, r0, c7, c1, 6 //invalidate BTB Inner Shareable
mcr p15, 0, r0, c7, c5, 6 // invalidate BTB
dsb
isb
bx lr
/**
* \brief Invalidate the data cache within the specified region; we will
* be performing a DMA operation in this region and we want to
* purge old data in the cache.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_invalidate_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_invalidate_dcache_for_dma
CP15_invalidate_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
tst r0, r3
bic r0, r0, r3
mcrne p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line
tst r1, r3
bic r1, r1, r3
mcrne p15, 0, r1, c7, c14, 1 // clean & invalidate D / U line
loop3:
mcr p15, 0, r0, c7, c6, 1 // invalidate D / U line
add r0, r0, r2
cmp r0, r1
blo loop3
dsb
bx lr
/**
* \brief Clean the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_clean_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_clean_dcache_for_dma
CP15_clean_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r0, r0, r3
loop4:
mcr p15, 0, r0, c7, c10, 1 // clean D / U line
add r0, r0, r2
cmp r0, r1
blo loop4
dsb
bx lr
/**
* \brief Flush the data cache within the specified region
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_flush_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_flush_dcache_for_dma
CP15_flush_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
sub r3, r2, #1
bic r0, r0, r3
loop5:
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line
add r0, r0, r2
cmp r0, r1
blo loop5
dsb
bx lr
/**
* \brief CP15_flush_kern_dcache_for_dma
* Ensure that the data held in the page kaddr is written back to the page in question.
* \param start virtual start address of region
* \param end virtual end address of region
*/
SECTION .CP15_flush_kern_dcache_for_dma:CODE:NOROOT(2)
PUBLIC CP15_flush_kern_dcache_for_dma
CP15_flush_kern_dcache_for_dma:
// dcache_line_size r2, r3
mrc p15, 0, r3, c0, c0, 1 // read ctr
lsr r3, r3, #16
and r3, r3, #0xf // cache line size encoding
mov r2, #4 // bytes per word
mov r2, r2, lsl r3 // actual cache line size
add r1, r0, r1
sub r3, r2, #1
bic r0, r0, r3
mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D line / unified line
add r0, r0, r2
cmp r0, r1
blo 1b
dsb
bx lr
END

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* USB Device Framework configurations.
*
*/
#ifndef USBD_CONFIG_H
#define USBD_CONFIG_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** \addtogroup usbd_config
*@{
*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_ids USBD Device IDs
* @{
*/
#define USBD_VID_ATMEL 0x03EB /**< Vendor ID: Atmel */
#define USBD_PID_ENUM 0x0001 /**< Product ID: Enum (Core) */
#define USBD_PID_CDCDSERIAL 0x6119 /**< Product ID: CDC Serial */
#define USBD_PID_HIDKEYBOARD 0x6127 /**< Product ID: HID Keyboard */
#define USBD_PID_AUDIO 0x6128 /**< Product ID: Audio devices */
#define USBD_PID_MSD 0x6129 /**< Product ID: Massstorage */
#define USBD_PID_CDCHID 0x6130 /**< Product ID: composite */
#define USBD_PID_CDCAUDIO 0x6131 /**< Product ID: composite */
#define USBD_PID_CDCMSD 0x6132 /**< Product ID: composite */
#define USBD_PID_CDCCDC 0x6133 /**< Product ID: composite */
#define USBD_PID_HIDAUDIO 0x6134 /**< Product ID: composite */
#define USBD_PID_HIDMSD 0x6135 /**< Product ID: composite */
#define USBD_PID_HIDMOUSE 0x6200 /**< Product ID: HID Mouse */
#define USBD_PID_HIDTRANSFER 0x6201 /**< Product ID: HID Transfer */
#define USBD_PID_CCID 0x6203 /**< Product ID: CCID */
#define USBD_RELEASE_1_00 0x0100 /**< Release: 1.00 */
/** @}*/
/** \addtogroup usbd_general_config USBD General Configure
* @{
* This page lists general configurations for all USB device drivers.
* - \ref USBD_BMATTRIBUTES
*/
/** default USB Device attributes configuration descriptor
* (bus or self powered, remote wakeup) */
#define USBD_BMATTRIBUTES BOARD_USB_BMATTRIBUTES
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Mass storage
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_msdd_config USB MassStorage Configure
* @{
* This page lists the defines used by the Mass Storage driver.
*
* \section msd_ep_addr Endpoint Addresses
* - \ref MSDDriverDescriptors_BULKOUT
* - \ref MSDDriverDescriptors_BULKIN
*/
/** Address of the Mass Storage bulk-out endpoint.*/
#define MSDDriverDescriptors_BULKOUT 1
/** Address of the Mass Storage bulk-in endpoint.*/
#define MSDDriverDescriptors_BULKIN 2
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - CDC Serial
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_cdc_serial_config USB CDC Serial Configure
* @{
* This page lists the defines used by the CDC Serial Device Driver.
*
* \section cdcd_ep_addr Endpoint Addresses
* - \ref CDCDSerialDriverDescriptors_DATAOUT
* - \ref CDCDSerialDriverDescriptors_DATAIN
* - \ref CDCDSerialDriverDescriptors_NOTIFICATION
*/
/** Data OUT endpoint number */
#define CDCDSerialDriverDescriptors_DATAOUT 1
/** Data IN endpoint number */
#define CDCDSerialDriverDescriptors_DATAIN 2
/** Notification endpoint number */
#define CDCDSerialDriverDescriptors_NOTIFICATION 3
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_config USB Audio General Configure
* @{
* This page lists definitions for USB Audio Devices Drivers.
* - \ref
*/
#if defined(at91sam7s) || defined(at91sam9xe)
/** Sample rate in Hz. */
#define AUDDevice_SAMPLERATE 32000UL
/** Number of channels in audio stream. */
#define AUDDevice_NUMCHANNELS 1
/** Number of bytes in one sample. */
#define AUDDevice_BYTESPERSAMPLE 2
#else
/** Sample rate in Hz. */
#define AUDDevice_SAMPLERATE 48000UL
/** Number of channels in audio stream. */
#define AUDDevice_NUMCHANNELS 2
/** Number of bytes in one sample. */
#define AUDDevice_BYTESPERSAMPLE 2
#endif
/** Number of bits in one sample. */
#define AUDDevice_BITSPERSAMPLE (AUDDevice_BYTESPERSAMPLE * 8)
/** Number of bytes in one USB subframe. */
#define AUDDevice_BYTESPERSUBFRAME (AUDDevice_NUMCHANNELS * \
AUDDevice_BYTESPERSAMPLE)
/** Number of samples in one USB frame. */
#define AUDDevice_SAMPLESPERFRAME (AUDDevice_SAMPLERATE / 1000 \
* AUDDevice_NUMCHANNELS)
/** Number of bytes in one USB frame. */
#define AUDDevice_BYTESPERFRAME (AUDDevice_SAMPLESPERFRAME * \
AUDDevice_BYTESPERSAMPLE)
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio - Desktop Speaker
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_speaker_config USB Speaker Configure
* @{
* This page lists the definitions for USB Audio Speaker Device Driver.
* - \ref AUDDSpeakerDriverDescriptors_DATAOUT
* - \ref AUDDSpeakerDriverDescriptors_FS_INTERVAL
* - \ref AUDDSpeakerDriverDescriptors_HS_INTERVAL
*
* \note for UDP, uses IN EPs that support double buffer; for UDPHS, uses
* IN EPs that support DMA and High bandwidth.
*/
/** Data out endpoint number. */
#define AUDDSpeakerDriverDescriptors_DATAOUT 0x04
/** Endpoint polling interval 2^(x-1) * 125us */
#define AUDDSpeakerDriverDescriptors_HS_INTERVAL 0x04
/** Endpoint polling interval 2^(x-1) * ms */
#define AUDDSpeakerDriverDescriptors_FS_INTERVAL 0x01
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Audio - Speaker Phone
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_audio_speakerphone_config USB Speaker Phone Configure
* @{
* This page lists the definitions for USB Audio Speaker Phone Device Driver.
* - \ref AUDDSpeakerPhoneDriverDescriptors_DATAOUT
* - \ref AUDDSpeakerPhoneDriverDescriptors_DATAIN
* - \ref AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL
* - \ref AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL
*/
#if defined(at91sam7s) || defined(at91sam9xe)
/** Data out endpoint number, size 64B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01
/** Data in endpoint number, size 64B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x02
#elif defined(CHIP_USB_UDP)
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x04
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x05
#elif defined(at91sam9m10ek)
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06
#else
/** Data out endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x05
/** Data in endpoint number, size 192B */
#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06
#endif
/** Endpoint polling interval 2^(x-1) * 125us */
#define AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL 0x04
/** Endpoint polling interval 2^(x-1) * ms */
#define AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL 0x01
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Keyboard
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_keyboard_config USB HID Keyboard Device Configure
* @{
* This page lists the defines used by the HID Keyboard Device Driver.
*
* \section hidd_k_ep_addr Endpoint Addresses
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT
* \section hidd_k_ep_polling Endpoint Polling Rate
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING
* - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING
*/
/** Interrupt IN endpoint number */
#define HIDDKeyboardDriverDescriptors_INTERRUPTIN 1
/** Interrupt IN endpoint polling rate (in milliseconds) */
#define HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING 10
/** Interrupt OUT endpoint number */
#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT 2
/** Interrupt OUT endpoint polling rate (in milliseconds) */
#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING 10
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Mouse
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_mouse_config USB HID Mouse Device Configure
* @{
* This page lists the defines used by the HID Mouse Device Driver.
*
* \section hidd_m_ep_addr Endpoint Addresses
* - \ref HIDDMouseDriverDescriptors_INTERRUPTIN
* \section hidd_m_ep_polling Endpoint Polling Rate
* - \ref HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING
*/
/** Interrupt IN endpoint number */
#define HIDDMouseDriverDescriptors_INTERRUPTIN 1
/** Interrupt IN endpoint polling rate (in milliseconds) */
#define HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING 10
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - HID - Transfer (Customize device)
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_hid_xfr_config USB HID Transfer Device Configure
* @{
* This page lists the defines used by the HID Transfer Device Driver.
*
* \section hidd_t_ep_addr Endpoint Addresses
* - \ref HIDDTransferDriverDescriptors_INTERRUPTIN
* - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT
* \section hidd_t_ep_polling Endpoint Polling Rate
* - \ref HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING
* - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING
*/
/** Interrupt IN endpoint number. */
#define HIDDTransferDriverDescriptors_INTERRUPTIN 1
/** Polling rate in ms */
#define HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING 50
/** Interrupt IN endpoint polling rate (in milliseconds). */
#define HIDDTransferDriverDescriptors_INTERRUPTOUT 2
/** Polling rate in ms */
#define HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING 50
/** @}*/
/*----------------------------------------------------------------------------
* USB Device - Composite
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_composite_config USB Composite Device Configure
* @{
*/
/** @}*/
/**@}*/
#endif //#ifndef USBD_CONFIG_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Collection of LEDs for using the USB device controller on AT91
* microcontrollers.
*/
#ifndef USBDLEDS_H
#define USBDLEDS_H
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "board.h"
/** \addtogroup usbd_hal
*@{
*/
/*----------------------------------------------------------------------------
* Constants
*----------------------------------------------------------------------------*/
/** \addtogroup usbd_leds USB Device LEDs
* @{
* This page lists the LEDs used in the USB %device driver.
*
* - USBD_LEDPOWER
* - USBD_LEDUSB
* - USBD_LEDOTHER
*/
/** LED for indicating that the device is powered. */
#define USBD_LEDPOWER 0
/** LED for indicating USB activity. */
#define USBD_LEDUSB 1
/** LED for custom usage. */
#define USBD_LEDOTHER 2
/** @}*/
/**@}*/
#endif //#ifndef USBDLEDS_H

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2011, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* \section Purpose
*
* Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.
*
* \section Usage
*
* -# Configurate the pins for ADC.
* -# Initialize the ADC with ADC_Initialize().
* -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming().
* -# Select the active channel using ADC_EnableChannel().
* -# Start the conversion with ADC_StartConversion().
* -# Wait the end of the conversion by polling status with ADC_GetStatus().
* -# Finally, get the converted data using ADC_GetConvertedData() or ADC_GetLastConvertedData().
*
*/
#ifndef _ADC_
#define _ADC_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <assert.h>
#include <stdint.h>
/*------------------------------------------------------------------------------
* Definitions
*------------------------------------------------------------------------------*/
/* Max. ADC Clock Frequency (Hz) */
#define ADC_CLOCK_MAX 20000000
/* Max. normal ADC startup time (us) */
#define ADC_STARTUP_NORMAL_MAX 40
/* Max. fast ADC startup time (us) */
#define ADC_STARTUP_FAST_MAX 12
/* Definitions for ADC channels */
#define ADC_CHANNEL_0 0
#define ADC_CHANNEL_1 1
#define ADC_CHANNEL_2 2
#define ADC_CHANNEL_3 3
#define ADC_CHANNEL_4 4
#define ADC_CHANNEL_5 5
#define ADC_CHANNEL_6 6
#define ADC_CHANNEL_7 7
#define ADC_CHANNEL_8 8
#define ADC_CHANNEL_9 9
#define ADC_CHANNEL_10 10
#define ADC_CHANNEL_11 11
#define ADC_CHANNEL_12 12
#define ADC_CHANNEL_13 13
#define ADC_CHANNEL_14 14
#define ADC_CHANNEL_15 15
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
* Macros function of register access
*------------------------------------------------------------------------------*/
#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR)
#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START)
#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL)
#define ADC_EnableChannel( pAdc, dwChannel ) {\
(pAdc)->ADC_CHER = (1 << (dwChannel));\
}
#define ADC_DisableChannel(pAdc, dwChannel) {\
(pAdc)->ADC_CHDR = (1 << (dwChannel));\
}
#define ADC_EnableIt(pAdc, dwMode) {\
(pAdc)->ADC_IER = (dwMode);\
}
#define ADC_DisableIt(pAdc, dwMode) {\
(pAdc)->ADC_IDR = (dwMode);\
}
#define ADC_SetChannelGain(pAdc,dwMode) {\
(pAdc)->ADC_CGR = dwMode;\
}
#define ADC_SetChannelOffset(pAdc,dwMode) {\
(pAdc)->ADC_COR = dwMode;\
}
#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY)
#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR)
#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk))
#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR)
#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR)
#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR)
/*------------------------------------------------------------------------------
* Exported functions
*------------------------------------------------------------------------------*/
extern void ADC_Initialize( Adc* pAdc, uint32_t dwId );
extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck );
extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling );
extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel );
extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode);
extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis );
extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 );
extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh );
extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis );
extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ;
extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ;
extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ;
extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ;
extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ;
extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv);
extern uint32_t ADC_GetTsXPosition(Adc *pADC);
extern uint32_t ADC_GetTsYPosition(Adc *pADC);
extern uint32_t ADC_GetTsPressure(Adc *pADC);
extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime);
extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis);
extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs );
extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs );
extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod);
extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode);
extern void ADC_TsCalibration( Adc *pAdc );
#ifdef __cplusplus
}
#endif
#endif /* #ifndef _ADC_ */

68
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2013, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _AES_
#define _AES_
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
/*------------------------------------------------------------------------------*/
/* Definition */
/*------------------------------------------------------------------------------*/
#define AES_MR_CIPHER_ENCRYPT 1
#define AES_MR_CIPHER_DECRYPT 0
/*------------------------------------------------------------------------------*/
/* Exported functions */
/*------------------------------------------------------------------------------*/
extern void AES_Start(void);
extern void AES_SoftReset(void);
extern void AES_Recount(void);
extern void AES_Configure(uint32_t mode);
extern void AES_EnableIt(uint32_t sources);
extern void AES_DisableIt(uint32_t sources);
extern uint32_t AES_GetStatus(void);
extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength);
extern void AES_SetInput(uint32_t *data);
extern void AES_GetOutput(uint32_t *data);
extern void AES_SetVector(const uint32_t *pVector);
extern void AES_SetAadLen(uint32_t len);
extern void AES_SetDataLen(uint32_t len);
extern void AES_SetGcmHash(uint32_t * hash);
extern void AES_GetGcmTag(uint32_t * tag);
extern void AES_GetGcmCounter(uint32_t * counter);
extern void AES_GetGcmH(uint32_t *h);
#endif /* #ifndef _AES_ */

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