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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
This commit is contained in:
Gaurav Aggarwal
parent
c3c9c12ce2
commit
5849459c65
45 changed files with 6989 additions and 6739 deletions
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@ -40,7 +40,7 @@
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* Bit[0] - 0 --> Thread mode is privileged.
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* Bit[1] - 1 --> Thread mode uses PSP.
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*/
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#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
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#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
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/**
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* @brief CONTROL value for un-privileged tasks.
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@ -48,7 +48,7 @@
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* Bit[0] - 1 --> Thread mode is un-privileged.
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* Bit[1] - 1 --> Thread mode uses PSP.
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*/
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#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
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#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
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/*-----------------------------------------------------------*/
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/**
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@ -59,146 +59,146 @@
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*/
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typedef struct SecureContext
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{
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uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
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uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
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uint8_t *pucStackStart; /**< First location of the stack memory. */
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uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
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uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
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uint8_t *pucStackStart; /**< First location of the stack memory. */
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} SecureContext_t;
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
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{
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uint32_t ulIPSR;
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uint32_t ulIPSR;
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* No stack for thread mode until a task's context is loaded. */
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secureportSET_PSPLIM( securecontextNO_STACK );
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secureportSET_PSP( securecontextNO_STACK );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* No stack for thread mode until a task's context is loaded. */
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secureportSET_PSPLIM( securecontextNO_STACK );
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secureportSET_PSP( securecontextNO_STACK );
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#if( configENABLE_MPU == 1 )
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{
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/* Configure thread mode to use PSP and to be unprivileged. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
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}
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#else /* configENABLE_MPU */
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{
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/* Configure thread mode to use PSP and to be privileged.. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
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}
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#endif /* configENABLE_MPU */
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}
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#if( configENABLE_MPU == 1 )
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{
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/* Configure thread mode to use PSP and to be unprivileged. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
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}
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#else /* configENABLE_MPU */
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{
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/* Configure thread mode to use PSP and to be privileged.. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
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}
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#endif /* configENABLE_MPU */
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}
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}
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/*-----------------------------------------------------------*/
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#if( configENABLE_MPU == 1 )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
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#else /* configENABLE_MPU */
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
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#endif /* configENABLE_MPU */
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{
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uint8_t *pucStackMemory = NULL;
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uint32_t ulIPSR;
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SecureContextHandle_t xSecureContextHandle = NULL;
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#if( configENABLE_MPU == 1 )
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uint32_t *pulCurrentStackPointer = NULL;
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#endif /* configENABLE_MPU */
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uint8_t *pucStackMemory = NULL;
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uint32_t ulIPSR;
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SecureContextHandle_t xSecureContextHandle = NULL;
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#if( configENABLE_MPU == 1 )
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uint32_t *pulCurrentStackPointer = NULL;
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#endif /* configENABLE_MPU */
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Allocate the context structure. */
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xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Allocate the context structure. */
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xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
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if( xSecureContextHandle != NULL )
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{
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/* Allocate the stack space. */
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pucStackMemory = pvPortMalloc( ulSecureStackSize );
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if( xSecureContextHandle != NULL )
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{
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/* Allocate the stack space. */
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pucStackMemory = pvPortMalloc( ulSecureStackSize );
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if( pucStackMemory != NULL )
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{
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/* Since stack grows down, the starting point will be the last
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* location. Note that this location is next to the last
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* allocated byte because the hardware decrements the stack
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* pointer before writing i.e. if stack pointer is 0x2, a push
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* operation will decrement the stack pointer to 0x1 and then
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* write at 0x1. */
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xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
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if( pucStackMemory != NULL )
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{
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/* Since stack grows down, the starting point will be the last
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* location. Note that this location is next to the last
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* allocated byte because the hardware decrements the stack
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* pointer before writing i.e. if stack pointer is 0x2, a push
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* operation will decrement the stack pointer to 0x1 and then
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* write at 0x1. */
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xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
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/* The stack cannot go beyond this location. This value is
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* programmed in the PSPLIM register on context switch.*/
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xSecureContextHandle->pucStackLimit = pucStackMemory;
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/* The stack cannot go beyond this location. This value is
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* programmed in the PSPLIM register on context switch.*/
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xSecureContextHandle->pucStackLimit = pucStackMemory;
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#if( configENABLE_MPU == 1 )
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{
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/* Store the correct CONTROL value for the task on the stack.
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* This value is programmed in the CONTROL register on
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* context switch. */
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pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
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pulCurrentStackPointer--;
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if( ulIsTaskPrivileged )
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
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}
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else
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
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}
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#if( configENABLE_MPU == 1 )
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{
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/* Store the correct CONTROL value for the task on the stack.
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* This value is programmed in the CONTROL register on
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* context switch. */
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pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
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pulCurrentStackPointer--;
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if( ulIsTaskPrivileged )
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
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}
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else
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
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}
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/* Store the current stack pointer. This value is programmed in
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* the PSP register on context switch. */
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xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
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}
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#else /* configENABLE_MPU */
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{
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/* Current SP is set to the starting of the stack. This
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* value programmed in the PSP register on context switch. */
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xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
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/* Store the current stack pointer. This value is programmed in
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* the PSP register on context switch. */
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xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
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}
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#else /* configENABLE_MPU */
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{
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/* Current SP is set to the starting of the stack. This
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* value programmed in the PSP register on context switch. */
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xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
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}
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#endif /* configENABLE_MPU */
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}
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else
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{
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/* Free the context to avoid memory leak and make sure to return
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* NULL to indicate failure. */
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vPortFree( xSecureContextHandle );
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xSecureContextHandle = NULL;
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}
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}
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}
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}
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#endif /* configENABLE_MPU */
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}
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else
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{
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/* Free the context to avoid memory leak and make sure to return
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* NULL to indicate failure. */
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vPortFree( xSecureContextHandle );
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xSecureContextHandle = NULL;
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}
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}
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}
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return xSecureContextHandle;
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return xSecureContextHandle;
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
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{
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uint32_t ulIPSR;
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uint32_t ulIPSR;
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Ensure that valid parameters are passed. */
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secureportASSERT( xSecureContextHandle != NULL );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Ensure that valid parameters are passed. */
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secureportASSERT( xSecureContextHandle != NULL );
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/* Free the stack space. */
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vPortFree( xSecureContextHandle->pucStackLimit );
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/* Free the stack space. */
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vPortFree( xSecureContextHandle->pucStackLimit );
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/* Free the context itself. */
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vPortFree( xSecureContextHandle );
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}
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/* Free the context itself. */
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vPortFree( xSecureContextHandle );
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}
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}
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/*-----------------------------------------------------------*/
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