mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-18 09:08:33 -04:00
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
This commit is contained in:
Gaurav Aggarwal
parent
c3c9c12ce2
commit
5849459c65
45 changed files with 6989 additions and 6739 deletions
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@ -33,56 +33,56 @@
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secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
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{
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/* xSecureContextHandle value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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#if( configENABLE_MPU == 1 )
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" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n" /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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" msr psplim, r2 \n" /* PSPLIM = r2. */
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" msr psp, r1 \n" /* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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:::"r0", "r1", "r2"
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);
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/* xSecureContextHandle value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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#if( configENABLE_MPU == 1 )
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" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n" /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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" msr psplim, r2 \n" /* PSPLIM = r2. */
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" msr psp, r1 \n" /* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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:::"r0", "r1", "r2"
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);
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
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{
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/* xSecureContextHandle value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n" /* r1 = PSP. */
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#if( configENABLE_FPU == 1 )
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" vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
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" vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
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#endif /* configENABLE_FPU */
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#if( configENABLE_MPU == 1 )
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" mrs r2, control \n" /* r2 = CONTROL. */
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" stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
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#endif /* configENABLE_MPU */
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" str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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:: "i" ( securecontextNO_STACK ) : "r1", "memory"
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);
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/* xSecureContextHandle value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n" /* r1 = PSP. */
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#if( configENABLE_FPU == 1 )
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" vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
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" vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
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#endif /* configENABLE_FPU */
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#if( configENABLE_MPU == 1 )
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" mrs r2, control \n" /* r2 = CONTROL. */
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" stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
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#endif /* configENABLE_MPU */
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" str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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:: "i" ( securecontextNO_STACK ) : "r1", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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@ -37,12 +37,12 @@ extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHa
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secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
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{
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SecureContext_LoadContextAsm( xSecureContextHandle );
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SecureContext_LoadContextAsm( xSecureContextHandle );
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
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{
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SecureContext_SaveContextAsm( xSecureContextHandle );
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SecureContext_SaveContextAsm( xSecureContextHandle );
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}
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/*-----------------------------------------------------------*/
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@ -25,49 +25,49 @@
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* 1 tab == 4 spaces!
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*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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SECTION .text:CODE:NOROOT(2)
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THUMB
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PUBLIC SecureContext_LoadContextAsm
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PUBLIC SecureContext_SaveContextAsm
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PUBLIC SecureContext_LoadContextAsm
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PUBLIC SecureContext_SaveContextAsm
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/*-----------------------------------------------------------*/
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SecureContext_LoadContextAsm:
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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#if ( configENABLE_MPU == 1 )
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ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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msr control, r3 /* CONTROL = r3. */
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ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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msr control, r3 /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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msr psplim, r2 /* PSPLIM = r2. */
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msr psp, r1 /* PSP = r1. */
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msr psplim, r2 /* PSPLIM = r2. */
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msr psp, r1 /* PSP = r1. */
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load_ctx_therad_mode:
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bx lr
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load_ctx_therad_mode:
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bx lr
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/*-----------------------------------------------------------*/
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SecureContext_SaveContextAsm:
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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mrs r1, psp /* r1 = PSP. */
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/* xSecureContextHandle value is in r0. */
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mrs r1, ipsr /* r1 = IPSR. */
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cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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mrs r1, psp /* r1 = PSP. */
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#if ( configENABLE_FPU == 1 )
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vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */
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vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */
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vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */
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vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */
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#endif /* configENABLE_FPU */
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#if ( configENABLE_MPU == 1 )
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mrs r2, control /* r2 = CONTROL. */
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stmdb r1!, {r2} /* Store CONTROL value on the stack. */
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mrs r2, control /* r2 = CONTROL. */
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stmdb r1!, {r2} /* Store CONTROL value on the stack. */
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#endif /* configENABLE_MPU */
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str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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movs r1, #0 /* r1 = securecontextNO_STACK. */
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msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
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msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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movs r1, #0 /* r1 = securecontextNO_STACK. */
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msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
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msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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save_ctx_therad_mode:
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bx lr
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save_ctx_therad_mode:
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bx lr
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/*-----------------------------------------------------------*/
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END
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END
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@ -40,7 +40,7 @@
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* Bit[0] - 0 --> Thread mode is privileged.
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* Bit[1] - 1 --> Thread mode uses PSP.
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*/
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#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
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#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
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/**
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* @brief CONTROL value for un-privileged tasks.
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@ -48,7 +48,7 @@
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* Bit[0] - 1 --> Thread mode is un-privileged.
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* Bit[1] - 1 --> Thread mode uses PSP.
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*/
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#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
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#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
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/*-----------------------------------------------------------*/
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/**
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@ -59,146 +59,146 @@
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*/
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typedef struct SecureContext
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{
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uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
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uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
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uint8_t *pucStackStart; /**< First location of the stack memory. */
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uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
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uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
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uint8_t *pucStackStart; /**< First location of the stack memory. */
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} SecureContext_t;
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
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{
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uint32_t ulIPSR;
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uint32_t ulIPSR;
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* No stack for thread mode until a task's context is loaded. */
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secureportSET_PSPLIM( securecontextNO_STACK );
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secureportSET_PSP( securecontextNO_STACK );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* No stack for thread mode until a task's context is loaded. */
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secureportSET_PSPLIM( securecontextNO_STACK );
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secureportSET_PSP( securecontextNO_STACK );
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#if( configENABLE_MPU == 1 )
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{
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/* Configure thread mode to use PSP and to be unprivileged. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
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}
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#else /* configENABLE_MPU */
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{
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/* Configure thread mode to use PSP and to be privileged.. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
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}
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#endif /* configENABLE_MPU */
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}
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#if( configENABLE_MPU == 1 )
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{
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/* Configure thread mode to use PSP and to be unprivileged. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
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}
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#else /* configENABLE_MPU */
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{
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/* Configure thread mode to use PSP and to be privileged.. */
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secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
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}
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#endif /* configENABLE_MPU */
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}
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}
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/*-----------------------------------------------------------*/
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#if( configENABLE_MPU == 1 )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
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#else /* configENABLE_MPU */
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
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secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
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#endif /* configENABLE_MPU */
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{
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uint8_t *pucStackMemory = NULL;
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uint32_t ulIPSR;
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SecureContextHandle_t xSecureContextHandle = NULL;
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#if( configENABLE_MPU == 1 )
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uint32_t *pulCurrentStackPointer = NULL;
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#endif /* configENABLE_MPU */
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uint8_t *pucStackMemory = NULL;
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uint32_t ulIPSR;
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SecureContextHandle_t xSecureContextHandle = NULL;
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#if( configENABLE_MPU == 1 )
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uint32_t *pulCurrentStackPointer = NULL;
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#endif /* configENABLE_MPU */
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Read the Interrupt Program Status Register (IPSR) value. */
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secureportREAD_IPSR( ulIPSR );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Allocate the context structure. */
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xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
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/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
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* when the processor is running in the Thread Mode. */
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if( ulIPSR != 0 )
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{
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/* Allocate the context structure. */
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xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
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if( xSecureContextHandle != NULL )
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{
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/* Allocate the stack space. */
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pucStackMemory = pvPortMalloc( ulSecureStackSize );
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if( xSecureContextHandle != NULL )
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{
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/* Allocate the stack space. */
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pucStackMemory = pvPortMalloc( ulSecureStackSize );
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if( pucStackMemory != NULL )
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{
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/* Since stack grows down, the starting point will be the last
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* location. Note that this location is next to the last
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* allocated byte because the hardware decrements the stack
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* pointer before writing i.e. if stack pointer is 0x2, a push
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* operation will decrement the stack pointer to 0x1 and then
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* write at 0x1. */
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xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
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if( pucStackMemory != NULL )
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{
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/* Since stack grows down, the starting point will be the last
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* location. Note that this location is next to the last
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* allocated byte because the hardware decrements the stack
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* pointer before writing i.e. if stack pointer is 0x2, a push
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* operation will decrement the stack pointer to 0x1 and then
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* write at 0x1. */
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xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
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/* The stack cannot go beyond this location. This value is
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* programmed in the PSPLIM register on context switch.*/
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xSecureContextHandle->pucStackLimit = pucStackMemory;
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/* The stack cannot go beyond this location. This value is
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* programmed in the PSPLIM register on context switch.*/
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xSecureContextHandle->pucStackLimit = pucStackMemory;
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#if( configENABLE_MPU == 1 )
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{
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/* Store the correct CONTROL value for the task on the stack.
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* This value is programmed in the CONTROL register on
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* context switch. */
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pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
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pulCurrentStackPointer--;
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if( ulIsTaskPrivileged )
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
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}
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else
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
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}
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#if( configENABLE_MPU == 1 )
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{
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/* Store the correct CONTROL value for the task on the stack.
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* This value is programmed in the CONTROL register on
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* context switch. */
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pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
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pulCurrentStackPointer--;
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if( ulIsTaskPrivileged )
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
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}
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else
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{
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*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
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||||
}
|
||||
|
||||
/* Store the current stack pointer. This value is programmed in
|
||||
* the PSP register on context switch. */
|
||||
xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
|
||||
}
|
||||
#else /* configENABLE_MPU */
|
||||
{
|
||||
/* Current SP is set to the starting of the stack. This
|
||||
* value programmed in the PSP register on context switch. */
|
||||
xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
|
||||
/* Store the current stack pointer. This value is programmed in
|
||||
* the PSP register on context switch. */
|
||||
xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
|
||||
}
|
||||
#else /* configENABLE_MPU */
|
||||
{
|
||||
/* Current SP is set to the starting of the stack. This
|
||||
* value programmed in the PSP register on context switch. */
|
||||
xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
|
||||
|
||||
}
|
||||
#endif /* configENABLE_MPU */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Free the context to avoid memory leak and make sure to return
|
||||
* NULL to indicate failure. */
|
||||
vPortFree( xSecureContextHandle );
|
||||
xSecureContextHandle = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* configENABLE_MPU */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Free the context to avoid memory leak and make sure to return
|
||||
* NULL to indicate failure. */
|
||||
vPortFree( xSecureContextHandle );
|
||||
xSecureContextHandle = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return xSecureContextHandle;
|
||||
return xSecureContextHandle;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
|
||||
{
|
||||
uint32_t ulIPSR;
|
||||
uint32_t ulIPSR;
|
||||
|
||||
/* Read the Interrupt Program Status Register (IPSR) value. */
|
||||
secureportREAD_IPSR( ulIPSR );
|
||||
/* Read the Interrupt Program Status Register (IPSR) value. */
|
||||
secureportREAD_IPSR( ulIPSR );
|
||||
|
||||
/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
|
||||
* when the processor is running in the Thread Mode. */
|
||||
if( ulIPSR != 0 )
|
||||
{
|
||||
/* Ensure that valid parameters are passed. */
|
||||
secureportASSERT( xSecureContextHandle != NULL );
|
||||
/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
|
||||
* when the processor is running in the Thread Mode. */
|
||||
if( ulIPSR != 0 )
|
||||
{
|
||||
/* Ensure that valid parameters are passed. */
|
||||
secureportASSERT( xSecureContextHandle != NULL );
|
||||
|
||||
/* Free the stack space. */
|
||||
vPortFree( xSecureContextHandle->pucStackLimit );
|
||||
/* Free the stack space. */
|
||||
vPortFree( xSecureContextHandle->pucStackLimit );
|
||||
|
||||
/* Free the context itself. */
|
||||
vPortFree( xSecureContextHandle );
|
||||
}
|
||||
/* Free the context itself. */
|
||||
vPortFree( xSecureContextHandle );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@
|
|||
/**
|
||||
* @brief PSP value when no task's context is loaded.
|
||||
*/
|
||||
#define securecontextNO_STACK 0x0
|
||||
#define securecontextNO_STACK 0x0
|
||||
|
||||
/**
|
||||
* @brief Opaque handle.
|
||||
*/
|
||||
struct SecureContext;
|
||||
typedef struct SecureContext* SecureContextHandle_t;
|
||||
typedef struct SecureContext* SecureContextHandle_t;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -70,9 +70,9 @@ void SecureContext_Init( void );
|
|||
* otherwise.
|
||||
*/
|
||||
#if( configENABLE_MPU == 1 )
|
||||
SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
|
||||
SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
|
||||
#else /* configENABLE_MPU */
|
||||
SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
|
||||
SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
|
||||
#endif /* configENABLE_MPU */
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue