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Update the A2F SoftConsole project to match the current A2F IAR project.

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This commit is contained in:
Richard Barry 2011-04-27 16:05:36 +00:00
parent 9b6bd9e419
commit 5831485bdf
10 changed files with 563 additions and 539 deletions
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39
Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/drivers/I2C/i2c.c
View file

@ -7,6 +7,8 @@
* SVN $Revision: 2152 $
* SVN $Date: 2010-02-11 14:44:11 +0000 (Thu, 11 Feb 2010) $
*/
#include "i2c.h"
#include "../../CMSIS/mss_assert.h"
@ -145,6 +147,14 @@ void MSS_I2C_init
this_i2c->hw_reg_bit->CTRL_CR1 = (clock_speed >> 1) & 0x01;
this_i2c->hw_reg_bit->CTRL_CR0 = clock_speed & 0x01;
this_i2c->hw_reg->ADDR = this_i2c->ser_address;
/* The interrupt can cause a context switch, so ensure its priority is
between configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY. */
NVIC_SetPriority( this_i2c->irqn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
vSemaphoreCreateBinary( ( this_i2c->xI2CCompleteSemaphore ) );
xSemaphoreTake( ( this_i2c->xI2CCompleteSemaphore ), 0 );
configASSERT( ( this_i2c->xI2CCompleteSemaphore ) );
}
/*------------------------------------------------------------------------------
@ -196,6 +206,7 @@ void MSS_I2C_write
uint32_t primask;
ASSERT( (this_i2c == &g_mss_i2c0) || (this_i2c == &g_mss_i2c1) );
configASSERT( ( this_i2c->xI2CCompleteSemaphore ) );
primask = disable_interrupts();
@ -431,11 +442,28 @@ mss_i2c_status_t MSS_I2C_wait_complete
{
ASSERT( (this_i2c == &g_mss_i2c0) || (this_i2c == &g_mss_i2c1) );
#ifdef USE_OLD_I2C_POLLING_CODE
while ( this_i2c->status == MSS_I2C_IN_PROGRESS )
{
/* Wait for transaction to compltete.*/
;
}
#else
configASSERT( ( this_i2c->xI2CCompleteSemaphore ) );
if( xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED )
{
while ( this_i2c->status == MSS_I2C_IN_PROGRESS )
{
/* Wait for transaction to compltete.*/
;
}
}
else
{
xSemaphoreTake( this_i2c->xI2CCompleteSemaphore, portMAX_DELAY );
}
#endif
return this_i2c->status;
}
@ -451,12 +479,14 @@ mss_i2c_status_t MSS_I2C_wait_complete
static void mss_i2c_isr
(
mss_i2c_instance_t * this_i2c
)
)
{
volatile uint8_t status;
uint8_t data;
uint8_t hold_bus;
uint8_t clear_irq = 1;
long lHigherPriorityTaskWoken = pdFALSE;
configASSERT( ( this_i2c->xI2CCompleteSemaphore ) );
ASSERT( (this_i2c == &g_mss_i2c0) || (this_i2c == &g_mss_i2c1) );
@ -539,6 +569,7 @@ static void mss_i2c_isr
clear_irq = 0;
}
this_i2c->status = MSS_I2C_SUCCESS;
xSemaphoreGiveFromISR( this_i2c->xI2CCompleteSemaphore, &lHigherPriorityTaskWoken );
}
break;
@ -577,6 +608,7 @@ static void mss_i2c_isr
clear_irq = 0;
}
this_i2c->status = MSS_I2C_SUCCESS;
xSemaphoreGiveFromISR( this_i2c->xI2CCompleteSemaphore, &lHigherPriorityTaskWoken );
}
break;
@ -600,6 +632,7 @@ static void mss_i2c_isr
case ST_SLAR_NACK: /* SLA+R tx'ed; let's release the bus (send a stop condition) */
this_i2c->hw_reg_bit->CTRL_STO = 0x01;
this_i2c->status = MSS_I2C_FAILED;
xSemaphoreGiveFromISR( this_i2c->xI2CCompleteSemaphore, &lHigherPriorityTaskWoken );
break;
case ST_RX_DATA_ACK: /* Data byte received, ACK returned */
@ -630,6 +663,7 @@ static void mss_i2c_isr
}
this_i2c->status = MSS_I2C_SUCCESS;
// xSemaphoreGiveFromISR( this_i2c->xI2CCompleteSemaphore, &lHigherPriorityTaskWoken );
break;
/******************** SLAVE RECEIVER **************************/
@ -696,6 +730,7 @@ static void mss_i2c_isr
}
/* Mark any previous master write transaction as complete. */
this_i2c->status = MSS_I2C_SUCCESS;
// xSemaphoreGiveFromISR( this_i2c->xI2CCompleteSemaphore, &lHigherPriorityTaskWoken );
break;
case ST_SLV_RST: /* SMBUS ONLY: timeout state. must clear interrupt */
@ -747,6 +782,8 @@ static void mss_i2c_isr
/* Read the status register to ensure the last I2C registers write took place
* in a system built around a bus making use of posted writes. */
status = this_i2c->hw_reg->STATUS;
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
/*------------------------------------------------------------------------------

10
Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/drivers/I2C/i2c.h
View file

@ -194,6 +194,11 @@
#include "../../CMSIS/a2fxxxm3.h"
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -324,7 +329,10 @@ typedef struct mss_i2c_instance
/* Slave data: */
uint_fast8_t slave_mem_offset_length;
mss_i2c_slave_wr_handler_t slave_write_handler;
/* Used to get access to and wait for completion of an I2C transaction. */
xSemaphoreHandle xI2CCompleteSemaphore;
} mss_i2c_instance_t;
/*-------------------------------------------------------------------------*//**

304
Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/drivers/mss_ethernet_mac/mss_ethernet_mac.c
View file

@ -9,9 +9,18 @@
*
******************************************************************************/
/*
*
*
* NOTE: This driver has been modified specifically for use with the* uIP stack.
* It is no longer a generic driver.
*
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#endif
#include "FreeRTOS.h"
#include "task.h"
@ -29,7 +38,7 @@ extern "C" {
/**************************** INTERNAL DEFINES ********************************/
#define MAC_CHECK(CHECK,ERRNO) \
{if(!(CHECK)){g_mss_mac.last_error=(ERRNO); ASSERT((CHECK));}}
{if(!(CHECK)){g_mss_mac.last_error=(ERRNO); configASSERT((CHECK));}}
/*
* Flags
@ -54,8 +63,8 @@ extern "C" {
/* Allocating this many buffers will always ensure there is one free as, even
though TX_RING_SIZE is set to two, the two Tx descriptors will only ever point
to the same buffer. */
#define macNUM_BUFFERS RX_RING_SIZE + TX_RING_SIZE
#define macBUFFER_SIZE 1500
#define macNUM_BUFFERS RX_RING_SIZE + TX_RING_SIZE + 1
#define macBUFFER_SIZE 1488
/***************************************************************/
MAC_instance_t g_mss_mac;
@ -78,15 +87,16 @@ static const int8_t ErrorMessages[][MAX_ERROR_MESSAGE_WIDTH] = {
/*
* Null variables
*/
static MAC_instance_t* NULL_instance;
static uint8_t* NULL_buffer;
static MSS_MAC_callback_t NULL_callback;
/* Declare the uip_buf as a pointer, rather than the traditional array, as this
is a zero copy driver. uip_buf just gets set to whichever buffer is being
processed. */
unsigned char *uip_buf = NULL;
/**************************** INTERNAL FUNCTIONS ******************************/
static int32_t MAC_test_instance( void );
static int32_t MAC_dismiss_bad_frames( void );
static int32_t MAC_send_setup_frame( void );
@ -109,12 +119,17 @@ static void MAC_release_buffer( unsigned char *pcBufferToRelease );
#error This uIP Ethernet driver required TX_RING_SIZE to be set to 2
#endif
/* Buffers that will dynamically be allocated to/from the Tx and Rx descriptors. */
static unsigned char ucMACBuffers[ macNUM_BUFFERS ][ macBUFFER_SIZE ];
/* Buffers that will dynamically be allocated to/from the Tx and Rx descriptors.
The union is used for alignment only. */
static union xMAC_BUFFERS
{
unsigned long ulAlignmentVariable; /* For alignment only, not used anywhere. */
unsigned char ucBuffer[ macNUM_BUFFERS ][ macBUFFER_SIZE ];
} xMACBuffers;
/* Each array position indicated whether or not the buffer of the same index
is currently allocated to a descriptor (pdFALSE) or is free for use (pdTRUE). */
static unsigned char ucMACBufferFree[ macNUM_BUFFERS ];
/* Each array position indicates whether or not the buffer of the same index
is currently allocated to a descriptor (pdTRUE) or is free for use (pdFALSE). */
static unsigned char ucMACBufferInUse[ macNUM_BUFFERS ] = { 0 };
/***************************************************************************//**
* Initializes the Ethernet Controller.
@ -138,7 +153,7 @@ MSS_MAC_init
/* To start with all buffers are free. */
for( a = 0; a < macNUM_BUFFERS; a++ )
{
ucMACBufferFree[ a ] = pdTRUE;
ucMACBufferInUse[ a ] = pdFALSE;
}
/* Try to reset chip */
@ -151,9 +166,9 @@ MSS_MAC_init
/* Check reset values of some registers to constrol
* base address validity */
ASSERT( MAC->CSR0 == 0xFE000000uL );
ASSERT( MAC->CSR5 == 0xF0000000uL );
ASSERT( MAC->CSR6 == 0x32000040uL );
configASSERT( MAC->CSR0 == 0xFE000000uL );
configASSERT( MAC->CSR5 == 0xF0000000uL );
configASSERT( MAC->CSR6 == 0x32000040uL );
/* Instance setup */
MAC_memset_All( &g_mss_mac, 0u );
@ -169,8 +184,8 @@ MSS_MAC_init
/* Allocate a buffer to the descriptor, then mark the buffer as in use
(not free). */
g_mss_mac.rx_descriptors[a].buffer_1 = ( unsigned long ) &( ucMACBuffers[ a ][ 0 ] );
ucMACBufferFree[ a ] = pdFALSE;
g_mss_mac.rx_descriptors[a].buffer_1 = ( unsigned long ) &( xMACBuffers.ucBuffer[ a ][ 0 ] );
ucMACBufferInUse[ a ] = pdTRUE;
}
g_mss_mac.rx_descriptors[RX_RING_SIZE-1].descriptor_1 |= RDES1_RER;
@ -189,8 +204,6 @@ MSS_MAC_init
MAC_BITBAND->CSR0_BAR = (uint32_t)BUS_ARBITRATION_SCHEME;
/* Fixed settings */
/* No automatic polling */
MAC->CSR0 = MAC->CSR0 &~ CSR0_TAP_MASK;
/* No space between descriptors */
MAC->CSR0 = MAC->CSR0 &~ CSR0_DSL_MASK;
/* General-purpose timer works in continuous mode */
@ -198,39 +211,41 @@ MSS_MAC_init
/* Start general-purpose */
MAC->CSR11 = (MAC->CSR11 & ~CSR11_TIM_MASK) | (0x0000FFFFuL << CSR11_TIM_SHIFT);
/* Disable promiscuous mode */
MAC_BITBAND->CSR6_PR = 0u;
/* Enable store and forward */
MAC_BITBAND->CSR6_SF = 1u;
/* Ensure promiscous mode is off (it should be by default anyway). */
MAC_BITBAND->CSR6_PR = 0;
/* Perfect filter. */
MAC_BITBAND->CSR6_HP = 1;
/* Pass multcast. */
MAC_BITBAND->CSR6_PM = 1;
/* Set descriptors */
MAC->CSR3 = (uint32_t)&(g_mss_mac.rx_descriptors[0].descriptor_0);
MAC->CSR4 = (uint32_t)&(g_mss_mac.tx_descriptors[0].descriptor_0);
/* enable normal interrupts */
MAC_BITBAND->CSR7_NIE = 1u;
/* Set default MAC address and reset mac filters */
MAC_memcpy( g_mss_mac.mac_address, mac_address, 6u );
MSS_MAC_set_mac_address((uint8_t *)mac_address);
/* Detect PHY */
if( g_mss_mac.phy_address > MSS_PHY_ADDRESS_MAX )
{
PHY_probe();
ASSERT( g_mss_mac.phy_address <= MSS_PHY_ADDRESS_MAX );
configASSERT( g_mss_mac.phy_address <= MSS_PHY_ADDRESS_MAX );
}
/* Reset PHY */
PHY_reset();
/* Set flags */
g_mss_mac.flags = FLAG_MAC_INIT_DONE | FLAG_PERFECT_FILTERING;
/* Configure chip according to PHY status */
MSS_MAC_auto_setup_link();
/* Set default MAC address and reset mac filters */
MAC_memcpy( g_mss_mac.mac_address, mac_address, 6u );
MSS_MAC_set_mac_filters( 0u, NULL_buffer );
MAC_BITBAND->CSR6_RA = 1; /* Receive all. */
/* Ensure uip_buf starts by pointing somewhere. */
uip_buf = MAC_obtain_buffer();
}
@ -259,18 +274,16 @@ MSS_MAC_configure
{
int32_t ret;
ASSERT( MAC_test_instance() == MAC_OK );
ret = MAC_stop_transmission();
ASSERT( ret == MAC_OK );
configASSERT( ret == MAC_OK );
ret = MAC_stop_receiving();
ASSERT( ret == MAC_OK );
configASSERT( ret == MAC_OK );
MAC_BITBAND->CSR6_RA = (uint32_t)(((configuration & MSS_MAC_CFG_RECEIVE_ALL) != 0u) ? 1u : 0u );
MAC_BITBAND->CSR6_TTM = (((configuration & MSS_MAC_CFG_TRANSMIT_THRESHOLD_MODE) != 0u) ? 1u : 0u );
MAC_BITBAND->CSR6_SF = (uint32_t)(((configuration & MSS_MAC_CFG_STORE_AND_FORWARD) != 0u) ? 1u : 0u );
switch( configuration & MSS_MAC_CFG_THRESHOLD_CONTROL_11 ) {
case MSS_MAC_CFG_THRESHOLD_CONTROL_00:
MAC->CSR6 = MAC->CSR6 & ~CSR6_TR_MASK;
@ -322,8 +335,6 @@ MSS_MAC_get_configuration( void )
{
uint32_t configuration;
ASSERT( MAC_test_instance() == MAC_OK );
configuration = 0u;
if( MAC_BITBAND->CSR6_RA != 0u ) {
configuration |= MSS_MAC_CFG_RECEIVE_ALL;
@ -370,7 +381,7 @@ MSS_MAC_get_configuration( void )
if( MAC_BITBAND->CSR6_HP != 0u ) {
configuration |= MSS_MAC_CFG_HASH_PERFECT_RECEIVE_FILTERING_MODE;
}
return (int32_t)configuration;
}
@ -382,11 +393,11 @@ MSS_MAC_get_configuration( void )
the transmit FIFO and then activates the transmitter for this packet. If space
is available in the FIFO, the function will return once pac_len bytes of the
packet have been placed into the FIFO and the transmitter has been started.
This function will not wait for the transmission to complete.
This function will not wait for the transmission to complete.
@return
The function returns zero if a timeout occurs otherwise it returns size of the packet.
@see MAC_rx_packet()
*/
@ -399,42 +410,42 @@ MSS_MAC_tx_packet
uint32_t desc;
unsigned long ulDescriptor;
int32_t error = MAC_OK;
extern unsigned char *uip_buf;
ASSERT( MAC_test_instance() == MAC_OK );
configASSERT( uip_buf != NULL_buffer );
ASSERT( uip_buf != NULL_buffer );
ASSERT( usLength >= 12 );
configASSERT( usLength >= 12 );
if( (g_mss_mac.flags & FLAG_EXCEED_LIMIT) == 0u )
{
ASSERT( usLength <= MSS_MAX_PACKET_SIZE );
configASSERT( usLength <= MSS_MAX_PACKET_SIZE );
}
/* Check if second descriptor is free, if it is then the first must
also be free. */
if(((g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == TDES0_OWN )
if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) || ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == TDES0_OWN ) )
{
error = MAC_BUFFER_IS_FULL;
}
if( error == MAC_OK ) {
/* Assumed TX_RING_SIZE == 2. */
if( error == MAC_OK )
{
/* Assumed TX_RING_SIZE == 2. A #error directive checks this is the
case. */
for( ulDescriptor = 0; ulDescriptor < TX_RING_SIZE; ulDescriptor++ )
{
g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_1 = 0u;
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 = 0u;
if( (g_mss_mac.flags & FLAG_CRC_DISABLE) != 0u ) {
g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_1 |= TDES1_AC;
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_AC;
}
/* Every buffer can hold a full frame so they are always first and last
descriptor */
g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_1 |= TDES1_LS | TDES1_FS;
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= TDES1_LS | TDES1_FS | TDES1_IC;
/* set data size */
g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_1 |= usLength;
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_1 |= usLength;
/* reset end of ring */
g_mss_mac.tx_descriptors[TX_RING_SIZE-1].descriptor_1 |= TDES1_TER;
@ -445,10 +456,10 @@ MSS_MAC_tx_packet
}
/* The data buffer is assigned to the Tx descriptor. */
g_mss_mac.tx_descriptors[ ulDescriptor ].buffer_1 = ( unsigned long ) uip_buf;
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].buffer_1 = ( unsigned long ) uip_buf;
/* update counters */
desc = g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_0;
desc = g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0;
if( (desc & TDES0_LO) != 0u ) {
g_mss_mac.statistics.tx_loss_of_carrier++;
}
@ -468,26 +479,22 @@ MSS_MAC_tx_packet
(desc >> TDES0_CC_OFFSET) & TDES0_CC_MASK;
/* Give ownership of descriptor to the MAC */
g_mss_mac.tx_descriptors[ ulDescriptor ].descriptor_0 = TDES0_OWN;
g_mss_mac.tx_desc_index = 0;
}
g_mss_mac.tx_descriptors[ g_mss_mac.tx_desc_index ].descriptor_0 = RDES0_OWN;
g_mss_mac.tx_desc_index = (g_mss_mac.tx_desc_index + 1u) % (uint32_t)TX_RING_SIZE;
MAC_start_transmission();
MAC->CSR1 = 1u;
}
}
/* Start transmission */
MAC_start_transmission();
/* transmit poll demand */
MAC->CSR1 = 1u;
if (error == MAC_OK)
{
/* The buffer uip_buf was pointing to is now under the control of the
MAC (it is being transmitted). Set uip_buf to point to a free buffer. */
uip_buf = MAC_obtain_buffer();
error = (int32_t)usLength;
/* The buffer pointed to by uip_buf is now assigned to a Tx descriptor.
Find anothere free buffer for uip_buf. */
uip_buf = MAC_obtain_buffer();
}
else
{
@ -512,8 +519,6 @@ MSS_MAC_rx_pckt_size
)
{
int32_t retval;
ASSERT( MAC_test_instance() == MAC_OK );
MAC_dismiss_bad_frames();
if( (g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 & RDES0_OWN) != 0u )
@ -535,7 +540,7 @@ MSS_MAC_rx_pckt_size
* Receives a packet from the Ethernet Controller into the uIP stack.
* This function reads a packet from the receive FIFO of the controller and
* places it into uip_buf.
* @return Size of packet if packet fits in uip_buf.
* 0 if there is no received packet.
* @see MAC_rx_pckt_size()
@ -549,8 +554,6 @@ MSS_MAC_rx_packet
{
uint16_t frame_length=0u;
ASSERT( MAC_test_instance() == MAC_OK );
MAC_dismiss_bad_frames();
if( (g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].descriptor_0 & RDES0_OWN) == 0u )
@ -565,7 +568,7 @@ MSS_MAC_rx_packet
if( frame_length > macBUFFER_SIZE ) {
return MAC_NOT_ENOUGH_SPACE;
}
/* uip_buf is about to point to the buffer that contains the received
data, mark the buffer that uip_buf is currently pointing to as free
again. */
@ -585,7 +588,7 @@ MSS_MAC_rx_packet
/***************************************************************************//**
* Receives a packet from the Ethernet Controller.
* This function reads a packet from the receive FIFO of the controller and
* sets the address of pacData to the received data.
* sets the address of pacData to the received data.
* If time_out parameter is zero the function will return
* immediately (after the copy operation if data is available. Otherwise the function
* will keep trying to read till time_out expires or data is read, if MSS_MAC_BLOCKING
@ -614,9 +617,7 @@ MSS_MAC_rx_packet_ptrset
uint16_t frame_length = 0u;
int8_t exit = 0;
ASSERT( MAC_test_instance() == MAC_OK );
ASSERT( (time_out == MSS_MAC_BLOCKING) ||
configASSERT( (time_out == MSS_MAC_BLOCKING) ||
(time_out == MSS_MAC_NONBLOCKING) ||
((time_out >= 1) && (time_out <= 0x01000000UL)) );
@ -653,11 +654,11 @@ MSS_MAC_rx_packet_ptrset
/* Here we are setting the buffer 'pacData' address to the address
RX descriptor address. After this is called, the following function
must be called 'MAC_prepare_rx_descriptor'
must be called 'MAC_prepare_rx_descriptor'
to prepare the current rx descriptor for receiving the next packet.
*/
*pacData = (uint8_t *)g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].buffer_1 ;
*/
*pacData = (uint8_t *)g_mss_mac.rx_descriptors[ g_mss_mac.rx_desc_index ].buffer_1 ;
}
return ((int32_t)frame_length);
}
@ -679,8 +680,6 @@ MSS_MAC_link_status
{
uint32_t link;
ASSERT( MAC_test_instance() == MAC_OK );
link = PHY_link_status();
if( link == MSS_MAC_LINK_STATUS_LINK ) {
link |= PHY_link_type();
@ -706,7 +705,6 @@ MSS_MAC_auto_setup_link
)
{
int32_t link;
ASSERT( MAC_test_instance() == MAC_OK );
PHY_auto_negotiate();
@ -741,9 +739,8 @@ MSS_MAC_set_mac_address
const uint8_t *new_address
)
{
ASSERT( MAC_test_instance() == MAC_OK );
/* Check if the new address is unicast */
ASSERT( (new_address[0]&1) == 0 );
configASSERT( (new_address[0]&1) == 0 );
MAC_memcpy( g_mss_mac.mac_address, new_address, 6u );
@ -777,8 +774,6 @@ MSS_MAC_get_mac_address
uint8_t *address
)
{
ASSERT( MAC_test_instance() == MAC_OK );
MAC_memcpy( address, g_mss_mac.mac_address, 6u );
}
@ -796,13 +791,12 @@ MSS_MAC_set_mac_filters
const uint8_t *filters
)
{
ASSERT( MAC_test_instance() == MAC_OK );
ASSERT( (filter_count==0) || (filters != NULL_buffer) );
configASSERT( (filter_count==0) || (filters != NULL_buffer) );
/* Check if the mac addresses is multicast */
{
int32_t a;
for( a = 0u; a < filter_count; a++ ) {
ASSERT( (filters[a*6]&1) == 1 );
configASSERT( (filters[a*6]&1) == 1 );
}
}
@ -852,8 +846,6 @@ void EthernetMAC_IRQHandler( void )
uint32_t events;
uint32_t intr_status;
ASSERT( MAC_test_instance() == MAC_OK );
events = 0u;
intr_status = MAC->CSR5;
@ -871,7 +863,7 @@ void EthernetMAC_IRQHandler( void )
/* Clear interrupts */
MAC->CSR5 = CSR5_INT_BITS;
if( (events != 0u) && (g_mss_mac.listener != NULL_callback) ) {
g_mss_mac.listener( events );
}
@ -896,12 +888,10 @@ MSS_MAC_set_callback
MSS_MAC_callback_t listener
)
{
ASSERT( MAC_test_instance() == MAC_OK );
/* disable tx and rx interrupts */
MAC_BITBAND->CSR7_RIE = 0u;
MAC_BITBAND->CSR7_TIE = 0u;
g_mss_mac.listener = listener;
if( listener != NULL_callback ) {
@ -929,8 +919,6 @@ MSS_MAC_last_error
{
int8_t error_msg_nb;
const int8_t* returnvalue;
ASSERT( MAC_test_instance() == MAC_OK );
error_msg_nb = -(g_mss_mac.last_error);
if( error_msg_nb >= ERROR_MESSAGE_COUNT ) {
@ -957,7 +945,6 @@ MSS_MAC_get_statistics
)
{
uint32_t returnval = 0u;
ASSERT( MAC_test_instance() == MAC_OK );
switch( stat_id ) {
case MSS_MAC_RX_INTERRUPTS:
@ -1024,31 +1011,6 @@ MSS_MAC_get_statistics
/**************************** INTERNAL FUNCTIONS ******************************/
/***************************************************************************//**
* Checks if instace is valid.
*/
static int32_t
MAC_test_instance
(
void
)
{
uint32_t val1;
uint32_t val2;
int32_t retval = MAC_WRONG_PARAMETER;
val1 = MAC->CSR3;
val2 = MAC->CSR4;
if( (&g_mss_mac != NULL_instance) &&
((g_mss_mac.flags & FLAG_MAC_INIT_DONE) != 0u) &&
( val1 == (uint32_t)g_mss_mac.rx_descriptors) &&
(val2 == (uint32_t)g_mss_mac.tx_descriptors ) )
{
retval = MAC_OK;
}
return retval;
}
/***************************************************************************//**
* Prepares current rx descriptor for receiving.
@ -1087,7 +1049,7 @@ MSS_MAC_prepare_rx_descriptor
if( (desc & RDES0_CE) != 0u ) {
g_mss_mac.statistics.rx_crc_error++;
}
desc = MAC->CSR8;
g_mss_mac.statistics.rx_fifo_overflow +=
(desc & (CSR8_OCO_MASK|CSR8_FOC_MASK)) >> CSR8_FOC_SHIFT;
@ -1166,22 +1128,22 @@ MAC_send_setup_frame
/* Stop transmission */
ret = MAC_stop_transmission();
ASSERT( ret == MAC_OK );
configASSERT( ret == MAC_OK );
ret = MAC_stop_receiving();
ASSERT( ret == MAC_OK );
configASSERT( ret == MAC_OK );
/* Set descriptor */
MAC->CSR4 = (uint32_t)&descriptor;
/* Start transmission */
MAC_start_transmission();
/* Wait until transmission over */
ret = MAC_OK;
MAC_set_time_out( (uint32_t)SETUP_FRAME_TIME_OUT );
while( (((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) !=
while( (((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) !=
CSR5_TS_SUSPENDED) && (MAC_OK == ret) )
{
/* transmit poll demand */
@ -1195,7 +1157,7 @@ MAC_send_setup_frame
/* Set tx descriptor */
MAC->CSR4 = (uint32_t)g_mss_mac.tx_descriptors;
/* Start receiving and transmission */
MAC_start_receiving();
MAC_start_transmission();
@ -1219,7 +1181,7 @@ MAC_stop_transmission
{
int32_t retval = MAC_OK;
MAC_set_time_out( (uint16_t)STATE_CHANGE_TIME_OUT );
while( (((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) !=
CSR5_TS_STOPPED) && (retval == MAC_OK) )
{
@ -1300,7 +1262,7 @@ MAC_dismiss_bad_frames
{
int32_t dc = 0;
int8_t cont = 1;
if( MAC_BITBAND->CSR6_PB != 0u ) {
/* User wants bad frames too, don't dismiss anything */
cont = 0;
@ -1357,14 +1319,14 @@ MAC_get_time_out
{
uint32_t timer;
uint32_t time = 0u;
timer = ( MAC->CSR11 & CSR11_TIM_MASK );
if( timer > g_mss_mac.last_timer_value ) {
time = 0x0000ffffUL;
}
time += g_mss_mac.last_timer_value - timer;
if( MAC_BITBAND->CSR6_TTM == 0u ) {
time *= 10u;
}
@ -1409,10 +1371,6 @@ static void MAC_memset_All(MAC_instance_t *s, uint32_t c)
MAC_memset( s->mac_address, (uint8_t)c, 6u );
MAC_memset( s->mac_filter_data, (uint8_t)c, 90u );
s->phy_address = (uint8_t)c;
// for(count = 0; count<RX_RING_SIZE ;count++)
// {
// MAC_memset(s->rx_buffers[count], (uint8_t)c, (MSS_RX_BUFF_SIZE + 4u) );
// }
s->rx_desc_index =c;
for(count = 0; count<RX_RING_SIZE ;count++)
{
@ -1440,10 +1398,6 @@ static void MAC_memset_All(MAC_instance_t *s, uint32_t c)
s->statistics.tx_no_carrier = c;
s->statistics.tx_underflow_error = c;
s->time_out_value = c;
// for(count = 0; count < TX_RING_SIZE ;count++)
// {
// MAC_memset( s->tx_buffers[count], (uint8_t)c, MSS_TX_BUFF_SIZE );
// }
s->tx_desc_index = c;
for(count = 0; count < TX_RING_SIZE ;count++)
{
@ -1470,21 +1424,28 @@ static void MAC_memcpy(uint8_t *dest, const uint8_t *src, uint32_t n)
}
}
void MSS_MAC_TxBufferCompleted( void )
/***************************************************************************//**
* Tx has completed, mark the buffers that were assigned to the Tx descriptors
* as free again.
*
*/
void MSS_MAC_FreeTxBuffers( void )
{
unsigned char *pxTransmittedBuffer;
/* Was it the second transmission that has completed? */
if( ( g_mss_mac.tx_descriptors[ 1 ].descriptor_0 & TDES0_OWN ) == 0UL )
if( ( ( (g_mss_mac.tx_descriptors[ 0 ].descriptor_0) & TDES0_OWN) == 0 ) && ( ( (g_mss_mac.tx_descriptors[ 1 ].descriptor_0) & TDES0_OWN) == 0 ) )
{
pxTransmittedBuffer = ( unsigned char * ) g_mss_mac.tx_descriptors[ 1 ].buffer_1;
/* The buffer has been transmitted and is no longer in use. */
MAC_release_buffer( pxTransmittedBuffer );
MAC_release_buffer( ( unsigned char * ) g_mss_mac.tx_descriptors[ 0 ].buffer_1 );
MAC_release_buffer( ( unsigned char * ) g_mss_mac.tx_descriptors[ 1 ].buffer_1 );
}
}
static unsigned char *MAC_obtain_buffer( void )
/***************************************************************************//**
* Look through the array of buffers until one is found that is free for use -
* that is, not currently assigned to an Rx or a Tx descriptor. Mark the buffer
* as in use, then return its address.
*
* @return a pointer to a free buffer.
*/
unsigned char *MAC_obtain_buffer( void )
{
long lIndex;
unsigned char *pcReturn = NULL;
@ -1493,9 +1454,10 @@ unsigned char *pcReturn = NULL;
the buffer as now in use. */
for( lIndex = 0; lIndex < macNUM_BUFFERS; lIndex++ )
{
if( ucMACBufferFree[ lIndex ] == pdTRUE )
if( ucMACBufferInUse[ lIndex ] == pdFALSE )
{
pcReturn = &( ucMACBuffers[ lIndex ][ 0 ] );
pcReturn = &( xMACBuffers.ucBuffer[ lIndex ][ 0 ] );
ucMACBufferInUse[ lIndex ] = pdTRUE;
break;
}
}
@ -1504,6 +1466,10 @@ unsigned char *pcReturn = NULL;
return pcReturn;
}
/***************************************************************************//**
* Return a buffer to the list of free buffers, it was in use, but is not now.
*
*/
void MAC_release_buffer( unsigned char *pucBufferToRelease )
{
long lIndex;
@ -1512,13 +1478,15 @@ long lIndex;
it is currently pointing to is marked as being free again. */
for( lIndex = 0; lIndex < macNUM_BUFFERS; lIndex++ )
{
if( pucBufferToRelease == &( ucMACBuffers[ lIndex ][ 0 ] ) )
if( pucBufferToRelease == &( xMACBuffers.ucBuffer[ lIndex ][ 0 ] ) )
{
/* This is the buffer in use, mark it as being free. */
ucMACBufferFree[ lIndex ] = pdTRUE;
ucMACBufferInUse[ lIndex ] = pdFALSE;
break;
}
}
configASSERT( lIndex < macNUM_BUFFERS );
}

46
Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/drivers/mss_ethernet_mac/mss_ethernet_mac.h
View file

@ -16,7 +16,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
/******************************** DEFINES *************************************/
@ -160,7 +160,7 @@ extern "C" {
#define MSS_PHY_ADDRESS_AUTO_DETECT 255u
/***************************************************************************//**
* Listener function type defines the function prototype that might be followed
* Listener function type defines the function prototype that might be followed
* by MAC_isr which is triggered with each receive and transmit related interrupts.
* Listener functions should follow the following prototype:
* void MAC_Listener( uint32_t events );
@ -168,7 +168,7 @@ extern "C" {
* or events. Events input to the system are:
* #define MSS_MAC_EVENT_PACKET_SEND 1
* #define MSS_MAC_EVENT_PACKET_RECEIVED 2
* Listener function should be defined by the application using this driver if
* Listener function should be defined by the application using this driver if
* needed. This function may be assigned to the driver using MAC_set_callback
* routine and may be un assigned again by using the same routine with a NULL pointer
* as the event listener function. It is recommended to use this property for interrupt
@ -177,7 +177,7 @@ extern "C" {
typedef void (*MSS_MAC_callback_t)(uint32_t events);
/***************************************************************************//**
* Statistics counter identifiers are used with MAC_get_statistics routine to
* Statistics counter identifiers are used with MAC_get_statistics routine to
* receive the count of the requested errors/interrupts occurrences.
*
* MSS_MAC_RX_INTERRUPTS
@ -270,7 +270,7 @@ typedef enum {
MSS_MAC_TX_EXCESSIVE_COLLISION,
MSS_MAC_TX_COLLISION_COUNT,
MSS_MAC_TX_UNDERFLOW_ERROR
} mss_mac_statistics_id_t;
} mss_mac_statistics_id_t;
/******************************* FUNCTIONS ************************************/
@ -317,7 +317,7 @@ MSS_MAC_configure
/***************************************************************************//**
* Returns the configuration of the Ethernet Controller.
* After the MAC_init function has been called, this API function can be used to
* After the MAC_init function has been called, this API function can be used to
* get the configuration of the Ethernet Controller.
*
* @return The logical OR of the following values:
@ -366,7 +366,7 @@ MSS_MAC_tx_packet
* Returns available packet's size.
*
* @return Size of packet, bigger than 0, if a packet is available,
* if not, returns 0.
* if not, returns 0.
* @see MAC_rx_packet()
*/
int32_t
@ -416,26 +416,26 @@ MSS_MAC_rx_packet
used by the user application or copied to another buffer, the
MSS_MAC_prepare_rx_descriptor() function must be called to free up the receive
memory buffer used by the MSS Ethernet MAC
@param pacData
The pacData parameter is a pointer to a memory buffer pointer. The uint8_t
pointer pointed to by the pacData parameter will contain the address of the
memory buffer containing the received packet after this function returns. The
value of pacData is only valid if the return value is larger than zero,
indicating that a packet was received.
@param time_out
The time_out parameter is the timeout value for the transmission in milliseconds.
The time_out parameter value can be one of the following values:
• Unsigned integer greater than 0 and less than 0x01000000
• MSS_MAC_BLOCKING – there will be no timeout.
• MSS_MAC_BLOCKING – there will be no timeout.
• MSS_MAC_NONBLOCKING – the function will return immediately if no packets
have been received.
have been received.
@return
The function returns the size of the packet if the packet fits in pacData.
Returns zero if there is no received packet.
@see MAC_rx_pckt_size()
@see MAC_tx_packet()
*/
@ -537,10 +537,10 @@ MSS_MAC_set_callback
/***************************************************************************//**
* Returns description of latest error happened.
*
* @return A string describing the error. This string must not be
* @return A string describing the error. This string must not be
* modified by the application.
*/
const int8_t*
const int8_t*
MSS_MAC_last_error
(
void
@ -549,7 +549,7 @@ MSS_MAC_last_error
/***************************************************************************//**
* Returns statistics counter of stat_id identifier.
*
*
* @param stat_id Identifier of statistics counter.
* @return Statistics counter of stat_id identifier.
* On error returns 0.
@ -560,23 +560,11 @@ MSS_MAC_get_statistics
mss_mac_statistics_id_t stat_id
);
/*
* Ensure uip_buf is pointing to a valid and free buffer before any transmissions
* initiated by the uIP stack occur.
*/
unsigned char *MSS_MAC_GetTxDescriptor( void );
/*
* A buffer is no longer required by the application. Hand it back to the
* control of the MAC hardware.
*/
void MSS_MAC_ReleaseBuffer( unsigned char *pucBuffer );
/*
* The double Tx has completed. Hand back the Tx buffer to the control of
* the MAC hardware.
* the MAC hardware.
*/
void MSS_MAC_TxBufferCompleted( void );
void MSS_MAC_FreeTxBuffers( void );
#ifdef __cplusplus
}
#endif

120
Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/drivers/mss_ethernet_mac/mss_ethernet_mac_regs.h
View file

@ -19,12 +19,12 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif
#include "../../CMSIS/a2fxxxm3.h"
#include "mss_ethernet_mac.h"
#include "mss_ethernet_mac_user_cfg.h"
typedef uint32_t addr_t;
@ -42,78 +42,78 @@ typedef struct {
/***************************************************************************//**
* There should be one instance of this structure for each instance of
* the MAC in your system. MSS_MAC_init routine initializes this structure.
* It is used to identify the various MACs in your system and an initilized
* MAC instance's structure should be passed as first parameter to MAC functions
* It is used to identify the various MACs in your system and an initilized
* MAC instance's structure should be passed as first parameter to MAC functions
* to identify which MAC should perform the requested operation.
* Software using the MAC driver should only need to create one single
* instance of this data structure for each MAC hardware instance in
* Software using the MAC driver should only need to create one single
* instance of this data structure for each MAC hardware instance in
* the system. Using MAC_get_configuration routine, latest status of the driver
* may be read by receiving its flags field, similarly MAC_configure routine lets
* you modify some of these flags.
*/
#include "net/pack_struct_start.h"
typedef struct {
addr_t base_address; /**< Register base address of the driver*/
uint8_t flags; /**< Configuration of the driver*/
int8_t last_error; /**< Index of last error happened inside the driver*/
uint8_t mac_address[6]; /**< MAC address of the drived instance*/
uint8_t mac_filter_data[90]; /**< MAC filter data, 15 addresses to be used for
uint8_t mac_filter_data[90]; /**< MAC filter data, 15 addresses to be used for
received data filtering*/
uint16_t last_timer_value; /**< Last read value of timer */
uint32_t time_out_value; /**< Time out value */
MSS_MAC_callback_t listener; /**< Pointer to the call-back function to be triggered
MSS_MAC_callback_t listener; /**< Pointer to the call-back function to be triggered
when a package is received*/
/* transmit related info: */
uint32_t tx_desc_index; /**< index of the transmit descriptor getting used*/
// uint8_t tx_buffers[TX_RING_SIZE][MSS_TX_BUFF_SIZE];/**< array of transmit buffers*/
MAC_descriptor_t tx_descriptors[TX_RING_SIZE];/**< array of transmit descriptors*/
/* receive related info: */
uint32_t rx_desc_index; /**< index of the receive descriptor getting used*/
// uint8_t rx_buffers[RX_RING_SIZE][MSS_RX_BUFF_SIZE+4];/**< array of receive buffers*/
MAC_descriptor_t rx_descriptors[RX_RING_SIZE];/**< array of receive descriptors*/
uint8_t phy_address; /**< MII address of the connected PHY*/
struct {
uint32_t rx_interrupts; /**< Number of receive interrupts occurred.*/
uint32_t rx_filtering_fail; /**< Number of received frames which did not pass
uint32_t rx_filtering_fail; /**< Number of received frames which did not pass
the address recognition process.*/
uint32_t rx_descriptor_error; /**< Number of occurrences of; no receive buffer was
available when trying to store the received data.*/
uint32_t rx_runt_frame; /**< Number of occurrences of; the frame is damaged by
a collision or by a premature termination before
uint32_t rx_runt_frame; /**< Number of occurrences of; the frame is damaged by
a collision or by a premature termination before
the end of a collision window.*/
uint32_t rx_not_first; /**< Number of occurrences of; start of the frame is
uint32_t rx_not_first; /**< Number of occurrences of; start of the frame is
not the first descriptor of a frame.*/
uint32_t rx_not_last; /**< Number of occurrences of; end of the frame is not
uint32_t rx_not_last; /**< Number of occurrences of; end of the frame is not
the first descriptor of a frame.*/
uint32_t rx_frame_too_long; /**< Number of occurrences of; a current frame is
longer than maximum size of 1,518 bytes, as specified
uint32_t rx_frame_too_long; /**< Number of occurrences of; a current frame is
longer than maximum size of 1,518 bytes, as specified
by 802.3.*/
uint32_t rx_collision_seen; /**< Number of occurrences of; a late collision was seen
uint32_t rx_collision_seen; /**< Number of occurrences of; a late collision was seen
(collision after 64 bytes following SFD).*/
uint32_t rx_crc_error; /**< Number of occurrences of; a CRC error has occurred
uint32_t rx_crc_error; /**< Number of occurrences of; a CRC error has occurred
in the received frame.*/
uint32_t rx_fifo_overflow; /**< Number of frames not accepted due to the receive
uint32_t rx_fifo_overflow; /**< Number of frames not accepted due to the receive
FIFO overflow.*/
uint32_t rx_missed_frame; /**< Number of frames not accepted due to the
uint32_t rx_missed_frame; /**< Number of frames not accepted due to the
unavailability of the receive descriptor.*/
uint32_t tx_interrupts; /**< Number of transmit interrupts occurred.*/
uint32_t tx_loss_of_carrier; /**< Number of occurrences of; a loss of the carrier
uint32_t tx_loss_of_carrier; /**< Number of occurrences of; a loss of the carrier
during a transmission.*/
uint32_t tx_no_carrier; /**< Number of occurrences of; the carrier was not asserted
by an external transceiver during the transmission.*/
uint32_t tx_late_collision; /**< Number of occurrences of; a collision was detected
uint32_t tx_late_collision; /**< Number of occurrences of; a collision was detected
after transmitting 64 bytes.*/
uint32_t tx_excessive_collision;/**< Number of occurrences of; the transmission was
uint32_t tx_excessive_collision;/**< Number of occurrences of; the transmission was
aborted after 16 retries.*/
uint32_t tx_collision_count; /**< Number of collisions occurred.*/
uint32_t tx_underflow_error; /**< Number of occurrences of; the FIFO was empty during
uint32_t tx_underflow_error; /**< Number of occurrences of; the FIFO was empty during
the frame transmission.*/
} statistics;
} MAC_instance_t;
} MAC_instance_t
#include "net/pack_struct_end.h"
/*------------------------------------------------------------------------------
@ -130,29 +130,29 @@ typedef struct
uint32_t CSR0_TAP[3];
uint32_t CSR0_DBO;
uint32_t CSR0_RESERVED1[11];
uint32_t MAC_CSR_RESERVED0[32];
uint32_t CSR1[32];
uint32_t MAC_CSR_RESERVED1[32];
uint32_t CSR2[32];
uint32_t MAC_CSR_RESERVED2[32];
uint32_t CSR3[32];
uint32_t MAC_CSR_RESERVED3[32];
uint32_t CSR4[32];
uint32_t MAC_CSR_RESERVED4[32];
uint32_t CSR5_TI;
uint32_t CSR5_TPS;
uint32_t CSR5_TU;
uint32_t CSR5_RESERVED0[2];
uint32_t CSR5_RESERVED0[2];
uint32_t CSR5_UNF;
uint32_t CSR5_RI;
uint32_t CSR5_RU;
@ -169,7 +169,7 @@ typedef struct
uint32_t CSR5_RESERVED3[9];
uint32_t MAC_CSR_RESERVED5[32];
uint32_t CSR6_HP;
uint32_t CSR6_SR;
uint32_t CSR6_HO;
@ -191,7 +191,7 @@ typedef struct
uint32_t CSR6_RESERVED5;
uint32_t MAC_CSR_RESERVED6[32];
uint32_t CSR7_TIE;
uint32_t CSR7_TSE;
uint32_t CSR7_TUE;
@ -210,11 +210,11 @@ typedef struct
uint32_t CSR7[15];
uint32_t MAC_CSR_RESERVED7[32];
uint32_t CSR8[32];
uint32_t MAC_CSR_RESERVED8[32];
uint32_t CSR9_SCS;
uint32_t CSR9_SCLK;
uint32_t CSR9_SDI;
@ -227,11 +227,11 @@ typedef struct
uint32_t CSR9_RESERVED1[12];
uint32_t MAC_CSR_RESERVED9[32];
uint32_t CSR10[32];
uint32_t MAC_CSR_RESERVED10[32];
uint32_t CSR11_TIM[16];
uint32_t CSR11_CON;
uint32_t CSR11_NRP[3];
@ -559,19 +559,19 @@ typedef struct
#define CSR5_TS_SHIFT 20
/** 000 - Stopped; RESET or STOP TRANSMIT command issued. */
#define CSR5_TS_STOPPED 0u
#define CSR5_TS_STOPPED 0u
/** 001 - Running, fetching the transmit descriptor. */
#define CSR5_TS_RUNNING_FD 1u
#define CSR5_TS_RUNNING_FD 1u
/** 010 - Running, waiting for end of transmission. */
#define CSR5_TS_RUNNING_WT 2u
#define CSR5_TS_RUNNING_WT 2u
/** 011 - Running, transferring data buffer from host memory to FIFO. */
#define CSR5_TS_RUNNING_TD 3u
#define CSR5_TS_RUNNING_TD 3u
/** 101 - Running, setup packet. */
#define CSR5_TS_RUNNING_SP 5u
#define CSR5_TS_RUNNING_SP 5u
/** 110 - Suspended; FIFO underflow or unavailable descriptor. */
#define CSR5_TS_SUSPENDED 6u
#define CSR5_TS_SUSPENDED 6u
/** 111 - Running, closing transmit descriptor. */
#define CSR5_TS_RUNNING_CD 7u
#define CSR5_TS_RUNNING_CD 7u
/*------------------------------------------------------------------------------
* CSR5_RS:
@ -584,19 +584,19 @@ typedef struct
#define CSR5_RS_SHIFT 17
/** 000 - Stopped; RESET or STOP RECEIVE command issued. */
#define CSR5_RS_STOPPED 0u
#define CSR5_RS_STOPPED 0u
/** 001 - Running, fetching the receive descriptor. */
#define CSR5_RS_RUNNING_FD 1u
#define CSR5_RS_RUNNING_FD 1u
/** 010 - Running, waiting for the end-of-receive packet before prefetch of the
*next descriptor. */
#define CSR5_RS_RUNNING_WR 2u
*next descriptor. */
#define CSR5_RS_RUNNING_WR 2u
/** 011 - Running, waiting for the receive packet. */
#define CSR5_RS_RUNNING_RB 3u
#define CSR5_RS_RUNNING_RB 3u
/** 100 - Suspended, unavailable receive buffer. */
#define CSR5_RS_SUSPENDED 4u
#define CSR5_RS_SUSPENDED 4u
/** 101 - Running, closing the receive descriptor. */
#define CSR5_RS_RUNNING_CD 5u
/** 111 - Running, transferring data from FIFO to host memory. */
#define CSR5_RS_RUNNING_CD 5u
/** 111 - Running, transferring data from FIFO to host memory. */
#define CSR5_RS_RUNNING_TD 7u
/*------------------------------------------------------------------------------