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Added initial RM48 project files. These are not in the correct directory structure yet.

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This commit is contained in:
Richard Barry 2012-10-04 19:47:41 +00:00
parent c403e974ee
commit 57fab18305
53 changed files with 18686 additions and 0 deletions
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198
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_common.h Normal file
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/*----------------------------------------------------------------------------*/
/* sys_common.h 10/20/10 15:19:19 */
/* */
/* (c) Texas Instruments 2003-2010, All rights reserved. */
/* */
#ifndef __sys_common_h__
#define __sys_common_h__
/*----------------------------------------------------------------------------*/
/* NULL */
#ifndef NULL
#define NULL ((void *) 0)
#endif
/*----------------------------------------------------------------------------*/
/* Error Codes */
#define IO_E_OK 0U
#define IO_E_BUSY 1U
#define IO_E_UNKNOWN_MODE 2U
#define IO_E_OVR 3U
#define IO_E_FCN_SUSPENDED 16U
#define IO_E_PARAM_IGNORED 17U
#define IO_E_INVALID_CHANNEL_ID 18U
#define IO_E_INVALID_VALUE 19U
#define IO_E_INVALID_SIZE 20U
#define IO_E_INVALID_POSITION 21U
#define IO_E_INVALID_NOTIF_TYPE 22U
#define IO_E_MISSING_INIT 64U
#define IO_E_INVALID_GROUP_ID 66U
#define IO_E_INVALID_POINTER 67U
#define IO_E_INVALID_NODE 68U
#define IO_E_INVALID_CAN_ID 69U
#define IO_E_INVALID_OVR 70U
#define IO_E_INVALID_CONFIG 72U
#define IO_E_MISSING_CONNECT 73U
#define IO_E_MISSING_DISCONNECT 74U
#define IO_E_ALREADY_CONNECTED 75U
#define IO_E_GRP_NOTACTIVATED 80U
#define IO_E_INVALID_RESULT 81U
#define IO_E_TIMEOUT 82U
#define IO_E_INVALID_PARITY 83U
#define IO_E_SINGLE_ERROR 84U
#define IO_E_DOUBLE_ERROR 85U
#define IO_E_SINGLE_ERROR_EVEN 86U
#define IO_E_SINGLE_ERROR_ODD 87U
#define IO_E_DOUBLE_ERROR_EVEN 88U
#define IO_E_DOUBLE_ERROR_ODD 89U
/*----------------------------------------------------------------------------*/
/* Device Types */
#define IO_SPI 0U
#define IO_DIO 1U
#define IO_TIM 2U
#define IO_PWM 3U
#define IO_CCU 4U
#define IO_RTI 5U
#define IO_WDT 6U
#define IO_ADC 7U
#define IO_SCI 8U
#define IO_FLS 9U
#define IO_CAN 10U
#define IO_QSPI 11U
#define IO_MSPI 11U
#define IO_LIN 12U
#define IO_CRC 13U
#define IO_DMA 14U
#define IO_HTU 15U
#define IO_PWD 16U
#define IO_HET 17U
#define IO_ESM 18U
#define IO_I2C 19U
#define IO_ECC 20U
#define IO_VIM 21U
#define IO_STC 22U
/*----------------------------------------------------------------------------*/
/* Device States */
#define IO_STATE_IDLE 0U
#define IO_STATE_ACTIVE 1U
/*----------------------------------------------------------------------------*/
/* Notification Types */
#define IO_N_RISING_EDGE 0U
#define IO_N_FALLING_EDGE 1U
#define IO_N_THRESHOLD_1 2U
#define IO_N_THRESHOLD_2 3U
#define IO_N_CAPTURE 4U
#define IO_N_ALL 5U
#define IO_N_ROLLOVER 6U
#define IO_N_READY 7U
#define IO_N_FCN_SUSPENDED 8U
#define IO_N_PARITY_ERROR 9U
#define IO_N_FRAMING_ERROR 10U
#define IO_N_BUFFER_OVERRUN 11U
#define IO_N_RECEIVE 12U
#define IO_N_TRANSMIT 13U
#define IO_N_TX_ERROR 15U
#define IO_N_RX_ERROR 16U
#define IO_N_BAUDRATE_ERROR 17U
#define IO_N_PHASE_ERROR 18U
#define IO_N_OCSET 19U
#define IO_N_OCRESET 20U
#define IO_N_RX_LOST 21U
#define IO_N_ACTIVE 22U
#define IO_N_WARNING 23U
#define IO_N_PASSIVE 24U
#define IO_N_BUS_OFF 25U
#define IO_N_WAKE_UP 26U
#define IO_N_LAST_ERROR 27U
#define IO_N_GRP_READY 30U
#define IO_N_ERROR 31U
#define IO_N_HDR_RECEIVE 32U
#define IO_N_HDR_TRANSMIT 33U
#define IO_N_ID_ERROR 34U
#define IO_N_CHECKSUM_ERROR 35U
#define IO_N_BIT_ERROR 36U
#define IO_N_FRAME_TIMEOUT 37U
#define IO_N_BUS_ERROR 38U
#define IO_N_SYNC_FIELD_ERROR 39U
#define IO_N_WAKE_UP_RECEIVE 40U
#define IO_N_WAKE_UP_TRANSMIT 41U
#define IO_N_ADJUST_BAUDRATE 42U
#define IO_N_BUS_IDLE_TIMEOUT 43U
#define IO_N_WAKE_UP_TIMEOUT 44U
/*----------------------------------------------------------------------------*/
/* Programming Interface Constants */
#define IO_LOW 0U
#define IO_HIGH 1U
#define IO_INVALID 0xFFFFU
/*----------------------------------------------------------------------------*/
/* Data Types */
typedef T_U32 IO_ErrorType;
typedef T_U32 IO_DeviceType;
typedef T_U32 IO_FunctionNrType;
typedef T_U32 IO_DeviceStateType;
typedef T_U32 IO_ChannelType;
typedef T_U32 IO_ModeType;
typedef T_U32 IO_ValueType;
typedef T_U32 IO_U32;
/*----------------------------------------------------------------------------*/
/* Error hook */
void IO_ErrorHook(IO_DeviceType device, IO_ErrorType error);
/*----------------------------------------------------------------------------*/
/* ISR Function Prototypes */
void IO_PHANTOM_INT(void);
void IO_ESM_INT_HIGH(void);
void IO_TIM0_INT(void);
void IO_TIM1_INT(void);
void IO_DIO_INT_HIGH(void);
void IO_HET_INT_HIGH(void);
void IO_HTU_INT_HIGH(void);
void IO_MIBSPI1_INT_HIGH(void);
void IO_LIN_INT_HIGH(void);
void IO_MIBADC_INT_GROUP0(void);
void IO_MIBADC_INT_GROUP1(void);
void IO_CAN1_INT_HIGH(void);
void IO_SPI2_INT_HIGH(void);
void IO_ESM_INT_LOW(void);
void IO_DIO_INT_LOW(void);
void IO_HET_INT_LOW(void);
void IO_HTU_INT_LOW(void);
void IO_MIBSPI1_INT_LOW(void);
void IO_LIN_INT_LOW(void);
void IO_MIBADC_INT_GROUP2(void);
void IO_CAN1_INT_LOW(void);
void IO_SPI2_INT_LOW(void);
void IO_MIBADC_INT_MAG(void);
void IO_DMA_INT_FTCA(void);
void IO_DMA_INT_LFSA(void);
void IO_CAN2_INT_HIGH(void);
void IO_MIBSPI3_INT_HIGH(void);
void IO_MIBSPI3_INT_LOW(void);
void IO_DMA_INT_HBCA(void);
void IO_DMA_INT_BTCA(void);
void IO_CAN2_INT_LOW(void);
/*----------------------------------------------------------------------------*/
/* Notification Function Prototypes */
#endif
/*----------------------------------------------------------------------------*/

165
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_core.asm Normal file
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;-------------------------------------------------------------------------------
; sys_core.asm
;
; (c) Texas Instruments 2009, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initialize CPU Registers
.def _coreInitRegisters
_coreInitRegisters:
mov r0, lr
mov r1, #0x0000
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mov r13, #0x0000
cps #0x11
mov lr, r0
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
mov r13, #0x0000
cps #0x12
mov r13, #0x0000
mov lr, r0
cps #0x17
mov r13, #0x0000
mov lr, r0
cps #0x1B
mov r13, #0x0000
mov lr, r0
cps #0x13
mov r13, #0x0000
.if (__TI_VFPV3D16_SUPPORT__)
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
fmdrr d11, r1, r1
fmdrr d12, r1, r1
fmdrr d13, r1, r1
fmdrr d14, r1, r1
fmdrr d15, r1, r1
.endif
bl $+4
bl $+4
bl $+4
bl $+4
bx r0
;-------------------------------------------------------------------------------
; Initialize Stack Pointers
.def _coreInitStackPointer
_coreInitStackPointer:
msr cpsr_c, #0xD1
ldr sp, fiqSp
msr cpsr_c, #0xD2
ldr sp, irqSp
msr cpsr_c, #0xD7
ldr sp, abortSp
msr cpsr_c, #0xDB
ldr sp, undefSp
msr cpsr_c, #0xDF
ldr sp, userSp
msr cpsr_c, #0xD3
ldr sp, svcSp
bx lr
userSp .word 0x00000000+0x00000000
svcSp .word 0x08000000+0x00000100
fiqSp .word 0x00000000+0x00000000
irqSp .word 0x08000100+0x00000100
abortSp .word 0x00000000+0x00000000
undefSp .word 0x00000000+0x00000000
;-------------------------------------------------------------------------------
; Enable VFP Unit
.def _coreEnableVfp
_coreEnableVfp:
.if (__TI_VFPV3D16_SUPPORT__)
mrc p15, #0x00, r0, c1, c0, #0x02
orr r0, r0, #0xF00000
mcr p15, #0x00, r0, c1, c0, #0x02
mov r0, #0x40000000
fmxr fpexc, r0
.endif
bx lr
;-------------------------------------------------------------------------------
; Enable Event Bus Export
.def _coreEnableEventBusExport
_coreEnableEventBusExport:
mrc p15, #0x00, r0, c9, c12, #0x00
orr r0, r0, #0x10
mcr p15, #0x00, r0, c9, c12, #0x00
bx lr
;-------------------------------------------------------------------------------
; Enable RAM ECC Support
.def _coreEnableRamEcc
_coreEnableRamEcc:
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
bx lr
;-------------------------------------------------------------------------------
; Enable Flash ECC Support
.def _coreEnableFlashEcc
_coreEnableFlashEcc:
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x02000000
mcr p15, #0x00, r0, c1, c0, #0x01
bx lr
;-------------------------------------------------------------------------------
; Enable Offset via Vic controller
.def _coreEnableIrqVicOffset
_coreEnableIrqVicOffset:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x01000000
mcr p15, #0, r0, c1, c0, #0
bx lr
;-------------------------------------------------------------------------------

61
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_core.h Normal file
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/** @file sys_core.h
* @brief System Core Header File
* @date 23.July.2009
* @version 1.00.000
*
* This file contains:
* - Core Interface Functions
* .
* which are relevant for the System driver.
*/
/* (c) Texas Instruments 2009, All rights reserved. */
#ifndef __SYS_CORE_H__
#define __SYS_CORE_H__
/* System Core Interface Functions */
/** @fn void _coreInitRegisters_(void)
* @brief Initialize Core register
*/
void _coreInitRegisters(void);
/** @fn void _coreInitStackPointer_(void)
* @brief Initialize Core stack pointer
*/
void _coreInitStackPointer(void);
/** @fn void _coreEnableIrqVicOffset_(void)
* @brief Enable Irq offset propagation via Vic controller
*/
void _coreEnableIrqVicOffset(void);
/** @fn void _coreEnableEventBusExport_(void)
* @brief Enable event bus export for external monitoring modules
* @note It is required to enable event bus export to process ecc issues.
*
* This function enables event bus exports to external monitoring modules
* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
*/
void _coreEnableEventBusExport(void);
/** @fn void _coreEnableRamEcc_(void)
* @brief Enable external ecc error for RAM odd and even bank
* @note It is required to enable event bus export to process ecc issues.
*/
void _coreEnableRamEcc(void);
/** @fn void _coreEnableFlashEcc_(void)
* @brief Enable external ecc error for the Flash
* @note It is required to enable event bus export to process ecc issues.
*/
void _coreEnableFlashEcc(void);
/** @fn void _coreEnableVfp(void)
* @brief Enable Cortex-R4 FPU
*/
void _coreEnableVfp();
#endif

28
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_intvecs.asm Normal file
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;-------------------------------------------------------------------------------
; sys_intvecs.asm
;
; (c) Texas Instruments 2009-2010, All rights reserved.
;
.sect ".intvecs"
;-------------------------------------------------------------------------------
; import reference for interrupt routines
.ref _c_int00
.ref vPortYieldProcessor
;-------------------------------------------------------------------------------
; interrupt vectors
b _c_int00
b #-8
b vPortYieldProcessor
b #-8
b #-8
b #-8
ldr pc,[pc,#-0x1b0]
ldr pc,[pc,#-0x1b0]
;-------------------------------------------------------------------------------

36
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_memory.asm Normal file
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;-------------------------------------------------------------------------------
; sys_memory.asm
;
; (c) Texas Instruments 2009, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initialize memory
.def _memoryInit
_memoryInit:
ldr r12, regMinitGcr ; MINITGCR register pointer
mov r4, #0xA
str r4, [r12]
ldr r4, ramInitMask ; load RAM initialization mask
str r4, [r12, #4]
mloop
ldr r5, [r12, #12]
tst r5, #0x100
beq mloop
mov r4, #5
str r4, [r12]
bx lr
ramInitMask .word 0x00000001
regMinitGcr .word 0xFFFFFF5C
;-------------------------------------------------------------------------------

22
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_memory.h Normal file
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/** @file sys_memory.h
* @brief System Memory Header File
* @date 23.July.2009
* @version 1.00.000
*
* This file contains:
* - Memory Interface Functions
* .
* which are relevant for the System driver.
*/
/* (c) Texas Instruments 2009, All rights reserved. */
#ifndef __SYS_MEMORY_H__
#define __SYS_MEMORY_H__
/** @fn void _memoryInit_(void)
* @brief Automatic hardware memory initialization
*/
void _memoryInit(void);
#endif

19
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_phantom.c Normal file
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/** @file sys_phantom.c
* @brief Phantom Interrupt Source File
* @date 15.July.2009
* @version 1.00.000
*
* This file contains:
* - Phantom Interrupt Handler
*/
/* (c) Texas Instruments 2009, All rights reserved. */
/* Phantom Interrupt Handler */
#pragma INTERRUPT(phantomInterrupt, IRQ)
void phantomInterrupt(void)
{
for(;;);
}

324
FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_startup.c Normal file
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/** @file sys_startup.c
* @brief Startup Source File
* @date 05.November.2010
* @version 1.01.001
*
* This file contains:
* - Include Files
* - Type Definitions
* - External Functions
* - VIM RAM Setup
* - Startup Routine
* .
* which are relevant for the Starup.
*/
/* (c) Texas Instruments 2010, All rights reserved. */
/* Include Files */
#include "sys_types.h"
#include "sys_common.h"
#include "sys_system.h"
#include "sys_vim.h"
#include "sys_core.h"
#include "sys_memory.h"
/* External Functions */
extern void __TI_auto_init(void);
extern void main(void);
extern void exit(int);
/* Vim Ram Definition */
/** @struct vimRam
* @brief Vim Ram Definition
*
* This type is used to access the Vim Ram.
*/
/** @typedef vimRAM_t
* @brief Vim Ram Type Definition
*
* This type is used to access the Vim Ram.
*/
typedef volatile struct vimRam
{
t_isrFuncPTR ISR[VIM_CHANNELS];
} vimRAM_t;
#define vimRAM ((vimRAM_t *)0xFFF82000U)
static const t_isrFuncPTR s_vim_init[] =
{
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
vPreemptiveTick, /* RTI */
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
vPortYeildWithinAPI, /* software interrupt */
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
phantomInterrupt,
};
/* Startup Routine */
#pragma INTERRUPT(_c_int00, RESET)
void _c_int00()
{
/* Enable VFP Unit */
_coreEnableVfp();
/* Initialize Core Registers */
_coreInitRegisters();
/* Initialize Stack Pointers */
_coreInitStackPointer();
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset();
/* Initialize System */
systemInit();
/* Initialize VIM table */
{
unsigned i;
for (i = 0; i < 96U; i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
| (SYS_FIQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U)
| (SYS_IRQ << 31U);
vimREG->FIRQPR1 = SYS_IRQ
| (SYS_IRQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U);
/* enable interrupts */
vimREG->REQMASKSET0 = 1U
| (0U << 1)
| (1U << 2) /* RTI */
| (0U << 3)
| (0U << 4)
| (0U << 5)
| (0U << 6)
| (0U << 7)
| (0U << 8)
| (0U << 9)
| (0U << 10)
| (0U << 11)
| (0U << 12)
| (0U << 13)
| (0U << 14)
| (0U << 15)
| (0U << 16)
| (0U << 17)
| (0U << 18)
| (0U << 19)
| (0U << 20)
| (1U << 21) /* Software Interrupt */
| (0U << 22)
| (0U << 23)
| (0U << 24)
| (0U << 25)
| (0U << 26)
| (0U << 27)
| (0U << 28)
| (0U << 29)
| (0U << 30)
| (0U << 31);
vimREG->REQMASKSET1 = 0U
| (0U << 1)
| (0U << 2)
| (0U << 3)
| (0U << 4)
| (0U << 5)
| (0U << 6)
| (0U << 7)
| (0U << 8)
| (0U << 9)
| (0U << 10)
| (0U << 11)
| (0U << 12)
| (0U << 13)
| (0U << 14)
| (0U << 15)
| (0U << 16)
| (0U << 17)
| (0U << 18)
| (0U << 19)
| (0U << 20)
| (0U << 21)
| (0U << 22)
| (0U << 23)
| (0U << 24)
| (0U << 25)
| (0U << 26)
| (0U << 27)
| (0U << 28)
| (0U << 29)
| (0U << 30);
/* initalise global variable and constructors */
__TI_auto_init();
/* call the application */
main();
exit(0);
}

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FreeRTOS/Demo/CORTEX_R4_RM48_CCS5/startup/sys_system.c Normal file
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/** @file system.c
* @brief System Driver Source File
* @date 05.November.2010
* @version 1.01.000
*
* This file contains:
* - API Funcions
* .
* which are relevant for the System driver.
*/
/* (c) Texas Instruments 2010, All rights reserved. */
/* Include Files */
#include "sys_system.h"
/** @fn void systemInit(void)
* @brief Initializes System Driver
*
* This function initializes the System driver.
*
*/
void systemInit(void)
{
/** @b Initialize @b Flash @b Wrapper: */
/** - Setup flash read mode, address wait states and data wait states */
flashWREG->FRDCNTL = 0x01000000U
| (3U << 8U)
| (1U << 4U)
| 1U;
#if 0
/** - Setup flash bank power modes */
flashWREG->FBFALLBACK = 0x05050000
| (SYS_ACTIVE << 14U)
| (SYS_SLEEP << 12U)
| (SYS_SLEEP << 10U)
| (SYS_SLEEP << 8U)
| (SYS_SLEEP << 6U)
| (SYS_SLEEP << 4U)
| (SYS_ACTIVE << 2U)
| SYS_ACTIVE;
/** @b Initialize @b Lpo: */
{
unsigned trim = *(volatile unsigned short *)0xF00801B4;
if (trim != 0xFFFF)
{
systemREG1->LPOMONCTL = (1U << 24U)
| (0U << 16U)
| trim;
}
else
{
systemREG1->LPOMONCTL = (1U << 24U)
| (0U << 16U)
| (systemREG1->LPOMONCTL & 0xFFFF);
}
}
#endif
/** @b Initialize @b Pll: */
/** - Setup pll control register 1:
* - Setup reset on oscillator slip
* - Setup bypass on pll slip
* - Setup Pll output clock divider
* - Setup reset on oscillator fail
* - Setup reference clock divider
* - Setup Pll multiplier
*/
#if 0
/* 180Mhz */
systemREG1->PLLCTL1 = 0x00000000U
| 0x20000000U
| (0U << 24U)
| 0x00000000U
| (5U << 16U)
| (134U << 8U);
#endif
#if 1
/* 160Mhz */
systemREG1->PLLCTL1 = 0x00000000U
| 0x20000000U
| (0U << 24U)
| 0x00000000U
| (5U << 16U)
| (113U << 8U);
#endif
/** - Setup pll control register 1
* - Enable/Disable frequency modulation
* - Setup spreading rate
* - Setup bandwidth adjustment
* - Setup internal Pll output divider
* - Setup spreading amount
*/
systemREG1->PLLCTL2 = 0x00000000U
| (255U << 22U)
| (7U << 12U)
| (1U << 9U)
| 61U;
/** @b Initialize @b Clock @b Tree: */
/** - Start clock source lock */
systemREG1->CSDISCLR = 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000002U;
/** - Wait for until clocks are locked */
while ((systemREG1->CSVSTAT & 0x00000002U) == 0x00); /* wait for PLL */
/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
systemREG1->GHVSRC = (SYS_PLL << 24U)
| (SYS_PLL << 16U)
| SYS_PLL;
/** - Power-up all peripharals */
pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
/** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2 */
systemREG1->PENA = 0U;
systemREG1->VCLKR = 15U;
systemREG1->VCLK2R = 1U;
systemREG1->VCLKR = 1U;
systemREG2->CLK2CNTRL = (1U << 8U)
| 1U;
/** - Setup RTICLK1 and RTICLK2 clocks */
systemREG1->RCLKSRC = (1U << 24U)
| (SYS_VCLK << 16U)
| (1U << 8U)
| SYS_VCLK;
/** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
systemREG1->VCLKASRC = (SYS_FR_PLL << 8U)
| SYS_VCLK;
/** - Setup asynchronous peripheral clock sources for AVCLK3 and AVCLK4 */
systemREG2->VCLKACON1 = (0U << 24U)
| (0U << 20U)
| (SYS_EXTERNAL2 << 16U)
| (3U << 8U)
| (0U << 4U)
| SYS_EXTERNAL;
/** - Enable Peripherals */
systemREG1->PENA = 1U;
/** @note: HCLK >= VCLK2 >= VCLK_sys */
}

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/** @file system.h
* @brief System Driver Header File
* @date 23.July.2009
* @version 1.01.001
*
* This file contains:
* - Definitions
* - Types
* .
* which are relevant for the System driver.
*/
/* (c) Texas Instruments 2009-2010, All rights reserved. */
#ifndef __SYS_SYSTEM_H__
#define __SYS_SYSTEM_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* System General Definitions */
/** @enum systemInterrupt
* @brief Alias names for clock sources
*
* This enumeration is used to provide alias names for the clock sources:
* - IRQ
* - FIQ
*/
enum systemInterrupt
{
SYS_IRQ, /**< Alias for IRQ interrupt */
SYS_FIQ /**< Alias for FIQ interrupt */
};
/** @enum systemClockSource
* @brief Alias names for clock sources
*
* This enumeration is used to provide alias names for the clock sources:
* - Oscillator
* - Pll
* - 32 kHz Oscillator
* - External1
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - Flexray Pll
* - External2
* - Synchronous VCLK1
*/
enum systemClockSource
{
SYS_OSC = 0, /**< Alias for oscillator clock Source */
SYS_PLL = 1, /**< Alias for Pll clock Source */
SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */
SYS_EXTERNAL = 3, /**< Alias for external clock Source */
SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */
SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */
SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */
SYS_EXTERNAL2 = 7, /**< Alias for external 2 clock Source */
SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */
};
#define SYS_DOZE_MODE 0x000F3F02U
#define SYS_SNOOZE_MODE 0x000F3F03U
#define SYS_SLEEP_MODE 0x000FFFFFU
/** @def SYS_PRE1
* @brief Alias name for RTI1CLK PRE clock source
*
* This is an alias name for the RTI1CLK pre clock source.
* This can be either:
* - Oscillator
* - Pll
* - 32 kHz Oscillator
* - External
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - Flexray Pll
*/
#define SYS_PRE1 SYS_PLL
/** @def SYS_PRE2
* @brief Alias name for RTI2CLK pre clock source
*
* This is an alias name for the RTI2CLK pre clock source.
* This can be either:
* - Oscillator
* - Pll
* - 32 kHz Oscillator
* - External
* - Low Power Oscillator Low
* - Low Power Oscillator High
* - Flexray Pll
*/
#define SYS_PRE2 SYS_PLL
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* System Register Frame 1 Definition */
/** @struct systemBase1
* @brief System Register Frame 1 Definition
*
* This type is used to access the System 1 Registers.
*/
/** @typedef systemBASE1_t
* @brief System Register Frame 1 Type Definition
*
* This type is used to access the System 1 Registers.
*/
typedef volatile struct systemBase1
{
unsigned SYSPC1; /* 0x0000 */
unsigned SYSPC2; /* 0x0004 */
unsigned SYSPC3; /* 0x0008 */
unsigned SYSPC4; /* 0x000C */
unsigned SYSPC5; /* 0x0010 */
unsigned SYSPC6; /* 0x0014 */
unsigned SYSPC7; /* 0x0018 */
unsigned SYSPC8; /* 0x001C */
unsigned SYSPC9; /* 0x0020 */
unsigned SSWPLL1; /* 0x0024 */
unsigned SSWPLL2; /* 0x0028 */
unsigned SSWPLL3; /* 0x002C */
unsigned CSDIS; /* 0x0030 */
unsigned CSDISSET; /* 0x0034 */
unsigned CSDISCLR; /* 0x0038 */
unsigned CSDDIS; /* 0x003C */
unsigned CSDDISSET; /* 0x0040 */
unsigned CSDDISCLR; /* 0x0044 */
unsigned GHVSRC; /* 0x0048 */
unsigned VCLKASRC; /* 0x004C */
unsigned RCLKSRC; /* 0x0050 */
unsigned CSVSTAT; /* 0x0054 */
unsigned MSTGCR; /* 0x0058 */
unsigned MINITGCR; /* 0x005C */
unsigned MSINENA; /* 0x0060 */
unsigned MSTFAIL; /* 0x0064 */
unsigned MSTCGSTAT; /* 0x0068 */
unsigned MINISTAT; /* 0x006C */
unsigned PLLCTL1; /* 0x0070 */
unsigned PLLCTL2; /* 0x0074 */
unsigned UERFLAG; /* 0x0078 */
unsigned DIEIDL; /* 0x007C */
unsigned DIEIDH; /* 0x0080 */
unsigned VRCTL; /* 0x0084 */
unsigned LPOMONCTL; /* 0x0088 */
unsigned CLKTEST; /* 0x008C */
unsigned DFTCTRLREG1; /* 0x0090 */
unsigned DFTCTRLREG2; /* 0x0094 */
unsigned : 32U; /* 0x0098 */
unsigned : 32U; /* 0x009C */
unsigned GPREG1; /* 0x00A0 */
unsigned BTRMSEL; /* 0x00A4 */
unsigned IMPFASTS; /* 0x00A8 */
unsigned IMPFTADD; /* 0x00AC */
unsigned SSISR1; /* 0x00B0 */
unsigned SSISR2; /* 0x00B4 */
unsigned SSISR3; /* 0x00B8 */
unsigned SSISR4; /* 0x00BC */
unsigned RAMGCR; /* 0x00C0 */
unsigned BMMCR1; /* 0x00C4 */
unsigned BMMCR2; /* 0x00C8 */
unsigned MMUGCR; /* 0x00CC */
#ifdef _little_endian__
unsigned : 8U; /* 0x00D0 */
unsigned PENA : 1U; /* 0x00D0 */
unsigned : 7U; /* 0x00D0 */
unsigned VCLKR : 4U; /* 0x00D0 */
unsigned : 4U; /* 0x00D0 */
unsigned VCLK2R : 4U; /* 0x00D0 */
unsigned : 4U; /* 0x00D0 */
#else
unsigned : 4U; /* 0x00D0 */
unsigned VCLK2R : 4U; /* 0x00D0 */
unsigned : 4U; /* 0x00D0 */
unsigned VCLKR : 4U; /* 0x00D0 */
unsigned : 7U; /* 0x00D0 */
unsigned PENA : 1U; /* 0x00D0 */
unsigned : 8U; /* 0x00D0 */
#endif
unsigned ECPCNTL; /* 0x00D4 */
unsigned DSPGCR; /* 0x00D8 */
unsigned DEVCR1; /* 0x00DC */
unsigned SYSECR; /* 0x00E0 */
unsigned SYSESR; /* 0x00E4 */
unsigned ITIFLAG; /* 0x00E8 */
unsigned GBLSTAT; /* 0x00EC */
unsigned DEV; /* 0x00F0 */
unsigned SSIVEC; /* 0x00F4 */
unsigned SSIF; /* 0x00F8 */
} systemBASE1_t;
/** @def systemREG1
* @brief System Register Frame 1 Pointer
*
* This pointer is used by the system driver to access the system frame 1 registers.
*/
#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
/** @def systemPORT
* @brief ECLK GIO Port Register Pointer
*
* Pointer used by the GIO driver to access I/O PORT of System/Eclk
* (use the GIO drivers to access the port pins).
*/
#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* System Register Frame 2 Definition */
/** @struct systemBase2
* @brief System Register Frame 2 Definition
*
* This type is used to access the System 2 Registers.
*/
/** @typedef systemBASE2_t
* @brief System Register Frame 2 Type Definition
*
* This type is used to access the System 2 Registers.
*/
typedef volatile struct systemBase2
{
unsigned PLLCTL3; /* 0x0000 */
unsigned : 32U; /* 0x0004 */
unsigned STCCLKDIV; /* 0x0008 */
unsigned CLKHB_GLBREG; /* 0x000C */
unsigned CLKHB_RTIDREG; /* 0x0010 */
unsigned HBCD_STAT; /* 0x0014 */
unsigned : 32U; /* 0x0018 */
unsigned : 32U; /* 0x001C */
unsigned CLKTRMI1; /* 0x0020 */
unsigned ECPCNTRL0; /* 0x0024 */
unsigned ECPCNTRL1; /* 0x0028 */
unsigned ECPCNTRL2; /* 0x002C */
unsigned ECPCNTRL3; /* 0x0030 */
unsigned : 32U; /* 0x0034 */
unsigned : 32U; /* 0x0038 */
unsigned CLK2CNTRL; /* 0x003C */
unsigned VCLKACON1; /* 0x0040 */
} systemBASE2_t;
/** @def systemREG2
* @brief System Register Frame 2 Pointer
*
* This pointer is used by the system driver to access the system frame 2 registers.
*/
#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** @struct pcrBase
* @brief Pcr Register Frame Definition
*
* This type is used to access the Pcr Registers.
*/
/** @typedef pcrBASE_t
* @brief PCR Register Frame Type Definition
*
* This type is used to access the PCR Registers.
*/
typedef volatile struct pcrBase
{
unsigned PMPROTSET0; /* 0x0000 */
unsigned PMPROTSET1; /* 0x0004 */
unsigned : 32U; /* 0x0008 */
unsigned : 32U; /* 0x000C */
unsigned PMPROTCLR0; /* 0x0010 */
unsigned PMPROTCLR1; /* 0x0014 */
unsigned : 32U; /* 0x0018 */
unsigned : 32U; /* 0x001C */
unsigned PPROTSET0; /* 0x0020 */
unsigned PPROTSET1; /* 0x0024 */
unsigned PPROTSET2; /* 0x0028 */
unsigned PPROTSET3; /* 0x002C */
unsigned : 32U; /* 0x0030 */
unsigned : 32U; /* 0x0034 */
unsigned : 32U; /* 0x0038 */
unsigned : 32U; /* 0x003C */
unsigned PPROTCLR0; /* 0x0040 */
unsigned PPROTCLR1; /* 0x0044 */
unsigned PPROTCLR2; /* 0x0048 */
unsigned PPROTCLR3; /* 0x004C */
unsigned : 32U; /* 0x0050 */
unsigned : 32U; /* 0x0054 */
unsigned : 32U; /* 0x0058 */
unsigned : 32U; /* 0x005C */
unsigned PCSPWRDWNSET0; /* 0x0060 */
unsigned PCSPWRDWNSET1; /* 0x0064 */
unsigned : 32U; /* 0x0068 */
unsigned : 32U; /* 0x006C */
unsigned PCSPWRDWNCLR0; /* 0x0070 */
unsigned PCSPWRDWNCLR1; /* 0x0074 */
unsigned : 32U; /* 0x0078 */
unsigned : 32U; /* 0x007C */
unsigned PSPWRDWNSET0; /* 0x0080 */
unsigned PSPWRDWNSET1; /* 0x0084 */
unsigned PSPWRDWNSET2; /* 0x0088 */
unsigned PSPWRDWNSET3; /* 0x008C */
unsigned : 32U; /* 0x0090 */
unsigned : 32U; /* 0x0094 */
unsigned : 32U; /* 0x0098 */
unsigned : 32U; /* 0x009C */
unsigned PSPWRDWNCLR0; /* 0x00A0 */
unsigned PSPWRDWNCLR1; /* 0x00A4 */
unsigned PSPWRDWNCLR2; /* 0x00A8 */
unsigned PSPWRDWNCLR3; /* 0x00AC */
} pcrBASE_t;
/** @def pcrREG
* @brief Pcr Register Frame Pointer
*
* This pointer is used by the system driver to access the Pcr registers.
*/
#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
/* USER CODE BEGIN (4) */
/* USER CODE END */
/* FlashW General Definitions */
/** @enum flashWPowerModes
* @brief Alias names for flash bank power modes
*
* This enumeration is used to provide alias names for the flash bank power modes:
* - sleep
* - standby
* - active
*/
enum flashWPowerModes
{
SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
};
/* USER CODE BEGIN (5) */
/* USER CODE END */
/** @struct flashWBase
* @brief Flash Wrapper Register Frame Definition
*
* This type is used to access the Flash Wrapper Registers.
*/
/** @typedef flashWBASE_t
* @brief Flash Wrapper Register Frame Type Definition
*
* This type is used to access the Flash Wrapper Registers.
*/
typedef volatile struct flashWBase
{
unsigned FRDCNTL; /* 0x0000 */
unsigned FSPRD; /* 0x0004 */
unsigned FEDACCTRL1; /* 0x0008 */
unsigned FEDACCTRL2; /* 0x000C */
unsigned FCORERRCNT; /* 0x0010 */
unsigned FCORERRADD; /* 0x0014 */
unsigned FCORERRPOS; /* 0x0018 */
unsigned FEDACSTATUS; /* 0x001C */
unsigned FUNCERRADD; /* 0x0020 */
unsigned FEDACSDIS; /* 0x0024 */
unsigned FPRIMADDTAG; /* 0x0028 */
unsigned FREDUADDTAG; /* 0x002C */
unsigned FBPROT; /* 0x0030 */
unsigned FBSE; /* 0x0034 */
unsigned FBBUSY; /* 0x0038 */
unsigned FBAC; /* 0x003C */
unsigned FBFALLBACK; /* 0x0040 */
unsigned FBPRDY; /* 0x0044 */
unsigned FPAC1; /* 0x0048 */
unsigned FPAC2; /* 0x004C */
unsigned FMAC; /* 0x0050 */
unsigned FMSTAT; /* 0x0054 */
unsigned FEMUDMSW; /* 0x0058 */
unsigned FEMUDLSW; /* 0x005C */
unsigned FEMUECC; /* 0x0060 */
unsigned FLOCK; /* 0x0064 */
unsigned FEMUADDR; /* 0x0068 */
unsigned FDIAGCTRL; /* 0x006C */
unsigned FRAWDATAH; /* 0x0070 */
unsigned FRAWDATAL; /* 0x0074 */
unsigned FRAWECC; /* 0x0078 */
unsigned FPAROVR; /* 0x007C */
unsigned FVREADCT; /* 0x0080 */
unsigned FVHVCT1; /* 0x0084 */
unsigned FVHVCT2; /* 0x0088 */
unsigned FVNVCT; /* 0x008C */
unsigned FVPPCT; /* 0x0090 */
unsigned FVWLCT; /* 0x0094 */
unsigned FEFUSE; /* 0x0098 */
unsigned : 32U; /* 0x009C */
unsigned : 32U; /* 0x00A0 */
unsigned : 32U; /* 0x00A4 */
unsigned : 32U; /* 0x00A8 */
unsigned : 32U; /* 0x00AC */
unsigned : 32U; /* 0x00B0 */
unsigned : 32U; /* 0x00B4 */
unsigned : 32U; /* 0x00B8 */
unsigned : 32U; /* 0x00BC */
unsigned FEDACSDIS2; /* 0x00C0 */
unsigned : 32U; /* 0x00C4 */
unsigned : 32U; /* 0x00C8 */
unsigned : 32U; /* 0x00CC */
unsigned : 32U; /* 0x00D0 */
unsigned : 32U; /* 0x00D4 */
unsigned : 32U; /* 0x00D8 */
unsigned : 32U; /* 0x00DC */
unsigned : 32U; /* 0x00E0 */
unsigned : 32U; /* 0x00E4 */
unsigned : 32U; /* 0x00E8 */
unsigned : 32U; /* 0x00EC */
unsigned : 32U; /* 0x00F0 */
unsigned : 32U; /* 0x00F4 */
unsigned : 32U; /* 0x00F8 */
unsigned : 32U; /* 0x00FC */
unsigned FBSTROBES; /* 0x0100 */
unsigned FPSTROBES; /* 0x0104 */
unsigned FBMODE; /* 0x0108 */
unsigned FTCR; /* 0x010C */
unsigned FADDR; /* 0x0110 */
unsigned FWRITE; /* 0x0114 */
unsigned FCBITSEL; /* 0x0118 */
unsigned FTCTRL; /* 0x011C */
unsigned FWPWRITE0; /* 0x0120 */
unsigned FWPWRITE1; /* 0x0124 */
unsigned FWPWRITE2; /* 0x0128 */
unsigned FWPWRITE3; /* 0x012C */
unsigned FWPWRITE4; /* 0x0130 */
} flashWBASE_t;
/** @def flashWREG
* @brief Flash Wrapper Register Frame Pointer
*
* This pointer is used by the system driver to access the flash wrapper registers.
*/
#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* System Interface Functions */
void systemInit(void);
void systemPowerDown(unsigned mode);
/* USER CODE BEGIN (7) */
/* USER CODE END */
#endif

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/*----------------------------------------------------------------------------*/
/* sys_types.h 10/20/10 15:19:19 */
/* */
/* (c) Texas Instruments 2003-2010, All rights reserved. */
/* */
#ifndef __sys_types_h__
#define __sys_types_h__
/*----------------------------------------------------------------------------*/
/* Standard Types */
typedef signed char T_S8;
#define MAX_S8 (127)
#define MIN_S8 (-128)
typedef unsigned char T_U8;
#define MAX_U8 (255)
#define MIN_U8 (0)
typedef signed short T_S16;
#define MAX_S16 (32767)
#define MIN_S16 (-32767-1)
typedef unsigned short T_U16;
#define MAX_U16 (0xFFFFU)
#define MIN_U16 (0)
typedef signed int T_S32;
#define MAX_S32 (2147483647L)
#define MIN_S32 (-2147483647L-1)
typedef unsigned int T_U32;
#define MAX_U32 (0xFFFFFFFFU)
#define MIN_U32 (0)
typedef float T_F32;
#define MAX_F32 (3.39e+38)
#define MIN_F32 (1.18e-38)
typedef double T_F64;
#define MAX_F64 (1.79e+308)
#define MIN_F64 (2.23e-308)
#endif
/*----------------------------------------------------------------------------*/

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/** @file sys_vim.h
* @brief Vectored Interrupt Module Header File
* @date 05.November.2010
* @version 1.01.000
*
* This file contains:
* - VIM Type Definitions
* - VIM General Definitions
* .
* which are relevant for the Vectored Interrupt Controller.
*/
/* (c) Texas Instruments 2010, All rights reserved. */
#ifndef __SYS_VIM_H__
#define __SYS_VIM_H__
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* VIM Type Definitions */
/** @typedef t_isrFuncPTR
* @brief ISR Function Pointer Type Definition
*
* This type is used to access the ISR handler.
*/
typedef void (*t_isrFuncPTR)();
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* VIM General Configuration */
#define VIM_CHANNELS 96U
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* Interrupt Handlers */
extern void phantomInterrupt(void);
extern void esmHighLevelInterrupt(void);
extern void vPreemptiveTick(void);
extern void vNonPreemptiveTick(void);
extern void vPortYeildWithinAPI(void);
/* Vim Register Frame Definition */
/** @struct vimBase
* @brief Vim Register Frame Definition
*
* This type is used to access the Vim Registers.
*/
/** @typedef vimBASE_t
* @brief VIM Register Frame Type Definition
*
* This type is used to access the VIM Registers.
*/
typedef volatile struct vimBase
{
unsigned : 24U; /* 0x0000 */
unsigned IRQIVEC : 8U; /* 0x0000 */
unsigned : 24U; /* 0x0004 */
unsigned FIQIVEC : 8U; /* 0x0004 */
unsigned : 32U; /* 0x0008 */
unsigned : 32U; /* 0x000C */
unsigned FIRQPR0; /* 0x0010 */
unsigned FIRQPR1; /* 0x0014 */
unsigned FIRQPR2; /* 0x0018 */
unsigned FIRQPR3; /* 0x001C */
unsigned INTREQ0; /* 0x0020 */
unsigned INTREQ1; /* 0x0024 */
unsigned INTREQ2; /* 0x0028 */
unsigned INTREQ3; /* 0x002C */
unsigned REQMASKSET0; /* 0x0030 */
unsigned REQMASKSET1; /* 0x0034 */
unsigned REQMASKSET2; /* 0x0038 */
unsigned REQMASKSET3; /* 0x003C */
unsigned REQMASKCLR0; /* 0x0040 */
unsigned REQMASKCLR1; /* 0x0044 */
unsigned REQMASKCLR2; /* 0x0048 */
unsigned REQMASKCLR3; /* 0x004C */
unsigned WAKEMASKSET0; /* 0x0050 */
unsigned WAKEMASKSET1; /* 0x0054 */
unsigned WAKEMASKSET2; /* 0x0058 */
unsigned WAKEMASKSET3; /* 0x005C */
unsigned WAKEMASKCLR0; /* 0x0060 */
unsigned WAKEMASKCLR1; /* 0x0064 */
unsigned WAKEMASKCLR2; /* 0x0068 */
unsigned WAKEMASKCLR3; /* 0x006C */
unsigned IRQVECREG; /* 0x0070 */
unsigned FIQVECREQ; /* 0x0074 */
unsigned : 9U; /* 0x0078 */
unsigned CAPEVTSRC1 : 7U; /* 0x0078 */
unsigned : 9U; /* 0x0078 */
unsigned CAPEVTSRC0 : 7U; /* 0x0078 */
unsigned : 32U; /* 0x007C */
unsigned char CHANMAP[64U]; /* 0x0080-0x017C */
} vimBASE_t;
#define vimREG ((vimBASE_t *)0xFFFFFE00U)
/* USER CODE BEGIN (3) */
/* USER CODE END */
#endif