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Preparing for maintenance release -
Bug fix - issue introduced in V8.2.2 when the current timer list is empty and the overflow timer list is not empty. Add PIC32MZ EF (floating point) support and update the MZ demo project to test the flop context switching. Improve efficiency of the stack overflow checking. Add CLI to RX71M demo. General tidy up of new RZ and RX projects - including ensuring the UART driver copes with 0 length strings. Add stack overflow checking to the [old] PIC24 demo.
This commit is contained in:
Richard Barry
parent
38cb08133d
commit
57cc3389a5
84 changed files with 4972 additions and 1813 deletions
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@ -69,9 +69,94 @@
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 160
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#define portEPC_STACK_LOCATION 152
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#define portSTATUS_STACK_LOCATION 156
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#define portCONTEXT_SIZE 160
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#define portEPC_STACK_LOCATION 152
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#define portSTATUS_STACK_LOCATION 156
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#define portFPCSR_STACK_LOCATION 0
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#define portTASK_HAS_FPU_STACK_LOCATION 0
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#define portFPU_CONTEXT_SIZE 264
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/******************************************************************/
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.macro portSAVE_FPU_REGS offset, base
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/* Macro to assist with saving just the FPU registers to the
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* specified address and base offset,
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* offset is a constant, base is the base pointer register */
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sdc1 $f31, \offset + 248(\base)
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sdc1 $f30, \offset + 240(\base)
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sdc1 $f29, \offset + 232(\base)
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sdc1 $f28, \offset + 224(\base)
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sdc1 $f27, \offset + 216(\base)
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sdc1 $f26, \offset + 208(\base)
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sdc1 $f25, \offset + 200(\base)
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sdc1 $f24, \offset + 192(\base)
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sdc1 $f23, \offset + 184(\base)
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sdc1 $f22, \offset + 176(\base)
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sdc1 $f21, \offset + 168(\base)
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sdc1 $f20, \offset + 160(\base)
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sdc1 $f19, \offset + 152(\base)
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sdc1 $f18, \offset + 144(\base)
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sdc1 $f17, \offset + 136(\base)
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sdc1 $f16, \offset + 128(\base)
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sdc1 $f15, \offset + 120(\base)
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sdc1 $f14, \offset + 112(\base)
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sdc1 $f13, \offset + 104(\base)
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sdc1 $f12, \offset + 96(\base)
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sdc1 $f11, \offset + 88(\base)
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sdc1 $f10, \offset + 80(\base)
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sdc1 $f9, \offset + 72(\base)
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sdc1 $f8, \offset + 64(\base)
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sdc1 $f7, \offset + 56(\base)
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sdc1 $f6, \offset + 48(\base)
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sdc1 $f5, \offset + 40(\base)
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sdc1 $f4, \offset + 32(\base)
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sdc1 $f3, \offset + 24(\base)
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sdc1 $f2, \offset + 16(\base)
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sdc1 $f1, \offset + 8(\base)
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sdc1 $f0, \offset + 0(\base)
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.endm
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/******************************************************************/
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.macro portLOAD_FPU_REGS offset, base
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/* Macro to assist with loading just the FPU registers from the
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* specified address and base offset, offset is a constant,
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* base is the base pointer register */
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ldc1 $f0, \offset + 0(\base)
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ldc1 $f1, \offset + 8(\base)
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ldc1 $f2, \offset + 16(\base)
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ldc1 $f3, \offset + 24(\base)
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ldc1 $f4, \offset + 32(\base)
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ldc1 $f5, \offset + 40(\base)
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ldc1 $f6, \offset + 48(\base)
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ldc1 $f7, \offset + 56(\base)
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ldc1 $f8, \offset + 64(\base)
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ldc1 $f9, \offset + 72(\base)
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ldc1 $f10, \offset + 80(\base)
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ldc1 $f11, \offset + 88(\base)
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ldc1 $f12, \offset + 96(\base)
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ldc1 $f13, \offset + 104(\base)
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ldc1 $f14, \offset + 112(\base)
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ldc1 $f15, \offset + 120(\base)
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ldc1 $f16, \offset + 128(\base)
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ldc1 $f17, \offset + 136(\base)
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ldc1 $f18, \offset + 144(\base)
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ldc1 $f19, \offset + 152(\base)
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ldc1 $f20, \offset + 160(\base)
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ldc1 $f21, \offset + 168(\base)
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ldc1 $f22, \offset + 176(\base)
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ldc1 $f23, \offset + 184(\base)
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ldc1 $f24, \offset + 192(\base)
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ldc1 $f25, \offset + 200(\base)
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ldc1 $f26, \offset + 208(\base)
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ldc1 $f27, \offset + 216(\base)
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ldc1 $f28, \offset + 224(\base)
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ldc1 $f29, \offset + 232(\base)
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ldc1 $f30, \offset + 240(\base)
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ldc1 $f31, \offset + 248(\base)
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.endm
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/******************************************************************/
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.macro portSAVE_CONTEXT
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@ -81,10 +166,37 @@
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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/* Test if we are already using the system stack. Only tasks may use the
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FPU so if we are already in a nested interrupt then the FPU context does
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not require saving. */
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la k1, uxInterruptNesting
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lw k1, 0(k1)
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bne k1, zero, 2f
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nop
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/* Test if the current task needs the FPU context saving. */
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la k1, ulTaskHasFPUContext
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lw k1, 0(k1)
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beq k1, zero, 1f
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nop
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/* Adjust the stack to account for the additional FPU context.*/
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addiu sp, sp, -portFPU_CONTEXT_SIZE
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1:
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/* Save the ulTaskHasFPUContext flag. */
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sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
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2:
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#endif
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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maintain the values of these registers across the ISR. */
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/* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
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should maintain the values of these registers across the ISR. */
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sw s7, 48(sp)
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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@ -173,6 +285,29 @@
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mflo s6, $ac0
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sw s6, 8(s5)
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/* Save the FPU context if the nesting count was zero. */
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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la s6, uxInterruptNesting
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lw s6, 0(s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Test if the current task needs the FPU context saving. */
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lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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beq s6, zero, 1f
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nop
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/* Save the FPU registers. */
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portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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/* Save the FPU status register */
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cfc1 s6, $f31
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sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
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1:
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#endif
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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@ -199,8 +334,24 @@
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la s6, uxSavedTaskStackPointer
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lw s5, (s6)
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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/* Restore the FPU context if required. */
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lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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beq s6, zero, 1f
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nop
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/* Restore the FPU registers. */
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portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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/* Restore the FPU status register. */
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lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
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ctc1 s6, $f31
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#endif
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1:
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/* Restore the context. */
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1: lw s6, 128(s5)
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lw s6, 128(s5)
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mthi s6, $ac1
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lw s6, 124(s5)
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mtlo s6, $ac1
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@ -213,7 +364,7 @@
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lw s6, 144(s5)
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mthi s6, $ac3
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lw s6, 140(s5)
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mtlo s6, $ac3
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mtlo s6, $ac3
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/* Restore DSPControl. */
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lw s6, 148(s5)
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@ -227,6 +378,7 @@
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/* s6 is loaded as it was used as a scratch register and therefore saved
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as part of the interrupt context. */
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lw s7, 48(s5)
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lw s6, 44(s5)
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lw v0, 52(s5)
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lw v1, 56(s5)
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@ -257,14 +409,60 @@
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addiu k1, k1, -1
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sw k1, 0(k0)
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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/* If the nesting count is now zero then the FPU context may be restored. */
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bne k1, zero, 1f
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nop
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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addiu sp, sp, portCONTEXT_SIZE
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/* Restore the value of ulTaskHasFPUContext */
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la k0, ulTaskHasFPUContext
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lw k1, 0(s5)
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sw k1, 0(k0)
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/* If the task does not have an FPU context then adjust the stack normally. */
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beq k1, zero, 1f
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nop
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/* Restore the STATUS and EPC registers */
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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/* Adjust the stack pointer to remove the FPU context */
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addiu sp, sp, portFPU_CONTEXT_SIZE
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beq zero, zero, 2f
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nop
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1: /* Restore the STATUS and EPC registers */
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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2: /* Adjust the stack pointer */
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addiu sp, sp, portCONTEXT_SIZE
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#else
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/* Restore the frame when there is no hardware FP support. */
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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addiu sp, sp, portCONTEXT_SIZE
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#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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mtc0 k0, _CP0_STATUS
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mtc0 k1, _CP0_EPC
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