mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-12-09 13:15:15 -05:00
Formatting changes, move function declarations around to make the file flow a bit better
This commit is contained in:
Soren Ptak
parent
ec1332e1f4
commit
56a51ff9f5
4 changed files with 246 additions and 257 deletions
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@ -62,55 +62,55 @@ extern "C" {
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* @brief CPSR Mode bit field value for User Mode.
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* @ingroup Port Privilege
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*/
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#define USER_MODE 0x10U
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#define USER_MODE 0x10U
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/**
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* @brief CPSR Mode bit field value for Fast Interrupt Handler (FIQ) Mode.
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* @ingroup Port Privilege
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*/
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#define FIQ_MODE 0x11U
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#define FIQ_MODE 0x11U
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/**
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* @brief CPSR Mode bit field value for Interrupt Handler (IRQ) Mode.
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* @ingroup Port Privilege
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*/
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#define IRQ_MODE 0x12U
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#define IRQ_MODE 0x12U
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/**
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* @brief CPSR Mode bit field value for Supervisor (SVC) Mode.
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* @ingroup Port Privilege
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*/
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#define SVC_MODE 0x13U
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#define SVC_MODE 0x13U
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/**
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* @brief CPSR Mode bit field value for Monitor (MON) Mode.
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* @ingroup Port Privilege
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*/
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#define MON_MODE 0x16U
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#define MON_MODE 0x16U
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/**
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* @brief CPSR Mode bit field value for Abort (ABT) Mode.
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* @ingroup Port Privilege
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*/
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#define ABT_MODE 0x17U
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#define ABT_MODE 0x17U
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/**
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* @brief CPSR Mode bit field value for Hypervisor (HYP) Mode.
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* @ingroup Port Privilege
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*/
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#define HYP_MODE 0x1AU
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#define HYP_MODE 0x1AU
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/**
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* @brief CPSR Mode bit field value for Undefined (UND) Mode.
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* @ingroup Port Privilege
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*/
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#define UND_MODE 0x1BU
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#define UND_MODE 0x1BU
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/**
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* @brief CPSR Mode bit field value for System (SYS) Mode.
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* @ingroup Port Privilege
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*/
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#define SYS_MODE 0x1FU
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#define SYS_MODE 0x1FU
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/**
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* @brief Used to mark if a task should be created as a privileged task.
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@ -122,27 +122,27 @@ extern "C" {
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* For example, to create a privileged task at priority 2 the uxPriority
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* parameter should be set to ( 2 | portPRIVILEGE_BIT ).
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*/
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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/**
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* @brief Flag uses to mark that a FreeRTOS Task is privileged.
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* @ingroup Port Privilege
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*/
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#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
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#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
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/**
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* @brief SVC Number to use when requesting a context swap.
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* @ingroup Scheduler
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* @note This value must not be in use in mpu_syscall_numbers.h
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*/
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#define portSVC_YIELD 0x0100
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#define portSVC_YIELD 0x0100
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/**
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* @brief SVC Number to use when exiting a FreeRTOS System Call.
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* @ingroup MPU Control
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* @note This value must not be in use in mpu_syscall_numbers.h
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*/
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#define portSVC_SYSTEM_CALL_EXIT 0x0104
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#define portSVC_SYSTEM_CALL_EXIT 0x0104
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/**
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* @addtogroup MPU Control
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@ -153,73 +153,73 @@ extern "C" {
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*/
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/* MPU Sub Region settings */
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#define portMPU_SUBREGION_0_DISABLE ( 0x1UL << 8UL )
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#define portMPU_SUBREGION_1_DISABLE ( 0x1UL << 9UL )
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#define portMPU_SUBREGION_2_DISABLE ( 0x1UL << 10UL )
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#define portMPU_SUBREGION_3_DISABLE ( 0x1UL << 11UL )
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#define portMPU_SUBREGION_4_DISABLE ( 0x1UL << 12UL )
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#define portMPU_SUBREGION_5_DISABLE ( 0x1UL << 13UL )
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#define portMPU_SUBREGION_6_DISABLE ( 0x1UL << 14UL )
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#define portMPU_SUBREGION_7_DISABLE ( 0x1UL << 15UL )
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#define portMPU_SUBREGION_0_DISABLE ( 0x1UL << 8UL )
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#define portMPU_SUBREGION_1_DISABLE ( 0x1UL << 9UL )
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#define portMPU_SUBREGION_2_DISABLE ( 0x1UL << 10UL )
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#define portMPU_SUBREGION_3_DISABLE ( 0x1UL << 11UL )
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#define portMPU_SUBREGION_4_DISABLE ( 0x1UL << 12UL )
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#define portMPU_SUBREGION_5_DISABLE ( 0x1UL << 13UL )
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#define portMPU_SUBREGION_6_DISABLE ( 0x1UL << 14UL )
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#define portMPU_SUBREGION_7_DISABLE ( 0x1UL << 15UL )
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/* Default MPU regions */
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#define portFIRST_CONFIGURABLE_REGION ( 0 )
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#define portLAST_CONFIGURABLE_REGION ( portMPU_TOTAL_REGIONS - 5UL )
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#define portSTACK_REGION ( portMPU_TOTAL_REGIONS - 4UL )
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#define portUNPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 3UL )
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#define portPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 2UL )
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#define portPRIVILEGED_RAM_REGION ( portMPU_TOTAL_REGIONS - 1UL )
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#define portFIRST_CONFIGURABLE_REGION ( 0 )
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#define portLAST_CONFIGURABLE_REGION ( portMPU_TOTAL_REGIONS - 5UL )
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#define portSTACK_REGION ( portMPU_TOTAL_REGIONS - 4UL )
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#define portUNPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 3UL )
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#define portPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 2UL )
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#define portPRIVILEGED_RAM_REGION ( portMPU_TOTAL_REGIONS - 1UL )
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#define portNUM_CONFIGURABLE_REGIONS \
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( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1UL )
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/* Plus one to make space for the stack region*/
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#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1UL )
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#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1UL )
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/* MPU region sizes */
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#define portMPU_SIZE_32B ( 0x04UL << 1UL )
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#define portMPU_SIZE_64B ( 0x05UL << 1UL )
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#define portMPU_SIZE_128B ( 0x06UL << 1UL )
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#define portMPU_SIZE_256B ( 0x07UL << 1UL )
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#define portMPU_SIZE_512B ( 0x08UL << 1UL )
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#define portMPU_SIZE_1KB ( 0x09UL << 1UL )
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#define portMPU_SIZE_2KB ( 0x0AUL << 1UL )
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#define portMPU_SIZE_4KB ( 0x0BUL << 1UL )
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#define portMPU_SIZE_8KB ( 0x0CUL << 1UL )
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#define portMPU_SIZE_16KB ( 0x0DUL << 1UL )
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#define portMPU_SIZE_32KB ( 0x0EUL << 1UL )
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#define portMPU_SIZE_64KB ( 0x0FUL << 1UL )
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#define portMPU_SIZE_128KB ( 0x10UL << 1UL )
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#define portMPU_SIZE_256KB ( 0x11UL << 1UL )
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#define portMPU_SIZE_512KB ( 0x12UL << 1UL )
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#define portMPU_SIZE_1MB ( 0x13UL << 1UL )
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#define portMPU_SIZE_2MB ( 0x14UL << 1UL )
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#define portMPU_SIZE_4MB ( 0x15UL << 1UL )
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#define portMPU_SIZE_8MB ( 0x16UL << 1UL )
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#define portMPU_SIZE_16MB ( 0x17UL << 1UL )
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#define portMPU_SIZE_32MB ( 0x18UL << 1UL )
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#define portMPU_SIZE_64MB ( 0x19UL << 1UL )
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#define portMPU_SIZE_128MB ( 0x1AUL << 1UL )
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#define portMPU_SIZE_256MB ( 0x1BUL << 1UL )
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#define portMPU_SIZE_512MB ( 0x1CUL << 1UL )
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#define portMPU_SIZE_1GB ( 0x1DUL << 1UL )
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#define portMPU_SIZE_2GB ( 0x1EUL << 1UL )
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#define portMPU_SIZE_4GB ( 0x1FUL << 1UL )
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#define portMPU_SIZE_32B ( 0x04UL << 1UL )
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#define portMPU_SIZE_64B ( 0x05UL << 1UL )
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#define portMPU_SIZE_128B ( 0x06UL << 1UL )
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#define portMPU_SIZE_256B ( 0x07UL << 1UL )
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#define portMPU_SIZE_512B ( 0x08UL << 1UL )
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#define portMPU_SIZE_1KB ( 0x09UL << 1UL )
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#define portMPU_SIZE_2KB ( 0x0AUL << 1UL )
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#define portMPU_SIZE_4KB ( 0x0BUL << 1UL )
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#define portMPU_SIZE_8KB ( 0x0CUL << 1UL )
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#define portMPU_SIZE_16KB ( 0x0DUL << 1UL )
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#define portMPU_SIZE_32KB ( 0x0EUL << 1UL )
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#define portMPU_SIZE_64KB ( 0x0FUL << 1UL )
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#define portMPU_SIZE_128KB ( 0x10UL << 1UL )
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#define portMPU_SIZE_256KB ( 0x11UL << 1UL )
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#define portMPU_SIZE_512KB ( 0x12UL << 1UL )
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#define portMPU_SIZE_1MB ( 0x13UL << 1UL )
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#define portMPU_SIZE_2MB ( 0x14UL << 1UL )
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#define portMPU_SIZE_4MB ( 0x15UL << 1UL )
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#define portMPU_SIZE_8MB ( 0x16UL << 1UL )
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#define portMPU_SIZE_16MB ( 0x17UL << 1UL )
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#define portMPU_SIZE_32MB ( 0x18UL << 1UL )
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#define portMPU_SIZE_64MB ( 0x19UL << 1UL )
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#define portMPU_SIZE_128MB ( 0x1AUL << 1UL )
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#define portMPU_SIZE_256MB ( 0x1BUL << 1UL )
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#define portMPU_SIZE_512MB ( 0x1CUL << 1UL )
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#define portMPU_SIZE_1GB ( 0x1DUL << 1UL )
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#define portMPU_SIZE_2GB ( 0x1EUL << 1UL )
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#define portMPU_SIZE_4GB ( 0x1FUL << 1UL )
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/* MPU Device Memory Types */
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#define portMPU_REGION_STRONGLY_ORDERED ( 0x00UL )
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#define portMPU_REGION_DEVICE ( 0x01UL )
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x03UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 12UL )
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#define portMPU_STRONGLYORDERED_SHAREABLE ( 0x0000UL )
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#define portMPU_DEVICE_SHAREABLE ( 0x0001UL )
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#define portMPU_DEVICE_NONSHAREABLE ( 0x0010UL )
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#define portMPU_NORMAL_OIWTNOWA_NONSHARED ( 0x0002UL )
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#define portMPU_NORMAL_OIWBNOWA_NONSHARED ( 0x0003UL )
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#define portMPU_NORMAL_OIWTNOWA_SHARED ( 0x0006UL )
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#define portMPU_NORMAL_OIWBNOWA_SHARED ( 0x0007UL )
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#define portMPU_NORMAL_OINC_NONSHARED ( 0x0008UL )
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#define portMPU_NORMAL_OIWBWA_NONSHARED ( 0x000BUL )
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#define portMPU_NORMAL_OINC_SHARED ( 0x000CUL )
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#define portMPU_NORMAL_OIWBWA_SHARED ( 0x000FUL )
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#define portMPU_REGION_STRONGLY_ORDERED ( 0x00UL )
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#define portMPU_REGION_DEVICE ( 0x01UL )
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x03UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 12UL )
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#define portMPU_STRONGLYORDERED_SHAREABLE ( 0x0000UL )
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#define portMPU_DEVICE_SHAREABLE ( 0x0001UL )
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#define portMPU_DEVICE_NONSHAREABLE ( 0x0010UL )
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#define portMPU_NORMAL_OIWTNOWA_NONSHARED ( 0x0002UL )
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#define portMPU_NORMAL_OIWBNOWA_NONSHARED ( 0x0003UL )
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#define portMPU_NORMAL_OIWTNOWA_SHARED ( 0x0006UL )
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#define portMPU_NORMAL_OIWBNOWA_SHARED ( 0x0007UL )
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#define portMPU_NORMAL_OINC_NONSHARED ( 0x0008UL )
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#define portMPU_NORMAL_OIWBWA_NONSHARED ( 0x000BUL )
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#define portMPU_NORMAL_OINC_SHARED ( 0x000CUL )
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#define portMPU_NORMAL_OIWBWA_SHARED ( 0x000FUL )
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/**
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* @brief MPU_CTRL value for: No Access and No Execute
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@ -230,7 +230,7 @@ extern "C" {
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* No Access in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_NA_USER_NA_NOEXEC ( 0x1000UL )
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#define portMPU_PRIV_NA_USER_NA_NOEXEC ( 0x1000UL )
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/**
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* @brief MPU_CTRL value for Privileged Read and Exec
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@ -241,7 +241,7 @@ extern "C" {
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* No Read/Write Access in User Mode
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* Allowed to Execute Code from this region
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*/
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#define portMPU_PRIV_RO_USER_NA_EXEC ( 0x0500UL )
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#define portMPU_PRIV_RO_USER_NA_EXEC ( 0x0500UL )
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/**
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* @brief MPU_CTRL value for Privileged Read, Write, and Exec
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@ -252,7 +252,7 @@ extern "C" {
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* No Access in User Mode
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* Allowed to Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_NA_EXEC ( 0x0100UL )
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#define portMPU_PRIV_RW_USER_NA_EXEC ( 0x0100UL )
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/**
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* @brief MPU_CTRL value for Read Only and Execute
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@ -263,7 +263,7 @@ extern "C" {
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* Read Only in User Mode
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* Allowed to Execute Code from this region
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* */
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#define portMPU_PRIV_RO_USER_RO_EXEC ( 0x0600UL )
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#define portMPU_PRIV_RO_USER_RO_EXEC ( 0x0600UL )
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/**
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* @brief MPU_CTRL value for: Read, Execute, and Privileged Write
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@ -274,7 +274,7 @@ extern "C" {
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* Read Only in User Mode
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* Allowed to Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_RO_EXEC ( 0x0200UL )
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#define portMPU_PRIV_RW_USER_RO_EXEC ( 0x0200UL )
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/**
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* @brief MPU_CTRL value for: Read, Write, and Execute
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@ -285,7 +285,7 @@ extern "C" {
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* Read/write in User Mode
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* Allowed to Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_RW_EXEC ( 0x0300UL )
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#define portMPU_PRIV_RW_USER_RW_EXEC ( 0x0300UL )
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/**
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* @brief MPU_CTRL value for: Privileged Read, Write Only, no Execute
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@ -296,7 +296,7 @@ extern "C" {
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* No Access in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_NA_NOEXEC ( 0x1100UL )
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#define portMPU_PRIV_RW_USER_NA_NOEXEC ( 0x1100UL )
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/**
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* @brief MPU_CTRL value for: All Read, Privileged Write, no Execute
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@ -307,7 +307,7 @@ extern "C" {
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* Read Only in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_RO_NOEXEC ( 0x1200UL )
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#define portMPU_PRIV_RW_USER_RO_NOEXEC ( 0x1200UL )
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/**
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* @brief MPU_CTRL value for: Read, Write, no Execute
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@ -318,7 +318,7 @@ extern "C" {
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* Read/Write in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_RW_USER_RW_NOEXEC ( 0x1300UL )
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#define portMPU_PRIV_RW_USER_RW_NOEXEC ( 0x1300UL )
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/**
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* @brief MPU_CTRL value for: Privileged Read Only, No Execute
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@ -329,7 +329,7 @@ extern "C" {
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* No Access in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_RO_USER_NA_NOEXEC ( 0x1500UL )
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#define portMPU_PRIV_RO_USER_NA_NOEXEC ( 0x1500UL )
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/**
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* @brief MPU_CTRL value for: Read Only, No Execute
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@ -340,13 +340,13 @@ extern "C" {
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* Read Only in User Mode
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* Cannot Execute Code from this region
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*/
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#define portMPU_PRIV_RO_USER_RO_NOEXEC ( 0x1600UL )
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#define portMPU_PRIV_RO_USER_RO_NOEXEC ( 0x1600UL )
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/**
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* @brief MPU_CTRL value to enable an MPU Region
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* @ingroup MPU Control
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*/
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#define portMPU_REGION_ENABLE ( 0x01UL )
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#define portMPU_REGION_ENABLE ( 0x01UL )
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/** This following section is used to create the proper size for the ulContext array.
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* This array is where all registers related to a task's context are saved.
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@ -384,7 +384,7 @@ extern "C" {
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* @note There are 13 GPRs, R0-R12, the SP, and the LR. Each are 32 bits,
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* which leads to the 15 registers * 4 in length.
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*/
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#define portREGISTER_LENGTH ( 15U * 4U )
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#define portREGISTER_LENGTH ( 15U * 4U )
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/**
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* If you KNOW that your system will not utilize the FPU in any capacity
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