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Add in the CORTEX_A53_64-bit_UltraScale_MPSoC demo application (a demo has been included in the Xilinx SDK download for some time already).

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Update a few demo application files to work with 64-bit data types.
This commit is contained in:
Richard Barry 2015-12-22 13:56:20 +00:00
parent 51560d9a96
commit 5690221c5c
360 changed files with 206264 additions and 53 deletions
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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject Normal file
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/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainSELECTED_APPLICATION setting in main.c is used to select between the
* two. See the notes on using mainSELECTED_APPLICATION in main.c. This file
* implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* basic demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 200 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles an LED. The 'block
* time' parameter passed to the queue receive function specifies that the
* task should be held in the Blocked state indefinitely to wait for data to
* be available on the queue. The queue receive task will only leave the
* Blocked state when the queue send task writes to the queue. As the queue
* send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Standard demo includes. */
#include "partest.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 200ms value is converted
to ticks using the portTICK_PERIOD_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200 )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* The LED toggled by the Rx task. */
#define mainTASK_LED ( 0 )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const uint32_t ulValueToSend = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0U );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
uint32_t ulReceivedValue;
const uint32_t ulExpectedValue = 100UL;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but is
it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
vParTestToggleLED( mainTASK_LED );
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include "xparameters.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/*
* The FreeRTOS Cortex-A port implements a full interrupt nesting model.
*
* Interrupts that are assigned a priority at or below
* configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM
* generic interrupt controller [GIC] means a priority that has a numerical
* value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API
* functions and will nest.
*
* Interrupts that are assigned a priority above
* configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical
* value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS
* API functions, will nest, and will not be masked by FreeRTOS critical
* sections (although it is necessary for interrupts to be globally disabled
* extremely briefly as the interrupt mask is updated in the GIC).
*
* FreeRTOS functions that can be called from an interrupt are those that end in
* "FromISR". FreeRTOS maintains a separate interrupt safe API to enable
* interrupt entry to be shorter, faster, simpler and smaller.
*
* For the purpose of setting configMAX_API_CALL_INTERRUPT_PRIORITY 255
* represents the lowest priority.
*/
#define configMAX_API_CALL_INTERRUPT_PRIORITY 18
#define configCPU_CLOCK_HZ 100000000UL
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_TICKLESS_IDLE 0
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configPERIPHERAL_CLOCK_HZ ( 33333000UL )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configMAX_PRIORITIES ( 8 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 )
#define configTOTAL_HEAP_SIZE ( 124 * 1024 )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_QUEUE_SETS 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_eTaskGetState 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Run time stats are not generated. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS and
portGET_RUN_TIME_COUNTER_VALUE must be defined if configGENERATE_RUN_TIME_STATS
is set to 1. */
#define configGENERATE_RUN_TIME_STATS 0
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#define portGET_RUN_TIME_COUNTER_VALUE()
/* The size of the global output buffer that is available for use when there
are multiple command interpreters running at once (for example, one on a UART
and one on TCP/IP). This is done to prevent an output buffer being defined by
each implementation - which would waste RAM. In this case, there is only one
command interpreter running. */
#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vAssertCalled( const char * pcFile, unsigned long ulLine );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );
/* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to
return from its implementing function will end up in a "task exit error"
function - which contains a call to configASSERT(). However this can give GCC
some problems when it tries to unwind the stack, as the exit error function has
nothing to return to. To avoid this define configTASK_RETURN_ADDRESS to 0. */
#define configTASK_RETURN_ADDRESS NULL
/* Bump up the priority of recmuCONTROLLING_TASK_PRIORITY to prevent false
positive errors being reported considering the priority of other tasks in the
system. */
#define recmuCONTROLLING_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
/****** Hardware specific settings. *******************************************/
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must
* be installed as the peripheral's interrupt handler.
*/
void vConfigureTickInterrupt( void );
#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
void vClearTickInterrupt( void );
#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()
/* The following constant describe the hardware, and are correct for the
Zynq MPU. */
#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_PSU_ACPU_GIC_DIST_BASEADDR )
#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( XPAR_PSU_ACPU_GIC_BASEADDR - XPAR_PSU_ACPU_GIC_DIST_BASEADDR )
#define configUNIQUE_INTERRUPT_PRIORITIES 32
#define fabs( x ) __builtin_fabs( x )
#define configUSE_TRACE_FACILITY 0
#endif /* FREERTOS_CONFIG_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.s
*
* This file contains the initial vector table for the Cortex A53 processor
* Currently NEON registers are not saved on stack if interrupt is taken.
* It will be implemented.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 5/21/14 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
.org 0
.text
.globl _boot
.globl _vector_table
.globl _freertos_vector_table
.globl FIQInterrupt
.globl IRQInterrupt
.globl SErrorInterrupt
.globl SynchronousInterrupt
.org 0
.section .vectors, "a"
_vector_table:
.set VBAR, _vector_table
.org VBAR
b _boot
.org (VBAR + 0x80)
b .
.org (VBAR + 0x100)
b .
.org (VBAR + 0x180)
b .
.org (VBAR + 0x200)
b .
.org (VBAR + 0x280)
b .
.org (VBAR + 0x300)
b .
.org (VBAR + 0x380)
b .
.org (VBAR + 0x400)
b .
.org (VBAR + 0x480)
b .
.org (VBAR + 0x500)
b .
.org (VBAR + 0x580)
b .
.org (VBAR + 0x600)
b .
.org (VBAR + 0x680)
b .
.org (VBAR + 0x700)
b .
.org (VBAR + 0x780)
b .
/******************************************************************************
* Vector table to use when FreeRTOS is running.
*****************************************************************************/
.set FREERTOS_VBAR, (VBAR+0x1000)
.org(FREERTOS_VBAR)
_freertos_vector_table:
b FreeRTOS_SWI_Handler
.org (FREERTOS_VBAR + 0x80)
b FreeRTOS_IRQ_Handler
.org (FREERTOS_VBAR + 0x100)
b .
.org (FREERTOS_VBAR + 0x180)
b .
.org (FREERTOS_VBAR + 0x200)
b FreeRTOS_SWI_Handler
.org (FREERTOS_VBAR + 0x280)
b FreeRTOS_IRQ_Handler
.org (FREERTOS_VBAR + 0x300)
b .
.org (FREERTOS_VBAR + 0x380)
b .
.org (FREERTOS_VBAR + 0x400)
b .
.org (FREERTOS_VBAR + 0x480)
b .
.org (FREERTOS_VBAR + 0x500)
b .
.org (FREERTOS_VBAR + 0x580)
b .
.org (FREERTOS_VBAR + 0x600)
b .
.org (FREERTOS_VBAR + 0x680)
b .
.org (FREERTOS_VBAR + 0x700)
b .
.org (FREERTOS_VBAR + 0x780)
b .
.org (FREERTOS_VBAR + 0x800)
SynchronousInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SynchronousInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
IRQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl IRQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
FIQInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl FIQInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
SErrorInterruptHandler:
stp X0,X1, [sp,#-0x10]!
stp X2,X3, [sp,#-0x10]!
stp X4,X5, [sp,#-0x10]!
stp X6,X7, [sp,#-0x10]!
stp X8,X9, [sp,#-0x10]!
stp X10,X11, [sp,#-0x10]!
stp X12,X13, [sp,#-0x10]!
stp X14,X15, [sp,#-0x10]!
stp X16,X17, [sp,#-0x10]!
stp X18,X19, [sp,#-0x10]!
stp X29,X30, [sp,#-0x10]!
bl SErrorInterrupt
ldp X29,X30, [sp], #0x10
ldp X18,X19, [sp], #0x10
ldp X16,X17, [sp], #0x10
ldp X14,X15, [sp], #0x10
ldp X12,X13, [sp], #0x10
ldp X10,X11, [sp], #0x10
ldp X8,X9, [sp], #0x10
ldp X6,X7, [sp], #0x10
ldp X4,X5, [sp], #0x10
ldp X2,X3, [sp], #0x10
ldp X0,X1, [sp], #0x10
eret
.end

169
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_tick_config.c Normal file
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@ -0,0 +1,169 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Xilinx includes. */
#include "platform.h"
#include "xttcps.h"
#include "xscugic.h"
/* Timer used to generate the tick interrupt. */
static XTtcPs xRTOSTickTimerInstance;
/*-----------------------------------------------------------*/
void vConfigureTickInterrupt( void )
{
BaseType_t xStatus;
XTtcPs_Config *pxTimerConfiguration;
uint16_t usInterval;
uint8_t ucPrescale;
const uint8_t ucLevelSensitive = 1;
extern XScuGic xInterruptController;
pxTimerConfiguration = XTtcPs_LookupConfig( XPAR_XTTCPS_3_DEVICE_ID );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called as
*xRTOSTickTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( &xRTOSTickTimerInstance );
xStatus = XTtcPs_CfgInitialize( &xRTOSTickTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( &xRTOSTickTimerInstance, ( XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ) );
/* Derive values from the tick rate. */
XTtcPs_CalcIntervalFromFreq( &xRTOSTickTimerInstance, configTICK_RATE_HZ, &( usInterval ), &( ucPrescale ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( &xRTOSTickTimerInstance, usInterval );
XTtcPs_SetPrescaler( &xRTOSTickTimerInstance, ucPrescale );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_XTTCPS_3_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucLevelSensitive );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, XPAR_XTTCPS_3_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xRTOSTickTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, XPAR_XTTCPS_3_INTR );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( &xRTOSTickTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( &xRTOSTickTimerInstance );
}
/*-----------------------------------------------------------*/
void vClearTickInterrupt( void )
{
volatile uint32_t ulInterruptStatus;
/* Read the interrupt status, then write it back to clear the interrupt. */
ulInterruptStatus = XTtcPs_GetInterruptStatus( &xRTOSTickTimerInstance );
XTtcPs_ClearInterruptStatus( &xRTOSTickTimerInstance, ulInterruptStatus );
__asm volatile( "DSB SY" );
__asm volatile( "ISB SY" );
}
/*-----------------------------------------------------------*/
void vApplicationIRQHandler( uint32_t ulICCIAR )
{
extern const XScuGic_Config XScuGic_ConfigTable[];
static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable;
uint32_t ulInterruptID;
const XScuGic_VectorTableEntry *pxVectorEntry;
/* Interrupts cannot be re-enabled until the source of the interrupt is
cleared. The ID of the interrupt is obtained by bitwise ANDing the ICCIAR
value with 0x3FF. */
ulInterruptID = ulICCIAR & 0x3FFUL;
if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS )
{
/* Call the function installed in the array of installed handler
functions. */
pxVectorEntry = &( pxVectorTable[ ulInterruptID ] );
configASSERT( pxVectorEntry );
pxVectorEntry->Handler( pxVectorEntry->CallBackRef );
}
}

273
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/IntQueueTimer.c Normal file
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@ -0,0 +1,273 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
* NOTE: Currently only timer 1 and timer 2 are used -
*
* This file initialises two timers as follows:
*
* Timer 0 and Timer 1 provide the interrupts that are used with the IntQ
* standard demo tasks, which test interrupt nesting and using queues from
* interrupts. Both these interrupts operate below the maximum syscall
* interrupt priority.
*
* Timer 2 is a much higher frequency timer that tests the nesting of interrupts
* that execute above the maximum syscall interrupt priority.
*
* All the timers can nest with the tick interrupt - creating a maximum
* interrupt nesting depth of 4.
*
* For convenience, the high frequency timer is also used to provide the time
* base for the run time stats.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo includes. */
#include "IntQueueTimer.h"
#include "IntQueue.h"
/* Xilinx includes. */
#include "xttcps.h"
#include "xscugic.h"
/* The frequencies at which the first two timers expire are slightly offset to
ensure they don't remain synchronised. The frequency of the interrupt that
operates above the max syscall interrupt priority is 10 times faster so really
hammers the interrupt entry and exit code. */
#define tmrTIMERS_USED 3
#define tmrTIMER_0_FREQUENCY ( 100UL )
#define tmrTIMER_1_FREQUENCY ( 111UL )
#define tmrTIMER_2_FREQUENCY ( 20000UL )
/*-----------------------------------------------------------*/
/*
* The single interrupt service routines that is used to service all three
* timers.
*/
static void prvTimerHandler( void *CallBackRef );
/*-----------------------------------------------------------*/
/* Hardware constants. */
static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };
static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };
/* Timer configuration settings. */
typedef struct
{
uint32_t OutputHz; /* Output frequency. */
uint16_t Interval; /* Interval value. */
uint8_t Prescaler; /* Prescaler value. */
uint16_t Options; /* Option settings. */
} TmrCntrSetup;
static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =
{
{ tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
{ tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
{ tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }
};
/* Lower priority number means higher logical priority, so
configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call
interrupt priority. */
static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =
{
configMAX_API_CALL_INTERRUPT_PRIORITY + 1,
configMAX_API_CALL_INTERRUPT_PRIORITY,
configMAX_API_CALL_INTERRUPT_PRIORITY - 1
};
static XTtcPs xTimerInstances[ tmrTIMERS_USED ];
/* Used to provide a means of ensuring the intended interrupt nesting depth is
actually being reached. */
extern uint64_t ullPortInterruptNesting;
static volatile uint32_t ulMaxRecordedNesting = 1;
/* Used to ensure the high frequency timer is running at the expected
frequency. */
static volatile uint32_t ulHighFrequencyTimerCounts = 0;
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
BaseType_t xStatus;
TmrCntrSetup *pxTimerSettings;
extern XScuGic xInterruptController;
BaseType_t xTimer;
XTtcPs *pxTimerInstance;
XTtcPs_Config *pxTimerConfiguration;
const uint8_t ucRisingEdge = 3;
/*_RB_ Currently only timer 1 and timer 2 are used. */
for( xTimer = 0; xTimer < ( tmrTIMERS_USED - 1 ); xTimer++ )
{
/* Look up the timer's configuration. */
pxTimerInstance = &( xTimerInstances[ xTimer ] );
pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
configASSERT( pxTimerConfiguration );
pxTimerSettings = &( xTimerSettings[ xTimer ] );
/* Initialise the device. */
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
if( xStatus != XST_SUCCESS )
{
/* Not sure how to do this before XTtcPs_CfgInitialize is called
as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
XTtcPs_Stop( pxTimerInstance );
xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
configASSERT( xStatus == XST_SUCCESS );
}
/* Set the options. */
XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
/* The timer frequency is preset in the pxTimerSettings structure.
Derive the values for the other structure members. */
XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
/* Set the interval and prescale. */
XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
/* The priority must be the lowest possible. */
XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge );
/* Connect to the interrupt controller. */
xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
configASSERT( xStatus == XST_SUCCESS);
/* Enable the interrupt in the GIC. */
XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
/* Enable the interrupts in the timer. */
XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
/* Start the timer. */
XTtcPs_Start( pxTimerInstance );
}
}
/*-----------------------------------------------------------*/
static void prvTimerHandler( void *pvCallBackRef )
{
uint32_t ulInterruptStatus;
XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;
BaseType_t xYieldRequired;
/* Read the interrupt status, then write it back to clear the interrupt. */
ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );
XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus );
__asm volatile( "DSB SY" );
__asm volatile( "ISB SY" );
/* Now the interrupt has been cleared, interrupts can be re-enabled. */
portENABLE_INTERRUPTS();
/* Only one interrupt event type is expected. */
configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );
/* Check the device ID to know which IntQueue demo to call. */
if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )
{
xYieldRequired = xFirstTimerHandler();
}
else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )
{
xYieldRequired = xSecondTimerHandler();
}
else
{
/* Used to check the timer is running at the expected frequency. */
ulHighFrequencyTimerCounts++;
xYieldRequired = pdFALSE;
}
/* Latch the highest interrupt nesting count detected. */
if( ullPortInterruptNesting > ulMaxRecordedNesting )
{
ulMaxRecordedNesting = ullPortInterruptNesting;
}
/* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()
or xSecondTimerHandler() resulted in a task leaving the blocked state and
the task that left the blocked state had a priority higher than the currently
running task (the task this interrupt interrupted) - so a context switch
should be performed so the interrupt returns directly to the higher priority
task. xYieldRequired is tested inside the following macro. */
portYIELD_FROM_ISR( xYieldRequired );
}

78
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/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef INT_QUEUE_TIMER_H
#define INT_QUEUE_TIMER_H
void vInitialiseTimerForIntQueueTest( void );
BaseType_t xTimer0Handler( void );
BaseType_t xTimer1Handler( void );
#endif

459
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c Normal file
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@ -0,0 +1,459 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainSELECTED_APPLICATION setting in main.c is used to select between the two.
* See the notes on using mainSELECTED_APPLICATION in main.c. This file
* implements the comprehensive version.
*
* NOTE 2: This file only contains the source code that is specific to the
* full demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware, are defined in main.c.
*
* NOTE 3: The full demo includes a test that checks the floating point context
* is maintained correctly across task switches. The standard GCC libraries can
* use floating point registers and made this test fail (unless the tasks that
* use the library are given a floating point context as described on the
* documentation page for this demo).
*
******************************************************************************
*
* main_full() creates all the demo application tasks and software timers, then
* starts the scheduler. The web documentation provides more details of the
* standard demo application tasks, which provide no particular functionality,
* but do provide a good example of how to use the FreeRTOS API.
*
* In addition to the standard demo tasks, the following tasks and tests are
* defined and/or created within this file:
*
* "Reg test" tasks - These fill both the core and floating point registers with
* known values, then check that each register maintains its expected value for
* the lifetime of the task. Each task uses a different set of values. The reg
* test tasks execute with a very low priority, so get preempted very
* frequently. A register containing an unexpected value is indicative of an
* error in the context switching mechanism.
*
* "Check" task - The check task period is initially set to three seconds. The
* task checks that all the standard demo tasks, and the register check tasks,
* are not only still executing, but are executing without reporting any errors.
* If the check task discovers that a task has either stalled, or reported an
* error, then it changes its own execution period from the initial three
* seconds, to just 200ms. The check task also toggles an LED each time it is
* called. This provides a visual indication of the system status: If the LED
* toggles every five seconds, then no issues have been discovered. If the LED
* toggles every 200ms, then an issue has been discovered with at least one
* task.
*/
/* Standard includes. */
#include <stdio.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "semphr.h"
/* Standard demo application includes. */
#include "flop.h"
#include "semtest.h"
#include "dynamic.h"
#include "blocktim.h"
#include "countsem.h"
#include "GenQTest.h"
#include "recmutex.h"
#include "partest.h"
#include "IntQueue.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
/* Priorities for the demo application tasks. */
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 3 )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * ( UBaseType_t ) 3 )
#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 )
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - ( UBaseType_t ) 1 )
/* The LED used by the check timer. */
#define mainCHECK_LED ( 0 )
/* A block time of zero simply means "don't block". */
#define mainDONT_BLOCK ( ( TickType_t ) 0 )
/* The period after which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_PERIOD_MS constant. */
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) 5000 )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_PERIOD_MS constant. */
#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) ( 200 ) )
/* Parameters that are passed into the register check tasks solely for the
purpose of ensuring parameters are passed into tasks correctly. */
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/* The base period used by the timer test tasks. */
#define mainTIMER_TEST_PERIOD ( 50 )
/*-----------------------------------------------------------*/
/*
* The check task, as described at the top of this file.
*/
static void prvCheckTask( void *pvParameters );
/*
* Register check tasks, and the tasks used to write over and check the contents
* of the FPU registers, as described at the top of this file. The nature of
* these files necessitates that they are written in an assembly file, but the
* entry points are kept in the C file for the convenience of checking the task
* parameter.
*/
static void prvRegTestTaskEntry1( void *pvParameters );
extern void vRegTest1Implementation( void );
static void prvRegTestTaskEntry2( void *pvParameters );
extern void vRegTest2Implementation( void );
/*
* Register commands that can be used with FreeRTOS+CLI. The commands are
* defined in CLI-Commands.c and File-Related-CLI-Command.c respectively.
*/
extern void vRegisterSampleCLICommands( void );
/*
* The task that manages the FreeRTOS+CLI input and output.
*/
extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority );
/*
* A high priority task that does nothing other than execute at a pseudo random
* time to ensure the other test tasks don't just execute in a repeating
* pattern.
*/
static void prvPseudoRandomiser( void *pvParameters );
/*-----------------------------------------------------------*/
/* The following two variables are used to communicate the status of the
register check tasks to the check task. If the variables keep incrementing,
then the register check tasks have not discovered any errors. If a variable
stops incrementing, then an error has been found. */
volatile uint64_t ullRegTest1LoopCounter = 0ULL, ullRegTest2LoopCounter = 0ULL;
/*-----------------------------------------------------------*/
void main_full( void )
{
/* Start all the other standard demo/test tasks. They have no particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
vStartInterruptQueueTasks();
vStartDynamicPriorityTasks();
vCreateBlockTimeTasks();
vStartCountingSemaphoreTasks();
vStartGenericQueueTasks( tskIDLE_PRIORITY );
vStartRecursiveMutexTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartMathTasks( mainFLOP_TASK_PRIORITY );
vStartEventGroupTasks();
vStartTaskNotifyTask();
vStartInterruptSemaphoreTasks();
/* Create the register check tasks, as described at the top of this file */
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
/* Create the task that just adds a little random behaviour. */
xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
/* Create the task that performs the 'check' functionality, as described at
the top of this file. */
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was either insufficient FreeRTOS heap memory available for the idle
and/or timer tasks to be created, or vTaskStartScheduler() was called from
User mode. See the memory management section on the FreeRTOS web site for
more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The
mode from which main() is called is set in the C start up code and must be
a privileged mode (not user mode). */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
static uint64_t ullLastRegTest1Value = 0, ullLastRegTest2Value = 0;
uint64_t ullErrorFound = pdFALSE;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. The onboard LED is toggled on each iteration.
If an error is detected then the delay period is decreased from
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
effect of increasing the rate at which the onboard LED toggles, and in so
doing gives visual feedback of the system status. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 0ULL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 1ULL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 2ULL;
}
if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 4ULL;
}
if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 5ULL;
}
if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 6ULL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 8ULL;
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 10ULL;
}
if( xAreEventGroupTasksStillRunning() != pdPASS )
{
ullErrorFound |= 1ULL << 12ULL;
}
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 13ULL;
}
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
ullErrorFound |= 1ULL << 14ULL;
}
/* Check that the register test 1 task is still running. */
if( ullLastRegTest1Value == ullRegTest1LoopCounter )
{
ullErrorFound |= 1ULL << 15ULL;
}
ullLastRegTest1Value = ullRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ullLastRegTest2Value == ullRegTest2LoopCounter )
{
ullErrorFound |= 1ULL << 16ULL;
}
ullLastRegTest2Value = ullRegTest2LoopCounter;
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
everything is ok. A faster toggle indicates an error. */
vParTestToggleLED( mainCHECK_LED );
if( ullErrorFound != pdFALSE )
{
/* An error has been detected in one of the tasks - flash the LED
at a higher frequency to give visible feedback that something has
gone wrong (it might just be that the loop back connector required
by the comtest tasks has not been fitted). */
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
}
configASSERT( ullErrorFound == pdFALSE );
}
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry1( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
vPortTaskUsesFPU();
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegTestTaskEntry2( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
written in C for convenience of checking the task parameter is being passed
in correctly. */
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
{
/* The reg test task also tests the floating point registers. Tasks
that use the floating point unit must call vPortTaskUsesFPU() before
any floating point instructions are executed. */
vPortTaskUsesFPU();
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
be incorrect. The check timer will detect that the regtest loop counter is
not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvPseudoRandomiser( void *pvParameters )
{
const uint64_t ullMultiplier = 0x015a4e35ULL, ullIncrement = 1ULL, ullMinDelay = pdMS_TO_TICKS( 95 );
volatile uint64_t ullNextRand = ( uint64_t ) &pvParameters, ullValue;
/* This task does nothing other than ensure there is a little bit of
disruption in the scheduling pattern of the other tasks. Normally this is
done by generating interrupts at pseudo random times. */
for( ;; )
{
ullNextRand = ( ullMultiplier * ullNextRand ) + ullIncrement;
ullValue = ( ullNextRand >> 16ULL ) & 0xffULL;
if( ullValue < ullMinDelay )
{
ullValue = ullMinDelay;
}
vTaskDelay( ullValue );
while( ullValue > 0 )
{
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
__asm volatile( "NOP" );
ullValue--;
}
}
}

605
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/reg_test.S Normal file
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@ -0,0 +1,605 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
.global vRegTest1Implementation
.global vRegTest2Implementation
.extern ullRegTest1LoopCounter
.extern ullRegTest2LoopCounter
.text
/* This function is explained in the comments at the top of main-full.c. */
.type vRegTest1Implementation, %function
vRegTest1Implementation:
/* Fill each general purpose register with a known value. */
mov x0, #0xff
mov x1, #0x01
mov x2, #0x02
mov x3, #0x03
mov x4, #0x04
mov x5, #0x05
mov x6, #0x06
mov x7, #0x07
mov x8, #0x08
mov x9, #0x09
mov x10, #0x10
mov x11, #0x11
mov x12, #0x12
mov x13, #0x13
mov x14, #0x14
mov x15, #0x15
mov x16, #0x16
mov x17, #0x17
mov x18, #0x18
mov x19, #0x19
mov x20, #0x20
mov x21, #0x21
mov x22, #0x22
mov x23, #0x23
mov x24, #0x24
mov x25, #0x25
mov x26, #0x26
mov x27, #0x27
mov x28, #0x28
mov x29, #0x29
mov x30, #0x30
/* Fill each FPU register with a known value. */
fmov v0.d[1], x0
fmov d1, x1
fmov d2, x2
fmov d3, x3
fmov d4, x4
fmov d5, x5
fmov d6, x6
fmov d7, x7
fmov d8, x8
fmov d9, x9
fmov d10, x10
fmov d11, x11
fmov d12, x12
fmov d13, x13
fmov d14, x14
fmov d15, x15
fmov d16, x16
fmov d17, x17
fmov d18, x18
fmov d19, x19
fmov d20, x20
fmov d21, x21
fmov d22, x22
fmov d23, x23
fmov d24, x24
fmov d25, x25
fmov d26, x26
fmov d27, x27
fmov d28, x28
fmov d29, x29
fmov v30.d[1], x30
fmov d31, xzr
/* Loop, checking each itteration that each register still contains the
expected value. */
reg1_loop:
/* Yield to increase test coverage */
SMC 0
/* Test each general purpose register to check that it still contains the
expected known value, jumping to reg1_error_loop if any register contains
an unexpected value. */
cmp x0, #0xFF
bne reg1_error_loop
cmp x1, #0x01
bne reg1_error_loop
cmp x2, #0x02
bne reg1_error_loop
cmp x3, #0x03
bne reg1_error_loop
cmp x4, #0x04
bne reg1_error_loop
cmp x5, #0x05
bne reg1_error_loop
cmp x6, #0x06
bne reg1_error_loop
cmp x7, #0x07
bne reg1_error_loop
cmp x8, #0x08
bne reg1_error_loop
cmp x9, #0x09
bne reg1_error_loop
cmp x10, #0x10
bne reg1_error_loop
cmp x11, #0x11
bne reg1_error_loop
cmp x12, #0x12
bne reg1_error_loop
cmp x13, #0x13
bne reg1_error_loop
cmp x14, #0x14
bne reg1_error_loop
cmp x15, #0x15
bne reg1_error_loop
cmp x16, #0x16
bne reg1_error_loop
cmp x17, #0x17
bne reg1_error_loop
cmp x18, #0x18
bne reg1_error_loop
cmp x19, #0x19
bne reg1_error_loop
cmp x20, #0x20
bne reg1_error_loop
cmp x21, #0x21
bne reg1_error_loop
cmp x22, #0x22
bne reg1_error_loop
cmp x23, #0x23
bne reg1_error_loop
cmp x24, #0x24
bne reg1_error_loop
cmp x25, #0x25
bne reg1_error_loop
cmp x26, #0x26
bne reg1_error_loop
cmp x27, #0x27
bne reg1_error_loop
cmp x28, #0x28
bne reg1_error_loop
cmp x29, #0x29
bne reg1_error_loop
cmp x30, #0x30
bne reg1_error_loop
/* Check every floating point register to ensure it contains the expected
value. First save the registers clobbered by the test. */
stp x0, x1, [sp,#-0x10]!
fmov x0, v0.d[1]
cmp x0, 0xff
bne reg1_error_loop
fmov x0, d1
cmp x0, 0x01
bne reg1_error_loop
fmov x0, d2
cmp x0, 0x02
bne reg1_error_loop
fmov x0, d3
cmp x0, 0x03
bne reg1_error_loop
fmov x0, d4
cmp x0, 0x04
bne reg1_error_loop
fmov x0, d5
cmp x0, 0x05
bne reg1_error_loop
fmov x0, d6
cmp x0, 0x06
bne reg1_error_loop
fmov x0, d7
cmp x0, 0x07
bne reg1_error_loop
fmov x0, d8
cmp x0, 0x08
bne reg1_error_loop
fmov x0, d9
cmp x0, 0x09
bne reg1_error_loop
fmov x0, d10
cmp x0, 0x10
bne reg1_error_loop
fmov x0, d11
cmp x0, 0x11
bne reg1_error_loop
fmov x0, d12
cmp x0, 0x12
bne reg1_error_loop
fmov x0, d13
cmp x0, 0x13
bne reg1_error_loop
fmov x0, d14
cmp x0, 0x14
bne reg1_error_loop
fmov x0, d15
cmp x0, 0x15
bne reg1_error_loop
fmov x0, d16
cmp x0, 0x16
bne reg1_error_loop
fmov x0, d17
cmp x0, 0x17
bne reg1_error_loop
fmov x0, d18
cmp x0, 0x18
bne reg1_error_loop
fmov x0, d19
cmp x0, 0x19
bne reg1_error_loop
fmov x0, d20
cmp x0, 0x20
bne reg1_error_loop
fmov x0, d21
cmp x0, 0x21
bne reg1_error_loop
fmov x0, d22
cmp x0, 0x22
bne reg1_error_loop
fmov x0, d23
cmp x0, 0x23
bne reg1_error_loop
fmov x0, d24
cmp x0, 0x24
bne reg1_error_loop
fmov x0, d25
cmp x0, 0x25
bne reg1_error_loop
fmov x0, d26
cmp x0, 0x26
bne reg1_error_loop
fmov x0, d27
cmp x0, 0x27
bne reg1_error_loop
fmov x0, d28
cmp x0, 0x28
bne reg1_error_loop
fmov x0, d29
cmp x0, 0x29
bne reg1_error_loop
fmov x0, v30.d[1]
cmp x0, 0x30
bne reg1_error_loop
fmov x0, d31
cmp x0, 0x00
bne reg1_error_loop
/* Restore the registers clobbered by the test. */
ldp x0, x1, [sp], #0x10
/* Everything passed, increment the loop counter. */
stp x0, x1, [sp,#-0x10]!
ldr x0, =ullRegTest1LoopCounter
ldr x1, [x0]
adds x1, x1, #1
str x1, [x0]
ldp x0, x1, [sp], #0x10
/* Start again. */
b reg1_loop
reg1_error_loop:
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
nop
/*-----------------------------------------------------------*/
.type vRegTest2Implementation, %function
vRegTest2Implementation:
/* Fill each general purpose register with a known value. */
mov x0, #0xff0
mov x1, #0x010
mov x2, #0x020
mov x3, #0x030
mov x4, #0x040
mov x5, #0x050
mov x6, #0x060
mov x7, #0x070
mov x8, #0x080
mov x9, #0x090
mov x10, #0x100
mov x11, #0x110
mov x12, #0x120
mov x13, #0x130
mov x14, #0x140
mov x15, #0x150
mov x16, #0x160
mov x17, #0x170
mov x18, #0x180
mov x19, #0x190
mov x20, #0x200
mov x21, #0x210
mov x22, #0x220
mov x23, #0x230
mov x24, #0x240
mov x25, #0x250
mov x26, #0x260
mov x27, #0x270
mov x28, #0x280
mov x29, #0x290
mov x30, #0x300
/* Fill each FPU register with a known value. */
fmov d0, x0
fmov d1, x1
fmov d2, x2
fmov d3, x3
fmov d4, x4
fmov d5, x5
fmov d6, x6
fmov d7, x7
fmov d8, x8
fmov d9, x9
fmov v10.d[1], x10
fmov d11, x11
fmov d12, x12
fmov d13, x13
fmov d14, x14
fmov d15, x15
fmov d16, x16
fmov d17, x17
fmov d18, x18
fmov d19, x19
fmov d20, x20
fmov d21, x21
fmov d22, x22
fmov d23, x23
fmov d24, x24
fmov d25, x25
fmov d26, x26
fmov v27.d[1], x27
fmov d28, x28
fmov d29, x29
fmov d30, x30
fmov d31, x0
/* Loop, checking each itteration that each register still contains the
expected value. */
reg2_loop:
/* Test each general purpose register to check that it still contains the
expected known value, jumping to reg2_error_loop if any register contains
an unexpected value. */
cmp x0, #0xFF0
bne reg2_error_loop
cmp x1, #0x010
bne reg2_error_loop
cmp x2, #0x020
bne reg2_error_loop
cmp x3, #0x030
bne reg2_error_loop
cmp x4, #0x040
bne reg2_error_loop
cmp x5, #0x050
bne reg2_error_loop
cmp x6, #0x060
bne reg2_error_loop
cmp x7, #0x070
bne reg2_error_loop
cmp x8, #0x080
bne reg2_error_loop
cmp x9, #0x090
bne reg2_error_loop
cmp x10, #0x100
bne reg2_error_loop
cmp x11, #0x110
bne reg2_error_loop
cmp x12, #0x120
bne reg2_error_loop
cmp x13, #0x130
bne reg2_error_loop
cmp x14, #0x140
bne reg2_error_loop
cmp x15, #0x150
bne reg2_error_loop
cmp x16, #0x160
bne reg2_error_loop
cmp x17, #0x170
bne reg2_error_loop
cmp x18, #0x180
bne reg2_error_loop
cmp x19, #0x190
bne reg2_error_loop
cmp x20, #0x200
bne reg2_error_loop
cmp x21, #0x210
bne reg2_error_loop
cmp x22, #0x220
bne reg2_error_loop
cmp x23, #0x230
bne reg2_error_loop
cmp x24, #0x240
bne reg2_error_loop
cmp x25, #0x250
bne reg2_error_loop
cmp x26, #0x260
bne reg2_error_loop
cmp x27, #0x270
bne reg2_error_loop
cmp x28, #0x280
bne reg2_error_loop
cmp x29, #0x290
bne reg2_error_loop
cmp x30, #0x300
bne reg2_error_loop
/* Check every floating point register to ensure it contains the expected
value. First save the registers clobbered by the test. */
stp x0, x1, [sp,#-0x10]!
fmov x0, d0
cmp x0, 0xff0
bne reg1_error_loop
fmov x0, d1
cmp x0, 0x010
bne reg1_error_loop
fmov x0, d2
cmp x0, 0x020
bne reg1_error_loop
fmov x0, d3
cmp x0, 0x030
bne reg1_error_loop
fmov x0, d4
cmp x0, 0x040
bne reg1_error_loop
fmov x0, d5
cmp x0, 0x050
bne reg1_error_loop
fmov x0, d6
cmp x0, 0x060
bne reg1_error_loop
fmov x0, d7
cmp x0, 0x070
bne reg1_error_loop
fmov x0, d8
cmp x0, 0x080
bne reg1_error_loop
fmov x0, d9
cmp x0, 0x090
bne reg1_error_loop
fmov x0, v10.d[1]
cmp x0, 0x100
bne reg1_error_loop
fmov x0, d11
cmp x0, 0x110
bne reg1_error_loop
fmov x0, d12
cmp x0, 0x120
bne reg1_error_loop
fmov x0, d13
cmp x0, 0x130
bne reg1_error_loop
fmov x0, d14
cmp x0, 0x140
bne reg1_error_loop
fmov x0, d15
cmp x0, 0x150
bne reg1_error_loop
fmov x0, d16
cmp x0, 0x160
bne reg1_error_loop
fmov x0, d17
cmp x0, 0x170
bne reg1_error_loop
fmov x0, d18
cmp x0, 0x180
bne reg1_error_loop
fmov x0, d19
cmp x0, 0x190
bne reg1_error_loop
fmov x0, d20
cmp x0, 0x200
bne reg1_error_loop
fmov x0, d21
cmp x0, 0x210
bne reg1_error_loop
fmov x0, d22
cmp x0, 0x220
bne reg1_error_loop
fmov x0, d23
cmp x0, 0x230
bne reg1_error_loop
fmov x0, d24
cmp x0, 0x240
bne reg1_error_loop
fmov x0, d25
cmp x0, 0x250
bne reg1_error_loop
fmov x0, d26
cmp x0, 0x260
bne reg1_error_loop
fmov x0, v27.d[1]
cmp x0, 0x270
bne reg1_error_loop
fmov x0, d28
cmp x0, 0x280
bne reg1_error_loop
fmov x0, d29
cmp x0, 0x290
bne reg1_error_loop
fmov x0, d30
cmp x0, 0x300
bne reg1_error_loop
fmov x0, d31
cmp x0, 0xff0
bne reg1_error_loop
/* Restore the registers clobbered by the test. */
ldp x0, x1, [sp], #0x10
/* Everything passed, increment the loop counter. */
stp x0, x1, [sp,#-0x10]!
ldr x0, =ullRegTest2LoopCounter
ldr x1, [x0]
adds x1, x1, #1
str x1, [x0]
ldp x0, x1, [sp], #0x10
/* Start again. */
b reg2_loop
reg2_error_loop:
/* If this line is hit then there was an error in a core register value.
The loop ensures the loop counter stops incrementing. */
b reg2_error_loop
nop
.end

105
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c Normal file
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@ -0,0 +1,105 @@
/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Simple IO routines to control the LEDs.
* This file is called ParTest.c for historic reasons. Originally it stood for
* PARallel port TEST.
*-----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo includes. */
#include "partest.h"
/* Don't have any real LEDs yet! */
volatile uint64_t ullLEDToggles = 0;
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
}
/*-----------------------------------------------------------*/
void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue )
{
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
ullLEDToggles++;
}

330
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld Normal file
View file

@ -0,0 +1,330 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A53 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000
psu_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x10000000
psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000
psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
psu_ocm_xmpu_cfg_S_AXI_BASEADDR : ORIGIN = 0xFFA70000, LENGTH = 0x10000
psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000
psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000
psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000
psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000
psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000
psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000
psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000
psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000
psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.init (ALIGN(64)) : {
KEEP (*(.init))
} > psu_r5_ddr_0_S_AXI_BASEADDR
.fini (ALIGN(64)) : {
KEEP (*(.fini))
} > psu_r5_ddr_0_S_AXI_BASEADDR
.interp : {
KEEP (*(.interp))
} > psu_r5_ddr_0_S_AXI_BASEADDR
.note-ABI-tag : {
KEEP (*(.note-ABI-tag))
} > psu_r5_ddr_0_S_AXI_BASEADDR
.rodata : {
. = ALIGN(64);
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.rodata1 : {
. = ALIGN(64);
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.sdata2 : {
. = ALIGN(64);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.sbss2 : {
. = ALIGN(64);
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.data : {
. = ALIGN(64);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.data1 : {
. = ALIGN(64);
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.got : {
*(.got)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.got1 : {
*(.got1)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.got2 : {
*(.got2)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.ctors : {
. = ALIGN(64);
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.dtors : {
. = ALIGN(64);
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > psu_r5_ddr_0_S_AXI_BASEADDR
.mmu_tbl0 (ALIGN(4096)) : {
__mmu_tbl0_start = .;
*(.mmu_tbl0)
__mmu_tbl0_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.mmu_tbl1 (ALIGN(4096)) : {
__mmu_tbl1_start = .;
*(.mmu_tbl1)
__mmu_tbl1_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.mmu_tbl2 (ALIGN(4096)) : {
__mmu_tbl2_start = .;
*(.mmu_tbl2)
__mmu_tbl2_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.preinit_array : {
. = ALIGN(64);
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.init_array : {
. = ALIGN(64);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.fini_array : {
. = ALIGN(64);
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.sdata : {
. = ALIGN(64);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
. = ALIGN(64);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(64);
__sbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.tdata : {
. = ALIGN(64);
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.tbss : {
. = ALIGN(64);
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
. = ALIGN(64);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(64);
__bss_end__ = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(64);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(64);
_el3_stack_end = .;
. += _STACK_SIZE;
__el3_stack = .;
_el2_stack_end = .;
. += _EL2_STACK_SIZE;
. = ALIGN(64);
__el2_stack = .;
_el1_stack_end = .;
. += _EL1_STACK_SIZE;
. = ALIGN(64);
__el1_stack = .;
_el0_stack_end = .;
. += _EL0_STACK_SIZE;
. = ALIGN(64);
__el0_stack = .;
} > psu_r5_ddr_0_S_AXI_BASEADDR
_end = .;
}

352
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c Normal file
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/*
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainSELECTED_APPLICATION setting (defined in this file) is used to select
* between the two. The simply blinky demo is implemented and described in
* main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and FreeRTOS hook functions.
*
* !!! IMPORTANT NOTE !!!
* Some GCC libraries can make use of the floating point registers. To avoid
* this causing corruption it is necessary to avoid their use. For this reason
* main.c contains very basic C implementations of the standard C library
* functions memset(), memcpy() and memcmp(), which are are used by FreeRTOS
* itself. Defining these functions in the project prevents the linker pulling
* them in from the library. Any other standard C library functions that are
* used by the application must likewise be defined in C.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* Standard includes. */
#include <stdio.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Standard demo includes. */
#include "partest.h"
#include "QueueOverwrite.h"
#include "EventGroupsDemo.h"
#include "TaskNotify.h"
#include "IntSemTest.h"
/* Xilinx includes. */
#include "platform.h"
#include "xttcps.h"
#include "xscugic.h"
/* mainSELECTED_APPLICATION is used to select between two demo applications,
* as described at the top of this file.
*
* When mainSELECTED_APPLICATION is set to 0 the simple blinky example will
* be run.
*
* When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo
* application will be run.
*/
#define mainSELECTED_APPLICATION 1
/*-----------------------------------------------------------*/
/*
* Configure the hardware as necessary to run this demo.
*/
static void prvSetupHardware( void );
/*
* See the comments at the top of this file and above the
* mainSELECTED_APPLICATION definition.
*/
#if ( mainSELECTED_APPLICATION == 0 )
extern void main_blinky( void );
#elif ( mainSELECTED_APPLICATION == 1 )
extern void main_full( void );
#else
#error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition.
#endif
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
within this file. */
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/*-----------------------------------------------------------*/
/* The interrupt controller is initialised in this file, and made available to
other modules. */
XScuGic xInterruptController;
/*-----------------------------------------------------------*/
int main( void )
{
/* Configure the hardware ready to run the demo. */
prvSetupHardware();
/* The mainSELECTED_APPLICATION setting is described at the top
of this file. */
#if( mainSELECTED_APPLICATION == 0 )
{
main_blinky();
}
#elif( mainSELECTED_APPLICATION == 1 )
{
main_full();
}
#endif
/* Don't expect to reach here. */
return 0;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
BaseType_t xStatus;
XScuGic_Config *pxGICConfig;
/* Ensure no interrupts execute while the scheduler is in an inconsistent
state. Interrupts are automatically enabled when the scheduler is
started. */
portDISABLE_INTERRUPTS();
/* Obtain the configuration of the GIC. */
pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID );
/* Sanity check the FreeRTOSConfig.h settings are correct for the
hardware. */
configASSERT( pxGICConfig );
configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) );
configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS );
/* Install a default handler for each GIC interrupt. */
xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
configASSERT( xStatus == XST_SUCCESS );
( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This is just a trivial example of an idle hook. It is called on each
cycle of the idle task. It must *NOT* attempt to block. In this case the
idle task just queries the amount of FreeRTOS heap that remains. See the
memory management section on the http://www.FreeRTOS.org web site for memory
management options. If there is a lot of heap memory free then the
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
RAM. */
xFreeHeapSpace = xPortGetFreeHeapSize();
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
( void ) xFreeHeapSpace;
}
/*-----------------------------------------------------------*/
void vAssertCalled( const char * pcFile, unsigned long ulLine )
{
volatile unsigned long ul = 0;
( void ) pcFile;
( void ) ulLine;
taskENTER_CRITICAL();
{
#if( configUSE_TRACE_FACILITY == 1 )
{
vTraceStop();
}
#endif
/* Set ul to a non-zero value using the debugger to step out of this
function. */
while( ul == 0 )
{
portNOP();
}
}
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
#if( mainSELECTED_APPLICATION == 1 )
{
/* Call the periodic event group from ISR demo. */
vPeriodicEventGroupsProcessing();
/* Use task notifications from an interrupt. */
xNotifyTaskFromISR();
/* Use mutexes from interrupts. */
vInterruptSemaphorePeriodicTest();
}
#endif
}
/*-----------------------------------------------------------*/
void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )
{
/* The compiler used during development seems to err unless these volatiles are
included at -O3 optimisation. */
volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;
size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
if( pvDest != pvSource )
{
for( x = 0; x < xBytes; x++ )
{
pcDest[ x ] = pcSource[ x ];
}
}
return pvDest;
}
/*-----------------------------------------------------------*/
void *memset( void *pvDest, int iValue, size_t xBytes )
{
/* The compiler used during development seems to err unless these volatiles are
included at -O3 optimisation. */
volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;
volatile size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
for( x = 0; x < xBytes; x++ )
{
pcDest[ x ] = ( unsigned char ) iValue;
}
return pvDest;
}
/*-----------------------------------------------------------*/
int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes )
{
const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;
volatile size_t x;
/* Extremely crude standard library implementations in lieu of having a C
library. */
for( x = 0; x < xBytes; x++ )
{
if( pucMem1[ x ] != pucMem2[ x ] )
{
break;
}
}
return xBytes - x;
}
/*-----------------------------------------------------------*/

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#include "xparameters.h"
#include "xil_cache.h"
#include "platform_config.h"
/*
* Uncomment the following line if ps7 init source files are added in the
* source directory for compiling example outside of SDK.
*/
/*#include "ps7_init.h"*/
#ifdef STDOUT_IS_16550
#include "xuartns550_l.h"
#define UART_BAUD 9600
#endif
void
enable_caches()
{
#ifdef __PPC__
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheEnable();
#endif
#endif
}
void
disable_caches()
{
Xil_DCacheDisable();
Xil_ICacheDisable();
}
void
init_uart()
{
#ifdef STDOUT_IS_16550
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
#ifdef STDOUT_IS_PS7_UART
/* Bootrom/BSP configures PS7 UART to 115200 bps */
#endif
}
void
init_platform()
{
/*
* If you want to run this example outside of SDK,
* uncomment the following line and also #include "ps7_init.h" at the top.
* Make sure that the ps7_init.c and ps7_init.h files are included
* along with this example source files for compilation.
*/
/* ps7_init();*/
enable_caches();
init_uart();
}
void
cleanup_platform()
{
disable_caches();
}

41
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/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef __PLATFORM_H_
#define __PLATFORM_H_
#include "platform_config.h"
void init_platform();
void cleanup_platform();
#endif

6
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/platform_config.h Normal file
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#ifndef __PLATFORM_CONFIG_H_
#define __PLATFORM_CONFIG_H_
#define STDOUT_IS_PSU_UART
#define UART_DEVICE_ID 0
#endif

13
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1425449123">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1425449123" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTOSDemo_A53_bsp</name>
<comment>Created by SDK v2015.1</comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>

4
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.sdkproject Normal file
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THIRPARTY=false
HW_PROJECT_REFERENCE=ZynqMP_hw_platform
PROCESSOR=psu_cortexa53_0
MSS_FILE=system.mss

31
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile Normal file
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# Makefile generated by Xilinx.
PROCESSOR = psu_cortexa53_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
ifneq (,$(findstring win,$(RDI_PLATFORM)))
SHELL = CMD
endif
all: libs
@echo 'Finished building libraries'
include: $(addsuffix /make.include,$(SUBDIRS))
libs: $(addsuffix /make.libs,$(SUBDIRS))
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -O0"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -O0"
clean:
rm -f ${PROCESSOR}/lib/libxil.a

40
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/bspconfig.h Normal file
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#define MICROBLAZE_PVR_NONE

50
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/sleep.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
s32 usleep(u32 useconds);
s32 sleep(u32 seconds);
#ifdef __cplusplus
}
#endif
#endif

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@ -0,0 +1,81 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.h
*
* This file contains the C level vector prototypes for the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _VECTORS_H_
#define _VECTORS_H_
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
void FIQInterrupt(void);
void IRQInterrupt(void);
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

931
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/******************************************************************************
*
* Copyright (C) 2007 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon.h
*
* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device.
*
* The AXI Performance Monitor device provides following features:
*
* Configurable number of Metric Counters and Incrementers
* Computes performance metrics for Agents connected to
* monitor slots (Up to 8 slots)
*
* The following Metrics can be computed:
*
* Metrics computed for an AXI4 MM agent:
* Write Request Count: Total number of write requests by/to the agent.
* Read Request Count: Total number of read requests given by/to the
* agent.
* Read Latency: It is defined as the time from the start of read address
* transaction to the beginning of the read data service.
* Write Latency: It is defined as the period needed a master completes
* write data transaction, i.e. from write address
* transaction to write response from slave.
* Write Byte Count: Total number of bytes written by/to the agent.
* This metric is helpful when calculating the
* throughput of the system.
* Read Byte Count: Total number of bytes read from/by the agent.
* Average Write Latency: Average write latency seen by the agent.
* It can be derived from total write latency
* and the write request count.
* Average Read Latency: Average read latency seen by the agent. It can be
* derived from total read latency and the read
* request count.
* Master Write Idle Cycle Count: Number of idle cycles caused by the
* masters during write transactions to
* the slave.
* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave
* during write transactions to the slave.
* Master Read Idle Cycle Count: Number of idle cycles caused by the
* master during read transactions to the
* slave.
* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave
* during read transactions to the slave.
*
* Metrics computed for an AXI4-Stream agent:
*
* Transfer Cycle Count: Total number of writes by/to the agent.
* Data Byte Count: Total number of data bytes written by/to the agent.
* This metric helps in calculating the throughput
* of the system.
* Position Byte Count: Total number of position bytes transferred.
* Null Byte Count: Total number of null bytes transferred.
* Packet Count: Total number of packets transferred.
*
* There are three modes : Advanced, Profile and Trace.
* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors
* and Sampled Incrementors.
* - Profile mode has only 47 Metric Counters and Sampled Metric Counters.
* - Trace mode has no Counters.
* User should refer to the hardware device specification for detailed
* information about the device.
*
* This header file contains the prototypes of driver functions that can
* be used to access the AXI Performance Monitor device.
*
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the AXI Performance Monitor device.
*
* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor
* device. The user needs to first call the XAxiPmon_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XAxiPmon_CfgInitialize() API.
*
*
* <b>Interrupts</b>
*
* The AXI Performance Monitor does not support Interrupts
*
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*
* <b> Building the driver </b>
*
* The XAxiPmon driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <b> Limitations of the driver </b>
*
*
* <br><br>
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 To support v2_01_a version of IP:
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
* XAPM_FLAG_EVNTSTOP.
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
* modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
* in xaxipmon.c
* Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
* Added XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
* (CR #683746) in xaxipmon.c
* Added XAxiPmon_EnableEventLog,
* XAxiPmon_DisableMetricsCounter,
* XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
* replace macros in this file.
* Added XAPM_FLAG_XXX macros.
* Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
* APIs (CR #683799).
* Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
* APIs (CR #683801).
* Added XAxiPmon_GetMetricName API (CR #683803).
* Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
* declarations (CR #677337)
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
* Added XAxiPmon_SetLogEnableRanges,
* XAxiPmon_GetLogEnableRanges,
* XAxiPmon_EnableMetricCounterTrigger,
* XAxiPmon_DisableMetricCounterTrigger,
* XAxiPmon_EnableEventLogTrigger,
* XAxiPmon_DisableEventLogTrigger,
* XAxiPmon_SetWriteLatencyId,
* XAxiPmon_SetReadLatencyId,
* XAxiPmon_GetWriteLatencyId,
* XAxiPmon_GetReadLatencyId APIs and removed
* XAxiPmon_SetMetricCounterCutOff,
* XAxiPmon_GetMetricCounterCutOff,
* XAxiPmon_EnableExternalTrigger and
* XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
* xaxipmon_hw.h
* 5.00a bss 08/26/13 To support new version of IP:
* XAxiPmon_SampleMetrics Macro.
* Modified XAxiPmon_CfgInitialize, Assert functions
* Added XAxiPmon_GetMetricCounter,
* XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
* XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
* XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
* XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
* XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
* XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
* Renamed :
* XAxiPmon_SetWriteLatencyId to
* XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
* XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
* XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
* XAxiPmon_GetReadId. in xaxipmon.c
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
* XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK and
* XAPM_MAX_COUNTERS_PROFILE.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
* in xaxipmon_hw.h.
* Modified driver tcl to generate new parameters
* ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
* in Config structure.
* 6.0 adk 19/12/13 Updated as per the New Tcl API's
* 6.1 adk 16/04/14 Updated the driver tcl for the newly added parameters in
* The Axi pmon IP.
* 6.2 bss 04/21/14 Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
* counters and FIFOs based on Modes(CR#782671). And if
* both profile and trace modes are present set mode as
* Advanced.
* 6.2 bss 03/02/15 To support Zynq MP APM:
* Added Is32BitFiltering in XAxiPmon_Config structure.
* Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
* XAxiPmon_GetWriteId, XAxiPmon_GetReadId
* XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
* XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
* functions in xaxipmon.c.
* Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
* xaxipmon_hw.h
*
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_H /* Prevent circular inclusions */
#define XAXIPMON_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xaxipmon_hw.h"
/************************** Constant Definitions ****************************/
/**
* @name Macro for Maximum number of Counters
*
* @{
*/
#define XAPM_MAX_COUNTERS 10 /**< Maximum number of Counters */
#define XAPM_MAX_COUNTERS_PROFILE 48 /**< Maximum number of Counters */
/*@}*/
/**
* @name Indices for Metric Counters and Sampled Metric Coounters used with
* XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs
* @{
*/
#define XAPM_METRIC_COUNTER_0 0 /**< Metric Counter 0 Register Index */
#define XAPM_METRIC_COUNTER_1 1 /**< Metric Counter 1 Register Index */
#define XAPM_METRIC_COUNTER_2 2 /**< Metric Counter 2 Register Index */
#define XAPM_METRIC_COUNTER_3 3 /**< Metric Counter 3 Register Index */
#define XAPM_METRIC_COUNTER_4 4 /**< Metric Counter 4 Register Index */
#define XAPM_METRIC_COUNTER_5 5 /**< Metric Counter 5 Register Index */
#define XAPM_METRIC_COUNTER_6 6 /**< Metric Counter 6 Register Index */
#define XAPM_METRIC_COUNTER_7 7 /**< Metric Counter 7 Register Index */
#define XAPM_METRIC_COUNTER_8 8 /**< Metric Counter 8 Register Index */
#define XAPM_METRIC_COUNTER_9 9 /**< Metric Counter 9 Register Index */
/*@}*/
/**
* @name Indices for Incrementers and Sampled Incrementers used with
* XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs
* @{
*/
#define XAPM_INCREMENTER_0 0 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_1 1 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_2 2 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_3 3 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_4 4 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_5 5 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_6 6 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_7 7 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_8 8 /**< Metric Counter 0 Register Index */
#define XAPM_INCREMENTER_9 9 /**< Metric Counter 0 Register Index */
/*@}*/
/**
* @name Macros for Metric Selector Settings
* @{
*/
#define XAPM_METRIC_SET_0 0 /**< Write Transaction Count */
#define XAPM_METRIC_SET_1 1 /**< Read Transaction Count */
#define XAPM_METRIC_SET_2 2 /**< Write Byte Count */
#define XAPM_METRIC_SET_3 3 /**< Read Byte Count */
#define XAPM_METRIC_SET_4 4 /**< Write Beat Count */
#define XAPM_METRIC_SET_5 5 /**< Total Read Latency */
#define XAPM_METRIC_SET_6 6 /**< Total Write Latency */
#define XAPM_METRIC_SET_7 7 /**< Slv_Wr_Idle_Cnt */
#define XAPM_METRIC_SET_8 8 /**< Mst_Rd_Idle_Cnt */
#define XAPM_METRIC_SET_9 9 /**< Num_BValids */
#define XAPM_METRIC_SET_10 10 /**< Num_WLasts */
#define XAPM_METRIC_SET_11 11 /**< Num_RLasts */
#define XAPM_METRIC_SET_12 12 /**< Minimum Write Latency */
#define XAPM_METRIC_SET_13 13 /**< Maximum Write Latency */
#define XAPM_METRIC_SET_14 14 /**< Minimum Read Latency */
#define XAPM_METRIC_SET_15 15 /**< Maximum Read Latency */
#define XAPM_METRIC_SET_16 16 /**< Transfer Cycle Count */
#define XAPM_METRIC_SET_17 17 /**< Packet Count */
#define XAPM_METRIC_SET_18 18 /**< Data Byte Count */
#define XAPM_METRIC_SET_19 19 /**< Position Byte Count */
#define XAPM_METRIC_SET_20 20 /**< Null Byte Count */
#define XAPM_METRIC_SET_21 21 /**< Slv_Idle_Cnt */
#define XAPM_METRIC_SET_22 22 /**< Mst_Idle_Cnt */
#define XAPM_METRIC_SET_30 30 /**< External event count */
/*@}*/
/**
* @name Macros for Maximum number of Agents
* @{
*/
#define XAPM_MAX_AGENTS 8 /**< Maximum number of Agents */
/*@}*/
/**
* @name Macros for Flags in Flag Enable Control Register
* @{
*/
#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */
#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */
#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */
#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */
#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */
#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */
#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */
#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */
#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */
#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */
#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow
* Flag */
#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */
#define XAPM_FLAG_MC0 0x00400000 /**< Metric Counter 0 Flag */
#define XAPM_FLAG_MC1 0x00800000 /**< Metric Counter 1 Flag */
#define XAPM_FLAG_MC2 0x01000000 /**< Metric Counter 2 Flag */
#define XAPM_FLAG_MC3 0x02000000 /**< Metric Counter 3 Flag */
#define XAPM_FLAG_MC4 0x04000000 /**< Metric Counter 4 Flag */
#define XAPM_FLAG_MC5 0x08000000 /**< Metric Counter 5 Flag */
#define XAPM_FLAG_MC6 0x10000000 /**< Metric Counter 6 Flag */
#define XAPM_FLAG_MC7 0x20000000 /**< Metric Counter 7 Flag */
#define XAPM_FLAG_MC8 0x40000000 /**< Metric Counter 8 Flag */
#define XAPM_FLAG_MC9 0x80000000 /**< Metric Counter 9 Flag */
/*@}*/
/**
* @name Macros for Read/Write Latency Start and End points
* @{
*/
#define XAPM_LATENCY_ADDR_ISSUE 0 /**< Address Issue as start
point for Latency calculation*/
#define XAPM_LATENCY_ADDR_ACCEPT 1 /**< Address Acceptance as start
point for Latency calculation*/
#define XAPM_LATENCY_LASTRD 0 /**< Last Read as end point for
Latency calculation */
#define XAPM_LATENCY_LASTWR 0 /**< Last Write as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTRD 1 /**< First Read as end point for
Latency calculation */
#define XAPM_LATENCY_FIRSTWR 1 /**< First Write as end point for
Latency calculation */
/*@}*/
/**
* @name Macros for Modes of APM
* @{
*/
#define XAPM_MODE_TRACE 2 /**< APM in Trace mode */
#define XAPM_MODE_PROFILE 1 /**< APM in Profile mode */
#define XAPM_MODE_ADVANCED 0 /**< APM in Advanced mode */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the AXI Performance
* Monitor device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Device base address */
int GlobalClkCounterWidth; /**< Global Clock Counter Width */
int MetricSampleCounterWidth ; /**< Metric Sample Counters Width */
u8 IsEventCount; /**< Event Count Enabled 1 - enabled
0 - not enabled */
u8 NumberofSlots; /**< Number of Monitor Slots */
u8 NumberofCounters; /**< Number of Counters */
u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present
0 - Not present */
u8 IsEventLog; /**< Event Logging Enabled 1 - enabled
0 - Not enabled */
u32 FifoDepth; /**< Event Log FIFO Depth */
u32 FifoWidth; /**< Event Log FIFO Width */
u32 TidWidth; /**< Streaming Interface TID Width */
u8 ScaleFactor; /**< Event Count Scaling factor */
u8 ModeAdvanced; /**< Advanced Mode */
u8 ModeProfile; /**< Profile Mode */
u8 ModeTrace; /**< Trace Mode */
u8 Is32BitFiltering; /**< 32 bit filtering enabled */
} XAxiPmon_Config;
/**
* The driver's instance data. The user is required to allocate a variable
* of this type for every AXI Performance Monitor device in system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */
u32 IsReady; /**< Device is initialized and ready */
u8 Mode; /**< APM Mode */
} XAxiPmon;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
*
* This routine enables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalEnable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 1)
/****************************************************************************/
/**
*
* This routine disables the Global Interrupt.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGlobalDisable(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \
XAPM_GIE_OFFSET, 0)
/****************************************************************************/
/**
*
* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to enable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to enable. Bit positions of 1 will be enabled.
* Bit positions of 0 will keep the previous setting. This mask is
* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrEnable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | Mask);
/****************************************************************************/
/**
*
* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in
* xaxipmon_hw.h to create the bit-mask to disable interrupts.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to disable. Bit positions of 1 will be
* disabled. Bit positions of 0 will keep the previous setting.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrDisable(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IE_OFFSET) | Mask);
/****************************************************************************/
/**
*
* This routine clears the specified interrupt(s).
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Mask is the mask to clear. Bit positions of 1 will be cleared.
* This mask is formed by OR'ing XAPM_IXR_* bits defined in
* xaxipmon_hw.h.
*
* @return None.
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XAxiPmon_IntrClear(InstancePtr, Mask) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET) | Mask);
/****************************************************************************/
/**
*
* This routine returns the Interrupt Status Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interrupt Status Register contents
*
* @note C-Style signature:
* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr)
*
*****************************************************************************/
#define XAxiPmon_IntrGetStatus(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_IS_OFFSET);
/****************************************************************************/
/**
*
* This function enables the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the Global Clock Counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function enables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_EnableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) | Flag);
/****************************************************************************/
/**
*
* This function disables the specified flag in Flag Control Register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_DisableFlag(InstancePtr, Flag) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_FEC_OFFSET) & ~(Flag));
/****************************************************************************/
/**
*
* This function loads the sample interval register value into the sample
* interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAPM_SICR_LOAD_MASK);
/****************************************************************************/
/**
*
* This enables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_ENABLE_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK));
/****************************************************************************/
/**
*
* This enables Reset of Metric Counters when Sample Interval Counter lapses.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\
XAPM_SICR_MCNTR_RST_MASK);
/****************************************************************************/
/**
*
* This disables the down count of the sample interval counter.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK));
/****************************************************************************/
/**
*
* This function enables the ID Filter Masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_EnableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK);
/****************************************************************************/
/**
*
* This function disbles the ID Filter masking.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return None
*
* @note C-Style signature:
* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_DisableIDFilter(InstancePtr) \
XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \
XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK));
/****************************************************************************/
/**
*
* This function samples Metric Counters to Sampled Metric Counters by
* reading Sample Register and also returns interval. i.e. the number of
* clocks in between previous read to the current read of sample register.
*
* @param InstancePtr is a pointer to the XAxiPmon instance.
*
* @return Interval. i.e. the number of clocks in between previous
* read to the current read of sample register.
*
* @note C-Style signature:
* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr);
*
*****************************************************************************/
#define XAxiPmon_SampleMetrics(InstancePtr) \
XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET);
/************************** Function Prototypes *****************************/
/**
* Functions in xaxipmon_sinit.c
*/
XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId);
/**
* Functions in xaxipmon.c
*/
int XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr,
XAxiPmon_Config *ConfigPtr, u32 EffectiveAddr);
int XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr);
void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr);
int XAxiPmon_ResetFifo(XAxiPmon *InstancePtr);
void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval);
void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval);
int XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics,
u8 CounterNum);
int XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics,
u8 *Slot);
void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue,
u32 *CntLowValue);
u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum);
u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum);
void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData);
u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr);
int XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables);
int XAxiPmon_StopEventLog(XAxiPmon *InstancePtr);
int XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval);
int XAxiPmon_StopCounters(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr);
void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 RangeUpper, u16 RangeLower);
void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum,
u16 *RangeUpper, u16 *RangeLower);
void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr);
void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr);
void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr);
const char * XAxiPmon_GetMetricName(u8 Metrics);
void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId);
void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId);
u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr);
void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param);
void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param);
u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr);
u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr);
void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask);
void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask);
u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr);
u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr);
/**
* Functions in xaxipmon_selftest.c
*/
int XAxiPmon_SelfTest(XAxiPmon *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xaxipmon_hw.h Normal file
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@ -0,0 +1,566 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xaxipmon_hw.h
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the AXI Performance Monitor.
*
* Refer to the device specification for more information about this driver.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 02/27/12 First release
* 2.00a bss 06/23/12 Updated to support v2_00a version of IP.
* 3.00a bss 09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
* v2_01a version of IP.
* 3.01a bss 10/25/12 To support new version of IP:
* Added XAPM_MCXLOGEN_OFFSET and
* XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
* 4.00a bss 01/17/13 To support new version of IP:
* Added XAPM_LATENCYID_OFFSET,
* XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
* XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
* 5.00a bss 08/26/13 To support new version of IP:
* Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
* XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
* Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
* Added XAPM_CR_IDFILTER_ENABLE_MASK,
* XAPM_CR_WRLATENCY_START_MASK,
* XAPM_CR_WRLATENCY_END_MASK,
* XAPM_CR_RDLATENCY_START_MASK,
* XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
* and XAPM_MASKID_WID_MASK macros.
* Renamed:
* XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
* XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
* XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
*
* 6.2 bss 03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
* Zynq MP APM.
* </pre>
*
*****************************************************************************/
#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */
#define XAXIPMON_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/**@name Register offsets of AXIMONITOR in the Device Config
*
* The following constants provide access to each of the registers of the
* AXI PERFORMANCE MONITOR device.
* @{
*/
#define XAPM_GCC_HIGH_OFFSET 0x0000 /**< Global Clock Counter
32 to 63 bits */
#define XAPM_GCC_LOW_OFFSET 0x0004 /**< Global Clock Counter Lower
0-31 bits */
#define XAPM_SI_HIGH_OFFSET 0x0020 /**< Sample Interval MSB */
#define XAPM_SI_LOW_OFFSET 0x0024 /**< Sample Interval LSB */
#define XAPM_SICR_OFFSET 0x0028 /**< Sample Interval Control
Register */
#define XAPM_SR_OFFSET 0x002C /**< Sample Register */
#define XAPM_GIE_OFFSET 0x0030 /**< Global Interrupt Enable
Register */
#define XAPM_IE_OFFSET 0x0034 /**< Interrupt Enable Register */
#define XAPM_IS_OFFSET 0x0038 /**< Interrupt Status Register */
#define XAPM_MSR0_OFFSET 0x0044 /**< Metric Selector 0 Register */
#define XAPM_MSR1_OFFSET 0x0048 /**< Metric Selector 1 Register */
#define XAPM_MSR2_OFFSET 0x004C /**< Metric Selector 2 Register */
#define XAPM_MC0_OFFSET 0x0100 /**< Metric Counter 0 Register */
#define XAPM_INC0_OFFSET 0x0104 /**< Incrementer 0 Register */
#define XAPM_RANGE0_OFFSET 0x0108 /**< Range 0 Register */
#define XAPM_MC0LOGEN_OFFSET 0x010C /**< Metric Counter 0
Log Enable Register */
#define XAPM_MC1_OFFSET 0x0110 /**< Metric Counter 1 Register */
#define XAPM_INC1_OFFSET 0x0114 /**< Incrementer 1 Register */
#define XAPM_RANGE1_OFFSET 0x0118 /**< Range 1 Register */
#define XAPM_MC1LOGEN_OFFSET 0x011C /**< Metric Counter 1
Log Enable Register */
#define XAPM_MC2_OFFSET 0x0120 /**< Metric Counter 2 Register */
#define XAPM_INC2_OFFSET 0x0124 /**< Incrementer 2 Register */
#define XAPM_RANGE2_OFFSET 0x0128 /**< Range 2 Register */
#define XAPM_MC2LOGEN_OFFSET 0x012C /**< Metric Counter 2
Log Enable Register */
#define XAPM_MC3_OFFSET 0x0130 /**< Metric Counter 3 Register */
#define XAPM_INC3_OFFSET 0x0134 /**< Incrementer 3 Register */
#define XAPM_RANGE3_OFFSET 0x0138 /**< Range 3 Register */
#define XAPM_MC3LOGEN_OFFSET 0x013C /**< Metric Counter 3
Log Enable Register */
#define XAPM_MC4_OFFSET 0x0140 /**< Metric Counter 4 Register */
#define XAPM_INC4_OFFSET 0x0144 /**< Incrementer 4 Register */
#define XAPM_RANGE4_OFFSET 0x0148 /**< Range 4 Register */
#define XAPM_MC4LOGEN_OFFSET 0x014C /**< Metric Counter 4
Log Enable Register */
#define XAPM_MC5_OFFSET 0x0150 /**< Metric Counter 5
Register */
#define XAPM_INC5_OFFSET 0x0154 /**< Incrementer 5 Register */
#define XAPM_RANGE5_OFFSET 0x0158 /**< Range 5 Register */
#define XAPM_MC5LOGEN_OFFSET 0x015C /**< Metric Counter 5
Log Enable Register */
#define XAPM_MC6_OFFSET 0x0160 /**< Metric Counter 6
Register */
#define XAPM_INC6_OFFSET 0x0164 /**< Incrementer 6 Register */
#define XAPM_RANGE6_OFFSET 0x0168 /**< Range 6 Register */
#define XAPM_MC6LOGEN_OFFSET 0x016C /**< Metric Counter 6
Log Enable Register */
#define XAPM_MC7_OFFSET 0x0170 /**< Metric Counter 7
Register */
#define XAPM_INC7_OFFSET 0x0174 /**< Incrementer 7 Register */
#define XAPM_RANGE7_OFFSET 0x0178 /**< Range 7 Register */
#define XAPM_MC7LOGEN_OFFSET 0x017C /**< Metric Counter 7
Log Enable Register */
#define XAPM_MC8_OFFSET 0x0180 /**< Metric Counter 8
Register */
#define XAPM_INC8_OFFSET 0x0184 /**< Incrementer 8 Register */
#define XAPM_RANGE8_OFFSET 0x0188 /**< Range 8 Register */
#define XAPM_MC8LOGEN_OFFSET 0x018C /**< Metric Counter 8
Log Enable Register */
#define XAPM_MC9_OFFSET 0x0190 /**< Metric Counter 9
Register */
#define XAPM_INC9_OFFSET 0x0194 /**< Incrementer 9 Register */
#define XAPM_RANGE9_OFFSET 0x0198 /**< Range 9 Register */
#define XAPM_MC9LOGEN_OFFSET 0x019C /**< Metric Counter 9
Log Enable Register */
#define XAPM_SMC0_OFFSET 0x0200 /**< Sampled Metric Counter
0 Register */
#define XAPM_SINC0_OFFSET 0x0204 /**< Sampled Incrementer
0 Register */
#define XAPM_SMC1_OFFSET 0x0210 /**< Sampled Metric Counter
1 Register */
#define XAPM_SINC1_OFFSET 0x0214 /**< Sampled Incrementer
1 Register */
#define XAPM_SMC2_OFFSET 0x0220 /**< Sampled Metric Counter
2 Register */
#define XAPM_SINC2_OFFSET 0x0224 /**< Sampled Incrementer
2 Register */
#define XAPM_SMC3_OFFSET 0x0230 /**< Sampled Metric Counter
3 Register */
#define XAPM_SINC3_OFFSET 0x0234 /**< Sampled Incrementer
3 Register */
#define XAPM_SMC4_OFFSET 0x0240 /**< Sampled Metric Counter
4 Register */
#define XAPM_SINC4_OFFSET 0x0244 /**< Sampled Incrementer
4 Register */
#define XAPM_SMC5_OFFSET 0x0250 /**< Sampled Metric Counter
5 Register */
#define XAPM_SINC5_OFFSET 0x0254 /**< Sampled Incrementer
5 Register */
#define XAPM_SMC6_OFFSET 0x0260 /**< Sampled Metric Counter
6 Register */
#define XAPM_SINC6_OFFSET 0x0264 /**< Sampled Incrementer
6 Register */
#define XAPM_SMC7_OFFSET 0x0270 /**< Sampled Metric Counter
7 Register */
#define XAPM_SINC7_OFFSET 0x0274 /**< Sampled Incrementer
7 Register */
#define XAPM_SMC8_OFFSET 0x0280 /**< Sampled Metric Counter
8 Register */
#define XAPM_SINC8_OFFSET 0x0284 /**< Sampled Incrementer
8 Register */
#define XAPM_SMC9_OFFSET 0x0290 /**< Sampled Metric Counter
9 Register */
#define XAPM_SINC9_OFFSET 0x0294 /**< Sampled Incrementer
9 Register */
#define XAPM_MC10_OFFSET 0x01A0 /**< Metric Counter 10
Register */
#define XAPM_MC11_OFFSET 0x01B0 /**< Metric Counter 11
Register */
#define XAPM_MC12_OFFSET 0x0500 /**< Metric Counter 12
Register */
#define XAPM_MC13_OFFSET 0x0510 /**< Metric Counter 13
Register */
#define XAPM_MC14_OFFSET 0x0520 /**< Metric Counter 14
Register */
#define XAPM_MC15_OFFSET 0x0530 /**< Metric Counter 15
Register */
#define XAPM_MC16_OFFSET 0x0540 /**< Metric Counter 16
Register */
#define XAPM_MC17_OFFSET 0x0550 /**< Metric Counter 17
Register */
#define XAPM_MC18_OFFSET 0x0560 /**< Metric Counter 18
Register */
#define XAPM_MC19_OFFSET 0x0570 /**< Metric Counter 19
Register */
#define XAPM_MC20_OFFSET 0x0580 /**< Metric Counter 20
Register */
#define XAPM_MC21_OFFSET 0x0590 /**< Metric Counter 21
Register */
#define XAPM_MC22_OFFSET 0x05A0 /**< Metric Counter 22
Register */
#define XAPM_MC23_OFFSET 0x05B0 /**< Metric Counter 23
Register */
#define XAPM_MC24_OFFSET 0x0700 /**< Metric Counter 24
Register */
#define XAPM_MC25_OFFSET 0x0710 /**< Metric Counter 25
Register */
#define XAPM_MC26_OFFSET 0x0720 /**< Metric Counter 26
Register */
#define XAPM_MC27_OFFSET 0x0730 /**< Metric Counter 27
Register */
#define XAPM_MC28_OFFSET 0x0740 /**< Metric Counter 28
Register */
#define XAPM_MC29_OFFSET 0x0750 /**< Metric Counter 29
Register */
#define XAPM_MC30_OFFSET 0x0760 /**< Metric Counter 30
Register */
#define XAPM_MC31_OFFSET 0x0770 /**< Metric Counter 31
Register */
#define XAPM_MC32_OFFSET 0x0780 /**< Metric Counter 32
Register */
#define XAPM_MC33_OFFSET 0x0790 /**< Metric Counter 33
Register */
#define XAPM_MC34_OFFSET 0x07A0 /**< Metric Counter 34
Register */
#define XAPM_MC35_OFFSET 0x07B0 /**< Metric Counter 35
Register */
#define XAPM_MC36_OFFSET 0x0900 /**< Metric Counter 36
Register */
#define XAPM_MC37_OFFSET 0x0910 /**< Metric Counter 37
Register */
#define XAPM_MC38_OFFSET 0x0920 /**< Metric Counter 38
Register */
#define XAPM_MC39_OFFSET 0x0930 /**< Metric Counter 39
Register */
#define XAPM_MC40_OFFSET 0x0940 /**< Metric Counter 40
Register */
#define XAPM_MC41_OFFSET 0x0950 /**< Metric Counter 41
Register */
#define XAPM_MC42_OFFSET 0x0960 /**< Metric Counter 42
Register */
#define XAPM_MC43_OFFSET 0x0970 /**< Metric Counter 43
Register */
#define XAPM_MC44_OFFSET 0x0980 /**< Metric Counter 44
Register */
#define XAPM_MC45_OFFSET 0x0990 /**< Metric Counter 45
Register */
#define XAPM_MC46_OFFSET 0x09A0 /**< Metric Counter 46
Register */
#define XAPM_MC47_OFFSET 0x09B0 /**< Metric Counter 47
Register */
#define XAPM_SMC10_OFFSET 0x02A0 /**< Sampled Metric Counter
10 Register */
#define XAPM_SMC11_OFFSET 0x02B0 /**< Sampled Metric Counter
11 Register */
#define XAPM_SMC12_OFFSET 0x0600 /**< Sampled Metric Counter
12 Register */
#define XAPM_SMC13_OFFSET 0x0610 /**< Sampled Metric Counter
13 Register */
#define XAPM_SMC14_OFFSET 0x0620 /**< Sampled Metric Counter
14 Register */
#define XAPM_SMC15_OFFSET 0x0630 /**< Sampled Metric Counter
15 Register */
#define XAPM_SMC16_OFFSET 0x0640 /**< Sampled Metric Counter
16 Register */
#define XAPM_SMC17_OFFSET 0x0650 /**< Sampled Metric Counter
17 Register */
#define XAPM_SMC18_OFFSET 0x0660 /**< Sampled Metric Counter
18 Register */
#define XAPM_SMC19_OFFSET 0x0670 /**< Sampled Metric Counter
19 Register */
#define XAPM_SMC20_OFFSET 0x0680 /**< Sampled Metric Counter
20 Register */
#define XAPM_SMC21_OFFSET 0x0690 /**< Sampled Metric Counter
21 Register */
#define XAPM_SMC22_OFFSET 0x06A0 /**< Sampled Metric Counter
22 Register */
#define XAPM_SMC23_OFFSET 0x06B0 /**< Sampled Metric Counter
23 Register */
#define XAPM_SMC24_OFFSET 0x0800 /**< Sampled Metric Counter
24 Register */
#define XAPM_SMC25_OFFSET 0x0810 /**< Sampled Metric Counter
25 Register */
#define XAPM_SMC26_OFFSET 0x0820 /**< Sampled Metric Counter
26 Register */
#define XAPM_SMC27_OFFSET 0x0830 /**< Sampled Metric Counter
27 Register */
#define XAPM_SMC28_OFFSET 0x0840 /**< Sampled Metric Counter
28 Register */
#define XAPM_SMC29_OFFSET 0x0850 /**< Sampled Metric Counter
29 Register */
#define XAPM_SMC30_OFFSET 0x0860 /**< Sampled Metric Counter
30 Register */
#define XAPM_SMC31_OFFSET 0x0870 /**< Sampled Metric Counter
31 Register */
#define XAPM_SMC32_OFFSET 0x0880 /**< Sampled Metric Counter
32 Register */
#define XAPM_SMC33_OFFSET 0x0890 /**< Sampled Metric Counter
33 Register */
#define XAPM_SMC34_OFFSET 0x08A0 /**< Sampled Metric Counter
34 Register */
#define XAPM_SMC35_OFFSET 0x08B0 /**< Sampled Metric Counter
35 Register */
#define XAPM_SMC36_OFFSET 0x0A00 /**< Sampled Metric Counter
36 Register */
#define XAPM_SMC37_OFFSET 0x0A10 /**< Sampled Metric Counter
37 Register */
#define XAPM_SMC38_OFFSET 0x0A20 /**< Sampled Metric Counter
38 Register */
#define XAPM_SMC39_OFFSET 0x0A30 /**< Sampled Metric Counter
39 Register */
#define XAPM_SMC40_OFFSET 0x0A40 /**< Sampled Metric Counter
40 Register */
#define XAPM_SMC41_OFFSET 0x0A50 /**< Sampled Metric Counter
41 Register */
#define XAPM_SMC42_OFFSET 0x0A60 /**< Sampled Metric Counter
42 Register */
#define XAPM_SMC43_OFFSET 0x0A70 /**< Sampled Metric Counter
43 Register */
#define XAPM_SMC44_OFFSET 0x0A80 /**< Sampled Metric Counter
44 Register */
#define XAPM_SMC45_OFFSET 0x0A90 /**< Sampled Metric Counter
45 Register */
#define XAPM_SMC46_OFFSET 0x0AA0 /**< Sampled Metric Counter
46 Register */
#define XAPM_SMC47_OFFSET 0x0AB0 /**< Sampled Metric Counter
47 Register */
#define XAPM_CTL_OFFSET 0x0300 /**< Control Register */
#define XAPM_ID_OFFSET 0x0304 /**< Latency ID Register */
#define XAPM_IDMASK_OFFSET 0x0308 /**< ID Mask Register */
#define XAPM_RID_OFFSET 0x030C /**< Latency Write ID Register */
#define XAPM_RIDMASK_OFFSET 0x0310 /**< Read ID Mask Register */
#define XAPM_FEC_OFFSET 0x0400 /**< Flag Enable
Control Register */
#define XAPM_SWD_OFFSET 0x0404 /**< Software-written
Data Register */
/* @} */
/**
* @name AXI Monitor Sample Interval Control Register mask(s)
* @{
*/
#define XAPM_SICR_MCNTR_RST_MASK 0x00000100 /**< Enable the Metric
Counter Reset */
#define XAPM_SICR_LOAD_MASK 0x00000002 /**< Load the Sample Interval
* Register Value into the
* counter */
#define XAPM_SICR_ENABLE_MASK 0x00000001 /**< Enable the downcounter */
/*@}*/
/** @name Interrupt Status/Enable Register Bit Definitions and Masks
* @{
*/
#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000 /**< Metric Counter 9
* Overflow> */
#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800 /**< Metric Counter 8
* Overflow> */
#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400 /**< Metric Counter 7
* Overflow> */
#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200 /**< Metric Counter 6
* Overflow> */
#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100 /**< Metric Counter 5
* Overflow> */
#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080 /**< Metric Counter 4
* Overflow> */
#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040 /**< Metric Counter 3
* Overflow> */
#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020 /**< Metric Counter 2
* Overflow> */
#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010 /**< Metric Counter 1
* Overflow> */
#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008 /**< Metric Counter 0
* Overflow> */
#define XAPM_IXR_FIFO_FULL_MASK 0x00000004 /**< Event Log FIFO
* full> */
#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002 /**< Sample Interval
* Counter Overflow> */
#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001 /**< Global Clock Counter
* Overflow> */
#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \
XAPM_IXR_GCC_OVERFLOW_MASK | \
XAPM_IXR_FIFO_FULL_MASK | \
XAPM_IXR_MC0_OVERFLOW_MASK | \
XAPM_IXR_MC1_OVERFLOW_MASK | \
XAPM_IXR_MC2_OVERFLOW_MASK | \
XAPM_IXR_MC3_OVERFLOW_MASK | \
XAPM_IXR_MC4_OVERFLOW_MASK | \
XAPM_IXR_MC5_OVERFLOW_MASK | \
XAPM_IXR_MC6_OVERFLOW_MASK | \
XAPM_IXR_MC7_OVERFLOW_MASK | \
XAPM_IXR_MC8_OVERFLOW_MASK | \
XAPM_IXR_MC9_OVERFLOW_MASK)
/* @} */
/**
* @name AXI Monitor Control Register mask(s)
* @{
*/
#define XAPM_CR_FIFO_RESET_MASK 0x02000000
/**< FIFO Reset */
#define XAPM_CR_GCC_RESET_MASK 0x00020000
/**< Global Clk
Counter Reset */
#define XAPM_CR_GCC_ENABLE_MASK 0x00010000
/**< Global Clk
Counter Enable */
#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200
/**< Enable External trigger
to start event Log */
#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100
/**< Event Log Enable */
#define XAPM_CR_RDLATENCY_END_MASK 0x00000080
/**< Write Latency
End point */
#define XAPM_CR_RDLATENCY_START_MASK 0x00000040
/**< Read Latency
Start point */
#define XAPM_CR_WRLATENCY_END_MASK 0x00000020
/**< Write Latency
End point */
#define XAPM_CR_WRLATENCY_START_MASK 0x00000010
/**< Write Latency
Start point */
#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008
/**< ID Filter Enable */
#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004
/**< Enable External
trigger to start
Metric Counters */
#define XAPM_CR_MCNTR_RESET_MASK 0x00000002
/**< Metrics Counter
Reset */
#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001
/**< Metrics Counter
Enable */
/*@}*/
/**
* @name AXI Monitor ID Register mask(s)
* @{
*/
#define XAPM_ID_RID_MASK 0xFFFF0000 /**< Read ID */
#define XAPM_ID_WID_MASK 0x0000FFFF /**< Write ID */
/*@}*/
/**
* @name AXI Monitor ID Mask Register mask(s)
* @{
*/
#define XAPM_MASKID_RID_MASK 0xFFFF0000 /**< Read ID Mask */
#define XAPM_MASKID_WID_MASK 0x0000FFFF /**< Write ID Mask*/
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/*****************************************************************************/
/**
*
* Write a register of the AXI Performance Monitor device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XAxiPmon_WriteReg(u32 BaseAddress,
* u32 RegOffset,u32 Data)
*
******************************************************************************/
#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* </pre>
*
******************************************************************************/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef unsigned char Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef unsigned short Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef unsigned long Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#endif /* end of protection macro */

567
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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcanps.h
*
* The Xilinx CAN driver component. This component supports the Xilinx
* CAN Controller.
*
* The CAN Controller supports the following features:
* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards.
* - Supports both Standard (11 bit Identifier) and Extended (29 bit
* Identifier) frames.
* - Supports Bit Rates up to 1 Mbps.
* - Transmit message object FIFO with a user configurable depth of
* up to 64 message objects.
* - Transmit prioritization through one TX High Priority Buffer.
* - Receive message object FIFO with a user configurable depth of
* up to 64 message objects.
* - Watermark interrupts for Rx FIFO with configurable Watermark.
* - Acceptance filtering with 4 acceptance filters.
* - Sleep mode with automatic wake up.
* - Loop Back mode for diagnostic applications.
* - Snoop mode for diagnostic applications.
* - Maskable Error and Status Interrupts.
* - Readable Error Counters.
* - External PHY chip required.
* - Receive Timestamp.
*
* The device driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the CAN. The driver handles transmission and reception of
* CAN frames, as well as configuration of the controller. The driver is simply a
* pass-through mechanism between a protocol stack and the CAN. A single device
* driver can support multiple CANs.
*
* Since the driver is a simple pass-through mechanism between a protocol stack
* and the CAN, no assembly or disassembly of CAN frames is done at the
* driver-level. This assumes that the protocol stack passes a correctly
* formatted CAN frame to the driver for transmission, and that the driver
* does not validate the contents of an incoming frame
*
* <b>Operation Modes</b>
*
* The CAN controller supports the following modes of operation:
* - <b>Configuration Mode</b>: In this mode the CAN timing parameters and
* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN
* controller loses synchronization with the CAN bus and drives a
* constant recessive bit on the bus line. The Error Counter Register are
* reset. The CAN controller does not receive or transmit any messages
* even if there are pending transmit requests from the TX FIFO or the TX
* High Priority Buffer. The Storage FIFOs and the CAN configuration
* registers are still accessible.
* - <b>Normal Mode</b>:In Normal Mode the CAN controller participates in bus
* communication, by transmitting and receiving messages.
* - <b>Sleep Mode</b>: In Sleep Mode the CAN Controller does not transmit any
* messages. However, if any other node transmits a message, then the CAN
* Controller receives the transmitted message and exits from Sleep Mode.
* If there are new transmission requests from either the TX FIFO or the
* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these
* requests are not serviced, and the CAN Controller continues to remain
* in Sleep Mode. Interrupts are generated when the CAN controller enters
* Sleep mode or Wakes up from Sleep mode.
* - <b>Loop Back Mode</b>: In Loop Back mode, the CAN controller transmits a
* recessive bit stream on to the CAN Bus. Any message that is transmitted
* is looped back to the <EFBFBD>Rx<EFBFBD> line and acknowledged. The CAN controller
* thus receives any message that it transmits. It does not participate in
* normal bus communication and does not receive any messages that are
* transmitted by other CAN nodes. This mode is used for diagnostic
* purposes.
* - <b>Snoop Mode</b>: In Snoop mode, the CAN controller transmits a
* recessive bit stream on to the CAN Bus and does not participate
* in normal bus communication but receives messages that are transmitted
* by other CAN nodes. This mode is used for diagnostic purposes.
*
*
* <b>Buffer Alignment</b>
*
* It is important to note that frame buffers passed to the driver must be
* 32-bit aligned.
*
* <b>Receive Address Filtering</b>
*
* The device can be set to accept frames whose Identifiers match any of the
* 4 filters set in the Acceptance Filter Mask/ID registers.
*
* The incoming Identifier is masked with the bits in the Acceptance Filter Mask
* Register. This value is compared with the result of masking the bits in the
* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If
* both these values are equal, the message will be stored in the RX FIFO.
*
* Acceptance Filtering is performed by each of the defined acceptance filters.
* If the incoming identifier passes through any acceptance filter then the
* frame is stored in the RX FIFO.
*
* If the Accpetance Filters are not set up then all the received messages are
* stroed in the RX FIFO.
*
* <b>PHY Communication</b>
*
* This driver does not provide any mechanism for directly programming PHY.
*
* <b>Interrupts</b>
*
* The driver has no dependencies on the interrupt controller. The driver
* provides an interrupt handler. User of this driver needs to provide
* callback functions. An interrupt handler example is available with
* the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Device Reset</b>
*
* Bus Off interrupt that can occur in the device requires a device reset.
* The user is responsible for resetting the device and re-configuring it
* based on its needs (the driver does not save the current configuration).
* When integrating into an RTOS, these reset and re-configure obligations are
* taken care of by the OS adapter software if it exists for that RTOS.
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xcanps_g.c files.
* A table is defined where each entry contains configuration information
* for a CAN device. This information includes such things as the base address
* of the memory-mapped device.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XCanPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00a xd/sv 01/12/10 First release
* 1.01a bss 12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
* XCanPs_GetTxIntrWatermark.
* Updated the Register/bit definitions
* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
* Changed XCANPS_IXR_RXFLL_MASK to
* XCANPS_IXR_RXFWMFLL_MASK
* Changed
* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
* 2.1 adk 23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
* SDK claims a 40kbps baud rate but it's not.
* 3.0 adk 09/12/14 Added support for Zynq Ultrascale Mp.Also code
* modified for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XCANPS_H /* prevent circular inclusions */
#define XCANPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xcanps_hw.h"
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/** @name CAN operation modes
* @{
*/
#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */
#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */
#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */
#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */
#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */
/* @} */
/** @name Callback identifiers used as parameters to XCanPs_SetHandler()
* @{
*/
#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */
#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/
#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */
#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */
/* @} */
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XCanPs_Config;
/******************************************************************************/
/**
* Callback type for frame sending and reception interrupts.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
*******************************************************************************/
typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef);
/******************************************************************************/
/**
* Callback type for error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* @param ErrorMask is a bit mask indicating the cause of the error. Its
* value equals 'OR'ing one or more XCANPS_ESR_* values defined in
* xcanps_hw.h
*******************************************************************************/
typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
/******************************************************************************/
/**
* Callback type for all kinds of interrupts except sending frame interrupt,
* receiving frame interrupt, and error interrupt.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions, and passed back to the
* upper layer when the callback is invoked.
* @param Mask is a bit mask indicating the pending interrupts. Its value
* equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h
*******************************************************************************/
typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask);
/**
* The XCanPs driver instance data. The user is required to allocate a
* variable of this type for every CAN device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XCanPs_Config CanConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
/**
* Callback and callback reference for TXOK interrupt.
*/
XCanPs_SendRecvHandler SendHandler;
void *SendRef;
/**
* Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts.
*/
XCanPs_SendRecvHandler RecvHandler;
void *RecvRef;
/**
* Callback and callback reference for ERROR interrupt.
*/
XCanPs_ErrorHandler ErrorHandler;
void *ErrorRef;
/**
* Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/
* Wakeup/Sleep/Bus off/ARBLST interrupts.
*/
XCanPs_EventHandler EventHandler;
void *EventRef;
} XCanPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro checks if the transmission is complete.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the transmission is done.
* - FALSE if the transmission is not done.
*
* @note C-Style signature:
* int XCanPs_IsTxDone(XCanPs *InstancePtr)
*
*******************************************************************************/
#define XCanPs_IsTxDone(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the transmission FIFO is full.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if TX FIFO is full.
* - FALSE if the TX FIFO is NOT full.
*
* @note C-Style signature:
* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsTxFifoFull(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the Transmission High Priority Buffer is full.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the TX High Priority Buffer is full.
* - FALSE if the TX High Priority Buffer is NOT full.
*
* @note C-Style signature:
* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsHighPriorityBufFull(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro checks if the receive FIFO is empty.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if RX FIFO is empty.
* - FALSE if the RX FIFO is NOT empty.
*
* @note C-Style signature:
* int XCanPs_IsRxEmpty(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsRxEmpty(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE)
/****************************************************************************/
/**
*
* This macro checks if the CAN device is ready for the driver to change
* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask
* Registers (AFMR).
*
* AFIR and AFMR for a filter are changeable only after the filter is disabled
* and this routine returns FALSE. The filter can be disabled using the
* XCanPs_AcceptFilterDisable function.
*
* Use the XCanPs_Accept_* functions for configuring the acceptance filters.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return
* - TRUE if the device is busy and NOT ready to accept writes to
* AFIR and AFMR.
* - FALSE if the device is ready to accept writes to AFIR and
* AFMR.
*
* @note C-Style signature:
* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_IsAcceptFilterBusy(InstancePtr) \
(((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \
XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro calculates CAN message identifier value given identifier field
* values.
*
* @param StandardId contains Standard Message ID value.
* @param SubRemoteTransReq contains Substitute Remote Transmission
* Request value.
* @param IdExtension contains Identifier Extension value.
* @param ExtendedId contains Extended Message ID value.
* @param RemoteTransReq contains Remote Transmission Request value.
*
* @return Message Identifier value.
*
* @note C-Style signature:
* u32 XCanPs_CreateIdValue(u32 StandardId,
* u32 SubRemoteTransReq,
* u32 IdExtension, u32 ExtendedId,
* u32 RemoteTransReq)
*
* Read the CAN specification for meaning of each parameter.
*
*****************************************************************************/
#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \
ExtendedId, RemoteTransReq) \
((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \
(((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\
(((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \
(((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \
((RemoteTransReq) & XCANPS_IDR_RTR_MASK))
/****************************************************************************/
/**
*
* This macro calculates value for Data Length Code register given Data
* Length Code value.
*
* @param DataLengCode indicates Data Length Code value.
*
* @return Value that can be assigned to Data Length Code register.
*
* @note C-Style signature:
* u32 XCanPs_CreateDlcValue(u32 DataLengCode)
*
* Read the CAN specification for meaning of Data Length Code.
*
*****************************************************************************/
#define XCanPs_CreateDlcValue(DataLengCode) \
(((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK)
/****************************************************************************/
/**
*
* This macro clears the timestamp in the Timestamp Control Register.
*
* @param InstancePtr is a pointer to the XCanPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XCanPs_ClearTimestamp(XCanPs *InstancePtr)
*
*****************************************************************************/
#define XCanPs_ClearTimestamp(InstancePtr) \
XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \
XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK)
/************************** Function Prototypes ******************************/
/*
* Functions in xcanps.c
*/
s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr,
u32 EffectiveAddr);
void XCanPs_Reset(XCanPs *InstancePtr);
u8 XCanPs_GetMode(XCanPs *InstancePtr);
void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode);
u32 XCanPs_GetStatus(XCanPs *InstancePtr);
void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount,
u8 *TxErrorCount);
u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr);
void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask);
s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr);
s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr);
s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr);
void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes);
void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes);
u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr);
s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex,
u32 MaskValue, u32 IdValue);
void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex,
u32 *MaskValue, u32 *IdValue);
s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler);
u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr);
s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth,
u8 TimeSegment2, u8 TimeSegment1);
void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth,
u8 *TimeSegment2, u8 *TimeSegment1);
s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr);
s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold);
u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr);
/*
* Diagnostic functions in xcanps_selftest.c
*/
s32 XCanPs_SelfTest(XCanPs *InstancePtr);
/*
* Functions in xcanps_intr.c
*/
void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask);
void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask);
u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr);
u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr);
void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask);
void XCanPs_IntrHandler(void *InstancePtr);
s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType,
void *CallBackFunc, void *CallBackRef);
/*
* Functions in xcanps_sinit.c
*/
XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

366
FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xcanps_hw.h Normal file
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@ -0,0 +1,366 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcanps_hw.h
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xcanps.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00a xd/sv 01/12/10 First release
* 1.01a sbs 12/27/11 Updated the Register/bit definitions
* Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
* Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
* Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
* Changed XCANPS_IXR_RXFLL_MASK to
* XCANPS_IXR_RXFWMFLL_MASK
* Changed
* XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
* XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
* XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
* XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
* 1.02a adk 08/08/13 Updated for inclding the function prototype
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XCANPS_HW_H /* prevent circular inclusions */
#define XCANPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the CAN. Each register is 32 bits.
* @{
*/
#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */
#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */
#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */
#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */
#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */
#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */
#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */
#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */
#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */
#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */
#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */
#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */
#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */
#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */
#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */
#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */
#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */
#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */
#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */
#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */
#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */
#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */
#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */
#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */
#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */
#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */
#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */
#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */
#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */
#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */
#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */
#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */
#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */
/* @} */
/** @name Software Reset Register (SRR) Bit Definitions and Masks
* @{
*/
#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */
#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */
/* @} */
/** @name Mode Select Register (MSR) Bit Definitions and Masks
* @{
*/
#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */
#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */
#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */
/* @} */
/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
* @{
*/
#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */
/* @} */
/** @name Bit Timing Register (BTR) Bit Definitions and Masks
* @{
*/
#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */
#define XCANPS_BTR_SJW_SHIFT 7U
#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */
#define XCANPS_BTR_TS2_SHIFT 4U
#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */
/* @} */
/** @name Error Counter Register (ECR) Bit Definitions and Masks
* @{
*/
#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */
#define XCANPS_ECR_REC_SHIFT 8U
#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */
/* @} */
/** @name Error Status Register (ESR) Bit Definitions and Masks
* @{
*/
#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */
#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */
#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */
#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */
#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */
/* @} */
/** @name Status Register (SR) Bit Definitions and Masks
* @{
*/
#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */
#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */
#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */
#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */
#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */
#define XCANPS_SR_ESTAT_SHIFT 7U
#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */
#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */
#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */
#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */
#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */
#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */
#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */
/* @} */
/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
* @{
*/
#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */
#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */
#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */
#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */
#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */
#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */
#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */
#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */
#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */
#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */
#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */
#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */
#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */
#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */
#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */
#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \
(u32)XCANPS_IXR_WKUP_MASK | \
(u32)XCANPS_IXR_SLP_MASK | \
(u32)XCANPS_IXR_BSOFF_MASK | \
(u32)XCANPS_IXR_ERROR_MASK | \
(u32)XCANPS_IXR_RXNEMP_MASK | \
(u32)XCANPS_IXR_RXOFLW_MASK | \
(u32)XCANPS_IXR_RXUFLW_MASK | \
(u32)XCANPS_IXR_RXOK_MASK | \
(u32)XCANPS_IXR_TXBFLL_MASK | \
(u32)XCANPS_IXR_TXFLL_MASK | \
(u32)XCANPS_IXR_TXOK_MASK | \
(u32)XCANPS_IXR_ARBLST_MASK)
/* @} */
/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
* @{
*/
#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */
/* @} */
/** @name CAN Watermark Register (WIR) Bit Definitions and Masks
* @{
*/
#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */
#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */
#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */
/* @} */
/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
Mask/Acceptance Filter ID)
* @{
*/
#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */
#define XCANPS_IDR_ID1_SHIFT 21U
#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */
#define XCANPS_IDR_SRR_SHIFT 20U
#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */
#define XCANPS_IDR_IDE_SHIFT 19U
#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */
#define XCANPS_IDR_ID2_SHIFT 1U
#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */
/* @} */
/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */
#define XCANPS_DLCR_DLC_SHIFT 28U
#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */
/* @} */
/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */
#define XCANPS_DW1R_DB0_SHIFT 24U
#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */
#define XCANPS_DW1R_DB1_SHIFT 16U
#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */
#define XCANPS_DW1R_DB2_SHIFT 8U
#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */
/* @} */
/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
* @{
*/
#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */
#define XCANPS_DW2R_DB4_SHIFT 24U
#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */
#define XCANPS_DW2R_DB5_SHIFT 16U
#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */
#define XCANPS_DW2R_DB6_SHIFT 8U
#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */
/* @} */
/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
* @{
*/
#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */
#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */
#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */
#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */
#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \
(u32)XCANPS_AFR_UAF3_MASK | \
(u32)XCANPS_AFR_UAF2_MASK | \
(u32)XCANPS_AFR_UAF1_MASK)
/* @} */
/** @name CAN frame length constants
* @{
*/
#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */
/* @} */
/* For backwards compatibilty */
#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET
#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET
#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET
#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET
#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET
#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XCanPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the CanPs interface
*/
void XCanPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa53.h
*
* dummy file
*
******************************************************************************/

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* The CSU_DMA is present inside CSU (Configuration Security Unit) module which
* is located within the Low-Power Subsystem (LPS) internal to the PS.
* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit
* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
* Stream Switch (SSS).
*
* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC
* (read) channel and DST (write) channel. The DMA is effectively able to
* transfer data:
* - From PS-side to the SSS-side (SRC DMA only)
* - From SSS-side to the PS-side (DST DMA only)
* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side
*
* <b>Initialization & Configuration</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the CSU_DMA core.
*
* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core.
* The user needs to first call the XCsuDma_LookupConfig() API which returns
* the Configuration structure pointer which is passed as a parameter to the
* XCsuDma_CfgInitialize() API.
*
* <b> Interrupts </b>
* This driver will not support handling of interrupts user should write handler
* to handle the interrupts.
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b> Building the driver </b>
*
* The XCsuDma driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* @file xcsudma.h
*
* This header file contains identifiers and register-level driver functions (or
* macros), range macros, structure typedefs that can be used to access the
* Xilinx CSU_DMA core instance.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_H_
#define XCSUDMA_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xcsudma_hw.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_cache.h"
/************************** Constant Definitions *****************************/
/** @name CSU_DMA Channels
* @{
*/
typedef enum {
XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */
XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */
}XCsuDma_Channel;
/*@}*/
/** @name CSU_DMA pause types
* @{
*/
typedef enum {
XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer
* to/from CSU_DMA */
XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer
* to/from CSU_DMA */
}XCsuDma_PauseType;
/*@}*/
/** @name Ranges of Size
* @{
*/
#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* This function resets the CSU_DMA core.
*
* @param None.
*
* @return None.
*
* @note None.
* C-style signature:
* void XCsuDma_Reset()
*
******************************************************************************/
#define XCsuDma_Reset() \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_SET_MASK)); \
Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \
(u32)(XCSUDMA_RESET_UNSET_MASK));
/*****************************************************************************/
/**
* This function will be in busy while loop until the data transfer is
* completed.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return None.
*
* @note This function should be called after XCsuDma_Transfer in polled
* mode to wait until the data gets transfered completely.
* C-style signature:
* void XCsuDma_WaitForDone(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_WaitForDone(InstancePtr,Channel) \
while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_I_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK))
/*****************************************************************************/
/**
*
* This function returns the number of completed SRC/DST DMA transfers that
* have not been acknowledged by software based on the channel selection.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count is number of completed DMA transfers but not acknowledged
* (Range is 0 to 7).
* - 000 - All finished transfers have been acknowledged.
* - Count - Count number of finished transfers are still
* outstanding.
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetDoneCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \
(u32)(XCSUDMA_STS_DONE_CNT_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current SRC/DST FIFO level in 32 bit words of the
* selected channel
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return FIFO level. (Range is 0 to 128)
* - 0 Indicates empty
* - Any number 1 to 128 indicates the number of entries in FIFO.
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \
(u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the current number of read(src)/write(dst) outstanding
* commands based on the type of channel selected.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Count of outstanding commands. (Range is 0 to 9).
*
* @note None.
* C-style signature:
* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr,
* XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \
(u32)(XCUSDMA_STS_OUTSTDG_SHIFT))
/*****************************************************************************/
/**
*
* This function returns the status of Channel either it is busy or not.
*
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
* @param Channel represents the type of channel either it is Source or
* Destination.
* Source channel - XCSUDMA_SRC_CHANNEL
* Destination Channel - XCSUDMA_DST_CHANNEL
*
* @return Returns the current status of the core.
* - TRUE represents core is currently busy.
* - FALSE represents core is not involved in any transfers.
*
* @note None.
* C-style signature:
* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
*
******************************************************************************/
#define XCsuDma_IsBusy(InstancePtr, Channel) \
((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \
((u32)(XCSUDMA_STS_OFFSET) + \
((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \
(u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \
(TRUE) : (FALSE)
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for a CSU_DMA core.
* Each CSU_DMA core should have a configuration structure associated.
*/
typedef struct {
u16 DeviceId; /**< DeviceId is the unique ID of the
* device */
u32 BaseAddress; /**< BaseAddress is the physical base address
* of the device's registers */
} XCsuDma_Config;
/******************************************************************************/
/**
*
* The XCsuDma driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XCsuDma_Config Config; /**< Hardware configuration */
u32 IsReady; /**< Device and the driver instance
* are initialized */
}XCsuDma;
/******************************************************************************/
/**
* This typedef contains all the configuration feilds which needs to be set
* before the start of the data transfer. All these feilds of CSU_DMA can be
* configured by using XCsuDma_SetConfig API.
*/
typedef struct {
u8 SssFifoThesh; /**< SSS FIFO threshold value */
u8 ApbErr; /**< ABP invalid access error */
u8 EndianType; /**< Type of endianess */
u8 AxiBurstType; /**< Type of AXI bus */
u32 TimeoutValue; /**< Time out value */
u8 FifoThresh; /**< FIFO threshold value */
u8 Acache; /**< AXI CACHE selection */
u8 RouteBit; /**< Selection of Route */
u8 TimeoutEn; /**< Enable of time out counters */
u16 TimeoutPre; /**< Pre scaler value */
u8 MaxOutCmds; /**< Maximum number of outstanding
* commands */
}XCsuDma_Configure;
/*****************************************************************************/
/************************** Function Prototypes ******************************/
XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId);
s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
u32 EffectiveAddr);
void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
UINTPTR Addr, u32 Size, u8 EnDataLast);
void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr,
u32 Size);
u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_PauseType Type);
u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr);
void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr);
void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
XCsuDma_Configure *ConfigurValues);
void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value);
u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr);
/* Interrupt related APIs */
u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
u32 Mask);
u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel);
s32 XCsuDma_SelfTest(XCsuDma *InstancePtr);
/******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcsudma_hw.h
*
* This header file contains identifiers and register-level driver functions (or
* macros) that can be used to access the Xilinx CSU_DMA core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ------------------------------------------------------
* 1.0 vnsld 22/10/14 First release
* </pre>
*
******************************************************************************/
#ifndef XCSUDMA_HW_H_
#define XCSUDMA_HW_H_ /**< Prevent circular inclusions
* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Registers offsets
* @{
*/
#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */
#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */
#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */
#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */
#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */
#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register
* Offset */
#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register
* Offset */
#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register
* Offset */
#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */
#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2
* Offset */
#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */
#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */
#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */
/*@}*/
/** @name CSU Base address and CSU_DMA reset offset
* @{
*/
#define XCSU_BASEADDRESS 0xFFCA0000
/**< CSU Base Address */
#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */
/*@}*/
/** @name CSU_DMA Reset register bit masks
* @{
*/
#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */
#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/
/*@}*/
/** @name Offset difference for Source and destination
* @{
*/
#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for
* source and
* destination channels */
/*@}*/
/** @name Address register bit masks
* @{
*/
#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */
#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check
* mask */
/*@}*/
/** @name Size register bit masks and shifts
* @{
*/
#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */
#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/
#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */
/*@}*/
/** @name Status register bit masks and shifts
* @{
*/
#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */
#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */
#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding
* read/write
* commands mask */
#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */
#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count
* done */
#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO
* level */
#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of
* outstanding
* read/write
* commands */
/*@}*/
/** @name Control register bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold
* value mask */
#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register
* access error
* mask */
#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */
#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type
* mask */
#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value
* mask */
#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold
* mask */
#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause
* mask */
#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause
* mask */
#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold
* shift */
#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */
#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */
#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type
* shift */
#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value
* shift */
#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh
* shift */
/*@}*/
/** @name CheckSum register bit masks
* @{
*/
#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset
* value of
* check sum */
/*@}*/
/** @name Interrupt Enable/Disable/Mask/Status registers bit masks
* @{
*/
#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow
* mask, it is valid
* only to Destination
* Channel */
#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access
* mask */
#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit
* indicator mask */
#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter
* expired to access
* memory mask */
#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter
* expired to access
* stream mask */
#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write
* error mask */
#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */
#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done
* mask, it is valid
* only for source
* channel*/
#define XCSUDMA_IXR_SRC_MASK 0x0000007FU
/**< ((XCSUDMA_IXR_INVALID_APB_MASK)|
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK) |
(XCSUDMA_IXR_MEM_DONE_MASK)) */
/**< All interrupt mask
* for source */
#define XCSUDMA_IXR_DST_MASK 0x000000FEU
/**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
(XCSUDMA_IXR_INVALID_APB_MASK) |
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) |
(XCSUDMA_IXR_TIMEOUT_MEM_MASK) |
(XCSUDMA_IXR_TIMEOUT_STRM_MASK) |
(XCSUDMA_IXR_AXI_WRERR_MASK) |
(XCSUDMA_IXR_DONE_MASK)) */
/**< All interrupt mask
* for destination */
/*@}*/
/** @name Control register 2 bit masks and shifts
* @{
*/
#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits
* mask */
#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */
#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */
#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters
* enable mask */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre
* mask */
#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands
* mask */
#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */
#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for
* AXI R/W CACHE */
#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */
#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout
* enable feild */
#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout
* pre feild */
/*@}*/
/** @name MSB Address register bit masks and shifts
* @{
*/
#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address
* mask */
#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of
* address */
/*@}*/
/***************** Macros (Inline Functions) Definitions *********************/
#define XCsuDma_In32 Xil_In32 /**< Input operation */
#define XCsuDma_Out32 Xil_Out32 /**< Output operation */
/*****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the Xilinx base address of the CSU_DMA core.
* @param RegOffset is the register offset of the register.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset)
*
******************************************************************************/
#define XCsuDma_ReadReg(BaseAddress, RegOffset) \
XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
/*****************************************************************************/
/**
*
* This macro writes the value into the given register.
*
* @param BaseAddress is the Xilinx base address of the CSU_DMA core.
* @param RegOffset is the register offset of the register.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \
XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

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#ifndef XDEBUG /* prevent circular inclusions */
#define XDEBUG /* by using protection macros */
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define xdbg_current_types (XDBG_DEBUG_GENERAL)
#define xdbg_stmnt(x) x
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_printf(...)
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#endif /* XDEBUG */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps.h
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
* For a full description of XEMACPS features, please see the hardware spec.
* This driver supports the following features:
* - Memory mapped access to host interface registers
* - Statistics counter registers for RMON/MIB
* - API for interrupt driven frame transfers for hardware configured DMA
* - Virtual memory support
* - Unicast, broadcast, and multicast receive address filtering
* - Full and half duplex operation
* - Automatic PAD & FCS insertion and stripping
* - Flow control
* - Support up to four 48bit addresses
* - Address checking for four specific 48bit addresses
* - VLAN frame support
* - Pause frame support
* - Large frame support up to 1536 bytes
* - Checksum offload
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XEmacPs. The driver handles transmission and reception
* of Ethernet frames, as well as configuration and control. No pre or post
* processing of frame data is performed. The driver does not validate the
* contents of an incoming frame in addition to what has already occurred in
* hardware.
* A single device driver can support multiple devices even when those devices
* have significantly different configurations.
*
* <b>Initialization & Configuration</b>
*
* The XEmacPs_Config structure is used by the driver to configure itself.
* This configuration structure is typically created by the tool-chain based
* on hardware build properties.
*
* The driver instance can be initialized in
*
* - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* The device supports DMA only as current development plan. No FIFO mode is
* supported. The driver expects to start the DMA channels and expects that
* the user has set up the buffer descriptor lists.
*
* <b>Interrupts and Asynchronous Callbacks</b>
*
* The driver has no dependencies on the interrupt controller. When an
* interrupt occurs, the handler will perform a small amount of
* housekeeping work, determine the source of the interrupt, and call the
* appropriate callback function. All callbacks are registered by the user
* level application.
*
* <b>Virtual Memory</b>
*
* All virtual to physical memory mappings must occur prior to accessing the
* driver API.
*
* For DMA transactions, user buffers supplied to the driver must be in terms
* of their physical address.
*
* <b>DMA</b>
*
* The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
* These BDs are typically chained together into a list the hardware follows
* when transferring data in and out of the packet buffers. Each BD describes
* a memory region containing either a full or partial Ethernet packet.
*
* Interrupt coalescing is not suppoted from this built-in DMA engine.
*
* This API requires the user to understand how the DMA operates. The
* following paragraphs provide some explanation, but the user is encouraged
* to read documentation in xemacps_bdring.h as well as study example code
* that accompanies this driver.
*
* The API is designed to get BDs to and from the DMA engine in the most
* efficient means possible. The first step is to establish a memory region
* to contain all BDs for a specific channel. This is done with
* XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
* follow as BDs are processed. The ring will consist of a user defined number
* of BDs which will all be partially initialized. For example on the transmit
* channel, the driver will initialize all BDs' so that they are configured
* for transmit. The more fields that can be permanently setup at
* initialization, then the fewer accesses will be needed to each BD while
* the DMA engine is in operation resulting in better throughput and CPU
* utilization. The best case initialization would require the user to set
* only a frame buffer address and length prior to submitting the BD to the
* engine.
*
* BDs move through the engine with the help of functions
* XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
* and XEmacPs_BdRingFree().
* All these functions handle BDs that are in place. That is, there are no
* copies of BDs kept anywhere and any BD the user interacts with is an actual
* BD from the same ring hardware accesses.
*
* BDs in the ring go through a series of states as follows:
* 1. Idle. The driver controls BDs in this state.
* 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
* reserve BD(s). Once allocated, the user may setup the BD(s) with
* frame buffer address, length, and other attributes. The user controls
* BDs in this state.
* 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
* in this state are either waiting to be processed by hardware, are in
* process, or have been processed. The DMA engine controls BDs in this
* state.
* 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
* user. Once retrieved, the user can examine each BD for the outcome of
* the DMA transfer. The user controls BDs in this state. After examining
* the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
* into state 1.
*
* Each of the four BD accessor functions operate on a set of BDs. A set is
* defined as a segment of the BD ring consisting of one or more BDs. The user
* views the set as a pointer to the first BD along with the number of BDs for
* that set. The set can be navigated by using macros XEmacPs_BdNext(). The
* user must exercise extreme caution when changing BDs in a set as there is
* nothing to prevent doing a mBdNext past the end of the set and modifying a
* BD out of bounds.
*
* XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
* XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
* tandem. The same BD set retrieved with BdRingAlloc should be the same one
* provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
* BdRIngFree.
*
* <b>Alignment & Data Cache Restrictions</b>
*
* Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
* aligned. Please reference xemacps_bd.h for cache related macros.
*
* DMA Tx:
*
* - If frame buffers exist in cached memory, then they must be flushed
* prior to committing them to hardware.
*
* DMA Rx:
*
* - If frame buffers exist in cached memory, then the cache must be
* invalidated for the memory region containing the frame prior to data
* access
*
* Both cache invalidate/flush are taken care of in driver code.
*
* <b>Buffer Copying</b>
*
* The driver is designed for a zero-copy buffer scheme. That is, the driver
* will not copy buffers. This avoids potential throughput bottlenecks within
* the driver. If byte copying is required, then the transfer will take longer
* to complete.
*
* <b>Checksum Offloading</b>
*
* The Embedded Processor Block Ethernet can be configured to perform IP, TCP
* and UDP checksum offloading in both receive and transmit directions.
*
* IP packets contain a 16-bit checksum field, which is the 16-bit 1s
* complement of the 1s complement sum of all 16-bit words in the header.
* TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
* 1s complement of the 1s complement sum of all 16-bit words in the header,
* the data and a conceptual pseudo header.
*
* To calculate these checksums in software requires each byte of the packet
* to be read. For TCP and UDP this can use a large amount of processing power.
* Offloading the checksum calculation to hardware can result in significant
* performance improvements.
*
* The transmit checksum offload is only available to use DMA in packet buffer
* mode. This is because the complete frame to be transmitted must be read
* into the packet buffer memory before the checksum can be calculated and
* written to the header at the beginning of the frame.
*
* For IP, TCP or UDP receive checksum offload to be useful, the operating
* system containing the protocol stack must be aware that this offload is
* available so that it can make use of the fact that the hardware has verified
* the checksum.
*
* When receive checksum offloading is enabled in the hardware, the IP header
* checksum is checked, where the packet meets the following criteria:
*
* 1. If present, the VLAN header must be four octets long and the CFI bit
* must not be set.
* 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
* encoding.
* 3. IP v4 packet.
* 4. IP header is of a valid length.
* 5. Good IP header checksum.
* 6. No IP fragmentation.
* 7. TCP or UDP packet.
*
* When an IP, TCP or UDP frame is received, the receive buffer descriptor
* gives an indication if the hardware was able to verify the checksums.
* There is also an indication if the frame had SNAP encapsulation. These
* indication bits will replace the type ID match indication bits when the
* receive checksum offload is enabled.
*
* If any of the checksums are verified incorrect by the hardware, the packet
* is discarded and the appropriate statistics counter incremented.
*
* <b>PHY Interfaces</b>
*
* RGMII 1.3 is the only interface supported.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on
* parameters. Asserts can be turned off on a system-wide basis by defining,
* at compile time, the NDEBUG identifier. By default, asserts are turned on
* and it is recommended that users leave asserts on during development. For
* deployment use -DNDEBUG compiler switch to remove assert code.
*
* @note
*
* Xilinx drivers are typically composed of two parts, one is the driver
* and the other is the adapter. The driver is independent of OS and processor
* and is intended to be highly portable. The adapter is OS-specific and
* facilitates communication between the driver and an OS.
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, or cache
* control must be satisfied bythe layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* Remove "used bit set" from TX error interrupt masks.
* </pre>
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemacps_hw.h"
#include "xemacps_bd.h"
#include "xemacps_bdring.h"
/************************** Constant Definitions ****************************/
/*
* Device information
*/
#define XEMACPS_DEVICE_NAME "xemacps"
#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
/** @name Configuration options
*
* Device configuration options. See the XEmacPs_SetOptions(),
* XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
* use options.
*
* The default state of the options are noted and are what the device and
* driver will be set to after calling XEmacPs_Reset() or
* XEmacPs_Initialize().
*
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001U
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002U
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004U
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received.
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400U
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800U
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
/** @name Callback identifiers
*
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1U
#define XEMACPS_HANDLER_DMARECV 2U
#define XEMACPS_HANDLER_ERROR 3U
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
* used to allow the driver to verify it can operate with the hardware.
*/
#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
/**************************** Type Definitions ******************************/
/** @name Typedefs for callback functions
*
* These callbacks are invoked in interrupt context.
* @{
*/
/**
* Callback invoked when frame(s) have been sent or received in interrupt
* driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
*
* @param CallBackRef is user data assigned when the callback was set.
*
* @note
* See xemacps_hw.h for bitmasks definitions and the device hardware spec for
* further information on their meaning.
*
*/
typedef void (*XEmacPs_Handler) (void *CallBackRef);
/**
* Callback when an asynchronous error occurs. To set this callback, invoke
* XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
* paramter.
*
* @param CallBackRef is user data assigned when the callback was set.
* @param Direction defines either receive or transmit error(s) has occurred.
* @param ErrorWord definition varies with Direction
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
/*@}*/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
} XEmacPs_Config;
/**
* The XEmacPs driver instance data. The user is required to allocate a
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
void *SendRef;
void *RecvRef;
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
u32 RxBufMask;
u32 MaxMtuSize;
u32 MaxFrameSize;
u32 MaxVlanFrameSize;
} XEmacPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Retrieve the Tx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return TxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
/****************************************************************************/
/**
* Retrieve the Rx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return RxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* This macro triggers trasmit circuit to send data currently in TX buffer(s).
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* @note
*
* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the receive channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the transmit channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
/*
* Initialization functions in xemacps.c
*/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
*/
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
/*
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xemacps_bd.h Normal file
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@ -0,0 +1,799 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bd.h
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
*
* The API exported by this header defines abstracted macros that allow the
* user to read/write specific BD fields.
*
* <b>Buffer Descriptors</b>
*
* A buffer descriptor (BD) defines a DMA transaction. The macros defined by
* this header file allow access to most fields within a BD to tailor a DMA
* transaction according to user and hardware requirements. See the hardware
* IP DMA spec for more information on BD fields and how they affect transfers.
*
* The XEmacPs_Bd structure defines a BD. The organization of this structure
* is driven mainly by the hardware for use in scatter-gather DMA transfers.
*
* <b>Performance</b>
*
* Limiting I/O to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
* and 64-bit changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
*
* </pre>
*
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <string.h>
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#else
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#endif
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
#define XEMACPS_BD_NUM_WORDS 2U
typedef UINTPTR XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Zero out BD fields
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nothing
*
* @note
* C-style signature:
* void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClear(BdPtr) \
memset((BdPtr), 0, sizeof(XEmacPs_Bd))
/****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
#endif
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note : Due to some bits are mixed within recevie BD's address field,
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
#endif
/*****************************************************************************/
/**
* Set the BD's Status field (word 1).
*
* @param BdPtr is the BD pointer to operate on
* @param Data is the value to write to BD's status field.
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
/*****************************************************************************/
/**
* Retrieve the BD's Packet DMA transfer status word (word 1).
*
* @param BdPtr is the BD pointer to operate on
*
* @return Status word
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
*
* Due to the BD bit layout differences in transmit and receive. User's
* caution is required.
*****************************************************************************/
#define XEmacPs_BdGetStatus(BdPtr) \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
/*****************************************************************************/
/**
* Get the address (bits 0..31) of the BD's buffer address (word 0)
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
#endif
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Retrieve the BD length field.
*
* For Tx channels, the returned value is the same as that written with
* XEmacPs_BdSetLength().
*
* For Rx channels, the returned value is the size of the received packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
#define XEmacPs_BdGetLength(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Retrieve the RX frame size.
*
* The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
* RxBufMask is dependent on whether jumbo is enabled or not.
*
*****************************************************************************/
#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
(InstancePtr)->RxBufMask)
/*****************************************************************************/
/**
* Test whether the given BD has been marked as the last BD of a packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Tell the DMA engine that the current packet does not end with the given
* BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the receive BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/*
* Must clear this bit to enable the MAC to write data to the receive
* buffer. Hardware sets this bit once it has successfully written a frame to
* memory. Once set, software has to clear the bit before the buffer can be
* used again. This macro clear the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearRxNew(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_NEW_MASK))
/*****************************************************************************/
/**
* Determine the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Software sets this bit to disable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro sets this bit of transmit BD to avoid
* confusion.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Determine the used bit of the transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to too many retries.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to data can not be
* feteched in time or buffers are exhausted.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to buffer is exhausted
* mid-frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit, no CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Clear this bit, CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Determine the broadcast bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the multicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the unicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame is a VLAN Tagged frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame has Type ID of 8100h and null VLAN
* identifier(Priority tag).
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame's Concatenation Format Indicator (CFI) of
* the frames VLANTCI field was set.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the End Of Frame (EOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the Start Of Frame (SOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bdring.h
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Type Definitions *******************************/
/** This is an internal structure used to maintain the DMA list */
typedef struct {
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
u32 AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
*
* The results of this macro can be provided to XEmacPs_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
*
******************************************************************************/
#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
(u32)((Bytes) / (sizeof(XEmacPs_Bd)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
* @param NumBd is the number of BDs to calculate memory size requirements for
*
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
*
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)(sizeof(XEmacPs_Bd) * (NumBd))
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XEmacPs_BdRingCreate().
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Return the next BD from BdPtr in a list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on.
*
* @return The next BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
(XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD from BdPtr in the list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on
*
* @return The previous BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macros */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.h
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
* High-level driver functions are defined in xemacps.h.
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release.
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
* Remove "used bit set" from TX error interrupt masks.
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
#ifdef __aarch64__
#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
on the local bus */
#else
#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
on the local bus */
#endif
#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
/** @name Direction identifiers
*
* These are used by several functions and callbacks that need
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_QBASE_OFFSET 0x000004C8U /**< MSB Buffer Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
(u32)XEMACPS_TXSR_URUN_MASK | \
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
(u32)XEMACPS_TXSR_RXOVR_MASK | \
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
(u32)XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
/*@}*/
/**
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
/*@}*/
/**
* @name interrupts bit definitions
* Bits definitions are same in XEMACPS_ISR_OFFSET,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req
transmitted */
#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted
*/
#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
(u32)XEMACPS_IXR_URUN_MASK)
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
(u32)XEMACPS_IXR_RXUSED_MASK | \
(u32)XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
/*
* @}
*/
/* Transmit buffer descriptor status words bit positions.
* Transmit buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit address pointing to the location of
* the transmit data.
* The following register - word1, consists of various information to control
* the XEmacPs transmit process. After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
/*
* @}
*/
/* Receive buffer descriptor status words bit positions.
* Receive buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit word aligned address pointing to the
* address of the buffer. The lower two bits make up the wrap bit indicating
* the last descriptor and the ownership bit to indicate it has been used by
* the XEmacPs.
* The following register - word1, contains status information regarding why
* the frame was received (the filter match condition) as well as other
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to memory mapped I/O or other
* interface if necessary.
*/
#define XEmacPs_In32 Xil_In32
#define XEmacPs_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the emacps interface
*/
void XEmacPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implemention MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */

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/* ### HEADER ### */
#ifndef __XFPD_SLCR_H__
#define __XFPD_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcr Base Address
*/
#define XFPD_SLCR_BASEADDR 0xFD610000UL
/**
* Register: XfpdSlcrWprot0
*/
#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
/**
* Register: XfpdSlcrCtrl
*/
#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIsr
*/
#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrImr
*/
#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrIer
*/
#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIdr
*/
#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrItr
*/
#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrWdtClkSel
*/
#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrIntFpd
*/
#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL
#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL
/**
* Register: XfpdSlcrGpu
*/
#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL
#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL
#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL
#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL
#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL
#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL
#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL
#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL
#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL
#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL
#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL
#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL
#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL
#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL
#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL
/**
* Register: XfpdSlcrGdmaCfg
*/
#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL
#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL
#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL
/**
* Register: XfpdSlcrGdma
*/
#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL
#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL
#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL
#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL
#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL
#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL
#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL
#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL
/**
* Register: XfpdSlcrAfiFs
*/
#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL
#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
/**
* Register: XfpdSlcrErrAtbIsr
*/
#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbImr
*/
#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrErrAtbIer
*/
#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrErrAtbIdr
*/
#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbCmdstore
*/
#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbRespEn
*/
#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL
/**
* Register: XfpdSlcrAtbResptype
*/
#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrAtbPrescale
*/
#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL
#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL
#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL
#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL
#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL
#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_H__ */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xfpd_slcr_secure.h Normal file
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/* ### HEADER ### */
#ifndef __XFPD_SLCR_SECURE_H__
#define __XFPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdSlcrSecure Base Address
*/
#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
/**
* Register: XfpdSlcrSecCtrl
*/
#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIsr
*/
#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecImr
*/
#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecIer
*/
#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecIdr
*/
#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecItr
*/
#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecSata
*/
#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL
#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL
/**
* Register: XfpdSlcrSecPcie
*/
#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecDpdma
*/
#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL
#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL
#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL
/**
* Register: XfpdSlcrSecGdma
*/
#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL
#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL
#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL
#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL
/**
* Register: XfpdSlcrSecGic
*/
#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL
#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_SLCR_SECURE_H__ */

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/* ### HEADER ### */
#ifndef __XFPD_XMPU_SINK_H__
#define __XFPD_XMPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XfpdXmpuSink Base Address
*/
#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
/**
* Register: XfpdXmpuSinkErrSts
*/
#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIsr
*/
#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkImr
*/
#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XfpdXmpuSinkIer
*/
#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XfpdXmpuSinkIdr
*/
#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XFPD_XMPU_SINK_H__ */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.h
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
*
* The GPIO Controller supports the following features:
* - 4 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
* This driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the GPIO.
*
* <b>Interrupts</b>
*
* The driver provides interrupt management functions and an interrupt handler.
* Users of this driver need to provide callback functions. An interrupt handler
* example is available with the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XGpioPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xgpiops_hw.h"
/************************** Constant Definitions *****************************/
/** @name Interrupt types
* @{
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/*@}*/
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#define XGPIOPS_MAX_BANKS 0x06U /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)174 /*< Max pins in the ZynqMP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#else
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /*< Max pins in the GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
#endif
/**************************** Type Definitions *******************************/
/****************************************************************************/
/**
* This handler data type allows the user to define a callback function to
* handle the interrupts for the GPIO device. The application using this
* driver is expected to define a handler of this type, to support interrupt
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XGpioPs_Config;
/**
* The XGpioPs driver instance data. The user is required to allocate a
* variable of this type for the GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
} XGpioPs;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Functions in xgpiops.c
*/
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
/*
* Bank APIs in xgpiops.c
*/
u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
/*
* Pin APIs in xgpiops.c
*/
u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
/*
* Diagnostic functions in xgpiops_selftest.c
*/
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/*
* Functions in xgpiops_intr.c
*/
/*
* Bank APIs in xgpiops_intr.c
*/
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
/*
* Pin APIs in xgpiops_intr.c
*/
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
/*
* Functions in xgpiops_sinit.c
*/
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
/* @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
/* @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
/** @name Interrupt type reset values for each bank
* @{
*/
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_INTTYPE_BANK0_RESET 0x3FFFFFFFU
#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFFU
#define XGPIOPS_INTTYPE_BANK2_RESET 0x3FFFFFFFU
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
#else
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFFU
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU
#endif
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps.h
*
* This is an implementation of IIC driver in the PS block. The device can
* be either a master or a slave on the IIC bus. This implementation supports
* both interrupt mode transfer and polled mode transfer. Only 7-bit address
* is used in the driver, although the hardware also supports 10-bit address.
*
* IIC is a 2-wire serial interface. The master controls the clock, so it can
* regulate when it wants to send or receive data. The slave is under control of
* the master, it must respond quickly since it has no control of the clock and
* must send/receive data as fast or as slow as the master does.
*
* The higher level software must implement a higher layer protocol to inform
* the slave what to send to the master.
*
* <b>Initialization & Configuration</b>
*
* The XIicPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
*
* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
* the static configuration structure defined in xiicps_g.c. This is
* setup by the tools. For some operating systems the config structure
* will be initialized by the software and this call is not needed.
*
* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base
* address replaces the physical address in the configuration
* structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, bus arbitration is defined in the IIC
* standard. Lost of arbitration causes arbitration loss interrupt on the device.
*
* <b>Multiple Slaves</b>
*
* Multiple slaves are supported by selecting them with unique addresses. It is
* up to the system designer to be sure all devices on the IIC bus have
* unique addresses.
*
* <b>Addressing</b>
*
* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
* ability to control which address size is sent in messages as a master to a
* slave device.
*
* <b>FIFO Size </b>
* The hardware FIFO is 32 bytes deep. The user must know the limitations of
* other IIC devices on the bus. Some are only able to receive a limited number
* of bytes in a single transfer.
*
* <b>Data Rates</b>
*
* The data rate is set by values in the control register. The formula for
* determining the correct register values is:
* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
*
* When the device is configured as a slave, the slck setting controls the
* sample rate and so must be set to be at least as fast as the fastest scl
* expected to be seen in the system.
*
* <b>Polled Mode Operation</b>
*
* This driver supports polled mode transfers.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XIicPs_InterruptHandler to an interrupt system such that it will be called
* when an interrupt occurs. This function does not save and restore the
* processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Transfer complete
* - More Data
* - Transfer not Acknowledged
* - Transfer Time out
* - Monitored slave ready - master mode only
* - Receive Overflow
* - Transmit FIFO overflow
* - Receive FIFO underflow
* - Arbitration lost
*
* <b>Bus Busy</b>
*
* Bus busy is checked before the setup of a master mode device, to avoid
* unnecessary arbitration loss interrupt.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied by
* the layer above this driver.
*
*<b>Repeated Start</b>
*
* The I2C controller does not indicate completion of a receive transfer if HOLD
* bit is set. Due to this errata, repeated start cannot be used if a receive
* transfer is followed by any other transfer.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/08 First release
* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
* XIicPs_ClearOptions where the InstancePtr->Options
* was not updated correctly.
* Updated the InstancePtr->Options in the
* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
* Updated the XIicPs_SetupMaster to not check for
* Bus Busy condition when the Hold Bit is set.
* Removed some unused variables.
* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
* check for transfer completion is added, which indicates
* the completion of current transfer.
* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
* to achieve I2C clock with minimum error for
* CR #674195
* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
* This is fix for CR#704398 to remove warning.
* 2.0 hk 03/07/14 Added check for error status in the while loop that
* checks for completion.
* (XIicPs_MasterSendPolled function). CR# 762244, 764875.
* Limited frequency set when 100KHz or 400KHz is
* selected. This is a hardware limitation. CR#779290.
* 2.1 hk 04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
* Explicitly reset CR and clear FIFO in Abort function
* and state the same in the comments. CR# 784254.
* Fix for CR# 761060 - provision for repeated start.
* 2.2 hk 08/23/14 Slave monitor mode changes - clear FIFO, enable
* read mode and clear transfer size register.
* Disable NACK to avoid interrupts on each retry.
* 2.3 sk 10/07/14 Repeated start feature deleted.
* 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
* in XIicPs_Reset.
* 12/06/14 Implemented Repeated start feature.
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* 02/18/15 Implemented larger data transfer using repeated start
* in Zynq UltraScale MP.
*
* </pre>
*
******************************************************************************/
#ifndef XIICPS_H /* prevent circular inclusions */
#define XIICPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xiicps_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options may be specified or retrieved for the device and
* enable/disable additional features of the IIC. Each of the options
* are bit fields, so more than one may be specified.
*
* @{
*/
#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to an application
* event handler from the driver. These constants are bit masks such that
* more than one event can be passed to the handler.
*
* @{
*/
#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/
#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/
#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */
#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */
#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */
#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */
#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */
#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */
#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */
#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */
/*@}*/
/** @name Role constants
*
* These constants are used to pass into the device setup routines to
* set up the device according to transfer direction.
*/
#define SENDING_ROLE 1 /**< Transfer direction is sending */
#define RECVING_ROLE 0 /**< Transfer direction is receiving */
/* Maximum transfer size */
#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U)
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so amount of processing should be minimized.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent indicates one or more status events that occurred.
*/
typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
} XIicPs_Config;
/**
* The XIicPs driver instance data. The user is required to allocate a
* variable of this type for each IIC device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIicPs_Config Config; /* Configuration structure */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Options set in the device */
u8 *SendBufferPtr; /* Pointer to send buffer */
u8 *RecvBufferPtr; /* Pointer to recv buffer */
s32 SendByteCount; /* Number of bytes still expected to send */
s32 RecvByteCount; /* Number of bytes still expected to receive */
s32 CurrByteCount; /* No. of bytes expected in current transfer */
s32 UpdateTxSize; /* If tx size register has to be updated */
s32 IsSend; /* Whether master is sending or receiving */
s32 IsRepeatedStart; /* Indicates if user set repeated start */
XIicPs_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */
} XIicPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Place one byte into the transmit FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_SendByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_SendByte(InstancePtr) \
{ \
u8 Data; \
Data = *((InstancePtr)->SendBufferPtr); \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ (u32)(XIICPS_DATA_OFFSET), \
(u32)(Data)); \
(InstancePtr)->SendBufferPtr += 1; \
(InstancePtr)->SendByteCount -= 1;\
}
/****************************************************************************/
/*
*
* Receive one byte from FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_RecvByte(InstancePtr) \
{ \
u8 *Data, Value; \
Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ (u32)XIICPS_DATA_OFFSET)); \
Data = &Value; \
*(InstancePtr)->RecvBufferPtr = *Data; \
(InstancePtr)->RecvBufferPtr += 1; \
(InstancePtr)->RecvByteCount --; \
}
/************************** Function Prototypes ******************************/
/*
* Function for configuration lookup, in xiicps_sinit.c
*/
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
/*
* Functions for general setup, in xiicps.c
*/
s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
u32 EffectiveAddr);
void XIicPs_Abort(XIicPs *InstancePtr);
void XIicPs_Reset(XIicPs *InstancePtr);
s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
s32 TransmitFifoFill(XIicPs *InstancePtr);
/*
* Functions for interrupts, in xiicps_intr.c
*/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FunctionPtr);
/*
* Functions for device as master, in xiicps_master.c
*/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
u16 SlaveAddr);
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for device as slave, in xiicps_slave.c
*/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for selftest, in xiicps_selftest.c
*/
s32 XIicPs_SelfTest(XIicPs *InstancePtr);
/*
* Functions for setting and getting data rate, in xiicps_options.c
*/
s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
u32 XIicPs_GetOptions(XIicPs *InstancePtr);
s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
u32 XIicPs_GetSClk(XIicPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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@ -0,0 +1,380 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_hw.h
*
* This header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
* the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.04a kpc 11/07/13 Added function prototype.
* 3.0 sk 11/03/14 Modified the TimeOut Register value to 0xFF
* 01/31/15 Modified the code according to MISRAC 2012 Compliant.
* </pre>
*
******************************************************************************/
#ifndef XIICPS_HW_H /* prevent circular inclusions */
#define XIICPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the IIC.
* @{
*/
#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */
#define XIICPS_SR_OFFSET 0x04U /**< Status */
#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */
#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */
#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */
#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */
#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */
#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */
#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */
#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */
#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */
/* @} */
/** @name Control Register
*
* This register contains various control bits that
* affects the operation of the IIC controller. Read/Write.
* @{
*/
#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */
#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */
#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */
#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */
#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/
#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */
#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl,
0=terminate transfer */
#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when
Master receiver*/
#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit,
0=10 bit */
#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master,
0=Slave */
#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master
transfer 0=Transmitter,
1=Receiver*/
#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control
register */
/* @} */
/** @name IIC Status Register
*
* This register is used to indicate status of the IIC controller. Read only
* @{
*/
#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */
#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */
#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */
#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */
#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */
/* @} */
/** @name IIC Address Register
*
* Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
* A write access to this register always initiates a transfer if the IIC is in
* master mode. Read/Write
* @{
*/
#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
/* @} */
/** @name IIC Data Register
*
* When written to, the data register sets data to transmit. When read from, the
* data register reads the last received byte of data. Read/Write
* @{
*/
#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
/* @} */
/** @name IIC Interrupt Registers
*
* <b>IIC Interrupt Status Register</b>
*
* This register holds the interrupt status flags for the IIC controller. Some
* of the flags are level triggered
* - i.e. are set as long as the interrupt condition exists. Other flags are
* edge triggered, which means they are set one the interrupt condition occurs
* then remain set until they are cleared by software.
* The interrupts are cleared by writing a one to the interrupt bit position
* in the Interrupt Status Register. Read/Write.
*
* <b>IIC Interrupt Enable Register</b>
*
* This register is used to enable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Disable Register </b>
*
* This register is used to disable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Mask Register</b>
*
* This register shows the enabled/disabled status of each IIC controller
* interrupt source. A bit set to 1 will ignore the corresponding interrupt in
* the status register. A bit set to 0 means the interrupt is enabled.
* All mask bits are set and all interrupts are disabled after reset. Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Interrupt Status Register
* @{
*/
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt
mask */
#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow
Interrupt mask */
#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow
Interrupt mask */
#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt
mask */
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready
Interrupt mask */
#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out
Interrupt mask */
#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */
#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */
#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete
Interrupt mask */
#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */
/* @} */
/** @name IIC Transfer Size Register
*
* The register's meaning varies according to the operating mode as follows:
* - Master transmitter mode: number of data bytes still not transmitted minus
* one
* - Master receiver mode: number of data bytes that are still expected to be
* received
* - Slave transmitter mode: number of bytes remaining in the FIFO after the
* master terminates the transfer
* - Slave receiver mode: number of valid data bytes in the FIFO
*
* This register is cleared if CLR_FIFO bit in the control register is set.
* Read/Write
* @{
*/
#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
/* @} */
/** @name IIC Slave Monitor Pause Register
*
* This register is associated with the slave monitor mode of the I2C interface.
* It is meaningful only when the module is in master mode and bit SLVMON in the
* control register is set.
*
* This register defines the pause interval between consecutive attempts to
* address the slave once a write to an I2C address register is done by the
* host. It represents the number of sclk cycles minus one between two attempts.
*
* The reset value of the register is 0, which results in the master repeatedly
* trying to access the slave immediately after unsuccessful attempt.
* Read/Write
* @{
*/
#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
/* @} */
/** @name IIC Time Out Register
*
* The value of time out register represents the time out interval in number of
* sclk cycles minus one.
*
* When the accessed slave holds the sclk line low for longer than the time out
* period, thus prohibiting the I2C interface in master mode to complete the
* current transfer, an interrupt is generated and TO interrupt flag is set.
*
* The reset value of the register is 0x1f.
* Read/Write
* @{
*/
#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XIicPs_In32 Xil_In32
#define XIicPs_Out32 Xil_Out32
/****************************************************************************/
/**
* Read an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XIicPs_ReadReg(BaseAddress, RegOffset) \
XIicPs_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/
/**
* Write an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
*
******************************************************************************/
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/***************************************************************************/
/**
* Read the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @return Current bit mask that represents currently enabled interrupts.
*
* @note C-Style signature:
* u32 XIicPs_ReadIER(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_ReadIER(BaseAddress) \
XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
/***************************************************************************/
/**
* Write to the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be enabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
/***************************************************************************/
/**
* Disable all interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_DisableAllInterrupts(BaseAddress) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
XIICPS_IXR_ALL_INTR_MASK)
/***************************************************************************/
/**
* Disable selected interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be disabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
(IntrMask))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the I2c interface
*/
void XIicPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* This file contains assert related functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern void Xil_Assert(const char8 *File, s32 Line);
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param Expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
* so that asserts which fail allow execution to continue.
*
* @param Expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* Contains required functions for the ARM cache functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
void Xil_DCacheInvalidateLine(INTPTR adr);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_DCacheFlushLine(INTPTR adr);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
void Xil_ICacheInvalidateLine(INTPTR adr);
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains ARM Cortex A53 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions ****************************/
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
#define XIL_EXCEPTION_ID_SYNC_INT 1U
#define XIL_EXCEPTION_ID_IRQ_INT 2U
#define XIL_EXCEPTION_ID_FIQ_INT 3U
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
#define XIL_EXCEPTION_ID_LAST 5U
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
/**************************** Type Definitions ******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *data);
typedef void (*Xil_InterruptHandler)(void *data);
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Enable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 0, exception is enabled.
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
/****************************************************************************/
/**
* Enable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
/****************************************************************************/
/**
* Disable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 1, exception is disabled.
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
/****************************************************************************/
/**
* Disable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_ExceptionInit(void);
void Xil_SyncAbortHandler(void *CallBackRef);
void Xil_SErrorAbortHandler(void *CallBackRef);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_EXCEPTION_H */

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#endif

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* This file contains the interface for the general IO component, which
* encapsulates the Input/Output functions for processors that do not
* require any special I/O handling.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "xil_printf.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
/*****************************************************************************/
/**
*
* Perform an big-endian input operation for a 16-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
* @note None.
*
******************************************************************************/
#define Xil_In16LE(Addr) Xil_In16((Addr))
/*****************************************************************************/
/**
*
* Perform a big-endian input operation for a 32-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
*
* @note None.
*
******************************************************************************/
#define Xil_In32LE(Addr) Xil_In32((Addr))
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 16-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 32-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
/*****************************************************************************/
/**
*
* Convert a 32-bit number from host byte order to network byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
/*****************************************************************************/
/**
*
* Convert a 16-bit number from host byte order to network byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htons(Data) Xil_EndianSwap16((Data))
/*****************************************************************************/
/**
*
* Convert a 32-bit number from network byte order to host byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
/*****************************************************************************/
/**
*
* Convert a 16-bit number from network byte order to host byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which may use memory mapped I/O or I/O which is mapped into a
* seperate address space.
*/
u8 Xil_In8(INTPTR Addr);
u16 Xil_In16(INTPTR Addr);
u32 Xil_In32(INTPTR Addr);
u64 Xil_In64(INTPTR Addr);
void Xil_Out8(INTPTR Addr, u8 Value);
void Xil_Out16(INTPTR Addr, u16 Value);
void Xil_Out32(INTPTR Addr, u32 Value);
void Xil_Out64(INTPTR Addr, u64 Value);
u16 Xil_In16BE(INTPTR Addr);
u32 Xil_In32BE(INTPTR Addr);
void Xil_Out16BE(INTPTR Addr, u16 Value);
void Xil_Out32BE(INTPTR Addr, u32 Value);
u16 Xil_EndianSwap16(u16 Data);
u32 Xil_EndianSwap32(u32 Data);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

1052
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79
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.h
*
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_MMU_H
#define XIL_MMU_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_MMU_H */

44
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#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
void xil_printf( const char8 *ctrl1, ...);
void print( const char8 *ptr);
extern void outbyte (char8 c);
extern char8 inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

63
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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* This file contains utility functions to test cache.
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern s32 Xil_TestDCacheRange(void);
extern s32 Xil_TestDCacheAll(void);
extern s32 Xil_TestICacheRange(void);
extern s32 Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

91
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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmemend.h
*
* This file contains utility functions to teach endian related memory
* IO functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

162
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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
*
* This file contains utility functions to test memory.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XIL_TESTMEM_ALLMEMTESTS:
* Runs all of the following tests
*
* XIL_TESTMEM_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
* incrementing value as the test value for memory.
*
* XIL_TESTMEM_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XIL_TESTMEM_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XIL_TESTMEM_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XIL_TESTMEM_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1U
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
#define XIL_TESTMEM_INCREMENT 0x01U
#define XIL_TESTMEM_WALKONES 0x02U
#define XIL_TESTMEM_WALKZEROS 0x03U
#define XIL_TESTMEM_INVERSEADDR 0x04U
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* This file contains basic types for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
* Define LONG and ULONG datatypes and mask values
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#include <stdint.h>
#include <stddef.h>
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/**
* guarded against xbasic_types.h.
*/
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/**
* xbasic_types.h does not typedef s* or u64
*/
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
typedef intptr_t INTPTR;
typedef uintptr_t UINTPTR;
typedef ptrdiff_t PTRDIFF;
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#else
#include <linux/types.h>
#endif
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
/*@}*/
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#endif /* end of protection macro */

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/* ### HEADER ### */
#ifndef __XIOU_SECURE_SLCR_H__
#define __XIOU_SECURE_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XiouSecureSlcr Base Address
*/
#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL
/**
* Register: XiouSecSlcrAxiWprtcn
*/
#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrAxiRprtcn
*/
#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrCtrl
*/
#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIsr
*/
#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrImr
*/
#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XiouSecSlcrIer
*/
#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrIdr
*/
#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XiouSecSlcrItr
*/
#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XIOU_SECURE_SLCR_H__ */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xipipsu.h
*
* This is the header file for implementation of IPIPSU driver.
* Inter Processor Interrupt (IPI) is used for communication between
* different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
* and Observation registers for communication between processors. Each IPI path
* has a 32 byte buffer associated with it and these buffers are located in the
* XPPU RAM. This driver supports the following operations:
*
* - Trigger IPIs to CPUs on the SoC
* - Write and Read Message buffers
* - Read the status of Observation Register to get status of Triggered IPI
* - Enable/Disable IPIs from selected Masters
* - Read the Status register to get the source of an incoming IPI
*
* <b>Initialization</b>
* The config data for the driver is loaded and is based on the HW build. The
* XIpiPsu_Config data structure contains all the data related to the
* IPI driver instance and also teh available Target CPUs.
*
* <b>Sending an IPI</b>
* The following steps can be followed to send an IPI:
* - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
* - Trigger IPI using XIpiPsu_TriggerIpi()
* - Wait for Ack using XIpiPsu_PollForAck()
* - Read response using XIpiPsu_ReadMessage()
*
* @note XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
* previous IPI was serviced by the target
*
* <b>Receiving an IPI</b>
* To receive an IPI, the following sequence can be followed:
* - Register an interrupt handler for the IPIs interrupt ID
* - Enable the required sources using XIpiPsu_InterruptEnable()
* - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
* - Read the message form source using XIpiPsu_ReadMessage()
* - Write the response using XIpiPsu_WriteMessage()
* - Ack the IPI using XIpiPsu_ClearInterruptStatus()
*
* @note XIpiPsu_Reset can be used at startup to clear the status and
* disable all sources
*
*/
/*****************************************************************************/
#ifndef XIPIPSU_H_
#define XIPIPSU_H_
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xstatus.h"
#include "xipipsu_hw.h"
/************************** Constant Definitions *****************************/
#define XIPIPSU_BUF_TYPE_MSG (0x00000001U)
#define XIPIPSU_BUF_TYPE_RESP (0x00000002U)
#define XIPIPSU_MAX_MSG_LEN XIPIPSU_MSG_BUF_SIZE
/**************************** Type Definitions *******************************/
/**
* Data structure used to refer IPI Targets
*/
typedef struct {
u32 Mask; /**< Bit Mask for the target */
u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
} XIpiPsu_Target;
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u32 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 BitMask; /**< BitMask to be used to identify this CPU */
u32 BufferIndex; /**< Index of the IPI Message Buffer */
u32 IntId; /**< Interrupt ID on GIC **/
u32 TargetCount; /**< Number of available IPI Targets */
XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
} XIpiPsu_Config;
/**
* The XIpiPsu driver instance data. The user is required to allocate a
* variable of this type for each IPI device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIpiPsu_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Options; /**< Options set in the device */
} XIpiPsu;
/***************** Macros (Inline Functions) Definitions *********************/
/**
*
* Read the register specified by the base address and offset
*
* @param BaseAddress is the base address of the IPI instance
* @param RegOffset is the offset of the register relative to base
*
* @return Value of the specified register
* @note
* C-style signature
* u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/****************************************************************************/
/**
*
* Write a value into a register specified by base address and offset
*
* @param BaseAddress is the base address of the IPI instance
* @param RegOffset is the offset of the register relative to base
* @param Data is a 32-bit value that is to be written into the specified register
*
* @note
* C-style signature
* void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values of individual CPU masks
*
* @note
* C-style signature
* void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_IER_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be disabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values of individual CPU masks
*
* @note
* C-style signature
* void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_InterruptDisable(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_IDR_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Get the <i>STATUS REGISTER</i> of the current IPI instance.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @return Returns the Interrupt Status register(ISR) contents
* @note User needs to parse this 32-bit value to check the source CPU
* C-style signature
* u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
*
*****************************************************************************/
#define XIpiPsu_GetInterruptStatus(InstancePtr) \
XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_ISR_OFFSET)
/****************************************************************************/
/**
*
* Clear the <i>STATUS REGISTER</i> of the current IPI instance.
* The corresponding interrupt status for
* each bit set to 1 in <i>Mask</i>, will be cleared
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask corresponding to the source CPU*
*
* @note This function should be used after handling the IPI.
* Clearing the status will automatically clear the corresponding bit in
* OBSERVATION register of Source CPU
* C-style signature
* void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask) \
XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_ISR_OFFSET, \
((Mask) & XIPIPSU_ALL_MASK));
/****************************************************************************/
/**
*
* Get the <i>OBSERVATION REGISTER</i> of the current IPI instance.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @return Returns the Observation register(OBS) contents
* @note User needs to parse this 32-bit value to check the status of
* individual CPUs
* C-style signature
* u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
*
*****************************************************************************/
#define XIpiPsu_GetObsStatus(InstancePtr) \
XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
XIPIPSU_OBS_OFFSET)
/****************************************************************************/
/************************** Function Prototypes *****************************/
/* Static lookup function implemented in xipipsu_sinit.c */
XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
/* Interface Functions implemented in xipipsu.c */
XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
UINTPTR EffectiveAddress);
void XIpiPsu_Reset(XIpiPsu *InstancePtr);
XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
u32 TimeOutCount);
XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufType);
XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
u32 MsgLength, u8 BufType);
#endif /* XIPIPSU_H_ */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/**
*
* @file xipipsu_hw.h
*
* This file contains macro definitions for low level HW related params
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 mjr 03/15/15 First release
*
* </pre>
*
******************************************************************************/
#ifndef XIPIPSU_HW_H_ /* prevent circular inclusions */
#define XIPIPSU_HW_H_ /* by using protection macros */
/************************** Constant Definitions *****************************/
/* Message RAM related params */
#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
#define XIPIPSU_MSG_BUF_SIZE 8U /* Size in Words */
#define XIPIPSU_MAX_BUFF_INDEX 7
/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
#define XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U)
#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U)
/* Max Number of IPI slots on the device */
#define XIPIPSU_MAX_TARGETS 11
/* Register Offsets for each member of IPI Register Set */
#define XIPIPSU_TRIG_OFFSET 0x00U
#define XIPIPSU_OBS_OFFSET 0x04U
#define XIPIPSU_ISR_OFFSET 0x10U
#define XIPIPSU_IMR_OFFSET 0x14U
#define XIPIPSU_IER_OFFSET 0x18U
#define XIPIPSU_IDR_OFFSET 0x1CU
/* MASK of all valid IPI bits in above registers */
#define XIPIPSU_ALL_MASK 0x0F0F0301U
#endif /* XIPIPSU_HW_H_ */

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/* ### HEADER ### */
#ifndef __XLPD_SLCR_SECURE_H__
#define __XLPD_SLCR_SECURE_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdSlcrSecure Base Address
*/
#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL
/**
* Register: XlpdSlcrSecCtrl
*/
#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIsr
*/
#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecImr
*/
#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
/**
* Register: XlpdSlcrSecIer
*/
#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecIdr
*/
#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecItr
*/
#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecRpu
*/
#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecAdma
*/
#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL
#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL
#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL
#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecSafetyChk
*/
#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSecUsb
*/
#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_SLCR_SECURE_H__ */

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/* ### HEADER ### */
#ifndef __XLPD_XPPU_H__
#define __XLPD_XPPU_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdXppu Base Address
*/
#define XLPD_XPPU_BASEADDR 0xFF980000UL
/**
* Register: XlpdXppuCtrl
*/
#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL
#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL
#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL
#define XLPD_XPPU_CTRL_EN_SHIFT 0UL
#define XLPD_XPPU_CTRL_EN_WIDTH 1UL
#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL
#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL
/**
* Register: XlpdXppuErrSts1
*/
#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL
/**
* Register: XlpdXppuErrSts2
*/
#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL
#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL
#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL
/**
* Register: XlpdXppuPoison
*/
#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL
#define XLPD_XPPU_POISON_BASE_SHIFT 0UL
#define XLPD_XPPU_POISON_BASE_WIDTH 20UL
#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL
#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL
/**
* Register: XlpdXppuIsr
*/
#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL
#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL
#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL
#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL
#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuImr
*/
#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL
#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL
#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL
/**
* Register: XlpdXppuIen
*/
#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL
#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuIds
*/
#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL
#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL
#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL
#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL
#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL
#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL
#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL
#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL
#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL
#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL
#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL
#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL
#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL
#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL
#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL
#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL
#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL
#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL
#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL
#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL
/**
* Register: XlpdXppuMMstrIds
*/
#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL
#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL
#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL
#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL
/**
* Register: XlpdXppuMAperture32b
*/
#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL
#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL
/**
* Register: XlpdXppuMAperture64kb
*/
#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL
/**
* Register: XlpdXppuMAperture1mb
*/
#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL
/**
* Register: XlpdXppuMAperture512mb
*/
#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL
#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL
#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL
/**
* Register: XlpdXppuBase32b
*/
#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL
#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL
/**
* Register: XlpdXppuBase64kb
*/
#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL
#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL
/**
* Register: XlpdXppuBase1mb
*/
#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL
#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL
/**
* Register: XlpdXppuBase512mb
*/
#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL
#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL
#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL
#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL
#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL
/**
* Register: XlpdXppuMstrId00
*/
#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL
#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL
#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL
/**
* Register: XlpdXppuMstrId01
*/
#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL
#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL
#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId02
*/
#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL
#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL
#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL
/**
* Register: XlpdXppuMstrId03
*/
#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL
#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL
#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL
/**
* Register: XlpdXppuMstrId04
*/
#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL
#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL
/**
* Register: XlpdXppuMstrId05
*/
#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL
#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL
/**
* Register: XlpdXppuMstrId06
*/
#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL
#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL
/**
* Register: XlpdXppuMstrId07
*/
#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL
#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL
#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL
#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL
/**
* Register: XlpdXppuMstrId08
*/
#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId09
*/
#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId10
*/
#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId11
*/
#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId12
*/
#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId13
*/
#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId14
*/
#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId15
*/
#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId16
*/
#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId17
*/
#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId18
*/
#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL
/**
* Register: XlpdXppuMstrId19
*/
#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL
#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL
#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL
#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL
#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL
#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL
#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL
#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL
#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL
#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL
#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL
#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL
#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_XPPU_H__ */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xlpd_xppu_sink.h Normal file
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/* ### HEADER ### */
#ifndef __XLPD_XPPU_SINK_H__
#define __XLPD_XPPU_SINK_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
* XlpdXppuSink Base Address
*/
#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL
/**
* Register: XlpdXppuSinkErrSts
*/
#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkIsr
*/
#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkImr
*/
#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
/**
* Register: XlpdXppuSinkIer
*/
#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
/**
* Register: XlpdXppuSinkIdr
*/
#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_XPPU_SINK_H__ */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandpsu.h
*
* This file implements a driver to support Arasan NAND controller
* present in Zynq Ultrascale Mp.
*
* <b>Driver Initialization</b>
*
* The function call XNandPsu_CfgInitialize() should be called by the application
* before any other function in the driver. The initialization function takes
* device specific data (like device id, instance id, and base address) and
* initializes the XNandPsu instance with the device specific data.
*
* <b>Device Geometry</b>
*
* NAND flash device is memory device and it is segmented into areas called
* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
* size. A block is the smallest erasable unit of data within the Flash array of
* a LUN. The size of each block is based on a power of 2. There is no
* restriction on the number of blocks within the LUN. A block contains a number
* of pages. A page is the smallest addressable unit for read and program
* operations. The arrangement of LUN, blocks, and pages is referred to by this
* module as the part's geometry.
*
* The cells within the part can be programmed from a logic 1 to a logic 0
* and not the other way around. To change a cell back to a logic 1, the
* entire block containing that cell must be erased. When a block is erased
* all bytes contain the value 0xFF. The number of times a block can be
* erased is finite. Eventually the block will wear out and will no longer
* be capable of erasure. As of this writing, the typical flash block can
* be erased 100,000 or more times.
*
* The jobs done by this driver typically are:
* - 8-bit operational mode
* - Read, Write, and Erase operation
*
* <b>Write Operation</b>
*
* The write call can be used to write a minimum of one byte and a maximum
* entire flash. If the address offset specified to write is out of flash or if
* the number of bytes specified from the offset exceed flash boundaries
* an error is reported back to the user. The write is blocking in nature in that
* the control is returned back to user only after the write operation is
* completed successfully or an error is reported.
*
* <b>Read Operation</b>
*
* The read call can be used to read a minimum of one byte and maximum of
* entire flash. If the address offset specified to read is out of flash or if
* the number of bytes specified from the offset exceed flash boundaries
* an error is reported back to the user. The read is blocking in nature in that
* the control is returned back to user only after the read operation is
* completed successfully or an error is reported.
*
* <b>Erase Operation</b>
*
* The erase operations are provided to erase a Block in the Flash memory. The
* erase call is blocking in nature in that the control is returned back to user
* only after the erase operation is completed successfully or an error is
* reported.
*
* @note Driver has been renamed to nandpsu after change in
* naming convention.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads,
* mutual exclusion, virtual memory, cache control, or HW write protection
* management must be satisfied by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 01/12/2015 Removed Null checks for Buffer passed
* as parameter to Read API's
* - XNandPsu_Read()
* - XNandPsu_ReadPage
* Modified
* - XNandPsu_SetFeature()
* - XNandPsu_GetFeature()
* and made them public.
* Removed Failure Return for BCF Error check in
* XNandPsu_ReadPage() and added BCH_Error counter
* in the instance pointer structure.
* Added XNandPsu_Prepare_Cmd API
* Replaced
* - XNandPsu_IntrStsEnable
* - XNandPsu_IntrStsClear
* - XNandPsu_IntrClear
* - XNandPsu_SetProgramReg
* with XNandPsu_WriteReg call
* Modified xnandpsu.c file API's with above changes.
* Corrected the program command for Set Feature API.
* Modified
* - XNandPsu_OnfiReadStatus
* - XNandPsu_GetFeature
* - XNandPsu_SetFeature
* to add support for DDR mode.
* Changed Convention for SLC/MLC
* SLC --> HAMMING
* MLC --> BCH
* SlcMlc --> IsBCH
* Added support for writing BBT signature and version
* in page section by enabling XNANDPSU_BBT_NO_OOB.
* Removed extra DMA mode initialization from
* the XNandPsu_CfgInitialize API.
* Modified
* - XNandPsu_SetEccAddrSize
* ECC address now is calculated based upon the
* size of spare area
* Modified Block Erase API, removed clearing of
* packet register before erase.
* Clearing Data Interface Register before
* XNandPsu_OnfiReset call.
* Modified XNandPsu_ChangeTimingMode API supporting
* SDR and NVDDR interface for timing modes 0 to 5.
* Modified Bbt Signature and Version Offset value for
* Oob and No-Oob region.
* </pre>
*
******************************************************************************/
#ifndef XNANDPSU_H /* prevent circular inclusions */
#define XNANDPSU_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include <string.h>
#include "xstatus.h"
#include "xil_assert.h"
#include "xnandpsu_hw.h"
#include "xnandpsu_onfi.h"
#include "xil_cache.h"
/************************** Constant Definitions *****************************/
#define XNANDPSU_DEBUG
#define XNANDPSU_MAX_TARGETS 1U /**< ce_n0, ce_n1 */
#define XNANDPSU_MAX_PKT_SIZE 0x7FFU /**< Max packet size */
#define XNANDPSU_MAX_PKT_COUNT 0xFFFU /**< Max packet count */
#define XNANDPSU_PAGE_SIZE_512 512U /**< 512 bytes page */
#define XNANDPSU_PAGE_SIZE_2K 2048U /**< 2K bytes page */
#define XNANDPSU_PAGE_SIZE_4K 4096U /**< 4K bytes page */
#define XNANDPSU_PAGE_SIZE_8K 8192U /**< 8K bytes page */
#define XNANDPSU_PAGE_SIZE_16K 16384U /**< 16K bytes page */
#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */
#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */
#define XNANDPSU_BUS_WIDTH_8 0U /**< 8-bit bus width */
#define XNANDPSU_BUS_WIDTH_16 1U /**< 16-bit bus width */
#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */
#define XNANDPSU_BCH 0x2U /**< BCH Flash */
#define XNANDPSU_MAX_BLOCKS 32768U /**< Max number of Blocks */
#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND
flash page of 16K */
#define XNANDPSU_INTR_POLL_TIMEOUT 10000U
#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
/**
* The XNandPsu_Config structure contains configuration information for NAND
* controller.
*/
typedef struct {
u16 DeviceId; /**< Instance ID of NAND flash controller */
u32 BaseAddress; /**< Base address of NAND flash controller */
} XNandPsu_Config;
/**
* The XNandPsu_DataInterface enum contains flash operating mode.
*/
typedef enum {
XNANDPSU_SDR = 0U, /**< Single Data Rate */
XNANDPSU_NVDDR /**< Double Data Rate */
} XNandPsu_DataInterface;
/**
* XNandPsu_TimingMode enum contains timing modes.
*/
typedef enum {
XNANDPSU_SDR0 = 0U,
XNANDPSU_SDR1,
XNANDPSU_SDR2,
XNANDPSU_SDR3,
XNANDPSU_SDR4,
XNANDPSU_SDR5,
XNANDPSU_NVDDR0,
XNANDPSU_NVDDR1,
XNANDPSU_NVDDR2,
XNANDPSU_NVDDR3,
XNANDPSU_NVDDR4,
XNANDPSU_NVDDR5
} XNandPsu_TimingMode;
/**
* The XNandPsu_SWMode enum contains the driver operating mode.
*/
typedef enum {
XNANDPSU_POLLING = 0, /**< Polling */
XNANDPSU_INTERRUPT /**< Interrupt */
} XNandPsu_SWMode;
/**
* The XNandPsu_DmaMode enum contains the controller MDMA mode.
*/
typedef enum {
XNANDPSU_PIO = 0, /**< PIO Mode */
XNANDPSU_SDMA, /**< SDMA Mode */
XNANDPSU_MDMA /**< MDMA Mode */
} XNandPsu_DmaMode;
/**
* The XNandPsu_EccMode enum contains ECC functionality.
*/
typedef enum {
XNANDPSU_NONE = 0,
XNANDPSU_HWECC,
XNANDPSU_EZNAND,
XNANDPSU_ONDIE
} XNandPsu_EccMode;
/**
* The XNandPsu_BbtOption enum contains the BBT storage option.
*/
typedef enum {
XNANDPSU_BBT_OOB = 0, /**< OOB area */
XNANDPSU_BBT_NO_OOB, /**< No OOB i.e page area */
} XNandPsu_BbtOption;
/**
* Bad block table descriptor
*/
typedef struct {
u32 PageOffset[XNANDPSU_MAX_TARGETS];
/**< Page offset where BBT resides */
u32 SigOffset; /**< Signature offset in Spare area */
u32 VerOffset; /**< Offset of BBT version */
u32 SigLength; /**< Length of the signature */
u32 MaxBlocks; /**< Max blocks to search for BBT */
char Signature[4]; /**< BBT signature */
u8 Version[XNANDPSU_MAX_TARGETS];
/**< BBT version */
u32 Valid; /**< BBT descriptor is valid or not */
XNandPsu_BbtOption Option; /**< BBT Oob option enabled/disabled */
} XNandPsu_BbtDesc;
/**
* Bad block pattern
*/
typedef struct {
u32 Options; /**< Options to search the bad block pattern */
u32 Offset; /**< Offset to search for specified pattern */
u32 Length; /**< Number of bytes to check the pattern */
u8 Pattern[2]; /**< Pattern format to search for */
} XNandPsu_BadBlockPattern;
/**
* The XNandPsu_Geometry structure contains the ONFI geometry information.
*/
typedef struct {
/*
* Parameter page information
*/
u32 BytesPerPage; /**< Number of bytes per page */
u16 SpareBytesPerPage; /**< Number of spare bytes per page */
u32 PagesPerBlock; /**< Number of pages per block */
u32 BlocksPerLun; /**< Number of blocks per LUN */
u8 NumLuns; /**< Number of LUN's */
u8 RowAddrCycles; /**< Row address cycles */
u8 ColAddrCycles; /**< Column address cycles */
u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */
u8 NumBitsECC; /**< Number of bits ECC correctability */
u32 EccCodeWordSize; /**< ECC codeword size */
/*
* Driver specific information
*/
u32 BlockSize; /**< Block size */
u32 NumTargetPages; /**< Total number of pages in a Target */
u32 NumTargetBlocks; /**< Total number of blocks in a Target */
u64 TargetSize; /**< Target size in bytes */
u8 NumTargets; /**< Number of targets present */
u32 NumPages; /**< Total number of pages */
u32 NumBlocks; /**< Total number of blocks */
u64 DeviceSize; /**< Total flash size in bytes */
} XNandPsu_Geometry;
/**
* The XNandPsu_Features structure contains the ONFI features information.
*/
typedef struct {
u32 BusWidth;
u32 NvDdr;
u32 EzNand;
u32 OnDie;
u32 ExtPrmPage;
} XNandPsu_Features;
/**
* The XNandPsu_EccMatrix structure contains ECC features information.
*/
typedef struct {
u16 PageSize;
u16 CodeWordSize;
u8 NumEccBits;
u8 IsBCH;
u16 EccAddr;
u16 EccSize;
} XNandPsu_EccMatrix;
/**
* The XNandPsu_EccCfg structure contains ECC configuration.
*/
typedef struct {
u16 EccAddr;
u16 EccSize;
u16 CodeWordSize;
u8 NumEccBits;
u8 IsBCH;
} XNandPsu_EccCfg;
/**
* The XNandPsu structure contains the driver instance data. The user is
* required to allocate a variable of this type for the NAND controller.
* A pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct {
u32 IsReady; /**< Device is initialized and ready */
XNandPsu_Config Config;
u16 Ecc_Stat_PerPage_flips; /**< Ecc Correctable Error Counter for Current Page */
u32 Ecc_Stats_total_flips; /**< Total Ecc Errors Corrected */
XNandPsu_DataInterface DataInterface;
XNandPsu_TimingMode TimingMode;
XNandPsu_SWMode Mode; /**< Driver operating mode */
XNandPsu_DmaMode DmaMode; /**< MDMA mode enabled/disabled */
XNandPsu_EccMode EccMode; /**< ECC Mode */
XNandPsu_EccCfg EccCfg; /**< ECC configuration */
XNandPsu_Geometry Geometry; /**< Flash geometry */
XNandPsu_Features Features; /**< ONFI features */
u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
/**< Partial read/write buffer */
/* Bad block table definitions */
XNandPsu_BbtDesc BbtDesc; /**< Bad block table descriptor */
XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */
XNandPsu_BadBlockPattern BbPattern; /**< Bad block pattern to
search */
u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2]; /**< Bad block table array */
} XNandPsu;
/******************* Macro Definitions (Inline Functions) *******************/
/*****************************************************************************/
/**
* This macro sets the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param RegOffset is the register offset.
* @param BitMask is the bitmask.
*
* @note C-style signature:
* void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
* u32 BitMask)
*
*****************************************************************************/
#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \
XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
(RegOffset)) | (BitMask))))
/*****************************************************************************/
/**
* This macro clears the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param RegOffset is the register offset.
* @param BitMask is the bitmask.
*
* @note C-style signature:
* void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
* u32 BitMask)
*
*****************************************************************************/
#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \
XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
(RegOffset)) & ~(BitMask))))
/*****************************************************************************/
/**
* This macro clears and updates the bitmask in the register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param RegOffset is the register offset.
* @param Mask is the bitmask.
* @param Value is the register value to write.
*
* @note C-style signature:
* void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
* u32 RegOffset, u32 Mask, u32 Val)
*
*****************************************************************************/
#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \
XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
(RegOffset), \
((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
/*****************************************************************************/
/**
* This macro enables bitmask in Interrupt Signal Enable register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \
XNandPsu_SetBits((InstancePtr), \
XNANDPSU_INTR_SIG_EN_OFFSET, \
(Mask))
/*****************************************************************************/
/**
* This macro clears bitmask in Interrupt Signal Enable register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPsu_IntrSigClear(InstancePtr, Mask) \
XNandPsu_ClrBits((InstancePtr), \
XNANDPSU_INTR_SIG_EN_OFFSET, \
(Mask))
/*****************************************************************************/
/**
* This macro enables bitmask in Interrupt Status Enable register.
*
* @param InstancePtr is a pointer to the XNandPsu instance of the
* controller.
* @param Mask is the bitmask.
*
* @note C-style signature:
* void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \
XNandPsu_SetBits((InstancePtr), \
XNANDPSU_INTR_STS_EN_OFFSET, \
(Mask))
/*****************************************************************************/
/**
* This macro checks for the ONFI ID.
*
* @param Buff is the buffer holding ONFI ID
*
* @note none.
*
*****************************************************************************/
#define IS_ONFI(Buff) \
(Buff[0] == (u8)'O') && (Buff[1] == (u8)'N') && \
(Buff[2] == (u8)'F') && (Buff[3] == (u8)'I')
/************************** Function Prototypes *****************************/
s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
u32 EffectiveAddr);
s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
u8 *SrcBuf);
s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
u8 *DestBuf);
s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
XNandPsu_DataInterface NewIntf,
XNandPsu_TimingMode NewMode);
s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
u8 *Buf);
s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
u8 *Buf);
s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
u8 DmaMode, u8 AddrCycles);
void XNandPsu_EnableBbtOobMode(XNandPsu *InstancePtr);
void XNandPsu_DisableBbtOobMode(XNandPsu *InstancePtr);
/*
* XNandPsu_LookupConfig in xnandpsu_sinit.c
*/
XNandPsu_Config *XNandPsu_LookupConfig(u16 DeviceID);
#ifdef __cplusplus
}
#endif
#endif /* XNANDPSU_H end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandpsu_bbm.h
*
* This file implements the Bad Block Management(BBM) functionality. This is
* similar to the Bad Block Management which is a part of the MTD subsystem in
* Linux. The factory marked bad blocks are scanned initially and a Bad Block
* Table(BBT) is created in the memory. This table is also written to the flash
* so that upon reboot, the BBT is read back from the flash and loaded into the
* memory instead of scanning every time. The Bad Block Table(BBT) is written
* into one of the the last four blocks in the flash memory. The last four
* blocks are marked as Reserved so that user can't erase/program those blocks.
*
* There are two bad block tables, a primary table and a mirror table. The
* tables are versioned and incrementing version number is used to detect and
* recover from interrupted updates. Each table is stored in a separate block,
* beginning in the first page of that block. Only two blocks would be necessary
* in the absence of bad blocks within the last four; the range of four provides
* a little slack in case one or two of those blocks is bad. These blocks are
* marked as reserved and cannot be programmed by the user. A NAND Flash device
* with 3 or more factory bad blocks in the last 4 cannot be used. The bad block
* table signature is written into the spare data area of the pages containing
* bad block table so that upon rebooting the bad block table signature is
* searched and the bad block table is loaded into RAM. The signature is "Bbt0"
* for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The
* version offset follows the signature offset in the spare data area. The
* version number increments on every update to the bad block table and the
* version wraps at 0xff.
*
* Each block in the Bad Block Table(BBT) is represented by 2 bits.
* The two bits are encoded as follows in RAM BBT.
* 0'b00 -> Good Block
* 0'b01 -> Block is bad due to wear
* 0'b10 -> Reserved block
* 0'b11 -> Factory marked bad block
*
* While writing to the flash the two bits are encoded as follows.
* 0'b00 -> Factory marked bad block
* 0'b01 -> Reserved block
* 0'b10 -> Block is bad due to wear
* 0'b11 -> Good Block
*
* The user can check for the validity of the block using the API
* XNandPsu_IsBlockBad and take the action based on the return value. Also user
* can update the bad block table using XNandPsu_MarkBlockBad API.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* 2.0 sb 01/12/2015 Added support for writing BBT signature and version
* in page section by enabling XNANDPSU_BBT_NO_OOB.
* Modified Bbt Signature and Version Offset value for
* Oob and No-Oob region.
* </pre>
*
******************************************************************************/
#ifndef XNANDPSU_BBM_H /* prevent circular inclusions */
#define XNANDPSU_BBM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xnandpsu.h"
/************************** Constant Definitions *****************************/
/*
* Block definitions for RAM based Bad Block Table (BBT)
*/
#define XNANDPSU_BLOCK_GOOD 0x0U /**< Block is good */
#define XNANDPSU_BLOCK_BAD 0x1U /**< Block is bad */
#define XNANDPSU_BLOCK_RESERVED 0x2U /**< Reserved block */
#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U /**< Factory marked bad
block */
/*
* Block definitions for FLASH based Bad Block Table (BBT)
*/
#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U /**< Block is good */
#define XNANDPSU_FLASH_BLOCK_BAD 0x2U /**< Block is bad */
#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U /**< Reserved block */
#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U /**< Factory marked bad
block */
#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U /**< Scan the
second page
for bad block
information
*/
#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U /**< Page offset of Bad
Block Table Desc */
#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U /**< Bad Block Table
signature offset */
#define XNANDPSU_BBT_DESC_VER_OFFSET 12U /**< Bad block Table
version offset */
#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U /**< Bad Block Table
signature offset in
page memory */
#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U /**< Bad block Table
version offset in
page memory */
#define XNANDPSU_BBT_DESC_SIG_LEN 4U /**< Bad block Table
signature length */
#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U /**< Bad block Table
max blocks */
#define XNANDPSU_BBT_BLOCK_SHIFT 2U /**< Block shift value
for a block in BBT */
#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U /**< Num of blocks in
one BBT entry */
#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U /**< Bad block pattern
offset in a page */
#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U /**< Bad block pattern
length */
#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U /**< Bad block pattern
offset in a large
page */
#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U /**< Bad block pattern
length */
#define XNANDPSU_BB_PATTERN 0xFFU /**< Bad block pattern
to search in a page
*/
#define XNANDPSU_BLOCK_TYPE_MASK 0x03U /**< Block type mask */
#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U /**< Block shift mask
for a Bad Block Table
entry byte */
#define XNANDPSU_ONDIE_SIG_OFFSET 0x4U
#define XNANDPSU_ONDIE_VER_OFFSET 0x14U
#define XNANDPSU_BBT_VERSION_LENGTH 1U
#define XNANDPSU_BBT_SIG_LENGTH 4U
#define XNANDPSU_BBT_BUF_LENGTH ((XNANDPSU_MAX_BLOCKS >> \
XNANDPSU_BBT_BLOCK_SHIFT) + \
(XNANDPSU_BBT_DESC_SIG_OFFSET + \
XNANDPSU_BBT_SIG_LENGTH + \
XNANDPSU_BBT_VERSION_LENGTH))
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro returns the Block shift value corresponding to a Block.
*
* @param Block is the block number.
*
* @return Block shift value
*
* @note None.
*
*****************************************************************************/
#define XNandPsu_BbtBlockShift(Block) \
((u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void XNandPsu_InitBbtDesc(XNandPsu *InstancePtr);
s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block);
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandpsu_hw.h
*
* This file contains identifiers and low-level macros/functions for the Arasan
* NAND flash controller driver.
*
* See xnandpsu.h for more information.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First Release
* 2.0 sb 11/04/2014 Changed XNANDPSU_ECC_SLC_MLC_MASK to
* XNANDPSU_ECC_HAMMING_BCH_MASK.
* </pre>
*
******************************************************************************/
#ifndef XNANDPSU_HW_H /* prevent circular inclusions */
#define XNANDPSU_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/************************** Register Offset Definitions **********************/
#define XNANDPSU_PKT_OFFSET 0x00U /**< Packet Register */
#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U /**< Memory Address
Register 1 */
#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U /**< Memory Address
Register 2 */
#define XNANDPSU_CMD_OFFSET 0x0CU /**< Command Register */
#define XNANDPSU_PROG_OFFSET 0x10U /**< Program Register */
#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U /**< Interrupt Status
Enable Register */
#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U /**< Interrupt Signal
Enable Register */
#define XNANDPSU_INTR_STS_OFFSET 0x1CU /**< Interrupt Status
Register */
#define XNANDPSU_READY_BUSY_OFFSET 0x20U /**< Ready/Busy status
Register */
#define XNANDPSU_FLASH_STS_OFFSET 0x28U /**< Flash Status Register */
#define XNANDPSU_TIMING_OFFSET 0x2CU /**< Timing Register */
#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U /**< Buffer Data Port
Register */
#define XNANDPSU_ECC_OFFSET 0x34U /**< ECC Register */
#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U /**< ECC Error Count
Register */
#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU /**< ECC Spare Command
Register */
#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U /**< Error Count 1bit
Register */
#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U /**< Error Count 2bit
Register */
#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U /**< Error Count 3bit
Register */
#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU /**< Error Count 4bit
Register */
#define XNANDPSU_CPU_REL_OFFSET 0x58U /**< CPU Release Register */
#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU /**< Error Count 5bit
Register */
#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U /**< Error Count 6bit
Register */
#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U /**< Error Count 7bit
Register */
#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U /**< Error Count 8bit
Register */
#define XNANDPSU_DATA_INTF_OFFSET 0x6CU /**< Data Interface Register */
#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U /**< DMA System Address 0
Register */
#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U /**< DMA System Address 1
Register */
#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U /**< DMA Buffer Boundary
Register */
#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U /**< Slave DMA Configuration
Register */
/** @name Packet Register bit definitions and masks
* @{
*/
#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU /**< Packet Size */
#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U /**< Packet Count*/
#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U /**< Packet Count Shift */
/* @} */
/** @name Memory Address Register 1 bit definitions and masks
* @{
*/
#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU /**< Column Address
Mask */
#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U /**< Page, Block
Address Mask */
#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U /**< Page Shift */
/* @} */
/** @name Memory Address Register 2 bit definitions and masks
* @{
*/
#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU /**< Memory Address
*/
#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U /**< Bus Width */
#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U /**< BCH Mode
Value */
#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U /**< Flash
Connection Mode */
#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U /**< Chip Select */
#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U /**< Chip select
shift */
#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U /**< Bus width shift */
#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U
/* @} */
/** @name Command Register bit definitions and masks
* @{
*/
#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU /**< 1st Cycle
Command */
#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U /**< 2nd Cycle
Command */
#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U /**< Page Size */
#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U /**< DMA Enable
Mode */
#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U /**< Number of
Address Cycles */
#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U /**< ECC ON/OFF */
#define XNANDPSU_CMD_CMD2_SHIFT 8U /**< 2nd Cycle Command
Shift */
#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U /**< Page Size Shift */
#define XNANDPSU_CMD_DMA_EN_SHIFT 26U /**< DMA Enable Shift */
#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U /**< Number of Address
Cycles Shift */
#define XNANDPSU_CMD_ECC_ON_SHIFT 31U /**< ECC ON/OFF */
/* @} */
/** @name Program Register bit definitions and masks
* @{
*/
#define XNANDPSU_PROG_RD_MASK 0x00000001U /**< Read */
#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U /**< Multi Die */
#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U /**< Block Erase */
#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U /**< Read Status */
#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U /**< Page Program */
#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U /**< Multi Die Rd */
#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U /**< Read ID */
#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U /**< Read Param
Page */
#define XNANDPSU_PROG_RST_MASK 0x00000100U /**< Reset */
#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U /**< Get Features */
#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U /**< Set Features */
#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U /**< Read Unique
ID */
#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U /**< Read Status
Enhanced */
#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U /**< Read
Interleaved */
#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U /**< Change Read
Column
Enhanced */
#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U /**< Copy Back
Interleaved */
#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U /**< Read Cache
Start */
#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U /**< Read Cache
Sequential */
#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U /**< Read Cache
Random */
#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U /**< Read Cache
End */
#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U /**< Small Data
Move */
#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U /**< Change Row
Address */
#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U /**< Change Row
Address End */
#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U /**< Reset LUN */
#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U /**< Enhanced
Program Page
Register Clear */
#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U /**< Volume Select */
#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U /**< ODT Configure */
/* @} */
/** @name Interrupt Status Enable Register bit definitions and masks
* @{
*/
#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write Ready
Status
Enable */
#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read Ready
Status
Enable */
#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete
Status
Enable */
#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error
Status
Enable */
#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error
Status
Enable,
BCH Detect
Error
Status
Enable */
#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Status
Enable */
#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB Status
Enable */
/* @} */
/** @name Interrupt Signal Enable Register bit definitions and masks
* @{
*/
#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write Ready
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read Ready
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error
Signal
Enable,
BCH Detect
Error
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Signal
Enable */
#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB Signal
Enable */
/* @} */
/** @name Interrupt Status Register bit definitions and masks
* @{
*/
#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer
Write
Ready */
#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer
Read
Ready */
#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete */
#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi
Bit Error */
#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single
Bit Error,
BCH Detect
Error */
#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA
Interrupt
*/
#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error
AHB */
/* @} */
/** @name Interrupt bit definitions and masks
* @{
*/
#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U /**< Buffer Write
Ready Status
Enable */
#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U /**< Buffer Read
Ready Status
Enable */
#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U /**< Transfer
Complete Status
Enable */
#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U /**< Multi Bit Error
Status Enable */
#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U /**< Single Bit Error
Status Enable,
BCH Detect Error
Status Enable */
#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U /**< DMA Status
Enable */
#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U /**< Error AHB Status
Enable */
/* @} */
/** @name ID2 Register bit definitions and masks
* @{
*/
#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU /**< MSB Device ID */
/* @} */
/** @name Flash Status Register bit definitions and masks
* @{
*/
#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU /**< Flash Status
Value */
/* @} */
/** @name Timing Register bit definitions and masks
* @{
*/
#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U /**< Change column
setup time */
#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U /**< Slow/Fast device
*/
#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U /**< Write/Read data
transaction value
*/
#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U /**< Address latch
enable to Data
loading time */
/* @} */
/** @name ECC Register bit definitions and masks
* @{
*/
#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU /**< ECC address */
#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U /**< ECC size */
#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U /**< Hamming/BCH
support */
/* @} */
/** @name ECC Error Count Register bit definitions and masks
* @{
*/
#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU /**< Packet
bound error
count */
#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U /**< Page
bound error
count */
/* @} */
/** @name ECC Spare Command Register bit definitions and masks
* @{
*/
#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU /**< ECC
spare
command */
#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U /**< Number
of ECC/
spare
address
cycles */
/* @} */
/** @name Data Interface Register bit definitions and masks
* @{
*/
#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U /**< SDR mode */
#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U /**< NVDDR mode */
#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U /**< NVDDR2 mode */
#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U /**< Data
Interface */
#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U /**< NVDDR mode shift */
#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U /**< Data Interface Shift */
/* @} */
/** @name DMA Buffer Boundary Register bit definitions and masks
* @{
*/
#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U /**< DMA buffer
boundary */
#define XNANDPSU_DMA_BUF_BND_4K 0x0U
#define XNANDPSU_DMA_BUF_BND_8K 0x1U
#define XNANDPSU_DMA_BUF_BND_16K 0x2U
#define XNANDPSU_DMA_BUF_BND_32K 0x3U
#define XNANDPSU_DMA_BUF_BND_64K 0x4U
#define XNANDPSU_DMA_BUF_BND_128K 0x5U
#define XNANDPSU_DMA_BUF_BND_256K 0x6U
#define XNANDPSU_DMA_BUF_BND_512K 0x7U
/* @} */
/** @name Slave DMA Configuration Register bit definitions and masks
* @{
*/
#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U /**< Slave
DMA
Transfer
Direction
*/
#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU /**< Slave
DMA
Transfer
Count */
#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U /**< Slave
DMA
Burst
Size */
#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U /**< DMA
Timeout
Counter
Value */
#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U /**< Slave
DMA
Enable */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddress is the base address of controller registers.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register.
*
* @note C-style signature:
* u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XNandPsu_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param BaseAddress is the the base address of controller registers.
* @param RegOffset is the register offset to be written.
* @param Data is the the 32-bit value to write to the register.
*
* @return None.
*
* @note C-style signature:
* void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
******************************************************************************/
#define XNandPsu_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* XNANDPSU_HW_H end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xnandpsu_onfi.h
*
* This file defines all the ONFI 3.1 specific commands and values.
*
* @note None
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- ---------- -----------------------------------------------
* 1.0 nm 05/06/2014 First release
* </pre>
*
******************************************************************************/
#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */
#define XNANDPSU_ONFI_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/*
* Standard ONFI 3.1 Commands
*/
/*
* ONFI 3.1 Mandatory Commands
*/
#define ONFI_CMD_RD1 0x00U /**< Read (1st cycle) */
#define ONFI_CMD_RD2 0x30U /**< Read (2nd cycle) */
#define ONFI_CMD_CHNG_RD_COL1 0x05U /**< Change Read Column
(1st cycle) */
#define ONFI_CMD_CHNG_RD_COL2 0xE0U /**< Change Read Column
(2nd cycle) */
#define ONFI_CMD_BLK_ERASE1 0x60U /**< Block Erase (1st cycle) */
#define ONFI_CMD_BLK_ERASE2 0xD0U /**< Block Erase (2nd cycle) */
#define ONFI_CMD_RD_STS 0x70U /**< Read Status */
#define ONFI_CMD_PG_PROG1 0x80U /**< Page Program(1st cycle) */
#define ONFI_CMD_PG_PROG2 0x10U /**< Page Program(2nd cycle) */
#define ONFI_CMD_CHNG_WR_COL 0x85U /**< Change Write Column */
#define ONFI_CMD_RD_ID 0x90U /**< Read ID */
#define ONFI_CMD_RD_PRM_PG 0xECU /**< Read Parameter Page */
#define ONFI_CMD_RST 0xFFU /**< Reset */
/*
* ONFI 3.1 Optional Commands
*/
#define ONFI_CMD_MUL_RD1 0x00U /**< Multiplane Read
(1st cycle) */
#define ONFI_CMD_MUL_RD2 0x32U /**< Multiplane Read
(2nd cycle) */
#define ONFI_CMD_CPBK_RD1 0x00U /**< Copyback Read
(1st cycle) */
#define ONFI_CMD_CPBK_RD2 0x35U /**< Copyback Read
(2nd cycle) */
#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U /**< Change Read Column
Enhanced (1st cycle) */
#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U /**< Change Read Column
Enhanced (2nd cycle) */
#define ONFI_CMD_RD_CACHE_RND1 0x00U /**< Read Cache Random
(1st cycle) */
#define ONFI_CMD_RD_CACHE_RND2 0x31U /**< Read Cache Random
(2nd cycle) */
#define ONFI_CMD_RD_CACHE_SEQ 0x31U /**< Read Cache Sequential */
#define ONFI_CMD_RD_CACHE_END 0x3FU /**< Read Cache End */
#define ONFI_CMD_MUL_BLK_ERASE1 0x60U /**< Multiplane Block Erase
(1st cycle) */
#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U /**< Multiplane Block Erase
(2nd cycle) */
#define ONFI_CMD_RD_STS_ENHCD 0x78U /**< Read Status Enhanced */
#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U /**< Block Erase Interleaved
(2nd cycle) */
#define ONFI_CMD_MUL_PG_PROG1 0x80U /**< Multiplane Page Program
(1st cycle) */
#define ONFI_CMD_MUL_PG_PROG2 0x11U /**< Multiplane Page Program
(2nd cycle) */
#define ONFI_CMD_PG_CACHE_PROG1 0x80U /**< Page Cache Program
(1st cycle) */
#define ONFI_CMD_PG_CACHE_PROG2 0x15U /**< Page Cache Program
(2nd cycle) */
#define ONFI_CMD_CPBK_PROG1 0x85U /**< Copyback Program
(1st cycle) */
#define ONFI_CMD_CPBK_PROG2 0x10U /**< Copyback Program
(2nd cycle) */
#define ONFI_CMD_MUL_CPBK_PROG1 0x85U /**< Multiplane Copyback
Program (1st cycle) */
#define ONFI_CMD_MUL_CPBK_PROG2 0x10U /**< Multiplane Copyback
Program (2nd cycle) */
#define ONFI_CMD_SMALL_DATA_MV1 0x85U /**< Small Data Move
(1st cycle) */
#define ONFI_CMD_SMALL_DATA_MV2 0x10U /**< Small Data Move
(2nd cycle) */
#define ONFI_CMD_CHNG_ROW_ADDR 0x85U /**< Change Row Address */
#define ONFI_CMD_VOL_SEL 0xE1U /**< Volume Select */
#define ONFI_CMD_ODT_CONF 0xE2U /**< ODT Configure */
#define ONFI_CMD_RD_UNIQID 0xEDU /**< Read Unique ID */
#define ONFI_CMD_GET_FEATURES 0xEEU /**< Get Features */
#define ONFI_CMD_SET_FEATURES 0xEFU /**< Set Features */
#define ONFI_CMD_LUN_GET_FEATURES 0xD4U /**< LUN Get Features */
#define ONFI_CMD_LUN_SET_FEATURES 0xD5U /**< LUN Set Features */
#define ONFI_CMD_RST_LUN 0xFAU /**< Reset LUN */
#define ONFI_CMD_SYN_RST 0xFCU /**< Synchronous Reset */
/*
* ONFI Status Register bit offsets
*/
#define ONFI_STS_FAIL 0x01U /**< FAIL */
#define ONFI_STS_FAILC 0x02U /**< FAILC */
#define ONFI_STS_CSP 0x08U /**< CSP */
#define ONFI_STS_VSP 0x10U /**< VSP */
#define ONFI_STS_ARDY 0x20U /**< ARDY */
#define ONFI_STS_RDY 0x40U /**< RDY */
#define ONFI_STS_WP 0x80U /**< WP_n */
/*
* ONFI constants
*/
#define ONFI_CRC_LEN 254U /**< ONFI CRC Buf Length */
#define ONFI_PRM_PG_LEN 256U /**< Parameter Page Length */
#define ONFI_MND_PRM_PGS 3U /**< Number of mandatory
parameter pages */
#define ONFI_SIG_LEN 4U /**< Signature Length */
#define ONFI_CMD_INVALID 0x00U /**< Invalid Command */
#define ONFI_READ_ID_LEN 4U /**< ONFI ID length */
#define ONFI_READ_ID_ADDR 0x20U /**< ONFI Read ID Address */
#define ONFI_READ_ID_ADDR_CYCLES 1U /**< ONFI Read ID Address
cycles */
#define ONFI_PRM_PG_ADDR_CYCLES 1U /**< ONFI Read Parameter page
address cycles */
/**
* This enum defines the ONFI 3.1 commands.
*/
enum OnfiCommandList {
READ=0, /**< Read */
MULTIPLANE_READ, /**< Multiplane Read */
COPYBACK_READ, /**< Copyback Read */
CHANGE_READ_COLUMN, /**< Change Read Column */
CHANGE_READ_COLUMN_ENHANCED, /**< Change Read Column Enhanced */
READ_CACHE_RANDOM, /**< Read Cache Random */
READ_CACHE_SEQUENTIAL, /**< Read Cache Sequential */
READ_CACHE_END, /**< Read Cache End */
BLOCK_ERASE, /**< Block Erase */
MULTIPLANE_BLOCK_ERASE, /**< Multiplane Block Erase */
READ_STATUS, /**< Read Status */
READ_STATUS_ENHANCED, /**< Read Status Enhanced */
PAGE_PROGRAM, /**< Page Program */
MULTIPLANE_PAGE_PROGRAM, /**< Multiplane Page Program */
PAGE_CACHE_PROGRAM, /**< Page Cache Program */
COPYBACK_PROGRAM, /**< Copyback Program */
MULTIPLANE_COPYBACK_PROGRAM, /**< Multiplance Copyback Program */
SMALL_DATA_MOVE, /**< Small Data Move */
CHANGE_WRITE_COLUMN, /**< Change Write Column */
CHANGE_ROW_ADDR, /**< Change Row Address */
READ_ID, /**< Read ID */
VOLUME_SELECT, /**< Volume Select */
ODT_CONFIGURE, /**< ODT Configure */
READ_PARAM_PAGE, /**< Read Parameter Page */
READ_UNIQUE_ID, /**< Read Unique ID */
GET_FEATURES, /**< Get Features */
SET_FEATURES, /**< Set Features */
LUN_GET_FEATURES, /**< LUN Get Features */
LUN_SET_FEATURES, /**< LUN Set Features */
RESET_LUN, /**< Reset LUN */
SYN_RESET, /**< Synchronous Reset */
RESET, /**< Reset */
MAX_CMDS /**< Dummy Command */
};
/**************************** Type Definitions *******************************/
/*
* Parameter page structure of ONFI 3.1 specification.
*/
typedef struct {
/*
* Revision information and features block
*/
u8 Signature[4]; /**< Parameter page signature */
u16 Revision; /**< Revision Number */
u16 Features; /**< Features supported */
u16 OptionalCmds; /**< Optional commands supported */
u8 JedecJtgPrmAdvCmd; /**< ONFI JEDEC JTG primary advanced
command support */
u8 Reserved0; /**< Reserved (11) */
u16 ExtParamPageLen; /**< Extended Parameter Page Length */
u8 NumOfParamPages; /**< Number of Parameter Pages */
u8 Reserved1[17]; /**< Reserved (15-31) */
/*
* Manufacturer information block
*/
u8 DeviceManufacturer[12]; /**< Device manufacturer */
u8 DeviceModel[20]; /**< Device model */
u8 JedecManufacturerId; /**< JEDEC Manufacturer ID */
u8 DateCode[2]; /**< Date code */
u8 Reserved2[13]; /**< Reserved (67-79) */
/*
* Memory organization block
*/
u32 BytesPerPage; /**< Number of data bytes per page */
u16 SpareBytesPerPage; /**< Number of spare bytes per page */
u32 BytesPerPartialPage; /**< Number of data bytes per
partial page */
u16 SpareBytesPerPartialPage; /**< Number of spare bytes per
partial page */
u32 PagesPerBlock; /**< Number of pages per block */
u32 BlocksPerLun; /**< Number of blocks per LUN */
u8 NumLuns; /**< Number of LUN's */
u8 AddrCycles; /**< Number of address cycles */
u8 BitsPerCell; /**< Number of bits per cell */
u16 MaxBadBlocksPerLun; /**< Bad blocks maximum per LUN */
u16 BlockEndurance; /**< Block endurance */
u8 GuaranteedValidBlock; /**< Guaranteed valid blocks at
beginning of target */
u16 BlockEnduranceGVB; /**< Block endurance for guaranteed
valid block */
u8 ProgramsPerPage; /**< Number of programs per page */
u8 PartialProgAttr; /**< Partial programming attributes */
u8 EccBits; /**< Number of bits ECC
correctability */
u8 PlaneAddrBits; /**< Number of plane address bits */
u8 PlaneOperationAttr; /**< Multi-plane operation
attributes */
u8 EzNandSupport; /**< EZ NAND support */
u8 Reserved3[12]; /**< Reserved (116 - 127) */
/*
* Electrical parameters block
*/
u8 IOPinCapacitance; /**< I/O pin capacitance, maximum */
u16 SDRTimingMode; /**< SDR Timing mode support */
u16 SDRPagecacheTimingMode; /**< SDR Program cache timing mode */
u16 TProg; /**< Maximum page program time */
u16 TBers; /**< Maximum block erase time */
u16 TR; /**< Maximum page read time */
u16 TCcs; /**< Maximum change column setup
time */
u8 NVDDRTimingMode; /**< NVDDR timing mode support */
u8 NVDDR2TimingMode; /**< NVDDR2 timing mode support */
u8 SynFeatures; /**< NVDDR/NVDDR2 features */
u16 ClkInputPinCap; /**< CLK input pin capacitance */
u16 IOPinCap; /**< I/O pin capacitance */
u16 InputPinCap; /**< Input pin capacitance typical */
u8 InputPinCapMax; /**< Input pin capacitance maximum */
u8 DrvStrength; /**< Driver strength support */
u16 TMr; /**< Maximum multi-plane read time */
u16 TAdl; /**< Program page register clear
enhancement value */
u16 TEr; /**< Typical page read time for
EZ NAND */
u8 NVDDR2Features; /**< NVDDR2 Features */
u8 NVDDR2WarmupCycles; /**< NVDDR2 Warmup Cycles */
u8 Reserved4[4]; /**< Reserved (160 - 163) */
/*
* Vendor block
*/
u16 VendorRevisionNum; /**< Vendor specific revision number */
u8 VendorSpecific[88]; /**< Vendor specific */
u16 Crc; /**< Integrity CRC */
}__attribute__((packed))OnfiParamPage;
/*
* ONFI extended parameter page structure.
*/
typedef struct {
u16 Crc;
u8 Sig[4];
u8 Reserved1[10];
u8 Section0Type;
u8 Section0Len;
u8 Section1Type;
u8 Section1Len;
u8 ResSection[12];
u8 SectionData[256];
}__attribute__((packed))OnfiExtPrmPage;
/*
* Driver extended parameter page information.
*/
typedef struct {
u8 NumBitsEcc;
u8 CodeWordSize;
u16 MaxBadBlocks;
u16 BlockEndurance;
u16 Reserved;
}__attribute__((packed))OnfiExtEccBlock;
typedef struct {
u8 Command1; /**< Command Cycle 1 */
u8 Command2; /**< Command Cycle 2 */
} OnfiCmdFormat;
extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
/************************** Function Prototypes ******************************/
u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
#ifdef __cplusplus
}
#endif
#endif /* XNANDPSU_ONFI_H end of protection macro */

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@ -0,0 +1,317 @@
/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for backwards compatibilty
*/
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
/* Shared Peripheral Interrupts (SPI) */
/* FIXME */
/*#define XPS_FPGA0_INT_ID 100U */
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_NAND_INT_ID (14U + 32U)
#define XPS_QSPI_INT_ID (15U + 32U)
#define XPS_GPIO_INT_ID (16U + 32U)
#define XPS_I2C0_INT_ID (17U + 32U)
#define XPS_I2C1_INT_ID (18U + 32U)
#define XPS_SPI0_INT_ID (19U + 32U)
#define XPS_SPI1_INT_ID (20U + 32U)
#define XPS_UART0_INT_ID (21U + 32U)
#define XPS_UART1_INT_ID (22U + 32U)
#define XPS_CAN0_INT_ID (23U + 32U)
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_WDT_INT_ID (52U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
#define XPS_TTC1_0_INT_ID (39U + 32U)
#define XPS_TTC1_1_INT_ID (40U + 32U)
#define XPS_TTC1_2_INT_ID (41U + 32U)
#define XPS_TTC2_0_INT_ID (42U + 32U)
#define XPS_TTC2_1_INT_ID (43U + 32U)
#define XPS_TTC2_2_INT_ID (44U + 32U)
#define XPS_TTC3_0_INT_ID (45U + 32U)
#define XPS_TTC3_1_INT_ID (46U + 32U)
#define XPS_TTC3_2_INT_ID (47U + 32U)
#define XPS_SDIO0_INT_ID (48U + 32U)
#define XPS_SDIO1_INT_ID (49U + 32U)
#define XPS_GEM0_INT_ID (57U + 32U)
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
#define XPS_GEM1_INT_ID (59U + 32U)
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
#define XPS_GEM2_INT_ID (61U + 32U)
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
#define XPS_GEM3_INT_ID (63U + 32U)
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
#define XPS_CSU_DMA_INT_ID (86U + 32U)
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
#define XPS_FPD_CCI_INT_ID (154U + 32U)
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
/* Private Peripheral Interrupts (PPI) */
/*#define XPS_GLOBAL_TMR_INT_ID 27 SCU Global Timer interrupt */
/*#define XPS_FIQ_INT_ID 28 FIQ from FPGA fabric */
/*#define XPS_SCU_TMR_INT_ID 29 SCU Private Timer interrupt */
/*#define XPS_SCU_WDT_INT_ID 30 SCU Private WDT interrupt */
/*#define XPS_IRQ_INT_ID 31 IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PS7_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PS7_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#endif
#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#endif
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.h
*
* This file contains definitions for various platforms available
*
******************************************************************************/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_ZYNQ_ULTRA_MP 0x1
#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
#define XPLAT_ZYNQ 0x4
#define XPLAT_MICROBLAZE 0x5
#define XPLAT_INFO_MASK (0xF)
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
u32 XGetPlatform_Info();
#if defined (ARMR5) || (__aarch64__)
u32 XGet_Zynq_UltraMp_Platform_info();
#endif
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm.h
*
* This header file contains macros for using inline assembler code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_H
#define XPSEUDO_ASM_H
#include "xreg_cortexa53.h"
#include "xpseudo_asm_gcc.h"
#endif /* XPSEUDO_ASM_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm_gcc.h
*
* This header file contains macros for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/21/14 First release
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
#define XPSEUDO_ASM_GCC_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval; \
asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
#define mtcpsr(v) asm ("msr DAIF, %0" : : "r" (v))
#define cpsiei() //__asm__ __volatile__("cpsie i\n")
#define cpsidi() //__asm__ __volatile__("cpsid i\n")
#define cpsief() //__asm__ __volatile__("cpsie f\n")
#define cpsidf() //__asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) /*__asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)*/
#define mfgpr(rn) /*({u32 rval; \
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})*/
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
#define isb() asm ("isb sy")
/* Data Synchronization Barrier */
#define dsb() asm("dsb sy")
/* Data Memory Barrier */
#define dmb() asm("dmb sy")
/* Memory Operations */
#define ldr(adr) ({u32 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define str(adr, val) __asm__ __volatile__(\
"str %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
#define strb(adr, val) __asm__ __volatile__(\
"strb %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
/* Count leading zeroes (clz) */
#define clz(arg) ({u8 rval; \
__asm__ __volatile__(\
"clz %0,%1"\
: "=r" (rval) : "r" (arg)\
);\
rval;\
})
#define mtcpdc(reg,val) asm("dc " #reg ",%0" : : "r" (val))
#define mtcpic(reg,val) asm("ic " #reg ",%0" : : "r" (val))
#define mtcpicall(reg) asm("ic " #reg)
#define mtcptlbi(reg) asm("tlbi " #reg)
#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val))
/* CP15 operations */
#define mfcp(reg) ({u32 rval;\
asm("mrs %0, " #reg : "=r" (rval));\
rval;\
})
#define mtcp(reg,val) asm("msr " #reg ",%0" : : "r" (val))
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XPSEUDO_ASM_GCC_H */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu.h
*
* This is the header file for the implementation of QSPIPSU driver.
* Generic QSPI interface allows for communication to any QSPI slave device.
* GQSPI contains a GENFIFO into which the bus transfers required are to be
* pushed with appropriate configuration. The controller provides TX and RX
* FIFO's and a DMA to be used for RX transfers. The controller executes each
* GENFIFO entry noting the configuration and places data on the bus as required
*
* The different options in GENFIFO are as follows:
* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
* number of bytes in transfer.
* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
* EXPONENT : e when 2^e bytes are involved in transfer.
* SPI_MODE : SPI/Dual SPI/Quad SPI
* CS : Lower or Upper CS or Both
* Bus : Lower or Upper Bus or Both
* TX : When selected, controller transmits data in IMM or fetches number of
* bytes mentioned form TX FIFO. If not selected, dummies are pumped.
* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
* of requested number of bytes. If not selected, RX data is discarded.
* Stripe : Byte stripe over lower and upper bus or not.
* Poll : Polls response to match for to a set value (used along with POLL_CFG
* registers) and then proceeds to next GENFIFO entry.
* This feature is not currently used in the driver.
*
* GENFIFO has manual and auto start options.
* All DMA requests need a 4-byte aligned destination address buffer and
* size of transfer should also be a multiple of 4.
* This driver supports DMA RX and IO RX.
*
* Initialization:
* This driver uses the GQSPI controller with RX DMA. It supports both
* interrupt and polled transfers. Manual start of GENFIFO is used.
* XQspiPsu_CfgInitialize() initializes the instance variables.
* Additional setting can be done using SetOptions/ClearOptions functions
* and SelectSlave function.
*
* Transfer:
* Polled or Interrupt transfers can be done. The transfer function needs the
* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
* This is supposed to contain the byte count and any TX/RX buffers as required.
* Flags can be used indicate further information such as whether the message
* should be striped. The transfer functions form and write GENFIFO entries,
* check the status of the transfer and report back to the application
* when done.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
* sk 03/13/15 Added IO mode support.
* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
* Clear and disbale DMA interrupts/status in abort.
* Use DMA DONE bit instead of BUSY as recommended.
*
* </pre>
*
******************************************************************************/
#ifndef _XQSPIPSU_H_ /* prevent circular inclusions */
#define _XQSPIPSU_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xqspipsu_hw.h"
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* handle the asynchronous processing for the QSPIPSU device. The application
* using this driver is expected to define a handler of this type to support
* interrupt driven mode. The handler executes in an interrupt context, so
* only minimal processing should be performed.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent holds one or more status events that have occurred.
* See the XQspiPsu_SetStatusHandler() for details on the status
* events that can be passed in the callback.
* @param ByteCount indicates how many bytes of data were successfully
* transferred. This may be less than the number of bytes
* requested if the status event indicates an error.
*/
typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
/**
* This typedef contains configuration information for a flash message.
*/
typedef struct {
u8 *TxBfrPtr;
u8 *RxBfrPtr;
u32 ByteCount;
u32 BusWidth;
u32 Flags;
} XQspiPsu_Msg;
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
u8 BusWidth; /**< Bus width available on board */
} XQspiPsu_Config;
/**
* The XQspiPsu driver instance data. The user is required to allocate a
* variable of this type for every QSPIPSU device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XQspiPsu_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
u8 *GenFifoBufferPtr; /**< Gen FIFO entries */
int TxBytes; /**< Number of bytes to transfer (state) */
int RxBytes; /**< Number of bytes left to transfer(state) */
int GenFifoEntries; /**< Number of Gen FIFO entries remaining */
u32 IsBusy; /**< A transfer is in progress (state) */
u32 ReadMode; /**< DMA or IO mode */
u32 GenFifoCS;
u32 GenFifoBus;
int NumMsg;
int MsgCnt;
int IsUnaligned;
XQspiPsu_Msg *Msg;
XQspiPsu_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
} XQspiPsu;
/***************** Macros (Inline Functions) Definitions *********************/
#define XQSPIPSU_READMODE_DMA 0x0
#define XQSPIPSU_READMODE_IO 0x1
#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3
#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1
#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2
#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3
#define XQSPIPSU_SELECT_MODE_SPI 0x1
#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2
#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4
#define XQSPIPSU_GENFIFO_CS_SETUP 0x04
#define XQSPIPSU_GENFIFO_CS_HOLD 0x03
#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2
#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4
#define XQSPIPSU_MANUAL_START_OPTION 0x8
#define XQSPIPSU_GENFIFO_EXP_START 0x100
#define XQSPIPSU_DMA_BYTES_MAX 0x10000000
#define XQSPIPSU_CLK_PRESCALE_2 0x00
#define XQSPIPSU_CLK_PRESCALE_4 0x01
#define XQSPIPSU_CLK_PRESCALE_8 0x02
#define XQSPIPSU_CLK_PRESCALE_16 0x03
#define XQSPIPSU_CLK_PRESCALE_32 0x04
#define XQSPIPSU_CLK_PRESCALE_64 0x05
#define XQSPIPSU_CLK_PRESCALE_128 0x06
#define XQSPIPSU_CLK_PRESCALE_256 0x07
#define XQSPIPSU_CR_PRESC_MAXIMUM 7
#define XQSPIPSU_CONNECTION_MODE_SINGLE 0
#define XQSPIPSU_CONNECTION_MODE_STACKED 1
#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2
/* Add more flags as required */
#define XQSPIPSU_MSG_FLAG_STRIPE 0x1
#define XQspiPsu_Select(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
#define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
#define XQspiPsu_Disable(InstancePtr) XQspiPsu_Out32((InstancePtr->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0)
#define XQspiPsu_IsManualStart(InstancePtr) ((XQspiPsu_GetOptions(InstancePtr) & XQSPIPSU_MANUAL_START_OPTION) ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
/* Initialization and reset */
XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
int XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
u32 EffectiveAddr);
void XQspiPsu_Reset(XQspiPsu *InstancePtr);
void XQspiPsu_Abort(XQspiPsu *InstancePtr);
/* Transfer functions and handlers */
int XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
unsigned NumMsg);
int XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
XQspiPsu_StatusHandler FuncPtr);
/* Configuration functions */
int XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
int XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
int XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
int XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
#ifdef __cplusplus
}
#endif
#endif /* _XQSPIPSU_H_ */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xqspipsu_hw.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspipsu_hw.h
*
* This file contains low level access funcitons using the base address
* directly without an instance.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------.
* 1.0 hk 08/21/14 First release
* hk 03/18/15 Add DMA status register masks required.
*
* </pre>
*
******************************************************************************/
#ifndef _XQSPIPSU_HW_H_ /* prevent circular inclusions */
#define _XQSPIPSU_HW_H_ /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**
* QSPI Base Address
*/
#define XQSPIPS_BASEADDR 0XFF0F0000
/**
* GQSPI Base Address
*/
#define XQSPIPSU_BASEADDR 0xFF0F0100
#define XQSPIPSU_OFFSET 0x100
/**
* Register: XQSPIPS_EN_REG
*/
#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014 )
#define XQSPIPS_EN_SHIFT 0
#define XQSPIPS_EN_WIDTH 1
#define XQSPIPS_EN_MASK 0X00000001
/**
* Register: XQSPIPSU_CFG
*/
#define XQSPIPSU_CFG_OFFSET 0X00000000
#define XQSPIPSU_CFG_MODE_EN_SHIFT 30
#define XQSPIPSU_CFG_MODE_EN_WIDTH 2
#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000
#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1
#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000
#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28
#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1
#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000
#define XQSPIPSU_CFG_ENDIAN_SHIFT 26
#define XQSPIPSU_CFG_ENDIAN_WIDTH 1
#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000
#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20
#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1
#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000
#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19
#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1
#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000
#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3
#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038
#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2
#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1
#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004
#define XQSPIPSU_CFG_CLK_POL_SHIFT 1
#define XQSPIPSU_CFG_CLK_POL_WIDTH 1
#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002
/**
* Register: XQSPIPSU_ISR
*/
#define XQSPIPSU_ISR_OFFSET 0X00000004
#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11
#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8
#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1
#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_ISR_RXFULL_SHIFT 5
#define XQSPIPSU_ISR_RXFULL_WIDTH 1
#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020
#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_ISR_TXFULL_SHIFT 3
#define XQSPIPSU_ISR_TXFULL_WIDTH 1
#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008
#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002
/**
* Register: XQSPIPSU_IER
*/
#define XQSPIPSU_IER_OFFSET 0X00000008
#define XQSPIPSU_IER_RXEMPTY_SHIFT 11
#define XQSPIPSU_IER_RXEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IER_TXEMPTY_SHIFT 8
#define XQSPIPSU_IER_TXEMPTY_WIDTH 1
#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IER_RXFULL_SHIFT 5
#define XQSPIPSU_IER_RXFULL_WIDTH 1
#define XQSPIPSU_IER_RXFULL_MASK 0X00000020
#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IER_TXFULL_SHIFT 3
#define XQSPIPSU_IER_TXFULL_WIDTH 1
#define XQSPIPSU_IER_TXFULL_MASK 0X00000008
#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002
/**
* Register: XQSPIPSU_IDR
*/
#define XQSPIPSU_IDR_OFFSET 0X0000000C
#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IDR_RXFULL_SHIFT 5
#define XQSPIPSU_IDR_RXFULL_WIDTH 1
#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IDR_TXFULL_SHIFT 3
#define XQSPIPSU_IDR_TXFULL_WIDTH 1
#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002
#define XQSPIPSU_IDR_ALL_MASK 0X0FBE
/**
* Register: XQSPIPSU_IMR
*/
#define XQSPIPSU_IMR_OFFSET 0X00000010
#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11
#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800
#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10
#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400
#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9
#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200
#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8
#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1
#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100
#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7
#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1
#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080
#define XQSPIPSU_IMR_RXFULL_SHIFT 5
#define XQSPIPSU_IMR_RXFULL_WIDTH 1
#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020
#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4
#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1
#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010
#define XQSPIPSU_IMR_TXFULL_SHIFT 3
#define XQSPIPSU_IMR_TXFULL_WIDTH 1
#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008
#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2
#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1
#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1
#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002
/**
* Register: XQSPIPSU_EN_REG
*/
#define XQSPIPSU_EN_OFFSET 0X00000014
#define XQSPIPSU_EN_SHIFT 0
#define XQSPIPSU_EN_WIDTH 1
#define XQSPIPSU_EN_MASK 0X00000001
/**
* Register: XQSPIPSU_TXD
*/
#define XQSPIPSU_TXD_OFFSET 0X0000001C
#define XQSPIPSU_TXD_SHIFT 0
#define XQSPIPSU_TXD_WIDTH 32
#define XQSPIPSU_TXD_MASK 0XFFFFFFFF
#define XQSPIPSU_TXD_DEPTH 32
/**
* Register: XQSPIPSU_RXD
*/
#define XQSPIPSU_RXD_OFFSET 0X00000020
#define XQSPIPSU_RXD_SHIFT 0
#define XQSPIPSU_RXD_WIDTH 32
#define XQSPIPSU_RXD_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_TX_THRESHOLD
*/
#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028
#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01
/**
* Register: XQSPIPSU_RX_THRESHOLD
*/
#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002C
#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6
#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003F
#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01
#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32
/**
* Register: XQSPIPSU_GPIO
*/
#define XQSPIPSU_GPIO_OFFSET 0X00000030
#define XQSPIPSU_GPIO_WP_N_SHIFT 0
#define XQSPIPSU_GPIO_WP_N_WIDTH 1
#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001
/**
* Register: XQSPIPSU_LPBK_DLY_ADJ
*/
#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1
#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2
#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3
#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007
/**
* Register: XQSPIPSU_GEN_FIFO
*/
#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040
#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0
#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20
#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFF
/**
* Register: XQSPIPSU_SEL
*/
#define XQSPIPSU_SEL_OFFSET 0X00000044
#define XQSPIPSU_SEL_SHIFT 0
#define XQSPIPSU_SEL_WIDTH 1
#define XQSPIPSU_SEL_MASK 0X00000001
/**
* Register: XQSPIPSU_FIFO_CTRL
*/
#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004C
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1
#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001
/**
* Register: XQSPIPSU_GF_THRESHOLD
*/
#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050
#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0
#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5
#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001F
#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
/**
* Register: XQSPIPSU_POLL_CFG
*/
#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1
#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000
#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8
#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8
#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00
#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0
#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8
#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FF
/**
* Register: XQSPIPSU_P_TIMEOUT
*/
#define XQSPIPSU_P_TO_OFFSET 0X00000058
#define XQSPIPSU_P_TO_VALUE_SHIFT 0
#define XQSPIPSU_P_TO_VALUE_WIDTH 32
#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_XFER_STS
*/
#define XQSPIPSU_XFER_STS_OFFSET 0X0000005C
#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0
#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32
#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_GF_SNAPSHOT
*/
#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060
#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0
#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20
#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFF
/**
* Register: XQSPIPSU_RX_COPY
*/
#define XQSPIPSU_RX_COPY_OFFSET 0X00000064
#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8
#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8
#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00
#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0
#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8
#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FF
/**
* Register: XQSPIPSU_MOD_ID
*/
#define XQSPIPSU_MOD_ID_OFFSET 0X000000FC
#define XQSPIPSU_MOD_ID_SHIFT 0
#define XQSPIPSU_MOD_ID_WIDTH 32
#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFF
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700
#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30
#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFC
/**
* Register: XQSPIPSU_QSPIDMA_DST_SIZE
*/
#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704
#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27
#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFC
/**
* Register: XQSPIPSU_QSPIDMA_DST_STS
*/
#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001E
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070C
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8
#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FC
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001
#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_STS
*/
#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002
#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FC
#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FE
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_EN
*/
#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_I_DIS
*/
#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071C
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_IMR
*/
#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002
/**
* Register: XQSPIPSU_QSPIDMA_DST_CTRL2
*/
#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3
#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4
#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000F
/**
* Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
*/
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12
#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFF
/**
* Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
*/
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFC
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32
#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFF
/*
* Generic FIFO masks
*/
#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFF
#define XQSPIPSU_GENFIFO_DATA_XFER 0x100
#define XQSPIPSU_GENFIFO_EXP 0x200
#define XQSPIPSU_GENFIFO_MODE_SPI 0x400
#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800
#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00
#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000
#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000
#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000
#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000
#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000 /* inverse is no bus */
#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000 /* And with ~MASK first */
#define XQSPIPSU_GENFIFO_TX 0x10000 /* inverse is zero pump */
#define XQSPIPSU_GENFIFO_RX 0x20000 /* inverse is RX discard */
#define XQSPIPSU_GENFIFO_STRIPE 0x40000
#define XQSPIPSU_GENFIFO_POLL 0x80000
/***************** Macros (Inline Functions) Definitions *********************/
#define XQspiPsu_In32 Xil_In32
#define XQspiPsu_Out32 Xil_Out32
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XQspiPsu_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPsu_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
#ifdef __cplusplus
}
#endif
#endif /* _XQSPIPSU_H_ */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexa53.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
******************************************************************************/
#ifndef XREG_CORTEXA53_H
#define XREG_CORTEXA53_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* GPRs */
#define XREG_GPR0 x0
#define XREG_GPR1 x1
#define XREG_GPR2 x2
#define XREG_GPR3 x3
#define XREG_GPR4 x4
#define XREG_GPR5 x5
#define XREG_GPR6 x6
#define XREG_GPR7 x7
#define XREG_GPR8 x8
#define XREG_GPR9 x9
#define XREG_GPR10 x10
#define XREG_GPR11 x11
#define XREG_GPR12 x12
#define XREG_GPR13 x13
#define XREG_GPR14 x14
#define XREG_GPR15 x15
#define XREG_GPR16 x16
#define XREG_GPR17 x17
#define XREG_GPR18 x18
#define XREG_GPR19 x19
#define XREG_GPR20 x20
#define XREG_GPR21 x21
#define XREG_GPR22 x22
#define XREG_GPR23 x23
#define XREG_GPR24 x24
#define XREG_GPR25 x25
#define XREG_GPR26 x26
#define XREG_GPR27 x27
#define XREG_GPR28 x28
#define XREG_GPR29 x29
#define XREG_GPR30 x30
#define XREG_CPSR cpsr
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_MODE_BITS 0x1F
#define XREG_CPSR_EL3h_MODE 0xD
#define XREG_CPSR_EL3t_MODE 0xC
#define XREG_CPSR_EL2h_MODE 0x9
#define XREG_CPSR_EL2t_MODE 0x8
#define XREG_CPSR_EL1h_MODE 0x5
#define XREG_CPSR_EL1t_MODE 0x4
#define XREG_CPSR_EL0t_MODE 0x0
#define XREG_CPSR_IRQ_ENABLE 0x80
#define XREG_CPSR_FIQ_ENABLE 0x40
#define XREG_CPSR_N_BIT 0x80000000U
#define XREG_CPSR_Z_BIT 0x40000000U
#define XREG_CPSR_C_BIT 0x20000000U
#define XREG_CPSR_V_BIT 0x10000000U
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24U)
#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (0X00000001U<<23U)
#define XREG_FPSID_ARCH_BIT (16U)
#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8U)
#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4U)
#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0U)
#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
#define XREG_FPSCR_QC (0X00000001U << 27U)
#define XREG_FPSCR_AHP (0X00000001U << 26U)
#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
#define XREG_FPSCR_RMODE_BIT (22U)
#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20U)
#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16U)
#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (0X00000001U << 7U)
#define XREG_FPSCR_IXC (0X00000001U << 4U)
#define XREG_FPSCR_UFC (0X00000001U << 3U)
#define XREG_FPSCR_OFC (0X00000001U << 2U)
#define XREG_FPSCR_DZC (0X00000001U << 1U)
#define XREG_FPSCR_IOC (0X00000001U << 0U)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28U)
#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24U)
#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20U)
#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16U)
#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U)
#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8U)
#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4U)
#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0U)
#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (0X00000001U << 31U)
#define XREG_FPEXC_EN (0X00000001U << 30U)
#define XREG_FPEXC_DEX (0X00000001U << 29U)
#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXA53_H */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xscugic.h
*
* The generic interrupt controller driver component.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 1 and 31 inclusive with
* default of 1 being the highest priority interrupt source. The priorities
* of the various sources can be dynamically altered as needed through
* hardware configuration.
*
* The generic interrupt controller supports the following
* features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - assigning desired priority to interrupt source if default is not
* acceptable.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xscugic_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table. The user should populate the
* vector table with handlers and callbacks at run-time using the
* XScuGic_Connect() and XScuGic_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an
* argument to be passed to the handler when an interrupt occurs. The
* user must use XScuGic_Connect() when the interrupt handler takes an
* argument other than the base address.
*
* <b>Nested Interrupts Processing</b>
*
* Nested interrupts are not supported by this driver.
*
* NOTE:
* The generic interrupt controller is not a part of the snoop control unit
* as indicated by the prefix "scu" in the name of the driver.
* It is an independent module in APU.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 1.00a drg 01/19/00 First release
* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
* The HandlerTable (of type XScuGic_VectorTableEntry) is
* moved to XScuGic_Config structure from XScuGic structure.
*
* The "Config" entry in XScuGic structure is made as
* pointer for better efficiency.
*
* A new file named as xscugic_hw.c is now added. It is
* to implement low level driver routines without using
* any xscugic instance pointer. They are useful when the
* user wants to use xscugic through device id or
* base address. The driver routines provided are explained
* below.
* XScuGic_DeviceInitialize that takes device id as
* argument and initializes the device (without calling
* XScuGic_CfgInitialize).
* XScuGic_DeviceInterruptHandler that takes device id
* as argument and calls appropriate handlers from the
* HandlerTable.
* XScuGic_RegisterHandler that registers a new handler
* by taking xscugic hardware base address as argument.
* LookupConfigByBaseAddress is used to return the
* corresponding config structure from XScuGic_ConfigTable
* based on the scugic base address passed.
* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
* structure.
* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
* *_hw.h
* Added APIs
* - XScuGic_SetPriTrigTypeByDistAddr()
* - XScuGic_GetPriTrigTypeByDistAddr()
* (CR 702687)
* Added support to direct interrupts to the appropriate CPU. Earlier
* interrupts were directed to CPU1 (hard coded). Now depending
* upon the CPU selected by the user (xparameters.h), interrupts
* will be directed to the relevant CPU. This fixes CR 699688.
* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
* This is fix for CR#705621.
* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
* xparameters.h. Fix for CR's 690505, 708928 & 719359.
* 2.0 adk 12/10/13 Updated as per the New Tcl API's
* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_H /* prevent circular inclusions */
#define XSCUGIC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xil_io.h"
#include "xscugic_hw.h"
#include "xil_exception.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* The following data type defines each entry in an interrupt vector table.
* The callback reference is the base address of the interrupting device
* for the low level driver and an instance pointer for the high level driver.
*/
typedef struct
{
Xil_InterruptHandler Handler;
void *CallBackRef;
} XScuGic_VectorTableEntry;
/**
* This typedef contains configuration information for the device.
*/
typedef struct
{
u16 DeviceId; /**< Unique ID of device */
u32 CpuBaseAddress; /**< CPU Interface Register base address */
u32 DistBaseAddress; /**< Distributor Register base address */
XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
Vector table of interrupt handlers */
} XScuGic_Config;
/**
* The XScuGic driver instance data. The user is required to allocate a
* variable of this type for every intc device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct
{
XScuGic_Config *Config; /**< Configuration table entry */
u32 IsReady; /**< Device is initialized and ready */
u32 UnhandledInterrupts; /**< Intc Statistics */
} XScuGic;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Write the given CPU Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
((u32)(Data))))
/****************************************************************************/
/**
*
* Read the given CPU Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
/****************************************************************************/
/**
*
* Write the given Distributor Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
((u32)(Data))))
/****************************************************************************/
/**
*
* Read the given Distributor Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
/************************** Function Prototypes ******************************/
/*
* Required functions in xscugic.c
*/
s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
Xil_InterruptHandler Handler, void *CallBackRef);
void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
u32 EffectiveAddr);
s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
u8 *Priority, u8 *Trigger);
void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
u8 Priority, u8 Trigger);
/*
* Initialization functions in xscugic_sinit.c
*/
XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
/*
* Interrupt functions in xscugic_intr.c
*/
void XScuGic_InterruptHandler(XScuGic *InstancePtr);
/*
* Self-test functions in xscugic_selftest.c
*/
s32 XScuGic_SelfTest(XScuGic *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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@ -0,0 +1,637 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xscugic_hw.h
*
* This header file contains identifiers and HW access functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* The driver functions/APIs are defined in xscugic.h.
*
* This GIC device has two parts, a distributor and CPU interface(s). Each part
* has separate register definition sections.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------------
* 1.00a drg 01/19/10 First release
* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
* added to enable or disable interrupts based on
* Distributor Register base address. Normally users use
* XScuGic instance and call XScuGic_Enable or
* XScuGic_Disable to enable/disable interrupts. These
* new macros are provided when user does not want to
* use an instance pointer but still wants to enable or
* disable interrupts.
* Function prototypes for functions (present in newly
* added file xscugic_hw.c) are added.
* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
* 702687).
* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
* XScuGic_SetPriTrigTypeByDistAddr and
* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
* Zynq Ultrascale Mp
* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
#define XSCUGIC_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xil_exception.h"
/************************** Constant Definitions *****************************/
/*
* The maximum number of interrupts supported by the hardware.
*/
#ifdef __ARM_NEON__
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
#else
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
#endif
/*
* The maximum priority value that can be used in the GIC.
*/
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
/** @name Distributor Interface Register Map
*
* Define the offsets from the base address for all Distributor registers of
* the interrupt controller, some registers may be reserved in the hardware
* device.
* @{
*/
#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
Register */
#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
Type Register */
#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
Register */
#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
Register */
#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
Register */
#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
Register */
#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
Register */
#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
Register 0x800-0x8FB */
#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
Register 0xC00-0xCFC */
#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
0xd04-0xd7C */
#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
Register */
#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
Interrupt Register */
#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
/* @} */
/** @name Distributor Enable Register
* Controls if the distributor response to external interrupt inputs.
* @{
*/
#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
/* @} */
/** @name Interrupt Controller Type Register
* @{
*/
#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
Shared Peripheral
Interrupts*/
#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
/* @} */
/** @name Implementor ID Register
* Implementor and revision information.
* @{
*/
#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
/* @} */
/** @name Interrupt Security Registers
* Each bit controls the security level of an interrupt, either secure or non
* secure. These registers can only be accessed using secure read and write.
* There are registers for each of the CPU interfaces at offset 0x080. A
* register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x084.
* @{
*/
#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Enable Set Register
* Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
* enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
* bit to 0.
* There are registers for each of the CPU interfaces at offset 0x100. With up
* to 8 registers aliased to the same address. A register set for the SPI
* interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x104.
* @{
*/
#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Enable Clear Register
* Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
* enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
* sets the corresponding bit to 0.
* There are registers for each of the CPU interfaces at offset 0x180. With up
* to 8 registers aliased to the same address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x184.
* @{
*/
#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Pending Set Register
* Each bit controls the Pending or Active and Pending state of an interrupt, a
* 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
* an interrupt to the pending state.
* There are registers for each of the CPU interfaces at offset 0x200. With up
* to 8 registers aliased to the same address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x204.
* @{
*/
#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Pending Clear Register
* Each bit can clear the Pending or Active and Pending state of an interrupt, a
* 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
* clears the pending state of an interrupt.
* There are registers for each of the CPU interfaces at offset 0x280. With up
* to 8 registers aliased to the same address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x284.
* @{
*/
#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Active Status Register
* Each bit provides the Active status of an interrupt, a
* 0 is not Active, a 1 is Active. This is a read only register.
* There are registers for each of the CPU interfaces at offset 0x300. With up
* to 8 registers aliased to each address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 32 of these registers staring at location 0x380.
* @{
*/
#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
INT_ID */
/* @} */
/** @name Priority Level Register
* Each byte in a Priority Level Register sets the priority level of an
* interrupt. Reading the register provides the priority level of an interrupt.
* There are registers for each of the CPU interfaces at offset 0x400 through
* 0x41C. With up to 8 registers aliased to each address.
* 0 is highest priority, 0xFF is lowest.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 255 of these registers staring at location 0x420.
* @{
*/
#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
INT_ID */
#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
actually the lowest priority*/
/* @} */
/** @name SPI Target Register 0x800-0x8FB
* Each byte references a separate SPI and programs which of the up to 8 CPU
* interfaces are sent a Pending interrupt.
* There are registers for each of the CPU interfaces at offset 0x800 through
* 0x81C. With up to 8 registers aliased to each address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 255 of these registers staring at location 0x820.
*
* This driver does not support multiple CPU interfaces. These are included
* for complete documentation.
* @{
*/
#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
#define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/
#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
/* @} */
/** @name Interrupt Configuration Register 0xC00-0xCFC
* The interrupt configuration registers program an SFI to be active HIGH level
* sensitive or rising edge sensitive.
* Each bit pair describes the configuration for an INT_ID.
* SFI Read Only b10 always
* PPI Read Only depending on how the PPIs are configured.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive
* SPI LSB is read only.
* b01 Active HIGH level sensitive
* b11 Rising edge sensitive/
* There are registers for each of the CPU interfaces at offset 0xC00 through
* 0xC04. With up to 8 registers aliased to each address.
* A register set for the SPI interrupts is available to all CPU interfaces.
* There are up to 255 of these registers staring at location 0xC08.
* @{
*/
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
/* @} */
/** @name PPI Status Register
* Enables an external AMBA master to access the status of the PPI inputs.
* A CPU can only read the status of its local PPI signals and cannot read the
* status for other CPUs.
* This register is aliased for each CPU interface.
* @{
*/
#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
/* @} */
/** @name SPI Status Register 0xd04-0xd7C
* Enables an external AMBA master to access the status of the SPI inputs.
* There are up to 63 registers if the maximum number of SPI inputs are
* configured.
* @{
*/
#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
input */
/* @} */
/** @name AHB Configuration Register
* Provides the status of the CFGBIGEND input signal and allows the endianess
* of the GIC to be set.
* @{
*/
#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
1-GIC uses Big Endian */
#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
1-use the AHB_END bit */
#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
/* @} */
/** @name Software Triggered Interrupt Register
* Controls issueing of software interrupts.
* @{
*/
#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
b00-Use the target List
b01-All CPUs except requester
b10-To Requester
b11-reserved */
#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
signaled to the CPU*/
/* @} */
/** @name CPU Interface Register Map
*
* Define the offsets from the base address for all CPU registers of the
* interrupt controller, some registers may be reserved in the hardware device.
* @{
*/
#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
Register */
#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
Register */
#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
Binary Point Register */
/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
* to. */
/* @} */
/** @name Control Register
* CPU Interface Control register definitions
* All bits are defined here although some are not available in the non-secure
* mode.
* @{
*/
#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
0=separate registers,
1=both use bin_pt_s */
#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
interrupts,
0= use IRQ for both,
1=Use FIQ for secure, IRQ for non*/
#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
/* @} */
/** @name Priority Mask Register
* Priority Mask register definitions
* The CPU interface does not send interrupt if the level of the interrupt is
* lower than the level of the register.
* @{
*/
/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
/* @} */
/** @name Binary Point Register
* Binary Point register definitions
* @{
*/
#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
Value Secure Non-secure
b000 0xFE 0xFF
b001 0xFC 0xFE
b010 0xF8 0xFC
b011 0xF0 0xF8
b100 0xE0 0xF0
b101 0xC0 0xE0
b110 0x80 0xC0
b111 0x00 0x80
*/
/*@}*/
/** @name Interrupt Acknowledge Register
* Interrupt Acknowledge register definitions
* Identifies the current Pending interrupt, and the CPU ID for software
* interrupts.
*/
#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
/* @} */
/** @name End of Interrupt Register
* End of Interrupt register definitions
* Allows the CPU to signal the GIC when it completes an interrupt service
* routine.
*/
#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
/* @} */
/** @name Running Priority Register
* Running Priority register definitions
* Identifies the interrupt priority level of the highest priority active
* interrupt.
*/
#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
/* @} */
/*
* Highest Pending Interrupt register definitions
* Identifies the interrupt priority of the highest priority pending interupt
*/
#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Read the Interrupt Configuration Register offset for an interrupt id.
*
* @param InterruptID is the interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
/****************************************************************************/
/**
*
* Read the Interrupt Priority Register offset for an interrupt id.
*
* @param InterruptID is the interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
/****************************************************************************/
/**
*
* Read the SPI Target Register offset for an interrupt id.
*
* @param InterruptID is the interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
/****************************************************************************/
/**
*
* Read the Interrupt Clear-Enable Register offset for an interrupt ID
*
* @param Register is the register offset for the clear/enable bank.
* @param InterruptID is the interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
((Register) + (((InterruptID)/32U) * 4U))
/****************************************************************************/
/**
*
* Read the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/****************************************************************************/
/**
*
* Write the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
/****************************************************************************/
/**
*
* Enable specific interrupt(s) in the interrupt controller.
*
* @param DistBaseAddress is the Distributor Register base address of the
* device
* @param Int_Id is the ID of the interrupt source and should be in the
* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
*
* @return None.
*
* @note C-style signature:
* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
*
*****************************************************************************/
#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
XScuGic_WriteReg((DistBaseAddress), \
XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
(0x00000001U << ((Int_Id) % 32U)))
/****************************************************************************/
/**
*
* Disable specific interrupt(s) in the interrupt controller.
*
* @param DistBaseAddress is the Distributor Register base address of the
* device
* @param Int_Id is the ID of the interrupt source and should be in the
* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
*
*
* @return None.
*
* @note C-style signature:
* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
*
*****************************************************************************/
#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
XScuGic_WriteReg((DistBaseAddress), \
XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
(0x00000001U << ((Int_Id) % 32U)))
/************************** Function Prototypes ******************************/
void XScuGic_DeviceInterruptHandler(void *DeviceId);
s32 XScuGic_DeviceInitialize(u32 DeviceId);
void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
Xil_InterruptHandler Handler, void *CallBackRef);
void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 Priority, u8 Trigger);
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
u8 *Priority, u8 *Trigger);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsdps.h
*
* This file contains the implementation of XSdPs driver.
* This driver is used initialize read from and write to the SD card.
* Features such as switching bus width to 4-bit and switching to high speed,
* changing clock frequency, block size etc. are supported.
* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
* is done using 1-bit bus width and 400KHz clock frequency.
* SD commands are classified as broadcast and addressed. Commands can be
* those with response only (using only command line) or
* response + data (using command and data lines).
* Only one command can be sent at a time. During a data transfer however,
* when dsta lines are in use, certain commands (which use only the command
* line) can be sent, most often to obtain status.
* This driver does not support multi card slots at present.
*
* Intialization:
* This includes initialization on the host controller side to select
* clock frequency, bus power and default transfer related parameters.
* The default voltage is 3.3V.
* On the SD card side, the initialization and identification state diagram is
* implemented. This resets the card, gives it a unique address/ID and
* identifies key card related specifications.
*
* Data transfer:
* The SD card is put in tranfer state to read from or write to it.
* The default block size is 512 bytes and if supported,
* default bus width is 4-bit and bus speed is High speed.
* The read and write functions are implemented in polled mode using ADMA2.
*
* At any point, when key parameters such as block size or
* clock/speed or bus width are modified, this driver takes care of
* maintaining the same selection on host and card.
* All error bits in host controller are monitored by the driver and in the
* event one of them is set, driver will clear the interrupt status and
* communicate failure to the upper layer.
*
* File system use:
* This driver can be used with xilffs library to read and write files to SD.
* (Please refer to procedure in diskio.c). The file system read/write example
* in polled mode can used for reference.
*
* There is no example for using SD driver without file system at present.
* However, the driver can be used without the file system. The glue layer
* in filesytem can be used as reference for the same. The block count
* passed to the read/write function in one call is limited by the ADMA2
* descriptor table and hence care will have to be taken to call read/write
* API's in a loop for large file sizes.
*
* Interrupt mode is not supported because it offers no improvement when used
* with file system.
*
* eMMC support:
* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
* The features of eMMC supported by the driver will depend on those supported
* by the host controller. The current driver supports read/write on eMMC card
* using 4-bit and high speed mode currently.
*
* Features not supported include - card write protect, password setting,
* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
* 64-bit addressed ADMA2, erase/pre-erase commands.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00a hk/sg 10/17/13 Initial release
* 2.0 hk 03/07/14 Version number revised.
* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
* Add sleep for microblaze designs. CR# 781117.
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
* 2.3 sk 09/23/14 Send command for relative card address
* when re-initialization is done.CR# 819614.
* Use XSdPs_Change_ClkFreq API whenever changing
* clock.CR# 816586.
* 2.4 sk 12/04/14 Added support for micro SD without
* WP/CD. CR# 810655.
* Checked for DAT Inhibit mask instead of CMD
* Inhibit mask in Cmd Transfer API.
* Added Support for SD Card v1.0
*
* </pre>
*
******************************************************************************/
#ifndef SDPS_H_
#define SDPS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xstatus.h"
#include "xsdps_hw.h"
#include <string.h>
/************************** Constant Definitions *****************************/
#define XSDPS_CLK_400_KHZ 400000 /**< 400 KHZ */
#define XSDPS_CLK_50_MHZ 50000000 /**< 50 MHZ */
#define CT_MMC 0x1 /**< MMC Card */
#define CT_SD1 0x2 /**< SD ver 1 */
#define CT_SD2 0x3 /**< SD ver 2 */
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u32 CardDetect; /**< Card Detect */
u32 WriteProtect; /**< Write Protect */
} XSdPs_Config;
/*
* ADMA2 descriptor table
*/
typedef struct {
u16 Attribute; /**< Attributes of descriptor */
u16 Length; /**< Length of current dma transfer */
u32 Address; /**< Address of current dma transfer */
} XSdPs_Adma2Descriptor;
/**
* The XSdPs driver instance data. The user is required to allocate a
* variable of this type for every SD device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XSdPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u32 Host_Caps; /**< Capabilities of host controller */
u32 HCS; /**< High capacity support in card */
u32 CardID[4]; /**< Card ID */
u32 RelCardAddr; /**< Relative Card Address */
u32 CardType; /**< Card Type(version) */
/**< ADMA Descriptors */
#ifdef __ICCARM__
#pragma data_alignment = 32
XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
#pragma data_alignment = 4
#else
XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
#endif
} XSdPs;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr);
int XSdPs_SdCardInitialize(XSdPs *InstancePtr);
int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
int XSdPs_Select_Card (XSdPs *InstancePtr);
int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
int XSdPs_Change_BusWidth(XSdPs *InstancePtr);
int XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
int XSdPs_Pullup(XSdPs *InstancePtr);
int XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
#ifdef __cplusplus
}
#endif
#endif /* SD_H_ */

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/******************************************************************************
*
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xsdps_hw.h
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
* functions are defined in xsdps.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00a hk/sg 10/17/13 Initial release
*
* </pre>
*
******************************************************************************/
#ifndef SD_HW_H_
#define SD_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets from the base address of an SD device.
* @{
*/
#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00 /**< SDMA System Address
Register */
#define XSDPS_BLK_SIZE_OFFSET 0x04 /**< Block Size Register */
#define XSDPS_BLK_CNT_OFFSET 0x06 /**< Block Count Register */
#define XSDPS_ARGMT_OFFSET 0x08 /**< Argument Register */
#define XSDPS_XFER_MODE_OFFSET 0x0C /**< Transfer Mode Register */
#define XSDPS_CMD_OFFSET 0x0E /**< Command Register */
#define XSDPS_RESP0_OFFSET 0x10 /**< Response0 Register */
#define XSDPS_RESP1_OFFSET 0x14 /**< Response1 Register */
#define XSDPS_RESP2_OFFSET 0x18 /**< Response2 Register */
#define XSDPS_RESP3_OFFSET 0x1C /**< Response3 Register */
#define XSDPS_BUF_DAT_PORT_OFFSET 0x20 /**< Buffer Data Port */
#define XSDPS_PRES_STATE_OFFSET 0x24 /**< Present State */
#define XSDPS_HOST_CTRL1_OFFSET 0x28 /**< Host Control 1 */
#define XSDPS_POWER_CTRL_OFFSET 0x29 /**< Power Control */
#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2A /**< Block Gap Control */
#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2B /**< Wake Up Control */
#define XSDPS_CLK_CTRL_OFFSET 0x2C /**< Clock Control */
#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2E /**< Timeout Control */
#define XSDPS_SW_RST_OFFSET 0x2F /**< Software Reset */
#define XSDPS_NORM_INTR_STS_OFFSET 0x30 /**< Normal Interrupt
Status Register */
#define XSDPS_ERR_INTR_STS_OFFSET 0x32 /**< Error Interrupt
Status Register */
#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34 /**< Normal Interrupt
Status Enable Register */
#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36 /**< Error Interrupt
Status Enable Register */
#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38 /**< Normal Interrupt
Signal Enable Register */
#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3A /**< Error Interrupt
Signal Enable Register */
#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3C /**< Auto CMD12 Error Status
Register */
#define XSDPS_HOST_CTRL2_OFFSET 0x3E /**< Host Control2 Register */
#define XSDPS_CAPS_OFFSET 0x40 /**< Capabilities Register */
#define XSDPS_CAPS_EXT_OFFSET 0x44 /**< Capabilities Extended */
#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48 /**< Maximum Current
Capabilities Register */
#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4C /**< Maximum Current
Capabilities Ext Register */
#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52 /**< Force Event for
Error Interrupt Status */
#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50 /**< Auto CM12 Error Interrupt
Status Register */
#define XSDPS_ADMA_ERR_STS_OFFSET 0x54 /**< ADMA Error Status
Register */
#define XSDPS_ADMA_SAR_OFFSET 0x58 /**< ADMA System Address
Register */
#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5C /**< ADMA System Address
Extended Register */
#define XSDPS_PRE_VAL_1_OFFSET 0x60 /**< Preset Value Register */
#define XSDPS_PRE_VAL_2_OFFSET 0x64 /**< Preset Value Register */
#define XSDPS_PRE_VAL_3_OFFSET 0x68 /**< Preset Value Register */
#define XSDPS_PRE_VAL_4_OFFSET 0x6C /**< Preset Value Register */
#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0 /**< Shared Bus Control
Register */
#define XSDPS_SLOT_INTR_STS_OFFSET 0xFC /**< Slot Interrupt Status
Register */
#define XSDPS_HOST_CTRL_VER_OFFSET 0xFE /**< Host Controller Version
Register */
/* @} */
/** @name Control Register - Host control, Power control,
* Block Gap control and Wakeup control
*
* This register contains bits for various configuration options of
* the SD host controller. Read/Write apart from the reserved bits.
* @{
*/
#define XSDPS_HC_LED_MASK 0x00000001 /**< LED Control */
#define XSDPS_HC_WIDTH_MASK 0x00000002 /**< Bus width */
#define XSDPS_HC_SPEED_MASK 0x00000004 /**< High Speed */
#define XSDPS_HC_DMA_MASK 0x00000018 /**< DMA Mode Select */
#define XSDPS_HC_DMA_SDMA_MASK 0x00000000 /**< SDMA Mode */
#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008 /**< ADMA1 Mode */
#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010 /**< ADMA2 Mode - 32 bit */
#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018 /**< ADMA2 Mode - 64 bit */
#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020 /**< Bus width - 8 bit */
#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040 /**< Card Detect Tst Lvl */
#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080 /**< Card Detect Sig Det */
#define XSDPS_PC_BUS_PWR_MASK 0x00000001 /**< Bus Power Control */
#define XSDPS_PC_BUS_VSEL_MASK 0x0000000E /**< Bus Voltage Select */
#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000E /**< Bus Voltage 3.3V */
#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000C /**< Bus Voltage 3.0V */
#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000A /**< Bus Voltage 1.8V */
#define XSDPS_BGC_STP_REQ_MASK 0x00000001 /**< Block Gap Stop Req */
#define XSDPS_BGC_CNT_REQ_MASK 0x00000002 /**< Block Gap Cont Req */
#define XSDPS_BGC_RWC_MASK 0x00000004 /**< Block Gap Rd Wait */
#define XSDPS_BGC_INTR_MASK 0x00000008 /**< Block Gap Intr */
#define XSDPS_BGC_SPI_MODE_MASK 0x00000010 /**< Block Gap SPI Mode */
#define XSDPS_BGC_BOOT_EN_MASK 0x00000020 /**< Block Gap Boot Enb */
#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040 /**< Block Gap Alt BootEn */
#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080 /**< Block Gap Boot Ack */
#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001 /**< Wakeup Card Intr */
#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002 /**< Wakeup Card Insert */
#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004 /**< Wakeup Card Removal */
/* @} */
/** @name Control Register - Clock control, Timeout control & Software reset
*
* This register contains bits for configuration options of clock, timeout and
* software reset.
* Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
* @{
*/
#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001
#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002
#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004
#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020
#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0
#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00
#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000
#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000
#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000
#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000
#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800
#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400
#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200
#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100
#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000
#define XSDPS_TC_CNTR_VAL_MASK 0x0000000F
#define XSDPS_SWRST_ALL_MASK 0x00000001
#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002
#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004
#define XSDPS_CC_MAX_NUM_OF_DIV 9
#define XSDPS_CC_DIV_SHIFT 8
/* @} */
/** @name SD Interrupt Registers
*
* <b> Normal and Error Interrupt Status Register </b>
* This register shows the normal and error interrupt status.
* Status enable register affects reads of this register.
* If Signal enable register is set and the corresponding status bit is set,
* interrupt is generated.
* Write to clear except
* Error_interrupt and Card_Interrupt bits - Read only
*
* <b> Normal and Error Interrupt Status Enable Register </b>
* Setting this register bits enables Interrupt status.
* Read/Write except Fixed_to_0 bit (Read only)
*
* <b> Normal and Error Interrupt Signal Enable Register </b>
* This register is used to select which interrupt status is
* indicated to the Host System as the interrupt.
* Read/Write except Fixed_to_0 bit (Read only)
*
* All three registers have same bit definitions
* @{
*/
#define XSDPS_INTR_CC_MASK 0x00000001 /**< Command Complete */
#define XSDPS_INTR_TC_MASK 0x00000002 /**< Transfer Complete */
#define XSDPS_INTR_BGE_MASK 0x00000004 /**< Block Gap Event */
#define XSDPS_INTR_DMA_MASK 0x00000008 /**< DMA Interrupt */
#define XSDPS_INTR_BWR_MASK 0x00000010 /**< Buffer Write Ready */
#define XSDPS_INTR_BRR_MASK 0x00000020 /**< Buffer Read Ready */
#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040 /**< Card Insert */
#define XSDPS_INTR_CARD_REM_MASK 0x00000080 /**< Card Remove */
#define XSDPS_INTR_CARD_MASK 0x00000100 /**< Card Interrupt */
#define XSDPS_INTR_INT_A_MASK 0x00000200 /**< INT A Interrupt */
#define XSDPS_INTR_INT_B_MASK 0x00000400 /**< INT B Interrupt */
#define XSDPS_INTR_INT_C_MASK 0x00000800 /**< INT C Interrupt */
#define XSDPS_INTR_RE_TUNING_MASK 0x00001000 /**< Re-Tuning Interrupt */
#define XSDPS_INTR_BOOT_TERM_MASK 0x00002000 /**< Boot Terminate
Interrupt */
#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00004000 /**< Boot Ack Recv
Interrupt */
#define XSDPS_INTR_ERR_MASK 0x00008000 /**< Error Interrupt */
#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFF
#define XSDPS_INTR_ERR_CT_MASK 0x00000001 /**< Command Timeout
Error */
#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002 /**< Command CRC Error */
#define XSDPS_INTR_ERR_CEB_MASK 0x00000004 /**< Command End Bit
Error */
#define XSDPS_INTR_ERR_CI_MASK 0x00000008 /**< Command Index Error */
#define XSDPS_INTR_ERR_DT_MASK 0x00000010 /**< Data Timeout Error */
#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020 /**< Data CRC Error */
#define XSDPS_INTR_ERR_DEB_MASK 0x00000040 /**< Data End Bit Error */
#define XSDPS_INTR_ERR_I_LMT_MASK 0x00000080 /**< Current Limit Error */
#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100 /**< Auto CMD12 Error */
#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200 /**< ADMA Error */
#define XSDPS_INTR_ERR_TR_MASK 0x00001000 /**< Tuning Error */
#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000 /**< Vendor Specific
Error */
#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FF /**< Mask for error bits */
/* @} */
/** @name Block Size and Block Count Register
*
* This register contains the block count for current transfer,
* block size and SDMA buffer size.
* Read/Write except for reserved bits.
* @{
*/
#define XSDPS_BLK_SIZE_MASK 0x00000FFF /**< Transfer Block Size */
#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000 /**< Host SDMA Buffer Size */
#define XSDPS_BLK_CNT_MASK 0x0000FFFF /**< Block Count for
Current Transfer */
/* @} */
/** @name Transfer Mode and Command Register
*
* The Transfer Mode register is used to control the data transfers and
* Command register is used for command generation
* Read/Write except for reserved bits.
* @{
*/
#define XSDPS_TM_DMA_EN_MASK 0x00000001 /**< DMA Enable */
#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002 /**< Block Count Enable */
#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004 /**< Auto CMD12 Enable */
#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010 /**< Data Transfer
Direction Select */
#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020 /**< Multi/Single
Block Select */
#define XSDPS_CMD_RESP_SEL_MASK 0x00000003 /**< Response Type
Select */
#define XSDPS_CMD_RESP_NONE_MASK 0x00000000 /**< No Response */
#define XSDPS_CMD_RESP_L136_MASK 0x00000001 /**< Response length 138 */
#define XSDPS_CMD_RESP_L48_MASK 0x00000002 /**< Response length 48 */
#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003 /**< Response length 48 &
check busy after
response */
#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008 /**< Command CRC Check
Enable */
#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010 /**< Command Index Check
Enable */
#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020 /**< Data Present Select */
#define XSDPS_CMD_TYPE_MASK 0x000000C0 /**< Command Type */
#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000 /**< CMD Type - Normal */
#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040 /**< CMD Type - Suspend */
#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080 /**< CMD Type - Resume */
#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0 /**< CMD Type - Abort */
#define XSDPS_CMD_MASK 0x00003F00 /**< Command Index Mask -
Set to CMD0-63,
AMCD0-63 */
/* @} */
/** @name Capabilities Register
*
* Capabilities register is a read only register which contains
* information about the host controller.
* Sufficient if read once after power on.
* Read Only
* @{
*/
#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003F /**< Timeout clock freq
select */
#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080 /**< Timeout clock unit -
MHz/KHz */
#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000 /**< Max block length */
#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000 /**< Max block 512 bytes */
#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000 /**< Extended media bus */
#define XSDPS_CAP_ADMA2_MASK 0x00080000 /**< ADMA2 support */
#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000 /**< High speed support */
#define XSDPS_CAP_SDMA_MASK 0x00400000 /**< SDMA support */
#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000 /**< Suspend/Resume
support */
#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000 /**< 3.3V support */
#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000 /**< 3.0V support */
#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000 /**< 1.8V support */
#define XSDPS_CAP_INTR_MODE_MASK 0x08000000 /**< Interrupt mode
support */
#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000 /**< 64 bit system bus
support */
#define XSDPS_CAP_SPI_MODE_MASK 0x20000000 /**< SPI mode */
#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x20000000 /**< SPI block mode */
/* @} */
/** @name Present State Register
*
* Gives the current status of the host controller
* Read Only
* @{
*/
#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001 /**< Command inhibit - CMD */
#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002 /**< Command Inhibit - DAT */
#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004 /**< DAT line active */
#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100 /**< Write transfer active */
#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200 /**< Read transfer active */
#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400 /**< Buffer write enable */
#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800 /**< Buffer read enable */
#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000 /**< Card inserted */
#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000 /**< Card state stable */
#define XSDPS_PSR_CARD_DPL_MASK 0x00040000 /**< Card detect pin level */
#define XSDPS_PSR_WPS_PL_MASK 0x00080000 /**< Write protect switch
pin level */
/* @} */
/** @name Block size mask for 512 bytes
*
* Block size mask for 512 bytes - This is the default block size.
* @{
*/
#define XSDPS_BLK_SIZE_512_MASK 0x200
/* @} */
/** @name Commands
*
* Constant definitions for commands and response related to SD
* @{
*/
#define XSDPS_APP_CMD_PREFIX 0x8000
#define CMD0 0x0000
#define CMD1 0x0100
#define CMD2 0x0200
#define CMD3 0x0300
#define CMD4 0x0400
#define CMD5 0x0500
#define CMD6 0x0600
#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600)
#define CMD7 0x0700
#define CMD8 0x0800
#define CMD9 0x0900
#define CMD10 0x0A00
#define CMD12 0x0C00
#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00)
#define CMD16 0x1000
#define CMD17 0x1100
#define CMD18 0x1200
#define CMD23 0x1700
#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700)
#define CMD24 0x1800
#define CMD25 0x1900
#define CMD41 0x2900
#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900)
#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00)
#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300)
#define CMD52 0x3400
#define CMD55 0x3700
#define CMD58 0x3A00
#define RESP_NONE XSDPS_CMD_RESP_NONE_MASK
#define RESP_R1 XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \
XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R1B XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R2 XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK
#define RESP_R3 XSDPS_CMD_RESP_L48_MASK
#define RESP_R6 XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
/* @} */
/** @name ADMA2 Descriptor related definitions
*
* ADMA2 Descriptor related definitions
* @{
*/
#define XSDPS_DESC_MAX_LENGTH 65536
#define XSDPS_DESC_VALID (0x1 << 0)
#define XSDPS_DESC_END (0x1 << 1)
#define XSDPS_DESC_INT (0x1 << 2)
#define XSDPS_DESC_TRAN (0x2 << 4)
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XSdPs_In32 Xil_In32
#define XSdPs_Out32 Xil_Out32
#define XSdPs_In16 Xil_In16
#define XSdPs_Out16 Xil_Out16
#define XSdPs_In8 Xil_In8
#define XSdPs_Out8 Xil_Out8
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg(BaseAddress, RegOffset) \
XSdPs_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
XSdPs_In16((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
XSdPs_In8((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
/***************************************************************************/
/**
* Macro to get present status register
*
* @param BaseAddress contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
#define XSdPs_GetPresentStatusReg(BaseAddress) \
XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* SD_HW_H_ */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xspips.h Normal file
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@ -0,0 +1,691 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xspips.h
*
* This file contains the implementation of the XSpiPs driver. It works for
* both the master and slave mode. User documentation for the driver functions
* is contained in this file in the form of comment blocks at the front of each
* function.
*
* An SPI device connects to an SPI bus through a 4-wire serial interface.
* The SPI bus is a full-duplex, synchronous bus that facilitates communication
* between one master and one slave. The device is always full-duplex,
* which means that for every byte sent, one is received, and vice-versa.
* The master controls the clock, so it can regulate when it wants to
* send or receive data. The slave is under control of the master, it must
* respond quickly since it has no control of the clock and must send/receive
* data as fast or as slow as the master does.
*
* <b>Initialization & Configuration</b>
*
* The XSpiPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
* - XSpiPs_LookupConfig(DeviceId) - Use the devide identifier to find the
* static configuration structure defined in xspips_g.c. This is setup by
* the tools. For some operating systems the config structure will be
* initialized by the software and this call is not needed.
* - XSpiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, but arbitration is the responsibility of
* the higher layer software. The device driver does not perform any type of
* arbitration.
*
* <b>Multiple Slaves</b>
*
* Contention between multiple masters is detected by the hardware, in which
* case a mode fault occurs on the device. The device is disabled immediately
* by hardware, and the current word transfer is stopped. The Aborted word
* transfer due to the mode fault is resumed once the devie is enabled again.
*
* <b>Modes of Operation</b>
*
* There are four modes to perform a data transfer and the selection of a mode
* is based on Chip Select(CS) and Start. These two options individually, can
* be controlled either by software(Manual) or hardware(Auto).
* - Auto CS: Chip select is automatically asserted as soon as the first word
* is written into the TXFIFO and deasserted when the TXFIFO becomes
* empty
* - Manual CS: Software must assert and deassert CS.
* - Auto Start: Data transmission starts as soon as there is data in the
* TXFIFO and stalls when the TXFIFO is empty
* - Manual Start: Software must start data transmission at the beginning of
* the transaction or whenever the TXFIFO has become empty
*
* The preferred combination is Manual CS and Auto Start.
* In this combination, the software asserts CS before loading any data into
* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
* data is available. If no further data, software disables CS.
*
* Risks/challenges of other combinations:
* - Manual CS and Manual Start: Manual Start bit should be set after each
* TXFIFO write otherwise there could be a race condition where the TXFIFO
* becomes empty before the new word is written. In that case the
* transmission stops.
* - Auto CS with Manual or Auto Start: It is very difficult for software to
* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is deasserted.
* This results in a single transaction to be split into multiple pieces each
* with its own chip select. This will result in garbage data to be sent.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XSpiPs_InterruptHandler, to an interrupt system such that it will be
* called when an interrupt occurs. This function does not save and restore
* the processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Data Transmit Register/FIFO Underflow
* - Data Receive Register/FIFO Full
* - Data Receive Register/FIFO Not Empty
* - Data Transmit Register/FIFO Full
* - Data Transmit Register/FIFO Overwater
* - Mode Fault Error
* - Data Receive Register/FIFO Overrun
*
* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
* SPI device has transmitted the data available to transmit, and now its data
* register and FIFO is ready to accept more data. The driver uses this
* interrupt to indicate progress while sending data. The driver may have
* more data to send, in which case the data transmit register and FIFO is
* filled for subsequent transmission. When this interrupt arrives and all
* the data has been sent, the driver invokes the status callback with a
* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
* all data has been sent.
*
* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
* as slave, the SPI device was required to transmit but there was no data
* available to transmit in the transmit register (or FIFO). This may not
* be an error if the master is not expecting data. But in the case where
* the master is expecting data, this serves as a notification of such a
* condition. The driver reports this condition to the upper layer
* software through the status handler.
*
* The Data Receive Register/FIFO Overrun interrupt -- indicates that the SPI
* device received data and subsequently dropped the data because the data
* receive register and FIFO was full. The interrupt applies to both master
* and slave operation. The driver reports this condition to the upper layer
* software through the status handler. This likely indicates a problem with
* the higher layer protocol, or a problem with the slave performance.
*
* The Mode Fault Error interrupt -- indicates that while configured as a
* master, the device was selected as a slave by another master. This can be
* used by the application for arbitration in a multimaster environment or to
* indicate a problem with arbitration. When this interrupt occurs, the
* driver invokes the status callback with a status value of
* XST_SPI_MODE_FAULT. It is up to the application to resolve the conflict.
* When configured as a slave, Mode Fault Error interrupt indicates that a slave
* device was selected as a slave by a master, but the slave device was
* disabled. When configured as a master, Mode Fault Error interrupt indicates
* that another SPI device is acting as a master on the bus.
*
*
* <b>Polled Operation</b>
*
* Transfer in polled mode is supported through a separate interface function
* XSpiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
* this function blocks until all data has been sent/received.
*
* <b>Device Busy</b>
*
* Some operations are disallowed when the device is busy. The driver tracks
* whether a device is busy. The device is considered busy when a data transfer
* request is outstanding, and is considered not busy only when that transfer
* completes (or is aborted with a mode fault error). This applies to both
* master and slave devices.
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xspips_g.c file or
* passed in via XSpiPs_CfgInitialize(). A table is defined where each entry
* contains configuration information for an SPI device, including the base
* address for the device.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied
* by the layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00 drg/jz 01/25/10 First release
* 1.00 sdm 10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
* options as this is not supported in the device.
* 1.01 sg 03/07/12 Updated the code to always clear the relevant bits
* before writing to config register.
* Always clear the slave select bits before write and
* clear the bits to no slave at the end of transfer
* Modified the Polled transfer transmit/receive logic.
* Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
* 1.02 sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
* for CR 658289
* 1.03 sg 09/21/12 Added memory barrier dmb in polled transfer and
* interrupt handler to overcome the clock domain
* crossing issue in the controller. For CR #679252.
* 1.04a sg 01/30/13 Created XSPIPS_MANUAL_START_OPTION. Created macros
* XSpiPs_IsMaster, XSpiPs_IsManualStart and
* XSpiPs_IsManualChipSelect. Changed SPI
* Enable/Disable macro argument from BaseAddress to
* Instance Pointer. Added DelayNss argument to SetDelays
* and GetDelays API's. Added macros to set/get the
* RX Watermark value.Created macros XSpiPs_IsMaster,
* XSpiPs_IsManualStart and XSpiPs_IsManualChipSelect.
* Changed SPI transfer logic for polled and interrupt
* modes to be based on filled tx fifo count and receive
* based on it. RXNEMPTY interrupt is not used.
* SetSlaveSelect API logic is modified to drive the bit
* position low based on the slave select value
* requested. GetSlaveSelect API will return the value
* based on bit position that is low.
* Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
* to XSPIPS_CR_RESET_STATE. Created
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
* write-to-clear. Added shift and mask macros for d_nss
* parameter. Added Rx Watermark mask.
* 1.05a hk 26/04/13 Added disable and enable in XSpiPs_SetOptions when
* CPOL/CPHA bits are set/reset. Fix for CR#707669.
* 1.06a hk 08/22/13 Changed GetSlaveSelect function. CR# 727866.
* Added masking ConfigReg before writing in SetSlaveSel
* Added extended slave select support - CR#722569.
* Added prototypes of reset API and related constant
* definitions.
* Added check for MODF in polled transfer function.
* 3.0 vm 12/09/14 Modified driver source code for MISRA-C:2012 compliance.
* Support for Zynq Ultrascale Mp added.
*
* </pre>
*
******************************************************************************/
#ifndef XSPIPS_H /* prevent circular inclusions */
#define XSPIPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xspips_hw.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options are supported to enable/disable certain features of
* an SPI device. Each of the options is a bit mask, so more than one may be
* specified.
*
* <b>The Master option</b> configures the SPI device as a master.
* By default, the device is a slave.
*
* The <b>Active Low Clock option</b> configures the device's clock polarity.
* Setting this option means the clock is active low and the SCK signal idles
* high. By default, the clock is active high and SCK idles low.
*
* The <b>Clock Phase option</b> configures the SPI device for one of two
* transfer formats. A clock phase of 0, the default, means data is valid on
* the first SCK edge (rising or falling) after the slave select (SS) signal
* has been asserted. A clock phase of 1 means data is valid on the second SCK
* edge (rising or falling) after SS has been asserted.
*
* The <b>Slave Select Decode Enable option</b> selects how the SPI_SS_outN are
* controlled by the SPI Slave Select Decode bits.
* 0: Use this setting for the standard configuration of up to three slave
* select outputs. Only one of the three slave select outputs will be low.
* (Default)
* 1: Use this setting for the optional configuration of an additional decoder
* to support 8 slave select outputs. SPI_SS_outN reflects the value in the
* register.
*
* The <b>SPI Force Slave Select option</b> is used to enable manual control of
* the signals SPI_SS_outN.
* 0: The SPI_SS_outN signals are controlled by the SPI controller during
* transfers. (Default)
* 1: The SPI_SS_outN signal indicated by the Slave Select Control bit is
* forced active (driven low) regardless of any transfers in progress.
*
* NOTE: The driver will handle setting and clearing the Slave Select when
* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
* SPI clock to be set to a faster speed. If the SPI clock is too fast, the
* processor cannot empty and refill the FIFOs before the TX FIFO is empty
* When the SPI hardware is controlling the Slave Select signals, this
* will cause slave to be de-selected and terminate the transfer.
*
* The <b>Manual Start option</b> is used to enable manual control of
* the Start command to perform data transfer.
* 0: The Start command is controlled by the SPI controller during
* transfers(Default). Data transmission starts as soon as there is data in
* the TXFIFO and stalls when the TXFIFO is empty
* 1: The Start command must be issued by software to perform data transfer.
* Bit 15 of Configuration register is used to issue Start command. This bit
* must be set whenever TXFIFO is filled with new data.
*
* NOTE: The driver will set the Manual Start Enable bit in Configuration
* Register, if Manual Start option is selected. Software will issue
* Manual Start command whenever TXFIFO is filled with data. When there is
* no further data, driver will clear the Manual Start Enable bit.
*
* @{
*/
#define XSPIPS_MASTER_OPTION 0x00000001U /**< Master mode option */
#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x00000002U /**< Active Low Clock option */
#define XSPIPS_CLK_PHASE_1_OPTION 0x00000004U /**< Clock Phase one option */
#define XSPIPS_DECODE_SSELECT_OPTION 0x00000008U /**< Select 16 slaves Option */
#define XSPIPS_FORCE_SSELECT_OPTION 0x00000010U /**< Force Slave Select */
#define XSPIPS_MANUAL_START_OPTION 0x00000020U /**< Manual Start mode option */
/*@}*/
/** @name SPI Clock Prescaler options
* The SPI Clock Prescaler Configuration bits are used to program master mode
* bit rate. The bit rate can be programmed in divide-by-two decrements from
* pclk/4 to pclk/256.
*
* @{
*/
#define XSPIPS_CLK_PRESCALE_4 0x01U /**< PCLK/4 Prescaler */
#define XSPIPS_CLK_PRESCALE_8 0x02U /**< PCLK/8 Prescaler */
#define XSPIPS_CLK_PRESCALE_16 0x03U /**< PCLK/16 Prescaler */
#define XSPIPS_CLK_PRESCALE_32 0x04U /**< PCLK/32 Prescaler */
#define XSPIPS_CLK_PRESCALE_64 0x05U /**< PCLK/64 Prescaler */
#define XSPIPS_CLK_PRESCALE_128 0x06U /**< PCLK/128 Prescaler */
#define XSPIPS_CLK_PRESCALE_256 0x07U /**< PCLK/256 Prescaler */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to
* a handler from the driver. These constants are not bit masks such that
* only one will be passed at a time to the handler.
*
* @{
*/
#define XSPIPS_EVENT_MODE_FAULT 1U /**< Mode fault error */
#define XSPIPS_EVENT_TRANSFER_DONE 2U /**< Transfer done */
#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3U /**< TX FIFO empty */
#define XSPIPS_EVENT_RECEIVE_OVERRUN 4U /**< Receive data loss because
RX FIFO full */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* handle the asynchronous processing for the SPI device. The application
* using this driver is expected to define a handler of this type to support
* interrupt driven mode. The handler executes in an interrupt context, so
* only minimal processing should be performed.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent holds one or more status events that have occurred.
* See the XSpiPs_SetStatusHandler() for details on the status
* events that can be passed in the callback.
* @param ByteCount indicates how many bytes of data were successfully
* transferred. This may be less than the number of bytes
* requested if the status event indicates an error.
*/
typedef void (*XSpiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
u32 ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
} XSpiPs_Config;
/**
* The XSpiPs driver instance data. The user is required to allocate a
* variable of this type for every SPI device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XSpiPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
u32 RequestedBytes; /**< Number of bytes to transfer (state) */
u32 RemainingBytes; /**< Number of bytes left to transfer(state) */
u32 IsBusy; /**< A transfer is in progress (state) */
u32 SlaveSelect; /**< The slave select value when
XSPIPS_FORCE_SSELECT_OPTION is set */
XSpiPs_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
} XSpiPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Start Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XSpiPs_IsManualStart(XSpiPs *InstancePtr);
*
*****************************************************************************/
#define XSpiPs_IsManualStart(InstancePtr) \
(((XSpiPs_GetOptions(InstancePtr) & \
XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XSpiPs_IsManualChipSelect(XSpiPs *InstancePtr);
*
*****************************************************************************/
#define XSpiPs_IsManualChipSelect(InstancePtr) \
(((XSpiPs_GetOptions(InstancePtr) & \
XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
*
* Check in OptionsTable if Decode Slave Select option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XSpiPs_IsDecodeSSelect(XSpiPs *InstancePtr);
*
*****************************************************************************/
#define XSpiPs_IsDecodeSSelect(InstancePtr) \
(((XSpiPs_GetOptions(InstancePtr) & \
XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/*
*
* Check in OptionsTable if Master Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XSpiPs_IsMaster(XSpiPs *InstancePtr);
*
*****************************************************************************/
#define XSpiPs_IsMaster(InstancePtr) \
(((XSpiPs_GetOptions(InstancePtr) & \
XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* Set the contents of the slave idle count register.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
* @param RegisterValue is the value to be writen, valid values are
* 0-255.
*
* @return None
*
* @note
* C-Style signature:
* void XSpiPs_SetSlaveIdle(XSpiPs *InstancePtr, u32 RegisterValue)
*
*****************************************************************************/
#define XSpiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XSPIPS_SICR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the slave idle count register. Use the XSPIPS_SICR_*
* constants defined in xspips_hw.h to interpret the bit-mask returned.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return 8-bit value representing the contents of the SIC register.
*
* @note C-Style signature:
* u32 XSpiPs_GetSlaveIdle(XSpiPs *InstancePtr)
*
*****************************************************************************/
#define XSpiPs_GetSlaveIdle(InstancePtr) \
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XSPIPS_SICR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the transmit FIFO watermark register.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
* @param RegisterValue is the value to be written, valid values
* are 1-128.
*
* @return None.
*
* @note
* C-Style signature:
* void XSpiPs_SetTXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
*
*****************************************************************************/
#define XSpiPs_SetTXWatermark(InstancePtr, RegisterValue) \
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XSPIPS_TXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the transmit FIFO watermark register.
* Use the XSPIPS_TXWR_* constants defined xspips_hw.h to interpret
* the bit-mask returned.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return 8-bit value representing the contents of the TXWR register.
*
* @note C-Style signature:
* u32 XSpiPs_GetTXWatermark(u32 *InstancePtr)
*
*****************************************************************************/
#define XSpiPs_GetTXWatermark(InstancePtr) \
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the receive FIFO watermark register.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
* @param RegisterValue is the value to be written, valid values
* are 1-128.
*
* @return None.
*
* @note
* C-Style signature:
* void XSpiPs_SetRXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
*
*****************************************************************************/
#define XSpiPs_SetRXWatermark(InstancePtr, RegisterValue) \
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XSPIPS_RXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the receive FIFO watermark register.
* Use the XSPIPS_RXWR_* constants defined xspips_hw.h to interpret
* the bit-mask returned.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return A 8-bit value representing the contents of the RXWR register.
*
* @note C-Style signature:
* u32 XSpiPs_GetRXWatermark(u32 *InstancePtr)
*
*****************************************************************************/
#define XSpiPs_GetRXWatermark(InstancePtr) \
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
*
* Enable the device and uninhibit master transactions.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XSpiPs_Enable(u32 *InstancePtr)
*
*****************************************************************************/
#define XSpiPs_Enable(InstancePtr) \
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
XSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable the device.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XSpiPs_Disable(u32 *InstancePtr)
*
*****************************************************************************/
#define XSpiPs_Disable(InstancePtr) \
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U)
/************************** Function Prototypes ******************************/
/*
* Initialization function, implemented in xspips_sinit.c
*/
XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xspips.c
*/
s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, XSpiPs_Config * ConfigPtr,
u32 EffectiveAddr);
void XSpiPs_Reset(XSpiPs *InstancePtr);
s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount);
s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount);
void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
XSpiPs_StatusHandler FunctionPtr);
void XSpiPs_InterruptHandler(XSpiPs *InstancePtr);
void XSpiPs_Abort(XSpiPs *InstancePtr);
s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel);
u8 XSpiPs_GetSlaveSelect(XSpiPs *InstancePtr);
/*
* Functions for selftest, in xspips_selftest.c
*/
s32 XSpiPs_SelfTest(XSpiPs *InstancePtr);
/*
* Functions for options, in xspips_options.c
*/
s32 XSpiPs_SetOptions(XSpiPs *InstancePtr, u32 Options);
u32 XSpiPs_GetOptions(XSpiPs *InstancePtr);
s32 XSpiPs_SetClkPrescaler(XSpiPs *InstancePtr, u8 Prescaler);
u8 XSpiPs_GetClkPrescaler(XSpiPs *InstancePtr);
s32 XSpiPs_SetDelays(XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
void XSpiPs_GetDelays(XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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@ -0,0 +1,310 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xspips_hw.h
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xspips.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00 drg/jz 01/25/10 First release
* 1.02a sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
* for CR 658289
* 1.04a sg 01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
* to XSPIPS_CR_RESET_STATE. Created
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
* write-to-clear. Added shift and mask macros for d_nss
* parameter. Added Rx Watermark mask.
* 1.06a hk 08/22/13 Added prototypes of reset API and related constant
* definitions.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XSPIPS_HW_H /* prevent circular inclusions */
#define XSPIPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets from the base address of an SPI device.
* @{
*/
#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */
#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */
#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */
#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */
#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */
#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */
#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */
#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */
#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */
#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */
#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */
#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */
/* @} */
/** @name Configuration Register
*
* This register contains various control bits that
* affects the operation of an SPI device. Read/Write.
* @{
*/
#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
Enable */
#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */
#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
Enable */
#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */
#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */
#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */
#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */
#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */
#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */
#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */
#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */
#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */
#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */
#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */
#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */
/* @} */
/** @name SPI Interrupt Registers
*
* <b>SPI Status Register</b>
*
* This register holds the interrupt status flags for an SPI device. Some
* of the flags are level triggered, which means that they are set as long
* as the interrupt condition exists. Other flags are edge triggered,
* which means they are set once the interrupt condition occurs and remain
* set until they are cleared by software. The interrupts are cleared by
* writing a '1' to the interrupt bit position in the Status Register.
* Read/Write.
*
* <b>SPI Interrupt Enable Register</b>
*
* This register is used to enable chosen interrupts for an SPI device.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* SPI Interrupt Mask register. Write only.
*
* <b>SPI Interrupt Disable Register </b>
*
* This register is used to disable chosen interrupts for an SPI device.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* SPI Interrupt Mask register. Write only.
*
* <b>SPI Interrupt Mask Register</b>
*
* This register shows the enabled/disabled interrupts of an SPI device.
* Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Channel Interrupt Status Register
* @{
*/
#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */
#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */
#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */
#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */
#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */
#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */
#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */
#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts
mask */
#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which
need write to clear */
#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx
* reg empty */
#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all
* interrupts */
/* @} */
/** @name Enable Register
*
* This register is used to enable or disable an SPI device.
* Read/Write
* @{
*/
#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */
/* @} */
/** @name Delay Register
*
* This register is used to program timing delays in
* slave mode. Read/Write
* @{
*/
#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select
* de-assertion between
* word transfers mask */
#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select
* de-assertion between
* word transfers shift */
#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */
#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */
#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */
#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */
#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */
/* @} */
/** @name Slave Idle Count Registers
*
* This register defines the number of pclk cycles the slave waits for a the
* SPI clock to become stable in quiescent state before it can detect the start
* of the next transfer in CPHA = 1 mode.
* Read/Write
*
* @{
*/
#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */
/* @} */
/** @name Transmit FIFO Watermark Register
*
* This register defines the watermark setting for the Transmit FIFO. The
* transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values
* are 1 to 128.
*
* @{
*/
#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */
#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark
* register reset value */
/* @} */
/** @name Receive FIFO Watermark Register
*
* This register defines the watermark setting for the Receive FIFO. The
* receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values
* are 1 to 128.
*
* @{
*/
#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */
#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark
* register reset value */
/* @} */
/** @name FIFO Depth
*
* This macro provides the depth of transmit FIFO and receive FIFO.
*
* @{
*/
#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XSpiPs_In32 Xil_In32
#define XSpiPs_Out32 Xil_Out32
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSpiPs_ReadReg(BaseAddress, RegOffset) \
XSpiPs_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Function Prototypes ******************************/
void XSpiPs_ResetHw(u32 BaseAddress);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

430
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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xstatus.h
*
* This file contains Xilinx software status codes. Status codes have their
* own data type called int. These codes are used throughout the Xilinx
* device drivers.
*
******************************************************************************/
#ifndef XSTATUS_H /* prevent circular inclusions */
#define XSTATUS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/*********************** Common statuses 0 - 500 *****************************/
#define XST_SUCCESS 0L
#define XST_FAILURE 1L
#define XST_DEVICE_NOT_FOUND 2L
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
#define XST_INVALID_VERSION 4L
#define XST_DEVICE_IS_STARTED 5L
#define XST_DEVICE_IS_STOPPED 6L
#define XST_FIFO_ERROR 7L /* an error occurred during an
operation with a FIFO such as
an underrun or overrun, this
error requires the device to
be reset */
#define XST_RESET_ERROR 8L /* an error occurred which requires
the device to be reset */
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
typically requires the device
using the DMA to be reset */
#define XST_NOT_POLLED 10L /* the device is not configured for
polled mode operation */
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
the specified data into */
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
to hold the expected data */
#define XST_NO_DATA 13L /* there was no data available */
#define XST_REGISTER_ERROR 14L /* a register did not contain the
expected value */
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
into the function */
#define XST_NOT_SGDMA 16L /* the device is not configured for
scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
#define XST_NO_CALLBACK 18L /* a callback has not yet been
registered */
#define XST_NO_FEATURE 19L /* device is not configured with
the requested feature */
#define XST_NOT_INTERRUPT 20L /* device is not configured for
interrupt mode operation */
#define XST_DEVICE_BUSY 21L /* device is busy */
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
have maxed out */
#define XST_IS_STARTED 23L /* used when part of device is
already started i.e.
sub channel */
#define XST_IS_STOPPED 24L /* used when part of device is
already stopped i.e.
sub channel */
#define XST_DATA_LOST 26L /* driver defined error */
#define XST_RECV_ERROR 27L /* generic receive error */
#define XST_SEND_ERROR 28L /* generic transmit error */
#define XST_NOT_ENABLED 29L /* a requested service is not
available because it has not
been enabled */
/***************** Utility Component statuses 401 - 500 *********************/
#define XST_MEMTEST_FAILED 401L /* memory test failed */
/***************** Common Components statuses 501 - 1000 *********************/
/********************* Packet Fifo statuses 501 - 510 ************************/
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
was invalid after reset */
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
* empty and full simultaneously
*/
/************************** DMA statuses 511 - 530 ***************************/
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
failed */
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
no buffer descriptors ready
to be processed */
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
the scatter gather list are
being used */
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
descriptor which is to be
copied over in the scatter
list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
put into the scatter gather
list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
specified was larger than the
total # of buffer descriptors
in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
already been created */
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
been created */
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
being started was not committed
to the list */
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
has already been used by the
hardware so it can't be reused
*/
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
error */
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
error */
/************************** IPIF statuses 531 - 550 ***************************/
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
status register did not read
back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
register did not reset when
acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
register was not updated when
other registers changed */
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
status register did not read
back correctly */
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
not updated correctly when other
registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
register did not indicate the
expected value */
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
did not indicate the expected
value */
#define XST_IPIF_ERROR 541L /* generic ipif error */
/****************** Device specific statuses 1001 - 4095 *********************/
/********************* Ethernet statuses 1001 - 1050 *************************/
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
* to hold the minimum number of
* buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
* collision on polled send */
/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART
#define XST_UART_INIT_ERROR 1051L
#define XST_UART_START_ERROR 1052L
#define XST_UART_CONFIG_ERROR 1053L
#define XST_UART_TEST_FAIL 1054L
#define XST_UART_BAUD_ERROR 1055L
#define XST_UART_BAUD_RANGE 1056L
/************************ IIC statuses 1076 - 1100 ***************************/
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
/* general call address */
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
/* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
/* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
/* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
/* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
/* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
/* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
/* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
/* didn't return written value */
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
/*********************** ATMC statuses 1101 - 1125 ***************************/
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
controller hit the max value
which requires the statistics
to be cleared */
/*********************** Flash statuses 1126 - 1150 **************************/
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
*/
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
error. Use XFlash_DeviceControl
to retrieve device specific codes
*/
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
*/
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
*/
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
driver */
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
addressible range */
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
write/erase function with
XFL_NON_BLOCKING_WRITE/ERASE
option cleared */
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
* selected */
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
*/
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
* one master assigned to two or more
* priorities, or one master not
* assigned to any priority
*/
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
* priority levels without first
* suspending the use of priority
* levels
*/
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
* bus parking was not enabled
*/
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
* priority mode to allow the
* priorities to be changed
*/
/************************ Intc statuses 1201 - 1225 **************************/
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
/********************** TmrCtr statuses 1226 - 1250 **************************/
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
/********************** WdtTb statuses 1251 - 1275 ***************************/
#define XST_WDTTB_TIMER_FAILED 1251L
/********************** PlbArb statuses 1276 - 1300 **************************/
#define XST_PLBARB_FAIL_SELFTEST 1276L
/********************** Plb2Opb statuses 1301 - 1325 *************************/
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
/********************** Opb2Plb statuses 1326 - 1350 *************************/
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
/********************** SysAce statuses 1351 - 1360 **************************/
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
/********************** PCI Bridge statuses 1361 - 1375 **********************/
#define XST_PCI_INVALID_ADDRESS 1361L
/********************** FlexRay constants 1400 - 1409 *************************/
#define XST_FR_TX_ERROR 1400
#define XST_FR_TX_BUSY 1401
#define XST_FR_BUF_LOCKED 1402
#define XST_FR_NO_BUF 1403
/****************** USB constants 1410 - 1420 *******************************/
#define XST_USB_ALREADY_CONFIGURED 1410
#define XST_USB_BUF_ALIGN_ERROR 1411
#define XST_USB_NO_DESC_AVAILABLE 1412
#define XST_USB_BUF_TOO_BIG 1413
#define XST_USB_NO_BUF 1414
/****************** HWICAP constants 1421 - 1429 *****************************/
#define XST_HWICAP_WRITE_DONE 1421
/****************** AXI VDMA constants 1430 - 1440 *****************************/
#define XST_VDMA_MISMATCH_ERROR 1430
/*********************** NAND Flash statuses 1441 - 1459 *********************/
#define XST_NAND_BUSY 1441L /* Flash is erasing or
* programming
*/
#define XST_NAND_READY 1442L /* Flash is ready for commands
*/
#define XST_NAND_ERROR 1443L /* Flash had detected an
* internal error.
*/
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
* driver
*/
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
*/
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
* operation aborted due to a
* timeout
*/
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
* addressible range
*/
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
*/
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
* page of the device
*/
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
*/
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
*/
/**************************** Type Definitions *******************************/
typedef int XStatus;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.h
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note None.
*
******************************************************************************/
#ifndef XTIME_H /* prevent circular inclusions */
#define XTIME_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xparameters.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
typedef u64 XTime;
/************************** Constant Definitions *****************************/
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_SECOND 0x007A1200U
#define XIOU_SCNTRS_BASEADDR 0XFF260000U
#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
#define XIOU_SCNTRS_FREQ 0x02FAF080U /* 50 MHz */
#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0X00000001U
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void XTime_SetTime(XTime Xtime_Global);
void XTime_GetTime(XTime *Xtime_Global);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XTIME_H */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xttcps.h
*
* This is the driver for one 16-bit timer counter in the Triple Timer Counter
* (TTC) module in the Ps block.
*
* The TTC module provides three independent timer/counter modules that can each
* be clocked using either the system clock (pclk) or an externally driven
* clock (ext_clk). In addition, each counter can independently prescale its
* selected clock input (divided by 2 to 65536). Counters can be set to
* decrement or increment.
*
* Each of the counters can be programmed to generate interrupt pulses:
* . At a regular, predefined period, that is on a timed interval
* . When the counter registers overflow
* . When the count matches any one of the three 'match' registers
*
* Therefore, up to six different events can trigger a timer interrupt: three
* match interrupts, an overflow interrupt, an interval interrupt and an event
* timer interrupt. Note that the overflow interrupt and the interval interrupt
* are mutually exclusive.
*
* <b>Initialization & Configuration</b>
*
* An XTtcPs_Config structure is used to configure a driver instance.
* Information in the XTtcPs_Config structure is the hardware properties
* about the device.
*
* A driver instance is initialized through
* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
* is a pointer to the XTtcPs_Config structure, it can be looked up statically
* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
* EffectiveAddr can be the static base address of the device or virtual
* mapped address if address translation is supported.
*
* <b>Interrupts</b>
*
* Interrupt handler is not provided by the driver, as handling of interrupt
* is application specific.
*
* @note
* The default setting for a timer/counter is:
* - Overflow Mode
* - Internal clock (pclk) selected
* - Counter disabled
* - All Interrupts disabled
* - Output waveforms disabled
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------------
* 1.00a drg/jz 01/20/10 First release..
* 2.0 adk 12/10/13 Updated as per the New Tcl API's
* 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code
* modified for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XTTCPS_H /* prevent circular inclusions */
#define XTTCPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xttcps_hw.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* Options for the device. Each of the options is bit field, so more than one
* options can be specified.
*
* @{
*/
#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */
#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for
external clock*/
#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */
#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */
#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */
#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */
#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */
/*@}*/
/**************************** Type Definitions *******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID for device */
u32 BaseAddress; /**< Base address for device */
u32 InputClockHz; /**< Input clock frequency */
} XTtcPs_Config;
/**
* The XTtcPs driver instance data. The user is required to allocate a
* variable of this type for each PS timer/counter device in the system. A
* pointer to a variable of this type is then passed to various driver API
* functions.
*/
typedef struct {
XTtcPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
} XTtcPs;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* Internal helper macros
*/
#define InstReadReg(InstancePtr, RegOffset) \
(Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
#define InstWriteReg(InstancePtr, RegOffset, Data) \
(Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
/*****************************************************************************/
/**
*
* This function starts the counter/timer without resetting the counter value.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return None
*
* @note C-style signature:
* void XTtcPs_Start(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_Start(InstancePtr) \
InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
~XTTCPS_CNT_CNTRL_DIS_MASK))
/*****************************************************************************/
/**
*
* This function stops the counter/timer. This macro may be called at any time
* to stop the counter. The counter holds the last value until it is reset,
* restarted or enabled.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return None
*
* @note C-style signature:
* void XTtcPs_Stop(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_Stop(InstancePtr) \
InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
XTTCPS_CNT_CNTRL_DIS_MASK))
/*****************************************************************************/
/**
*
* This function checks whether the timer counter has already started.
*
* @param InstancePtr is a pointer to the XTtcPs instance
*
* @return Non-zero if the device has started, '0' otherwise.
*
* @note C-style signature:
* int XTtcPs_IsStarted(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_IsStarted(InstancePtr) \
((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
/*****************************************************************************/
/**
*
* This function returns the current 16-bit counter value. It may be called at
* any time.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return 16-bit counter value.
*
* @note C-style signature:
* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_GetCounterValue(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
/*****************************************************************************/
/**
*
* This function sets the interval value to be used in interval mode.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
* @param Value is the 16-bit value to be set in the interval register.
*
* @return None
*
* @note C-style signature:
* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
*
****************************************************************************/
#define XTtcPs_SetInterval(InstancePtr, Value) \
InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
/*****************************************************************************/
/**
*
* This function gets the interval value from the interval register.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return 16-bit interval value
*
* @note C-style signature:
* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_GetInterval(InstancePtr) \
(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
/*****************************************************************************/
/**
*
* This macro resets the count register. It may be called at any time. The
* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
* the increment/decrement mode. The state of the counter, as started or
* stopped, is not affected by calling reset.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return None
*
* @note C-style signature:
* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
*
****************************************************************************/
#define XTtcPs_ResetCounterValue(InstancePtr) \
InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
(u32)XTTCPS_CNT_CNTRL_RST_MASK))
/*****************************************************************************/
/**
*
* This function enables the interrupts.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
* @param InterruptMask defines which interrupt should be enabled.
* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
* This is a bit mask, all set bits will be enabled, cleared bits
* will not be disabled.
*
* @return None.
*
* @note
* C-style signature:
* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
*
******************************************************************************/
#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \
InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \
(InterruptMask)))
/*****************************************************************************/
/**
*
* This function disables the interrupts.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
* @param InterruptMask defines which interrupt should be disabled.
* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
* This is a bit mask, all set bits will be disabled, cleared bits
* will not be disabled.
*
* @return None.
*
* @note
* C-style signature:
* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
*
******************************************************************************/
#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \
(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \
~(InterruptMask)))
/*****************************************************************************/
/**
*
* This function reads the interrupt status.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
*
* @return None.
*
* @note C-style signature:
* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
*
******************************************************************************/
#define XTtcPs_GetInterruptStatus(InstancePtr) \
InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
/*****************************************************************************/
/**
*
* This function clears the interrupt status.
*
* @param InstancePtr is a pointer to the XTtcPs instance.
* @param InterruptMask defines which interrupt should be cleared.
* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
* This is a bit mask, all set bits will be cleared, cleared bits
* will not be cleared.
*
* @return None.
*
* @note
* C-style signature:
* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
*
******************************************************************************/
#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
(InterruptMask))
/************************** Function Prototypes ******************************/
/*
* Initialization functions in xttcps_sinit.c
*/
XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
/*
* Required functions, in xttcps.c
*/
s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
u16 *Interval, u8 *Prescaler);
/*
* Functions for options, in file xttcps_options.c
*/
s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
/*
* Function for self-test, in file xttcps_selftest.c
*/
s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xttcps_hw.h
*
* This file defines the hardware interface to one of the three timer counters
* in the Ps block.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -------------------------------------------------
* 1.00a drg/jz 01/21/10 First release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XTTCPS_HW_H /* prevent circular inclusions */
#define XTTCPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets from the base address of the device.
*
* @{
*/
#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
/* @} */
/** @name Clock Control Register
* Clock Control Register definitions
* @{
*/
#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
/* @} */
/** @name Counter Control Register
* Counter Control Register definitions
* @{
*/
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
/* @} */
/** @name Current Counter Value Register
* Current Counter Value Register definitions
* @{
*/
#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */
/* @} */
/** @name Interval Value Register
* Interval Value Register is the maximum value the counter will count up or
* down to.
* @{
*/
#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/
/* @} */
/** @name Match Registers
* Definitions for Match registers, each timer counter has three match
* registers.
* @{
*/
#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */
#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */
/* @} */
/** @name Interrupt Registers
* Following register bit mask is for all interrupt registers.
*
* @{
*/
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Read the given Timer Counter register.
*
* @param BaseAddress is the base address of the timer counter device.
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note C-style signature:
* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (u32)(RegOffset)))
/****************************************************************************/
/**
*
* Write the given Timer Counter register.
*
* @param BaseAddress is the base address of the timer counter device.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note C-style signature:
* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
/****************************************************************************/
/**
*
* Calculate a match register offset using the Match Register index.
*
* @param MatchIndex is the 0-2 value of the match register
*
* @return MATCH_N_OFFSET.
*
* @note C-style signature:
* u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
*
*****************************************************************************/
#define XTtcPs_Match_N_Offset(MatchIndex) \
((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

509
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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xuartps.h
*
* This driver supports the following features:
*
* - Dynamic data format (baud rate, data bits, stop bits, parity)
* - Polled mode
* - Interrupt driven mode
* - Transmit and receive FIFOs (32 byte FIFO depth)
* - Access to the external modem control lines
*
* <b>Initialization & Configuration</b>
*
* The XUartPs_Config structure is used by the driver to configure itself.
* Fields inside this structure are properties of XUartPs based on its hardware
* build.
*
* To support multiple runtime loading and initialization strategies employed
* by various operating systems, the driver instance can be initialized in the
* following way:
*
* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the parameter EffectiveAddr should be the
* virtual address.
*
* <b>Baud Rate</b>
*
* The UART has an internal baud rate generator, which furnishes the baud rate
* clock for both the receiver and the transmitter. Ther input clock frequency
* can be either the master clock or the master clock divided by 8, configured
* through the mode register.
*
* Accompanied with the baud rate divider register, the baud rate is determined
* by:
* <pre>
* baud_rate = input_clock / (bgen * (bdiv + 1)
* </pre>
* where bgen is the value of the baud rate generator, and bdiv is the value of
* baud rate divider.
*
* <b>Interrupts</b>
*
* The FIFOs are not flushed when the driver is initialized, but a function is
* provided to allow the user to reset the FIFOs if desired.
*
* The driver defaults to no interrupts at initialization such that interrupts
* must be enabled if desired. An interrupt is generated for one of the
* following conditions.
*
* - A change in the modem signals
* - Data in the receive FIFO for a configuable time without receiver activity
* - A parity error
* - A framing error
* - An overrun error
* - Transmit FIFO is full
* - Transmit FIFO is empty
* - Receive FIFO is full
* - Receive FIFO is empty
* - Data in the receive FIFO equal to the receive threshold
*
* The application can control which interrupts are enabled using the
* XUartPs_SetInterruptMask() function.
*
* In order to use interrupts, it is necessary for the user to connect the
* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
* system of the application. A separate handler should be provided by the
* application to communicate with the interrupt system, and conduct
* application specific interrupt handling. An application registers its own
* handler through the XUartPs_SetHandler() function.
*
* <b>Data Transfer</b>
*
* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
* driver to allow data to be sent and received. They can be used in either
* polled or interrupt mode.
*
* @note
*
* The default configuration for the UART after initialization is:
*
* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
* - 8 data bits
* - 1 stop bit
* - no parity
* - FIFO's are enabled with a receive threshold of 8 bytes
* - The RX timeout is enabled with a timeout of 1 (4 char times)
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00a drg/jz 01/12/10 First Release
* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
* in XUartPs_SetFlowDelay where the value was not
* being written to the register.
* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
* instance structure and the driver is updated to use
* InputClockHz parameter from the XUartPs_Config config
* structure.
* Added a parameter to XUartPs_Config structure which
* specifies whether the user has selected Modem pins
* to be connected to MIO or FMIO.
* Added the tcl file to generate the xparameters.h
* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
* with the correct values for CR 666724
* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
* and XUARTPS_IXR_TTRIG.
* Modified the name of these defines
* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
* 1.05a hk 08/22/13 Added API for uart reset and related
* constant definitions.
* 2.0 hk 03/07/14 Version number revised.
* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
* baud rate. CR# 804281.
* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
* Support for Zynq Ultrascale Mp added.
*
* </pre>
*
*****************************************************************************/
#ifndef XUARTPS_H /* prevent circular inclusions */
#define XUARTPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xuartps_hw.h"
/************************** Constant Definitions ****************************/
/*
* The following constants indicate the max and min baud rates and these
* numbers are based only on the testing that has been done. The hardware
* is capable of other baud rates.
*/
#define XUARTPS_MAX_RATE 921600U
#define XUARTPS_MIN_RATE 110U
#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
/** @name Configuration options
* @{
*/
/**
* These constants specify the options that may be set or retrieved
* with the driver, each is a unique bit mask such that multiple options
* may be specified. These constants indicate the available options
* in active state.
*
*/
#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
/*@}*/
/** @name Channel Operational Mode
*
* The UART can operate in one of four modes: Normal, Local Loopback, Remote
* Loopback, or automatic echo.
*
* @{
*/
#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
/* @} */
/** @name Data format values
*
* These constants specify the data format that the driver supports.
* The data format includes the number of data bits, the number of stop
* bits and parity.
*
* @{
*/
#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that an application can handle
* using its specific handler function. Note that these constants are not bit
* mask, so only one event can be passed to an application at a time.
*
* @{
*/
#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
/*@}*/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of device (IPIF) */
u32 InputClockHz;/**< Input clock frequency */
s32 ModemPinsConnected; /** Specifies whether modem pins are connected
* to MIO or FMIO */
} XUartPs_Config;
/*
* Keep track of state information about a data buffer in the interrupt mode.
*/
typedef struct {
u8 *NextBytePtr;
u32 RequestedBytes;
u32 RemainingBytes;
} XUartPsBuffer;
/**
* Keep track of data format setting of a device.
*/
typedef struct {
u32 BaudRate; /**< In bps, ie 1200 */
u32 DataBits; /**< Number of data bits */
u32 Parity; /**< Parity */
u8 StopBits; /**< Number of stop bits */
} XUartPsFormat;
/******************************************************************************/
/**
* This data type defines a handler that an application defines to communicate
* with interrupt system to retrieve state information about an application.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the handler, and is passed back to the upper layer
* when the handler is called. It is used to find the device driver
* instance.
* @param Event contains one of the event constants indicating events that
* have occurred.
* @param EventData contains the number of bytes sent or received at the
* time of the call for send and receive events and contains the
* modem status for modem events.
*
******************************************************************************/
typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
u32 EventData);
/**
* The XUartPs driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XUartPs_Config Config; /* Configuration data structure */
u32 InputClockHz; /* Input clock frequency */
u32 IsReady; /* Device is initialized and ready */
u32 BaudRate; /* Current baud rate */
XUartPsBuffer SendBuffer;
XUartPsBuffer ReceiveBuffer;
XUartPs_Handler Handler;
void *CallBackRef; /* Callback reference for event handler */
} XUartPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Get the UART Channel Status Register.
*
* @param InstancePtr is a pointer to the XUartPs instance.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
*
******************************************************************************/
#define XUartPs_GetChannelStatus(InstancePtr) \
Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
/****************************************************************************/
/**
* Get the UART Mode Control Register.
*
* @param InstancePtr is a pointer to the XUartPs instance.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XUartPs_GetControl(XUartPs *InstancePtr)
*
******************************************************************************/
#define XUartPs_GetModeControl(InstancePtr) \
Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
/****************************************************************************/
/**
* Set the UART Mode Control Register.
*
* @param InstancePtr is a pointer to the XUartPs instance.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
*
******************************************************************************/
#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
(u32)(RegisterValue))
/****************************************************************************/
/**
* Enable the transmitter and receiver of the UART.
*
* @param InstancePtr is a pointer to the XUartPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XUartPs_EnableUart(XUartPs *InstancePtr)
*
******************************************************************************/
#define XUartPs_EnableUart(InstancePtr) \
Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
(u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
/****************************************************************************/
/**
* Disable the transmitter and receiver of the UART.
*
* @param InstancePtr is a pointer to the XUartPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XUartPs_DisableUart(XUartPs *InstancePtr)
*
******************************************************************************/
#define XUartPs_DisableUart(InstancePtr) \
Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
(((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
(u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
/****************************************************************************/
/**
* Determine if the transmitter FIFO is empty.
*
* @param InstancePtr is a pointer to the XUartPs instance.
*
* @return
* - TRUE if a byte can be sent
* - FALSE if the Transmitter Fifo is not empty
*
* @note C-Style signature:
* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
*
******************************************************************************/
#define XUartPs_IsTransmitEmpty(InstancePtr) \
((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
/************************** Function Prototypes *****************************/
/*
* Static lookup function implemented in xuartps_sinit.c
*/
XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
/*
* Interface functions implemented in xuartps.c
*/
s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
XUartPs_Config * Config, u32 EffectiveAddr);
u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
u32 NumBytes);
u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
u32 NumBytes);
s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
/*
* Options functions in xuartps_options.c
*/
void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
u16 XUartPs_GetOptions(XUartPs *InstancePtr);
void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
u32 XUartPs_IsSending(XUartPs *InstancePtr);
u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
/*
* interrupt functions in xuartps_intr.c
*/
u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
void XUartPs_InterruptHandler(XUartPs *InstancePtr);
void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
void *CallBackRef);
/*
* self-test functions in xuartps_selftest.c
*/
s32 XUartPs_SelfTest(XUartPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xuartps_hw.h Normal file
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@ -0,0 +1,424 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xuartps_hw.h
*
* This header file contains the hardware interface of an XUartPs device.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00 drg/jz 01/12/10 First Release
* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
* and XUARTPS_IXR_TTRIG.
* Modified the names of these defines
* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
* 1.05a hk 08/22/13 Added prototype for uart reset and related
* constant definitions.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
*
* </pre>
*
******************************************************************************/
#ifndef XUARTPS_HW_H /* prevent circular inclusions */
#define XUARTPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the UART.
* @{
*/
#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
/* @} */
/** @name Control Register
*
* The Control register (CR) controls the major functions of the device.
*
* Control Register Bit Definition
*/
#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
/* @}*/
/** @name Mode Register
*
* The mode register (MR) defines the mode of transfer as well as the data
* format. If this register is modified during transmission or reception,
* data validity cannot be guaranteed.
*
* Mode Register Bit Definition
* @{
*/
#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
/* @} */
/** @name Interrupt Registers
*
* Interrupt control logic uses the interrupt enable register (IER) and the
* interrupt disable register (IDR) to set the value of the bits in the
* interrupt mask register (IMR). The IMR determines whether to pass an
* interrupt to the interrupt status register (ISR).
* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
* Reading either IER or IDR returns 0x00.
*
* All four registers have the same bit definitions.
*
* @{
*/
#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
#define XUARTPS_IXR_MASK 0x00001FFFU /**< Valid bit mask */
/* @} */
/** @name Baud Rate Generator Register
*
* The baud rate generator control register (BRGR) is a 16 bit register that
* controls the receiver bit sample clock and baud rate.
* Valid values are 1 - 65535.
*
* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
* in the MR register.
* @{
*/
#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
/** @name Baud Divisor Rate register
*
* The baud rate divider register (BDIV) controls how much the bit sample
* rate is divided by. It sets the baud rate.
* Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
*
* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
* the MR_CCLK bit in the MR register.
* @{
*/
#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
/* @} */
/** @name Receiver Timeout Register
*
* Use the receiver timeout register (RTR) to detect an idle condition on
* the receiver data line.
*
* @{
*/
#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
/** @name Receiver FIFO Trigger Level Register
*
* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
* which the RX FIFO triggers an interrupt event.
* @{
*/
#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
/* @} */
/** @name Transmit FIFO Trigger Level Register
*
* Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
* which the TX FIFO triggers an interrupt event.
* @{
*/
#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
/* @} */
/** @name Modem Control Register
*
* This register (MODEMCR) controls the interface with the modem or data set,
* or a peripheral device emulating a modem.
*
* @{
*/
#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
/* @} */
/** @name Modem Status Register
*
* This register (MODEMSR) indicates the current state of the control lines
* from a modem, or another peripheral device, to the CPU. In addition, four
* bits of the modem status register provide change information. These bits
* are set to a logic 1 whenever a control input from the modem changes state.
*
* Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
* status interrupt is generated and this is reflected in the modem status
* register.
*
* @{
*/
#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
/* @} */
/** @name Channel Status Register
*
* The channel status register (CSR) is provided to enable the control logic
* to monitor the status of bits in the channel interrupt status register,
* even if these are masked out by the interrupt mask register.
*
* @{
*/
#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
#define XUARTPS_SR_DMS 0x00000200U /**< Delta modem status change */
#define XUARTPS_SR_TOUT 0x00000100U /**< RX timeout */
#define XUARTPS_SR_PARITY 0x00000080U /**< RX parity error */
#define XUARTPS_SR_FRAME 0x00000040U /**< RX frame error */
#define XUARTPS_SR_OVER 0x00000020U /**< RX overflow error */
#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
/* @} */
/** @name Flow Delay Register
*
* Operation of the flow delay register (FLOWDEL) is very similar to the
* receive FIFO trigger register. An internal trigger signal activates when the
* FIFO is filled to the level set by this register. This trigger will not
* cause an interrupt, although it can be read through the channel status
* register. In hardware flow control mode, RTS is deactivated when the trigger
* becomes active. RTS only resets when the FIFO level is four less than the
* level of the flow delay trigger and the flow delay trigger is not activated.
* A value less than 4 disables the flow delay.
* @{
*/
#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
/* @} */
/*
* Defines for backwards compatabilty, will be removed
* in the next version of the driver
*/
#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
* Read a UART register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the base address of the
* device.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
*
******************************************************************************/
#define XUartPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (u32)(RegOffset))
/***************************************************************************/
/**
* Write a UART register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the base address of the
* device.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
/****************************************************************************/
/**
* Determine if there is receive data in the receiver and/or FIFO.
*
* @param BaseAddress contains the base address of the device.
*
* @return TRUE if there is receive data, FALSE otherwise.
*
* @note C-Style signature:
* u32 XUartPs_IsReceiveData(u32 BaseAddress)
*
******************************************************************************/
#define XUartPs_IsReceiveData(BaseAddress) \
!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
/****************************************************************************/
/**
* Determine if a byte of data can be sent with the transmitter.
*
* @param BaseAddress contains the base address of the device.
*
* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
* FIFO.
*
* @note C-Style signature:
* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
*
******************************************************************************/
#define XUartPs_IsTransmitFull(BaseAddress) \
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
/************************** Function Prototypes ******************************/
void XUartPs_SendByte(u32 BaseAddress, u8 Data);
u8 XUartPs_RecvByte(u32 BaseAddress);
void XUartPs_ResetHw(u32 BaseAddress);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu.h
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 01/22/15 First release
* 1.00a bss 03/18/15 Added support for Non-control endpoints
* Added mass storage example
*
* </pre>
*
*****************************************************************************/
#ifndef XUSBPSU_H /* Prevent circular inclusions */
#define XUSBPSU_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xusbpsu_hw.h"
/************************** Constant Definitions ****************************/
#define ALIGNMENT_CACHELINE __attribute__ ((aligned(64)))
#define XUSBPSU_PHY_TIMEOUT 5000 /* in micro seconds */
#define XUSBPSU_EP_DIR_IN 1
#define XUSBPSU_EP_DIR_OUT 0
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80
#define TEST_J 1
#define TEST_K 2
#define TEST_SE0_NAK 3
#define TEST_PACKET 4
#define TEST_FORCE_ENABLE 5
#define XUSBPSU_NUM_TRBS 8
#define XUSBPSU_EVENT_PENDING (1 << 0)
#define XUSBPSU_EP_ENABLED (1 << 0)
#define XUSBPSU_EP_STALL (1 << 1)
#define XUSBPSU_EP_WEDGE (1 << 2)
#define XUSBPSU_EP_BUSY (1 << 4)
#define XUSBPSU_EP_PENDING_REQUEST (1 << 5)
#define XUSBPSU_EP_MISSED_ISOC (1 << 6)
#define XUSBPSU_GHWPARAMS0 0
#define XUSBPSU_GHWPARAMS1 1
#define XUSBPSU_GHWPARAMS2 2
#define XUSBPSU_GHWPARAMS3 3
#define XUSBPSU_GHWPARAMS4 4
#define XUSBPSU_GHWPARAMS5 5
#define XUSBPSU_GHWPARAMS6 6
#define XUSBPSU_GHWPARAMS7 7
/* HWPARAMS0 */
#define XUSBPSU_MODE(n) ((n) & 0x7)
#define XUSBPSU_MDWIDTH(n) (((n) & 0xff00) >> 8)
/* HWPARAMS1 */
#define XUSBPSU_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
/* HWPARAMS3 */
#define XUSBPSU_NUM_IN_EPS_MASK (0x1f << 18)
#define XUSBPSU_NUM_EPS_MASK (0x3f << 12)
#define XUSBPSU_NUM_EPS(p) (((p) & \
(XUSBPSU_NUM_EPS_MASK)) >> 12)
#define XUSBPSU_NUM_IN_EPS(p) (((p) & \
(XUSBPSU_NUM_IN_EPS_MASK)) >> 18)
/* HWPARAMS7 */
#define XUSBPSU_RAM1_DEPTH(n) ((n) & 0xffff)
#define XUSBPSU_DEPEVT_XFERCOMPLETE 0x01
#define XUSBPSU_DEPEVT_XFERINPROGRESS 0x02
#define XUSBPSU_DEPEVT_XFERNOTREADY 0x03
#define XUSBPSU_DEPEVT_STREAMEVT 0x06
#define XUSBPSU_DEPEVT_EPCMDCMPLT 0x07
/* Within XferNotReady */
#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
/* Within XferComplete */
#define DEPEVT_STATUS_BUSERR (1 << 0)
#define DEPEVT_STATUS_SHORT (1 << 1)
#define DEPEVT_STATUS_IOC (1 << 2)
#define DEPEVT_STATUS_LST (1 << 3)
/* Stream event only */
#define DEPEVT_STREAMEVT_FOUND 1
#define DEPEVT_STREAMEVT_NOTFOUND 2
/* Control-only Status */
#define DEPEVT_STATUS_CONTROL_DATA 1
#define DEPEVT_STATUS_CONTROL_STATUS 2
#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB 9
#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB 0xA
#define XUSBPSU_ENDPOINTS_NUM 12
#define XUSBPSU_EVENT_SIZE 4 /* bytes */
#define XUSBPSU_EVENT_MAX_NUM 64 /* 2 events/endpoint */
#define XUSBPSU_EVENT_BUFFERS_SIZE (XUSBPSU_EVENT_SIZE * \
XUSBPSU_EVENT_MAX_NUM)
#define XUSBPSU_EVENT_TYPE_MASK 0xfe
#define XUSBPSU_EVENT_TYPE_DEV 0
#define XUSBPSU_EVENT_TYPE_CARKIT 3
#define XUSBPSU_EVENT_TYPE_I2C 4
#define XUSBPSU_DEVICE_EVENT_DISCONNECT 0
#define XUSBPSU_DEVICE_EVENT_RESET 1
#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE 2
#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3
#define XUSBPSU_DEVICE_EVENT_WAKEUP 4
#define XUSBPSU_DEVICE_EVENT_HIBER_REQ 5
#define XUSBPSU_DEVICE_EVENT_EOPF 6
#define XUSBPSU_DEVICE_EVENT_SOF 7
#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR 9
#define XUSBPSU_DEVICE_EVENT_CMD_CMPL 10
#define XUSBPSU_DEVICE_EVENT_OVERFLOW 11
#define XUSBPSU_GEVNTCOUNT_MASK 0xfffc
/*
* Control Endpoint state
*/
#define XUSBPSU_EP0_SETUP_PHASE 1 /**< Setup Phase */
#define XUSBPSU_EP0_DATA_PHASE 2 /**< Data Phase */
#define XUSBPSU_EP0_STATUS_PHASE 3 /**< Status Pahse */
/*
* Link State
*/
#define XUSBPSU_LINK_STATE_U0 0x00 /**< in HS - ON */
#define XUSBPSU_LINK_STATE_U1 0x01
#define XUSBPSU_LINK_STATE_U2 0x02 /**< in HS - SLEEP */
#define XUSBPSU_LINK_STATE_U3 0x03 /**< in HS - SUSPEND */
#define XUSBPSU_LINK_STATE_SS_DIS 0x04
#define XUSBPSU_LINK_STATE_RX_DET 0x05
#define XUSBPSU_LINK_STATE_SS_INACT 0x06
#define XUSBPSU_LINK_STATE_POLL 0x07
#define XUSBPSU_LINK_STATE_RECOV 0x08
#define XUSBPSU_LINK_STATE_HRESET 0x09
#define XUSBPSU_LINK_STATE_CMPLY 0x0A
#define XUSBPSU_LINK_STATE_LPBK 0x0B
#define XUSBPSU_LINK_STATE_RESET 0x0E
#define XUSBPSU_LINK_STATE_RESUME 0x0F
#define XUSBPSU_LINK_STATE_MASK 0x0F
/*
* Device States
*/
#define XUSBPSU_STATE_ATTACHED 0
#define XUSBPSU_STATE_POWERED 1
#define XUSBPSU_STATE_DEFAULT 2
#define XUSBPSU_STATE_ADDRESS 3
#define XUSBPSU_STATE_CONFIGURED 4
#define XUSBPSU_STATE_SUSPENDED 5
/*
* Device Speeds
*/
#define XUSBPSU_SPEED_UNKNOWN 0
#define XUSBPSU_SPEED_LOW 1
#define XUSBPSU_SPEED_FULL 2
#define XUSBPSU_SPEED_HIGH 3
#define XUSBPSU_SPEED_SUPER 4
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the XUSBPSU
* device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of controller */
u32 BaseAddress; /**< Core register base address */
} XUsbPsu_Config;
/**
* Software Event buffer representation
*/
struct XUsbPsu_EvtBuffer {
void *BuffAddr;
u32 Offset;
u32 Count;
u32 Flags;
};
/**
* Transfer Request Block - Hardware format
*/
struct XUsbPsu_Trb {
u32 BufferPtrLow;
u32 BufferPtrHigh;
u32 Size;
u32 Ctrl;
} __attribute__((packed));
/*
* Endpoint Parameters
*/
struct XUsbPsu_EpParams {
u32 Param2; /**< Parameter 2 */
u32 Param1; /**< Parameter 1 */
u32 Param0; /**< Parameter 0 */
};
/**
* USB Standard Control Request
*/
typedef struct {
u8 bRequestType;
u8 bRequest;
u16 wValue;
u16 wIndex;
u16 wLength;
} __attribute__ ((packed)) SetupPacket;
/**
* Endpoint representation
*/
struct XUsbPsu_Ep {
void (*Handler)(void *, u32, u32);
/** < User handler called
* when data is sent for IN Ep
* and received for OUT Ep
*/
struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
u32 EpStatus; /**< Flags to represent Endpoint status */
u32 RequestedBytes; /**< RequestedBytes for transfer */
u32 BytesTxed; /**< Actual Bytes transferred */
u32 Cmd; /**< command issued to EP lately */
u16 MaxSize; /**< Size of endpoint */
u8 *BufferPtr; /**< Buffer location */
u8 ResourceIndex; /**< Resource Index assigned to
* Endpoint by core
*/
u8 PhyEpNum; /**< Physical Endpoint Number in core */
u8 UsbEpNum; /**< USB Endpoint Number */
u8 Type; /**< Type of Endpoint -
* Control/BULK/INTERRUPT/ISOC
*/
u8 Direction; /**< Direction - EP_DIR_OUT/EP_DIR_IN */
u8 UnalignedTx;
};
/**
* USB Device Controller representation
*/
struct XUsbPsu {
SetupPacket SetupData ALIGNMENT_CACHELINE;
/**< Setup Packet buffer */
struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
/**< TRB for control transfers */
XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */
struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
struct XUsbPsu_EvtBuffer Evt;
struct XUsbPsu_EpParams EpParams;
u32 BaseAddress; /**< Core register base address */
u32 MaxSpeed;
u32 DevDescSize;
u32 ConfigDescSize;
void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
void *DevDesc;
void *ConfigDesc;
u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
__attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
u8 NumOutEps;
u8 NumInEps;
u8 ControlDir;
u8 IsInTestMode;
u8 TestMode;
u8 Speed;
u8 State;
u8 Ep0State;
u8 LinkState;
u8 UnalignedTx;
u8 IsConfigDone;
u8 IsThreeStage;
};
struct XUsbPsu_Event_Type {
u32 Is_DevEvt:1;
u32 Type:7;
u32 Reserved8_31:24;
} __attribute__((packed));
/**
* struct XUsbPsu_event_depvt - Device Endpoint Events
* @Is_EpEvt: indicates this is an endpoint event
* @endpoint_number: number of the endpoint
* @endpoint_event: The event we have:
* 0x00 - Reserved
* 0x01 - XferComplete
* 0x02 - XferInProgress
* 0x03 - XferNotReady
* 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
* 0x05 - Reserved
* 0x06 - StreamEvt
* 0x07 - EPCmdCmplt
* @Reserved11_10: Reserved, don't use.
* @Status: Indicates the status of the event. Refer to databook for
* more information.
* @Parameters: Parameters of the current event. Refer to databook for
* more information.
*/
struct XUsbPsu_Event_Epevt {
u32 Is_EpEvt:1;
u32 Epnumber:5;
u32 Endpoint_Event:4;
u32 Reserved11_10:2;
u32 Status:4;
u32 Parameters:16;
} __attribute__((packed));
/**
* struct XUsbPsu_event_devt - Device Events
* @Is_DevEvt: indicates this is a non-endpoint event
* @Device_Event: indicates it's a device event. Should read as 0x00
* @Type: indicates the type of device event.
* 0 - DisconnEvt
* 1 - USBRst
* 2 - ConnectDone
* 3 - ULStChng
* 4 - WkUpEvt
* 5 - Reserved
* 6 - EOPF
* 7 - SOF
* 8 - Reserved
* 9 - ErrticErr
* 10 - CmdCmplt
* 11 - EvntOverflow
* 12 - VndrDevTstRcved
* @Reserved15_12: Reserved, not used
* @Event_Info: Information about this event
* @Reserved31_25: Reserved, not used
*/
struct XUsbPsu_Event_Devt {
u32 Is_DevEvt:1;
u32 Device_Event:7;
u32 Type:4;
u32 Reserved15_12:4;
u32 Event_Info:9;
u32 Reserved31_25:7;
} __attribute__((packed));
/**
* struct XUsbPsu_event_gevt - Other Core Events
* @one_bit: indicates this is a non-endpoint event (not used)
* @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
* @phy_port_number: self-explanatory
* @reserved31_12: Reserved, not used.
*/
struct XUsbPsu_Event_Gevt {
u32 Is_GlobalEvt:1;
u32 Device_Event:7;
u32 Phy_Port_Number:4;
u32 Reserved31_12:20;
} __attribute__((packed));
/**
* union XUsbPsu_event - representation of Event Buffer contents
* @raw: raw 32-bit event
* @type: the type of the event
* @depevt: Device Endpoint Event
* @devt: Device Event
* @gevt: Global Event
*/
union XUsbPsu_Event {
u32 Raw;
struct XUsbPsu_Event_Type Type;
struct XUsbPsu_Event_Epevt Epevt;
struct XUsbPsu_Event_Devt Devt;
struct XUsbPsu_Event_Gevt Gevt;
};
/***************** Macros (Inline Functions) Definitions *********************/
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
#define roundup(x, y) ( \
{ \
const typeof(y) __y = y; \
(((x) + (__y - 1)) / __y) * __y; \
} \
)
#define DECLARE_DEV_DESC(Instance, desc) \
(Instance).DevDesc = &(desc); \
(Instance).DevDescSize = sizeof((desc))
#define DECLARE_CONFIG_DESC(Instance, desc) \
(Instance).ConfigDesc = &(desc); \
(Instance).ConfigDescSize = sizeof((desc))
/************************** Function Prototypes ******************************/
/*
* Functions in xusbpsu.c
*/
int XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout);
int XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
u32 BitMask, u32 Timeout);
void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 mode);
void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
int XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
int XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
int XUsbPsu_Start(struct XUsbPsu *InstancePtr);
int XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
int XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, int mode);
u32 XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
int XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
u8 state);
int XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
int cmd, u32 param);
void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
int XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
/*
* Functions in xusbpsu_endpoint.c
*/
struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
u8 dir);
const char *XUsbPsu_EpCmdString(u8 cmd);
int XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 ep, u8 direction,
u32 cmd, struct XUsbPsu_EpParams *params);
int XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 ep,
u8 dir);
int XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 ep, u8 dir,
u16 size, u8 type);
int XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 ep, u8 dir);
int XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir,
u16 maxsize, u8 type);
int XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 dir);
int XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 size);
void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 ep, u8 dir);
void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
int XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 EpNum,
u8 *BufferPtr, u32 BufferLen);
int XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 EpNum,
u8 *BufferPtr, u32 length);
void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir);
void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 epnum, u8 Dir);
void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 epnum,
u8 dir, void (*Handler)(void *, u32, u32));
int XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
/*
* Functions in xusbpsu_controltransfers.c
*/
int XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
int XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
SetupPacket *ctrl);
void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
int XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
struct XUsbPsu_Ep *dep);
void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
int XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
u32 BufferLen);
int XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
/*
* Functions in xusbpsu_intr.c
*/
void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Epevt *event);
void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
u32 evtinfo);
void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
const struct XUsbPsu_Event_Devt *event);
void XUsbPsu_ProcessEvent(struct XUsbPsu *InstancePtr,
const union XUsbPsu_Event *event);
void XUsbPsu_ProcessEvtBuffer(struct XUsbPsu *InstancePtr);
void XUsbPsu_IntrHandler(void *XUsbPsu);
/*
* Functions in xusbpsu_sinit.c
*/
XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */

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/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xusbpsu_hw.h
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 01/22/15 First release
*
* </pre>
*
*****************************************************************************/
#ifndef XUSBPSU_HW_H /* Prevent circular inclusions */
#define XUSBPSU_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
/************************** Constant Definitions ****************************/
/**@name Register offsets
*
* The following constants provide access to each of the registers of the
* USBPSU device.
* @{
*/
/* XUSBPSU registers memory space boundries */
#define XUSBPSU_GLOBALS_REGS_START 0xc100
#define XUSBPSU_GLOBALS_REGS_END 0xc6ff
#define XUSBPSU_DEVICE_REGS_START 0xc700
#define XUSBPSU_DEVICE_REGS_END 0xcbff
#define XUSBPSU_OTG_REGS_START 0xcc00
#define XUSBPSU_OTG_REGS_END 0xccff
/* Global Registers */
#define XUSBPSU_GSBUSCFG0 0xc100
#define XUSBPSU_GSBUSCFG1 0xc104
#define XUSBPSU_GTXTHRCFG 0xc108
#define XUSBPSU_GRXTHRCFG 0xc10c
#define XUSBPSU_GCTL 0xc110
#define XUSBPSU_GEVTEN 0xc114
#define XUSBPSU_GSTS 0xc118
#define XUSBPSU_GSNPSID 0xc120
#define XUSBPSU_GGPIO 0xc124
#define XUSBPSU_GUID 0xc128
#define XUSBPSU_GUCTL 0xc12c
#define XUSBPSU_GBUSERRADDR0 0xc130
#define XUSBPSU_GBUSERRADDR1 0xc134
#define XUSBPSU_GPRTBIMAP0 0xc138
#define XUSBPSU_GPRTBIMAP1 0xc13c
#define XUSBPSU_GHWPARAMS0_OFFSET 0xc140
#define XUSBPSU_GHWPARAMS1_OFFSET 0xc144
#define XUSBPSU_GHWPARAMS2_OFFSET 0xc148
#define XUSBPSU_GHWPARAMS3_OFFSET 0xc14c
#define XUSBPSU_GHWPARAMS4_OFFSET 0xc150
#define XUSBPSU_GHWPARAMS5_OFFSET 0xc154
#define XUSBPSU_GHWPARAMS6_OFFSET 0xc158
#define XUSBPSU_GHWPARAMS7_OFFSET 0xc15c
#define XUSBPSU_GDBGFIFOSPACE 0xc160
#define XUSBPSU_GDBGLTSSM 0xc164
#define XUSBPSU_GPRTBIMAP_HS0 0xc180
#define XUSBPSU_GPRTBIMAP_HS1 0xc184
#define XUSBPSU_GPRTBIMAP_FS0 0xc188
#define XUSBPSU_GPRTBIMAP_FS1 0xc18c
#define XUSBPSU_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
#define XUSBPSU_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
#define XUSBPSU_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
#define XUSBPSU_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
#define XUSBPSU_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
#define XUSBPSU_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
#define XUSBPSU_GEVNTADRLO(n) (0xc400 + (n * 0x10))
#define XUSBPSU_GEVNTADRHI(n) (0xc404 + (n * 0x10))
#define XUSBPSU_GEVNTSIZ(n) (0xc408 + (n * 0x10))
#define XUSBPSU_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
#define XUSBPSU_GHWPARAMS8 0xc600
/* Device Registers */
#define XUSBPSU_DCFG 0xc700
#define XUSBPSU_DCTL 0xc704
#define XUSBPSU_DEVTEN 0xc708
#define XUSBPSU_DSTS 0xc70c
#define XUSBPSU_DGCMDPAR 0xc710
#define XUSBPSU_DGCMD 0xc714
#define XUSBPSU_DALEPENA 0xc720
#define XUSBPSU_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
#define XUSBPSU_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
#define XUSBPSU_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
#define XUSBPSU_DEPCMD(n) (0xc80c + (n * 0x10))
/* OTG Registers */
#define XUSBPSU_OCFG 0xcc00
#define XUSBPSU_OCTL 0xcc04
#define XUSBPSU_OEVT 0xcc08
#define XUSBPSU_OEVTEN 0xcc0C
#define XUSBPSU_OSTS 0xcc10
/* Bit fields */
/* Global Configuration Register */
#define XUSBPSU_GCTL_PWRDNSCALE(n) ((n) << 19)
#define XUSBPSU_GCTL_U2RSTECN (1 << 16)
#define XUSBPSU_GCTL_RAMCLKSEL(x) (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
#define XUSBPSU_GCTL_CLK_BUS (0)
#define XUSBPSU_GCTL_CLK_PIPE (1)
#define XUSBPSU_GCTL_CLK_PIPEHALF (2)
#define XUSBPSU_GCTL_CLK_MASK (3)
#define XUSBPSU_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
#define XUSBPSU_GCTL_PRTCAPDIR(n) ((n) << 12)
#define XUSBPSU_GCTL_PRTCAP_HOST 1
#define XUSBPSU_GCTL_PRTCAP_DEVICE 2
#define XUSBPSU_GCTL_PRTCAP_OTG 3
#define XUSBPSU_GCTL_CORESOFTRESET (1 << 11)
#define XUSBPSU_GCTL_SOFITPSYNC (1 << 10)
#define XUSBPSU_GCTL_SCALEDOWN(n) ((n) << 4)
#define XUSBPSU_GCTL_SCALEDOWN_MASK XUSBPSU_GCTL_SCALEDOWN(3)
#define XUSBPSU_GCTL_DISSCRAMBLE (1 << 3)
#define XUSBPSU_GCTL_GBLHIBERNATIONEN (1 << 1)
#define XUSBPSU_GCTL_DSBLCLKGTNG (1 << 0)
/* Global Status Register Device Interrupt Mask */
#define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040
/* Global USB2 PHY Configuration Register */
#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
#define XUSBPSU_GUSB2PHYCFG_SUSPHY (1 << 6)
/* Global USB3 PIPE Control Register */
#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
#define XUSBPSU_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
/* Global Event Size Registers */
#define XUSBPSU_GEVNTSIZ_INTMASK (1 << 31)
#define XUSBPSU_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
/* Global HWPARAMS1 Register */
#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO 0
#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK 1
#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB 2
#define XUSBPSU_GHWPARAMS1_PWROPT(n) ((n) << 24)
#define XUSBPSU_GHWPARAMS1_PWROPT_MASK XUSBPSU_GHWPARAMS1_PWROPT(3)
/* Global HWPARAMS4 Register */
#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
#define XUSBPSU_MAX_HIBER_SCRATCHBUFS 15
/* Device Configuration Register */
#define XUSBPSU_DCFG_DEVADDR(addr) ((addr) << 3)
#define XUSBPSU_DCFG_DEVADDR_MASK XUSBPSU_DCFG_DEVADDR(0x7f)
#define XUSBPSU_DCFG_SPEED_MASK 7
#define XUSBPSU_DCFG_SUPERSPEED 4
#define XUSBPSU_DCFG_HIGHSPEED 0
#define XUSBPSU_DCFG_FULLSPEED2 1
#define XUSBPSU_DCFG_LOWSPEED 2
#define XUSBPSU_DCFG_FULLSPEED1 3
#define XUSBPSU_DCFG_LPM_CAP (1 << 22)
/* Device Control Register */
#define XUSBPSU_DCTL_RUN_STOP (1 << 31)
#define XUSBPSU_DCTL_CSFTRST (1 << 30)
#define XUSBPSU_DCTL_LSFTRST (1 << 29)
#define XUSBPSU_DCTL_HIRD_THRES_MASK (0x1f << 24)
#define XUSBPSU_DCTL_HIRD_THRES(n) ((n) << 24)
#define XUSBPSU_DCTL_APPL1RES (1 << 23)
/* These apply for core versions 1.87a and earlier */
#define XUSBPSU_DCTL_TRGTULST_MASK (0x0f << 17)
#define XUSBPSU_DCTL_TRGTULST(n) ((n) << 17)
#define XUSBPSU_DCTL_TRGTULST_U2 (XUSBPSU_DCTL_TRGTULST(2))
#define XUSBPSU_DCTL_TRGTULST_U3 (XUSBPSU_DCTL_TRGTULST(3))
#define XUSBPSU_DCTL_TRGTULST_SS_DIS (XUSBPSU_DCTL_TRGTULST(4))
#define XUSBPSU_DCTL_TRGTULST_RX_DET (XUSBPSU_DCTL_TRGTULST(5))
#define XUSBPSU_DCTL_TRGTULST_SS_INACT (XUSBPSU_DCTL_TRGTULST(6))
/* These apply for core versions 1.94a and later */
#define XUSBPSU_DCTL_KEEP_CONNECT (1 << 19)
#define XUSBPSU_DCTL_L1_HIBER_EN (1 << 18)
#define XUSBPSU_DCTL_CRS (1 << 17)
#define XUSBPSU_DCTL_CSS (1 << 16)
#define XUSBPSU_DCTL_INITU2ENA (1 << 12)
#define XUSBPSU_DCTL_ACCEPTU2ENA (1 << 11)
#define XUSBPSU_DCTL_INITU1ENA (1 << 10)
#define XUSBPSU_DCTL_ACCEPTU1ENA (1 << 9)
#define XUSBPSU_DCTL_TSTCTRL_MASK (0xf << 1)
#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION (XUSBPSU_DCTL_ULSTCHNGREQ(0))
#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED (XUSBPSU_DCTL_ULSTCHNGREQ(4))
#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT (XUSBPSU_DCTL_ULSTCHNGREQ(5))
#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE (XUSBPSU_DCTL_ULSTCHNGREQ(6))
#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY (XUSBPSU_DCTL_ULSTCHNGREQ(8))
#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE (XUSBPSU_DCTL_ULSTCHNGREQ(10))
#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK (XUSBPSU_DCTL_ULSTCHNGREQ(11))
/* Device Event Enable Register */
#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN (1 << 11)
#define XUSBPSU_DEVTEN_CMDCMPLTEN (1 << 10)
#define XUSBPSU_DEVTEN_ERRTICERREN (1 << 9)
#define XUSBPSU_DEVTEN_SOFEN (1 << 7)
#define XUSBPSU_DEVTEN_EOPFEN (1 << 6)
#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
#define XUSBPSU_DEVTEN_WKUPEVTEN (1 << 4)
#define XUSBPSU_DEVTEN_ULSTCNGEN (1 << 3)
#define XUSBPSU_DEVTEN_CONNECTDONEEN (1 << 2)
#define XUSBPSU_DEVTEN_USBRSTEN (1 << 1)
#define XUSBPSU_DEVTEN_DISCONNEVTEN (1 << 0)
/* Device Status Register */
#define XUSBPSU_DSTS_DCNRD (1 << 29)
/* This applies for core versions 1.87a and earlier */
#define XUSBPSU_DSTS_PWRUPREQ (1 << 24)
/* These apply for core versions 1.94a and later */
#define XUSBPSU_DSTS_RSS (1 << 25)
#define XUSBPSU_DSTS_SSS (1 << 24)
#define XUSBPSU_DSTS_COREIDLE (1 << 23)
#define XUSBPSU_DSTS_DEVCTRLHLT (1 << 22)
#define XUSBPSU_DSTS_USBLNKST_MASK (0x0f << 18)
#define XUSBPSU_DSTS_USBLNKST(n) (((n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
#define XUSBPSU_DSTS_RXFIFOEMPTY (1 << 17)
#define XUSBPSU_DSTS_SOFFN_MASK (0x3fff << 3)
#define XUSBPSU_DSTS_SOFFN(n) (((n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
#define XUSBPSU_DSTS_CONNECTSPD (7 << 0)
#define XUSBPSU_DSTS_SUPERSPEED (4 << 0)
#define XUSBPSU_DSTS_HIGHSPEED (0 << 0)
#define XUSBPSU_DSTS_FULLSPEED2 (1 << 0)
#define XUSBPSU_DSTS_LOWSPEED (2 << 0)
#define XUSBPSU_DSTS_FULLSPEED1 (3 << 0)
/* Device Generic Command Register */
#define XUSBPSU_DGCMD_SET_LMP 0x01
#define XUSBPSU_DGCMD_SET_PERIODIC_PAR 0x02
#define XUSBPSU_DGCMD_XMIT_FUNCTION 0x03
/* These apply for core versions 1.94a and later */
#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH 0x09
#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH 0x0a
#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY 0x0c
#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
#define XUSBPSU_DGCMD_STATUS(n) (((n) >> 15) & 1)
#define XUSBPSU_DGCMD_CMDACT (1 << 10)
#define XUSBPSU_DGCMD_CMDIOC (1 << 8)
/* Device Generic Command Parameter Register */
#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
#define XUSBPSU_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
#define XUSBPSU_DGCMDPAR_RX_FIFO (0 << 5)
#define XUSBPSU_DGCMDPAR_TX_FIFO (1 << 5)
#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS (0 << 0)
#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA (1 << 0)
/* Device Endpoint Command Register */
#define XUSBPSU_DEPCMD_PARAM_SHIFT 16
#define XUSBPSU_DEPCMD_PARAM(x) ((x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
#define XUSBPSU_DEPCMD_GET_RSC_IDX(x) (((x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
0x7f)
#define XUSBPSU_DEPCMD_STATUS(x) (((x) >> 12) & 0xF)
#define XUSBPSU_DEPCMD_HIPRI_FORCERM (1 << 11)
#define XUSBPSU_DEPCMD_CMDACT (1 << 10)
#define XUSBPSU_DEPCMD_CMDIOC (1 << 8)
#define XUSBPSU_DEPCMD_DEPSTARTCFG 0x09
#define XUSBPSU_DEPCMD_ENDTRANSFER 0x08
#define XUSBPSU_DEPCMD_UPDATETRANSFER 0x07
#define XUSBPSU_DEPCMD_STARTTRANSFER 0x06
#define XUSBPSU_DEPCMD_CLEARSTALL 0x05
#define XUSBPSU_DEPCMD_SETSTALL 0x04
#define XUSBPSU_DEPCMD_GETEPSTATE 0x03
#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE 0x02
#define XUSBPSU_DEPCMD_SETEPCONFIG 0x01
/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
#define XUSBPSU_DALEPENA_EP(n) (1 << n)
#define XUSBPSU_DEPCFG_INT_NUM(n) ((n) << 0)
#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN (1 << 8)
#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN (1 << 10)
#define XUSBPSU_DEPCFG_FIFO_ERROR_EN (1 << 11)
#define XUSBPSU_DEPCFG_STREAM_EVENT_EN (1 << 13)
#define XUSBPSU_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
#define XUSBPSU_DEPCFG_STREAM_CAPABLE (1 << 24)
#define XUSBPSU_DEPCFG_EP_NUMBER(n) ((n) << 25)
#define XUSBPSU_DEPCFG_BULK_BASED (1 << 30)
#define XUSBPSU_DEPCFG_FIFO_BASED (1 << 31)
/* DEPCFG parameter 0 */
#define XUSBPSU_DEPCFG_EP_TYPE(n) ((n) << 1)
#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
#define XUSBPSU_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
#define XUSBPSU_DEPCFG_BURST_SIZE(n) ((n) << 22)
#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
/* This applies for core versions earlier than 1.94a */
#define XUSBPSU_DEPCFG_IGN_SEQ_NUM (1 << 31)
/* These apply for core versions 1.94a and later */
#define XUSBPSU_DEPCFG_ACTION_INIT (0 << 30)
#define XUSBPSU_DEPCFG_ACTION_RESTORE (1 << 30)
#define XUSBPSU_DEPCFG_ACTION_MODIFY (2 << 30)
/* DEPXFERCFG parameter 0 */
#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
#define XUSBPSU_DEPCMD_TYPE_BULK 2
#define XUSBPSU_DEPCMD_TYPE_INTR 3
/* TRB Length, PCM and Status */
#define XUSBPSU_TRB_SIZE_MASK (0x00ffffff)
#define XUSBPSU_TRB_SIZE_LENGTH(n) ((n) & XUSBPSU_TRB_SIZE_MASK)
#define XUSBPSU_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
#define XUSBPSU_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
#define XUSBPSU_TRBSTS_OK 0
#define XUSBPSU_TRBSTS_MISSED_ISOC 1
#define XUSBPSU_TRBSTS_SETUP_PENDING 2
#define XUSBPSU_TRB_STS_XFER_IN_PROG 4
/* TRB Control */
#define XUSBPSU_TRB_CTRL_HWO (1 << 0)
#define XUSBPSU_TRB_CTRL_LST (1 << 1)
#define XUSBPSU_TRB_CTRL_CHN (1 << 2)
#define XUSBPSU_TRB_CTRL_CSP (1 << 3)
#define XUSBPSU_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
#define XUSBPSU_TRB_CTRL_ISP_IMI (1 << 10)
#define XUSBPSU_TRB_CTRL_IOC (1 << 11)
#define XUSBPSU_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
#define XUSBPSU_TRBCTL_NORMAL XUSBPSU_TRB_CTRL_TRBCTL(1)
#define XUSBPSU_TRBCTL_CONTROL_SETUP XUSBPSU_TRB_CTRL_TRBCTL(2)
#define XUSBPSU_TRBCTL_CONTROL_STATUS2 XUSBPSU_TRB_CTRL_TRBCTL(3)
#define XUSBPSU_TRBCTL_CONTROL_STATUS3 XUSBPSU_TRB_CTRL_TRBCTL(4)
#define XUSBPSU_TRBCTL_CONTROL_DATA XUSBPSU_TRB_CTRL_TRBCTL(5)
#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST XUSBPSU_TRB_CTRL_TRBCTL(6)
#define XUSBPSU_TRBCTL_ISOCHRONOUS XUSBPSU_TRB_CTRL_TRBCTL(7)
#define XUSBPSU_TRBCTL_LINK_TRB XUSBPSU_TRB_CTRL_TRBCTL(8)
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the USBPS8 device. This macro provides register
* access to all registers using the register offsets defined above.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param Offset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
*
******************************************************************************/
#define XUsbPsu_ReadReg(InstancePtr, Offset) \
Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (Offset))
/*****************************************************************************/
/**
*
* Write a register of the USBPS8 device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param InstancePtr is a pointer to the XUsbPsu instance.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
* u32 Offset,u32 Data)
*
******************************************************************************/
#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (Offset), (Data))
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */

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