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Update the memory alignment within the Cortex-A9 port asm code (#426)

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Update alignment in ARM_CA9 port.
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RichardBarry 2023-12-09 01:19:39 -08:00 committed by GitHub
parent a79752a04a
commit 553caa18ce
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 16 additions and 3 deletions
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19
portable/GCC/ARM_CA9/portASM.S
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@ -75,9 +75,9 @@
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
PUSHNE {R1}
VPUSHNE {D0-D15}
VPUSHNE {D16-D31}
PUSHNE {R1}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
@ -106,9 +106,9 @@
CMP R1, #0
/* Restore the floating point context, if any. */
POPNE {R0}
VPOPNE {D16-D31}
VPOPNE {D0-D15}
POPNE {R0}
VMSRNE FPSCR, R0
/* Restore the critical section nesting depth. */
@ -145,8 +145,15 @@
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
/* Ensure bit 2 of the stack pointer is clear. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
LDR R0, vTaskSwitchContextConst
BLX R0
portRESTORE_CONTEXT
@ -256,7 +263,13 @@ switch_before_exit:
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
LDR R0, vTaskSwitchContextConst
BLX R0