len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-04-21 05:52:09 -04:00
Code Issues Packages Projects Releases Wiki Activity

Update LPC18xx FreeRTOS+UDP demo to use LPCOpen USB and Ethernet drivers.

Browse source 
Update LPC18xx FreeRTOS+UDP eclipse project to use linked resources rather than a CreateProjectDirectoryStructure.bat batch file.
This commit is contained in:
Richard Barry 2013-06-03 20:21:38 +00:00
parent 0158039f99
commit 54c62d429f
314 changed files with 63143 additions and 60065 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

60
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject
View file

@ -40,19 +40,27 @@
<listOptionValue builtIn="false" value="CORE_M3"/>
<listOptionValue builtIn="false" value="__LPC18XX__"/>
</option>
<option id="gnu.c.compiler.option.misc.other.732935978" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -Wextra" valueType="string"/>
<option id="gnu.c.compiler.option.misc.other.732935978" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -std=gnu99" valueType="string"/>
<option id="com.crt.advproject.gcc.hdrlib.1620518189" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.codered" valueType="enumerated"/>
<option id="gnu.c.compiler.option.include.paths.1643954527" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Examples/Ethernet/EchoClients}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Examples/Ethernet/UDP-Trace-Macros/Example1}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Examples/USB_CDC}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_common}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/CMSIS/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_ip}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/TraceRecorderSrc/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Plus_CLI}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Examples/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/USB_CDC/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM3}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Plus_UDP/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Plus_UDP/portable/Compiler/GCC}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS-Plus-CLI}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS-Source/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS-Source/portable/GCC/ARM_CM3}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS-Plus-UDP/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS-Plus-UDP/portable/Compiler/GCC}&quot;"/>
</option>
<inputType id="com.crt.advproject.compiler.input.927112517" superClass="com.crt.advproject.compiler.input"/>
</tool>
@ -78,6 +86,7 @@
</option>
<option id="com.crt.advproject.link.gcc.hdrlib.2006557555" name="Use C library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.codered.nohost" valueType="enumerated"/>
<option id="gnu.c.link.option.nodeflibs.2072403274" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.c.link.option.nodeflibs" value="false" valueType="boolean"/>
<option id="com.crt.advproject.link.gcc.multicore.slave.1593308693" name="Multicore slave" superClass="com.crt.advproject.link.gcc.multicore.slave"/>
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1085761099" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@ -101,40 +110,9 @@
<tool id="com.crt.advproject.link.exe.debug.953255510" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>
</toolChain>
</folderInfo>
<folderInfo id="com.crt.advproject.config.exe.debug.56486929.1781697322" name="/" resourcePath="ThirdParty/CMSISv2p10_LPC18xx_DriverLib">
<toolChain id="com.crt.advproject.toolchain.exe.debug.222538953" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">
<tool id="com.crt.advproject.cpp.exe.debug.906161578" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.359174792"/>
<tool id="com.crt.advproject.gcc.exe.debug.1015468334" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.517029683">
<option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.2021633161" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>
<inputType id="com.crt.advproject.compiler.input.1878730423" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool id="com.crt.advproject.gas.exe.debug.253843695" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.281614531">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1935362347" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
<inputType id="com.crt.advproject.assembler.input.190369423" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
</tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.1715304950" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.1490011469"/>
<tool id="com.crt.advproject.link.exe.debug.536813209" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>
</toolChain>
</folderInfo>
<folderInfo id="com.crt.advproject.config.exe.debug.56486929.2106668528" name="/" resourcePath="ThirdParty/USB_CDC">
<toolChain id="com.crt.advproject.toolchain.exe.debug.1865989435" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">
<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.1158267972" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.359174792"/>
<tool id="com.crt.advproject.gcc.exe.debug.1784372430" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.517029683">
<option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.369260631" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>
<inputType id="com.crt.advproject.compiler.input.466388069" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool id="com.crt.advproject.gas.exe.debug.401476199" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.281614531">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1255426283" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
<inputType id="com.crt.advproject.assembler.input.882456885" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
</tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.2009352548" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.1490011469"/>
<tool id="com.crt.advproject.link.exe.debug.1734116997" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>
</toolChain>
</folderInfo>
<fileInfo id="com.crt.advproject.config.exe.debug.56486929.src/cr_startup_lpc18xx.cpp" name="cr_startup_lpc18xx.cpp" rcbsApplicability="disable" resourcePath="src/cr_startup_lpc18xx.cpp" toolsToInvoke=""/>
<sourceEntries>
<entry excluding="ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

153
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project
View file

@ -23,4 +23,157 @@
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>FreeRTOS-Plus-CLI</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Source</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>Examples/Ethernet</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/FreeRTOS_DNS.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DNS.c</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/include</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Source/include</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/include</locationURI>
</link>
<link>
<name>FreeRTOS-Source/list.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/list.c</locationURI>
</link>
<link>
<name>FreeRTOS-Source/portable</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Source/queue.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/queue.c</locationURI>
</link>
<link>
<name>FreeRTOS-Source/tasks.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/tasks.c</locationURI>
</link>
<link>
<name>FreeRTOS-Source/timers.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/timers.c</locationURI>
</link>
<link>
<name>Examples/Ethernet/EchoClients</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients</locationURI>
</link>
<link>
<name>Examples/Ethernet/UDP-Trace-Macros</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/BufferManagement</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/Compiler</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/NetworkInterface</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Source/portable/GCC</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>FreeRTOS-Source/portable/MemMang</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>Examples/Ethernet/UDP-Trace-Macros/Example1</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/Compiler/GCC</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC</locationURI>
</link>
<link>
<name>FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx</locationURI>
</link>
<link>
<name>FreeRTOS-Source/portable/GCC/ARM_CM3</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/GCC/ARM_CM3</locationURI>
</link>
<link>
<name>FreeRTOS-Source/portable/MemMang/heap_4.c</name>
<type>1</type>
<locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c</locationURI>
</link>
</linkedResources>
<variableList>
<variable>
<name>FREERTOS_ROOT</name>
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
</variable>
</variableList>
</projectDescription>

76
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat
View file

@ -1,76 +0,0 @@
REM This file should be executed from the command line prior to the first
REM build. It will be necessary to refresh the Eclipse project once the
REM .bat file has been executed (normally just press F5 to refresh).
REM Copies all the required files from their location within the standard
REM FreeRTOS directory structure to under the Eclipse project directory.
REM This permits the Eclipse project to be used in 'managed' mode and without
REM having to setup any linked resources.
REM Standard paths
SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source
SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP
SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI
REM Have the files already been copied?
IF EXIST FreeRTOS_Source Goto END
REM Create the required directory structure.
MD FreeRTOS_Source
MD FreeRTOS_Source\include
MD FreeRTOS_Source\portable\
MD FreeRTOS_Source\portable\GCC
MD FreeRTOS_Source\portable\GCC\ARM_CM3
MD FreeRTOS_Source\portable\MemMang
MD FreeRTOS_Plus_UDP
MD FreeRTOS_Plus_UDP\include
MD FreeRTOS_Plus_UDP\portable
MD FreeRTOS_Plus_UDP\portable\Compiler
MD FreeRTOS_Plus_UDP\portable\Compiler\GCC
MD FreeRTOS_Plus_UDP\portable\BufferManagement
MD FreeRTOS_Plus_UDP\portable\NetworkInterface
MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
MD FreeRTOS_Plus_CLI
MD Examples\Ethernet
REM Copy the core kernel files into the SDK projects directory
copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source
copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source
REM Copy the common header files into the SDK projects directory
copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include
REM Copy the portable layer files into the projects directory
copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3
REM Copy the memory allocation file into the project's directory
copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang
REM Copy the FreeRTOS+UDP core files
copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP
copy %FREERTOS_UDP_SOURCE%\include\*.h FreeRTOS_Plus_UDP
copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP
copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include
REM Copy the FreeRTOS+UDP portable layer files
copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement
copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC
REM Copy the FreeRTOS+CLI files
copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI
REM Copy the echo client example implementation
copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet
copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include
REM Copy the example IP trace macro implementation
copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet
copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include
REM Copy the CLI commands implementation into the project directory.
copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c .
: END

313
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c
View file

@ -58,17 +58,16 @@
/* Standard includes. */
#include "string.h"
#include "stdio.h"
#include "limits.h"
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* Driver includes. */
#include "usbhw.h"
#include "cdcuser.h"
#include "usbcfg.h"
#include "usbuser.h"
/* LPCUSB includes. */
#include "USB.h"
#include "Descriptors.h"
/* Example includes. */
#include "FreeRTOS_CLI.h"
@ -88,30 +87,48 @@
static void prvCDCCommandConsoleTask( void *pvParameters );
/*
* Obtain a character from the CDC input. The calling task will be held in the
* Blocked state (so other tasks can execute) until a character is avilable.
* Some USB processing is deferred from LPCUSB interrupt service routines to
* LPCUSB functions that are called from a FreeRTOS task.
* prvNotifyTaskofUSBEvent() is used from interrupt event callback functions.
* It uses a semaphore to unblock the handling task whenever task level
* processing might be required.
*/
int8_t cGetCDCChar( void );
/*
* Initialise the third party virtual comport files driver
*/
static void prvSetupUSBDrivers( void );
static void prvNotifyTaskOfUSBEvent( void );
/*-----------------------------------------------------------*/
/* 'Given' by the CDC interrupt to unblock the receiving task when new data
is available. */
static xSemaphoreHandle xNewDataSemaphore = NULL;
/* 'Given' by the CDC interrupt to unblock the command console task when CDC
events are potentially waiting to be processed. */
static xSemaphoreHandle xCDCEventSemaphore = NULL;
/* Used to guard access to the CDC output, which is used by more than one
task. */
static xSemaphoreHandle xCDCMutex = NULL;
/* Const messages output by the command console. */
static const uint8_t * const pcWelcomeMessage = ( uint8_t * ) "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
static const uint8_t * const pcEndOfOutputMessage = ( uint8_t * ) "\r\n[Press ENTER to execute the previous command again]\r\n>";
static const uint8_t * const pcNewLine = ( uint8_t * ) "\r\n";
static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";
static const char * const pcNewLine = "\r\n";
/* LPCUSBlib CDC Class driver interface configuration and state information. */
static USB_ClassInfo_CDC_Device_t xVirtualCOMPort = {
.Config = {
.ControlInterfaceNumber = 0,
.DataINEndpointNumber = CDC_TX_EPNUM,
.DataINEndpointSize = CDC_TXRX_EPSIZE,
.DataINEndpointDoubleBank = false,
.DataOUTEndpointNumber = CDC_RX_EPNUM,
.DataOUTEndpointSize = CDC_TXRX_EPSIZE,
.DataOUTEndpointDoubleBank = false,
.NotificationEndpointNumber = CDC_NOTIFICATION_EPNUM,
.NotificationEndpointSize = CDC_NOTIFICATION_EPSIZE,
.NotificationEndpointDoubleBank = false,
.PortNumber = 0,
},
};
/*-----------------------------------------------------------*/
@ -119,14 +136,14 @@ void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPri
{
/* Create the semaphores and mutexes used by the CDC to task interface. */
xCDCMutex = xSemaphoreCreateMutex();
vSemaphoreCreateBinary( xNewDataSemaphore );
xCDCEventSemaphore = xSemaphoreCreateCounting( UINT_MAX, 0 );
configASSERT( xCDCMutex );
configASSERT( xNewDataSemaphore );
configASSERT( xCDCEventSemaphore );
/* Add the semaphore and mutex to the queue registry for viewing in the
kernel aware state viewer. */
vQueueAddToRegistry( xCDCMutex, ( signed char * ) "CDCMu" );
vQueueAddToRegistry( xNewDataSemaphore, ( signed char * ) "CDCDat" );
vQueueAddToRegistry( xCDCEventSemaphore, ( signed char * ) "CDCDat" );
/* Create that task that handles the console itself. */
xTaskCreate( prvCDCCommandConsoleTask, /* The task that implements the command console. */
@ -140,103 +157,114 @@ void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPri
static void prvCDCCommandConsoleTask( void *pvParameters )
{
int8_t cRxedChar, cInputIndex = 0, *pcOutputString;
static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
portBASE_TYPE xReturned;
char cRxedChar, *pcOutputString;
static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
portBASE_TYPE xReturned, xInputIndex = 0;
/* Just to avoid warnings about unused parameters. */
( void ) pvParameters;
/* Initialise LPCUSB CDC driver. */
USB_Init( xVirtualCOMPort.Config.PortNumber, USB_MODE_Device );
/* Obtain the address of the output buffer. Note there is no mutual
exclusion on this buffer as it is assumed only one command console
interface will be used at any one time. */
pcOutputString = FreeRTOS_CLIGetOutputBuffer();
/* Initialise the virtual com port (CDC) interface. */
prvSetupUSBDrivers();
pcOutputString = ( char * ) FreeRTOS_CLIGetOutputBuffer();
/* Send the welcome message. This probably won't be seen as the console
will not have been connected yet. */
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ) );
will not have been connected yet (the console cannot be connected until the
virtual COM port has enumerated). */
CDC_Device_SendData( &xVirtualCOMPort, pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ) );
for( ;; )
{
/* No characters received yet for the current input string. */
cRxedChar = 0;
/* Wait for new events to originate from the LPCUSB interrupts. */
// xSemaphoreTake( xCDCEventSemaphore, 100 );
/* Only interested in reading one character at a time. */
cRxedChar = cGetCDCChar();
/* LPCUSB function to process events latched by the USB interrupts. */
CDC_Device_USBTask( &xVirtualCOMPort );
USB_USBTask( xVirtualCOMPort.Config.PortNumber, USB_MODE_Device );
/* Ensure no other tasks are using the COM port. */
if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
{
/* Echo the character back. */
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) &cRxedChar, sizeof( uint8_t ) );
/* Was it the end of the line? */
if( cRxedChar == '\n' || cRxedChar == '\r' )
/* Have any characters been received? */
if( CDC_Device_BytesReceived( &xVirtualCOMPort ) != 0 )
{
/* Just to space the output from the input. */
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcNewLine, strlen( ( const char * ) pcNewLine ) );
/* Only interested in reading one character at a time. */
cRxedChar = CDC_Device_ReceiveByte( &xVirtualCOMPort );
/* See if the command is empty, indicating that the last command is
to be executed again. */
if( cInputIndex == 0 )
/* Echo the character back. */
CDC_Device_SendData( &xVirtualCOMPort, &cRxedChar, sizeof( uint8_t ) );
/* Was it an end of line character? */
if( cRxedChar == '\n' || cRxedChar == '\r' )
{
/* Copy the last command back into the input string. */
strcpy( ( char * ) cInputString, ( char * ) cLastInputString );
}
/* Just to space the output from the input. */
CDC_Device_SendData( &xVirtualCOMPort, pcNewLine, strlen( ( const char * ) pcNewLine ) );
/* Pass the received command to the command interpreter. The
command interpreter is called repeatedly until it returns pdFALSE
(indicating there is no more output) as it might generate more than
one string. */
do
{
/* Get the next output string from the command interpreter. */
xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
/* Write the generated string to the CDC. */
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcOutputString, strlen( ( const char * ) pcOutputString ) );
vTaskDelay( 1 );
} while( xReturned != pdFALSE );
/* All the strings generated by the input command have been sent.
Clear the input string ready to receive the next command. Remember
the command that was just processed first in case it is to be
processed again. */
strcpy( ( char * ) cLastInputString, ( char * ) cInputString );
cInputIndex = 0;
memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcEndOfOutputMessage, strlen( ( const char * ) pcEndOfOutputMessage ) );
}
else
{
if( cRxedChar == '\r' )
{
/* Ignore the character. */
}
else if( cRxedChar == '\b' )
{
/* Backspace was pressed. Erase the last character in the
string - if any. */
if( cInputIndex > 0 )
/* See if the command is empty, indicating that the last
command is to be executed again. */
if( xInputIndex == 0 )
{
cInputIndex--;
cInputString[ cInputIndex ] = '\0';
/* Copy the last command back into the input string. */
strcpy( ( char * ) cInputString, ( char * ) cLastInputString );
}
/* Pass the received command to the command interpreter.
The command interpreter is called repeatedly until it
returns pdFALSE (indicating there is no more output) as it
might generate more than one string. */
do
{
/* Get the next output string from the command
interpreter. */
xReturned = FreeRTOS_CLIProcessCommand( ( const int8_t * const ) cInputString, ( int8_t * ) pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
/* Write the generated string to the CDC. */
CDC_Device_SendData( &xVirtualCOMPort, pcOutputString, strlen( ( const char * ) pcOutputString ) );
} while( xReturned != pdFALSE );
/* All the strings generated by the input command have been
sent. Clear the input string ready to receive the next
command. Remember the command that was just processed first
in case it is to be processed again. */
strcpy( ( char * ) cLastInputString, ( char * ) cInputString );
xInputIndex = 0;
memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
CDC_Device_SendData( &xVirtualCOMPort, pcEndOfOutputMessage, strlen( ( const char * ) pcEndOfOutputMessage ) );
}
else
{
/* A character was entered. Add it to the string
entered so far. When a \n is entered the complete
string will be passed to the command interpreter. */
if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
if( cRxedChar == '\r' )
{
if( cInputIndex < cmdMAX_INPUT_SIZE )
/* Ignore the character. */
}
else if( cRxedChar == '\b' )
{
/* Backspace was pressed. Erase the last character in
thestring - if any. */
if( xInputIndex > 0 )
{
cInputString[ cInputIndex ] = cRxedChar;
cInputIndex++;
xInputIndex--;
cInputString[ xInputIndex ] = '\0';
}
}
else
{
/* A character was entered. Add it to the string
entered so far. When a \n is entered the complete
string will be passed to the command interpreter. */
if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
{
if( xInputIndex < cmdMAX_INPUT_SIZE )
{
cInputString[ xInputIndex ] = cRxedChar;
xInputIndex++;
}
}
}
}
@ -253,73 +281,64 @@ void vOutputString( const uint8_t * const pucMessage )
{
if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
{
USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pucMessage, strlen( ( const char * ) pucMessage ) );
CDC_Device_SendData( &xVirtualCOMPort, ( const char * const ) pucMessage, strlen( ( const char * ) pucMessage ) );
xSemaphoreGive( xCDCMutex );
}
}
/*-----------------------------------------------------------*/
int8_t cGetCDCChar( void )
{
int32_t lAvailableBytes, xBytes = 0;
int8_t cInputChar;
do
{
/* Are there any characters already available? */
CDC_OutBufAvailChar( &lAvailableBytes );
if( lAvailableBytes > 0 )
{
if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
{
/* Attempt to read one character. */
xBytes = 1;
xBytes = CDC_RdOutBuf( ( char * ) &cInputChar, &xBytes );
xSemaphoreGive( xCDCMutex );
}
}
if( xBytes == 0 )
{
/* A character was not available. Wait until signalled by the
CDC Rx callback function that new data has arrived. */
xSemaphoreTake( xNewDataSemaphore, portMAX_DELAY );
}
} while( xBytes == 0 );
return cInputChar;
}
/*-----------------------------------------------------------*/
/* Callback function executed by the USB interrupt when new data arrives. */
void vCDCNewDataNotify( void )
static void prvNotifyTaskOfUSBEvent( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
configASSERT( xNewDataSemaphore );
/* 'Give' the semaphore that signals the arrival of new data to the command
console task. */
xSemaphoreGiveFromISR( xNewDataSemaphore, &xHigherPriorityTaskWoken );
configASSERT( xCDCEventSemaphore );
xSemaphoreGiveFromISR( xCDCEventSemaphore, &xHigherPriorityTaskWoken );
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvSetupUSBDrivers( void )
/* Standard LPCUSB event handler. */
void EVENT_USB_Device_ConfigurationChanged( void )
{
LPC_USBDRV_INIT_T xUSBCallback;
/* Initialise the callback structure. */
memset( ( void * ) &xUSBCallback, 0, sizeof( LPC_USBDRV_INIT_T ) );
xUSBCallback.USB_Reset_Event = USB_Reset_Event;
xUSBCallback.USB_P_EP[ 0 ] = USB_EndPoint0;
xUSBCallback.USB_P_EP[ 1 ] = USB_EndPoint1;
xUSBCallback.USB_P_EP[ 2 ] = USB_EndPoint2;
xUSBCallback.ep0_maxp = USB_MAX_PACKET0;
/* Initialise then connect the USB. */
USB_Init( &xUSBCallback );
USB_Connect( pdTRUE );
CDC_Device_ConfigureEndpoints( &xVirtualCOMPort );
prvNotifyTaskOfUSBEvent();
}
/*-----------------------------------------------------------*/
/* Standard LPCUSB event handler. */
void EVENT_USB_Device_ControlRequest( void )
{
CDC_Device_ProcessControlRequest( &xVirtualCOMPort );
prvNotifyTaskOfUSBEvent();
}
/*-----------------------------------------------------------*/
/* Standard LPCUSB event handler. */
void EVENT_USB_Device_Connect(void)
{
prvNotifyTaskOfUSBEvent();
}
/*-----------------------------------------------------------*/
/* Standard LPCUSB event handler. */
void EVENT_USB_Device_Disconnect(void)
{
prvNotifyTaskOfUSBEvent();
}
/*-----------------------------------------------------------*/
/* Standard LPCUSB event handler. */
void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t *const CDCInterfaceInfo)
{
prvNotifyTaskOfUSBEvent();
}
/*-----------------------------------------------------------*/
/* Standard LPCUSB event handler. */
void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t *const CDCInterfaceInfo)
{
prvNotifyTaskOfUSBEvent();
}

0
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h → FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.h
View file

295
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/Descriptors.c Normal file
View file

@ -0,0 +1,295 @@
/*
* @brief USB Device Descriptors, for library use when in USB device mode. Descriptors are special
* computer-readable structures which the host requests upon device enumeration, to determine
* the device's capabilities and functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "Descriptors.h"
/* On some devices, there is a factory set internal serial number which can be automatically sent to the host as
* the device's serial number when the Device Descriptor's .SerialNumStrIndex entry is set to USE_INTERNAL_SERIAL.
* This allows the host to track a device across insertions on different ports, allowing them to retain allocated
* resources like COM port numbers and drivers. On demos using this feature, give a warning on unsupported devices
* so that the user can supply their own serial number descriptor instead or remove the USE_INTERNAL_SERIAL value
* from the Device Descriptor (forcing the host to generate a serial number for each device from the VID, PID and
* port location).
*/
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/** Device descriptor structure. This descriptor, located in FLASH memory, describes the overall
* device characteristics, including the supported USB version, control endpoint size and the
* number of device configurations. The descriptor is read out by the USB host when the enumeration
* process begins.
*/
USB_Descriptor_Device_t DeviceDescriptor = {
.Header = {.Size = sizeof(USB_Descriptor_Device_t), .Type = DTYPE_Device},
.USBSpecification = VERSION_BCD(01.10),
.Class = CDC_CSCP_CDCClass,
.SubClass = CDC_CSCP_NoSpecificSubclass,
.Protocol = CDC_CSCP_NoSpecificProtocol,
.Endpoint0Size = FIXED_CONTROL_ENDPOINT_SIZE,
.VendorID = 0x1fc9, /* NXP */
.ProductID = 0x2047,
.ReleaseNumber = VERSION_BCD(00.01),
.ManufacturerStrIndex = 0x01,
.ProductStrIndex = 0x02,
.SerialNumStrIndex = USE_INTERNAL_SERIAL,
.NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS
};
/** Configuration descriptor structure. This descriptor, located in FLASH memory, describes the usage
* of the device in one of its supported configurations, including information about any device interfaces
* and endpoints. The descriptor is read out by the USB host during the enumeration process when selecting
* a configuration so that the host may correctly communicate with the USB device.
*/
USB_Descriptor_Configuration_t ConfigurationDescriptor = {
.Config = {
.Header = {.Size = sizeof(USB_Descriptor_Configuration_Header_t), .Type = DTYPE_Configuration},
.TotalConfigurationSize = sizeof(USB_Descriptor_Configuration_t) - 1, // termination byte not included in size
.TotalInterfaces = 2,
.ConfigurationNumber = 1,
.ConfigurationStrIndex = NO_DESCRIPTOR,
.ConfigAttributes = (USB_CONFIG_ATTR_BUSPOWERED | USB_CONFIG_ATTR_SELFPOWERED),
.MaxPowerConsumption = USB_CONFIG_POWER_MA(100)
},
.CDC_CCI_Interface = {
.Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},
.InterfaceNumber = 0,
.AlternateSetting = 0,
.TotalEndpoints = 1,
.Class = CDC_CSCP_CDCClass,
.SubClass = CDC_CSCP_ACMSubclass,
.Protocol = CDC_CSCP_ATCommandProtocol,
.InterfaceStrIndex = NO_DESCRIPTOR
},
.CDC_Functional_Header = {
.Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalHeader_t), .Type = DTYPE_CSInterface},
.Subtype = CDC_DSUBTYPE_CSInterface_Header,
.CDCSpecification = VERSION_BCD(01.10),
},
.CDC_Functional_ACM = {
.Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalACM_t), .Type = DTYPE_CSInterface},
.Subtype = CDC_DSUBTYPE_CSInterface_ACM,
.Capabilities = 0x06,
},
.CDC_Functional_Union = {
.Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalUnion_t), .Type = DTYPE_CSInterface},
.Subtype = CDC_DSUBTYPE_CSInterface_Union,
.MasterInterfaceNumber = 0,
.SlaveInterfaceNumber = 1,
},
.CDC_NotificationEndpoint = {
.Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},
// .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_IN | CDC_NOTIFICATION_EPNUM),
.EndpointAddress = (ENDPOINT_DIR_IN | CDC_NOTIFICATION_EPNUM),
.Attributes = (EP_TYPE_INTERRUPT | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),
.EndpointSize = CDC_NOTIFICATION_EPSIZE,
.PollingIntervalMS = 0xFF
},
.CDC_DCI_Interface = {
.Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},
.InterfaceNumber = 1,
.AlternateSetting = 0,
.TotalEndpoints = 2,
.Class = CDC_CSCP_CDCDataClass,
.SubClass = CDC_CSCP_NoDataSubclass,
.Protocol = CDC_CSCP_NoDataProtocol,
.InterfaceStrIndex = NO_DESCRIPTOR
},
.CDC_DataOutEndpoint = {
.Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},
// .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_OUT | CDC_RX_EPNUM),
.EndpointAddress = (ENDPOINT_DIR_OUT | CDC_RX_EPNUM),
.Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),
.EndpointSize = CDC_TXRX_EPSIZE,
.PollingIntervalMS = 0x01
},
.CDC_DataInEndpoint = {
.Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},
// .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_IN | CDC_TX_EPNUM),
.EndpointAddress = (ENDPOINT_DIR_IN | CDC_TX_EPNUM),
.Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),
.EndpointSize = CDC_TXRX_EPSIZE,
.PollingIntervalMS = 0x01
},
.CDC_Termination = 0x00
};
/** Language descriptor structure. This descriptor, located in FLASH memory, is returned when the host requests
* the string descriptor with index 0 (the first index). It is actually an array of 16-bit integers, which indicate
* via the language ID table available at USB.org what languages the device supports for its string descriptors.
*/
uint8_t LanguageString[] = {
USB_STRING_LEN(1),
DTYPE_String,
WBVAL(LANGUAGE_ID_ENG),
};
USB_Descriptor_String_t *LanguageStringPtr = (USB_Descriptor_String_t *) LanguageString;
/** Manufacturer descriptor string. This is a Unicode string containing the manufacturer's details in human readable
* form, and is read out upon request by the host when the appropriate string ID is requested, listed in the Device
* Descriptor.
*/
uint8_t ManufacturerString[] = {
USB_STRING_LEN(3),
DTYPE_String,
WBVAL('N'),
WBVAL('X'),
WBVAL('P'),
};
USB_Descriptor_String_t *ManufacturerStringPtr = (USB_Descriptor_String_t *) ManufacturerString;
/** Product descriptor string. This is a Unicode string containing the product's details in human readable form,
* and is read out upon request by the host when the appropriate string ID is requested, listed in the Device
* Descriptor.
*/
uint8_t ProductString[] = {
USB_STRING_LEN(18),
DTYPE_String,
WBVAL('L'),
WBVAL('P'),
WBVAL('C'),
WBVAL('U'),
WBVAL('S'),
WBVAL('B'),
WBVAL('l'),
WBVAL('i'),
WBVAL('b'),
WBVAL(' '),
WBVAL('C'),
WBVAL('D'),
WBVAL('C'),
WBVAL(' '),
WBVAL('D'),
WBVAL('e'),
WBVAL('m'),
WBVAL('o'),
};
USB_Descriptor_String_t *ProductStringPtr = (USB_Descriptor_String_t *) ProductString;
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/** This function is called by the library when in device mode, and must be overridden (see library "USB Descriptors"
* documentation) by the application code so that the address and size of a requested descriptor can be given
* to the USB library. When the device receives a Get Descriptor request on the control endpoint, this function
* is called so that the descriptor details can be passed back and the appropriate descriptor sent back to the
* USB host.
*/
uint16_t CALLBACK_USB_GetDescriptor(uint8_t corenum,
const uint16_t wValue,
const uint8_t wIndex,
const void * *const DescriptorAddress)
{
const uint8_t DescriptorType = (wValue >> 8);
const uint8_t DescriptorNumber = (wValue & 0xFF);
const void *Address = NULL;
uint16_t Size = NO_DESCRIPTOR;
switch (DescriptorType) {
case DTYPE_Device:
Address = &DeviceDescriptor;
Size = sizeof(USB_Descriptor_Device_t);
break;
case DTYPE_Configuration:
Address = &ConfigurationDescriptor;
Size = sizeof(USB_Descriptor_Configuration_t);
break;
case DTYPE_String:
switch (DescriptorNumber) {
case 0x00:
Address = LanguageStringPtr;
Size = pgm_read_byte(&LanguageStringPtr->Header.Size);
break;
case 0x01:
Address = ManufacturerStringPtr;
Size = pgm_read_byte(&ManufacturerStringPtr->Header.Size);
break;
case 0x02:
Address = ProductStringPtr;
Size = pgm_read_byte(&ProductStringPtr->Header.Size);
break;
}
break;
}
*DescriptorAddress = Address;
return Size;
}

91
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/Descriptors.h Normal file
View file

@ -0,0 +1,91 @@
/*
* @brief Virtual Serial device class declarations, definitions for using in application
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __DESCRIPTORS_H_
#define __DESCRIPTORS_H_
#include "USB.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup Virtual_Serial_Device_Descriptor Class descriptors
* @ingroup USB_Virtual_Serial_Device_18xx43xx USB_Virtual_Serial_Device_17xx40xx USB_Virtual_Serial_Device_11Uxx
* @{
*/
/** Endpoint number of the CDC device-to-host notification IN endpoint. */
#define CDC_NOTIFICATION_EPNUM 1
/** Endpoint number of the CDC device-to-host data IN endpoint. */
#define CDC_TX_EPNUM 2
/** Endpoint number of the CDC host-to-device data OUT endpoint. */
#if defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)
#define CDC_RX_EPNUM 5
#else
#define CDC_RX_EPNUM 3
#endif
/** Size in bytes of the CDC device-to-host notification IN endpoint. */
#define CDC_NOTIFICATION_EPSIZE 8
/** Size in bytes of the CDC data IN and OUT endpoints. */
#define CDC_TXRX_EPSIZE 16
/** @brief Type define for the device configuration descriptor structure. This must be defined in the
* application code, as the configuration descriptor contains several sub-descriptors which
* vary between devices, and which describe the device's usage to the host.
*/
typedef struct {
USB_Descriptor_Configuration_Header_t Config;
USB_Descriptor_Interface_t CDC_CCI_Interface;
USB_CDC_Descriptor_FunctionalHeader_t CDC_Functional_Header;
USB_CDC_Descriptor_FunctionalACM_t CDC_Functional_ACM;
USB_CDC_Descriptor_FunctionalUnion_t CDC_Functional_Union;
USB_Descriptor_Endpoint_t CDC_NotificationEndpoint;
USB_Descriptor_Interface_t CDC_DCI_Interface;
USB_Descriptor_Endpoint_t CDC_DataOutEndpoint;
USB_Descriptor_Endpoint_t CDC_DataInEndpoint;
unsigned char CDC_Termination;
} USB_Descriptor_Configuration_t;
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __DESCRIPTORS_H_ */

106
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/LPCUSBlib VirtualSerial.inf Normal file
View file

@ -0,0 +1,106 @@
;************************************************************
; Windows USB CDC ACM Setup File
; Copyright (c) 2000 Microsoft Corporation
[Version]
Signature="$Windows NT$"
Class=Ports
ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
Provider=%MFGNAME%
LayoutFile=layout.inf
CatalogFile=%MFGFILENAME%.cat
DriverVer=11/15/2007,5.1.2600.0
[Manufacturer]
%MFGNAME%=DeviceList, NTamd64
[DestinationDirs]
DefaultDestDir=12
;------------------------------------------------------------------------------
; Windows 2000/XP/Vista-32bit Sections
;------------------------------------------------------------------------------
[DriverInstall.nt]
include=mdmcpq.inf
CopyFiles=DriverCopyFiles.nt
AddReg=DriverInstall.nt.AddReg
[DriverCopyFiles.nt]
usbser.sys,,,0x20
[DriverInstall.nt.AddReg]
HKR,,DevLoader,,*ntkern
HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
[DriverInstall.nt.Services]
AddService=usbser, 0x00000002, DriverService.nt
[DriverService.nt]
DisplayName=%SERVICE%
ServiceType=1
StartType=3
ErrorControl=1
ServiceBinary=%12%\%DRIVERFILENAME%.sys
;------------------------------------------------------------------------------
; Vista-64bit Sections
;------------------------------------------------------------------------------
[DriverInstall.NTamd64]
include=mdmcpq.inf
CopyFiles=DriverCopyFiles.NTamd64
AddReg=DriverInstall.NTamd64.AddReg
[DriverCopyFiles.NTamd64]
%DRIVERFILENAME%.sys,,,0x20
[DriverInstall.NTamd64.AddReg]
HKR,,DevLoader,,*ntkern
HKR,,NTMPDriver,,%DRIVERFILENAME%.sys
HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
[DriverInstall.NTamd64.Services]
AddService=usbser, 0x00000002, DriverService.NTamd64
[DriverService.NTamd64]
DisplayName=%SERVICE%
ServiceType=1
StartType=3
ErrorControl=1
ServiceBinary=%12%\%DRIVERFILENAME%.sys
;------------------------------------------------------------------------------
; Vendor and Product ID Definitions
;------------------------------------------------------------------------------
; When developing your USB device, the VID and PID used in the PC side
; application program and the firmware on the microcontroller must match.
; Modify the below line to use your VID and PID. Use the format as shown below.
; Note: One INF file can be used for multiple devices with different VID and PIDs.
; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.
;------------------------------------------------------------------------------
[SourceDisksFiles]
[SourceDisksNames]
[DeviceList]
%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_2047
[DeviceList.NTamd64]
%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_2047
;------------------------------------------------------------------------------
; String Definitions
;------------------------------------------------------------------------------
;Modify these strings to customize your device
;------------------------------------------------------------------------------
[Strings]
MFGFILENAME="CDC_vista"
DRIVERFILENAME ="usbser"
MFGNAME="http://www.lpcware.com/content/project/nxpusblib"
INSTDISK="nxpUSBlib CDC Driver Installer"
DESCRIPTION="Communications Port"
SERVICE="USB RS-232 Emulation Driver"

164
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/DemoIPTrace.h
View file

@ -1,164 +0,0 @@
/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
/*
* This file, along with DemoIPTrace.h, provides a basic example use of the
* FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in
* the command line interface.
* See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml
*/
#ifndef DEMO_IP_TRACE_MACROS_H
#define DEMO_IP_TRACE_MACROS_H
typedef void ( *vTraceAction_t )( uint32_t *, uint32_t );
/* Type that defines each statistic being gathered. */
typedef struct ExampleDebugStatEntry
{
uint8_t ucIdentifier; /* Unique identifier for statistic. */
const uint8_t * const pucDescription; /* Text description for the statistic. */
vTraceAction_t vPerformAction; /* Action to perform when the statistic is updated (increment counter, store minimum value, store maximum value, etc. */
uint32_t ulData; /* The meaning of this data is dependent on the trace macro ID. */
} xExampleDebugStatEntry_t;
/* Unique identifiers used to locate the entry for each trace macro in the
xIPTraceValues[] table defined in DemoIPTrace.c. */
#define iptraceID_NETWORK_BUFFER_OBTAINED 1
#define iptraceID_NETWORK_BUFFER_OBTAINED_FROM_ISR 2
#define iptraceID_NETWORK_EVENT_RECEIVED 3
#define iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER 4
#define iptraceID_ARP_TABLE_ENTRY_EXPIRED 5
#define iptraceID_PACKET_DROPPED_TO_GENERATE_ARP 6
#define iptraceID_FAILED_TO_CREATE_SOCKET 7
#define iptraceID_RECVFROM_DISCARDING_BYTES 8
#define iptraceID_ETHERNET_RX_EVENT_LOST 9
#define iptraceID_STACK_TX_EVENT_LOST 10
#define ipconfigID_BIND_FAILED 11
#define iptraceID_NETWORK_INTERFACE_TRANSMIT 12
#define iptraceID_RECVFROM_TIMEOUT 13
#define iptraceID_SENDTO_DATA_TOO_LONG 14
#define iptraceID_SENDTO_SOCKET_NOT_BOUND 15
#define iptraceID_NO_BUFFER_FOR_SENDTO 16
#define iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR 17
#define iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP 18
/* It is possible to remove the trace macros using the
configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */
#if configINCLUDE_DEMO_DEBUG_STATS == 1
/* The trace macro definitions themselves. Any trace macros left undefined
will default to be empty macros. */
#define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
#define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
#define iptraceNETWORK_EVENT_RECEIVED( eEvent ) { \
uint16_t usSpace; \
usSpace = ( uint16_t ) uxQueueMessagesWaiting( xNetworkEventQueue ); \
/* Minus one as an event was removed before the space was queried. */ \
usSpace = ( ipconfigEVENT_QUEUE_LENGTH - usSpace ) - 1; \
vExampleDebugStatUpdate( iptraceID_NETWORK_EVENT_RECEIVED, usSpace ); \
}
#define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() vExampleDebugStatUpdate( iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, 0 )
#define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_ARP_TABLE_ENTRY_EXPIRED, 0 )
#define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, 0 )
#define iptraceFAILED_TO_CREATE_SOCKET() vExampleDebugStatUpdate( iptraceID_FAILED_TO_CREATE_SOCKET, 0 )
#define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) vExampleDebugStatUpdate( iptraceID_RECVFROM_DISCARDING_BYTES, 0 )
#define iptraceETHERNET_RX_EVENT_LOST() vExampleDebugStatUpdate( iptraceID_ETHERNET_RX_EVENT_LOST, 0 )
#define iptraceSTACK_TX_EVENT_LOST( xEvent ) vExampleDebugStatUpdate( iptraceID_STACK_TX_EVENT_LOST, 0 )
#define iptraceBIND_FAILED( xSocket, usPort ) vExampleDebugStatUpdate( ipconfigID_BIND_FAILED, 0 )
#define iptraceNETWORK_INTERFACE_TRANSMIT() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_TRANSMIT, 0 )
#define iptraceRECVFROM_TIMEOUT() vExampleDebugStatUpdate( iptraceID_RECVFROM_TIMEOUT, 0 )
#define iptraceSENDTO_DATA_TOO_LONG() vExampleDebugStatUpdate( iptraceID_SENDTO_DATA_TOO_LONG, 0 )
#define iptraceSENDTO_SOCKET_NOT_BOUND() vExampleDebugStatUpdate( iptraceID_SENDTO_SOCKET_NOT_BOUND, 0 )
#define iptraceNO_BUFFER_FOR_SENDTO() vExampleDebugStatUpdate( iptraceID_NO_BUFFER_FOR_SENDTO, 0 )
#define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() vExampleDebugStatUpdate( iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, 0 )
#define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) vExampleDebugStatUpdate( iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, 0 )
/*
* The function that updates a line in the xIPTraceValues table.
*/
void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue );
/*
* Returns the number of entries in the xIPTraceValues table.
*/
portBASE_TYPE xExampleDebugStatEntries( void );
#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */
#endif /* DEMO_IP_TRACE_MACROS_H */

85
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h
View file

@ -1,85 +0,0 @@
/*
FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
details. You should have received a copy of the GNU General Public License
and the FreeRTOS license exception along with FreeRTOS; if not it can be
viewed here: http://www.freertos.org/a00114.html and also obtained by
writing to Real Time Engineers Ltd., contact details for whom are available
on the FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, and our new
fully thread aware and reentrant UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems, who sell the code with commercial support,
indemnification and middleware, under the OpenRTOS brand.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
*/
#ifndef TWO_ECHO_CLIENTS_H
#define TWO_ECHO_CLIENTS_H
/*
* Create the two UDP echo client tasks. One task uses the standard interface
* to send to and receive from an echo server. The other task uses the zero
* copy interface to send to and receive from an echo server.
*/
void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );
#endif /* TWO_ECHO_CLIENTS_H */

14
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h
View file

@ -177,7 +177,7 @@ function can have. Note that lower priority have numerically higher values. */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVCall_Handler
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
@ -233,11 +233,11 @@ the iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() IP trace macro. */
/* The address of an echo server that will be used by the two demo echo client
tasks.
http://localhost/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
#define configECHO_SERVER_ADDR0 172
#define configECHO_SERVER_ADDR1 25
#define configECHO_SERVER_ADDR2 218
#define configECHO_SERVER_ADDR3 103
#define configECHO_SERVER_ADDR3 100
/* MAC address configuration. In a deployed production system this would
probably be read from an EEPROM. In the demo it is just hard coded. Make sure
@ -251,10 +251,10 @@ each node on the network has a unique MAC address. */
/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or
ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 1
#define configIP_ADDR3 125
#define configIP_ADDR0 172
#define configIP_ADDR1 25
#define configIP_ADDR2 218
#define configIP_ADDR3 200
/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to
0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */

20
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c
View file

@ -79,9 +79,7 @@
#include "timers.h"
/* Library includes. */
#include "lpc18xx_gpio.h"
#include "lpc18xx_scu.h"
#include "lpc18xx_cgu.h"
#include "board.h"
#define ledTOGGLE_RATE ( 500 / portTICK_RATE_MS )
@ -102,12 +100,6 @@ void vLEDsInitialise( void )
{
static xTimerHandle xLEDToggleTimer = NULL;
/* Set the LED pin-muxing and configure as output. */
scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 );
scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 );
GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 );
GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 );
/* Create the timer used to toggle LED0. */
xLEDToggleTimer = xTimerCreate( ( const int8_t * ) "LEDTmr", /* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */
ledTOGGLE_RATE, /* The period of the timer. */
@ -132,15 +124,7 @@ static uint8_t ucState = 0;
( void ) xTimer;
/* Just toggle an LED to show the program is running. */
if( ucState == 0 )
{
GPIO_SetValue( ledLED0_PORT, ledLED0_BIT );
}
else
{
GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT );
}
Board_LED_Set( ledLED0_PORT, ucState );
ucState = !ucState;
}

66
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LPCUSBlibConfig.h Normal file
View file

@ -0,0 +1,66 @@
/*
* @brief LPCUSB library's configurations
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @defgroup USB_Config USB Configuration
* @ingroup LPCUSBlib
* @{
*/
#ifndef LPCUSBLIB_CONFIG_H_
#define LPCUSBLIB_CONFIG_H_
/** Define NXPUSBLIB_DEBUG to allow the library prints out diagnostic messages */
//#define NXPUSBLIB_DEBUG
/** Available configuration number in a device */
#define FIXED_NUM_CONFIGURATIONS 1
/** Control endpoint max packet size */
#define FIXED_CONTROL_ENDPOINT_SIZE 64
//#define __TEST__ /* Test development */
/** Size of share memory that a device uses to store data transfer to/ receive from host
* or a host uses to store data transfer to/ receive from device.
*/
#define USBRAM_BUFFER_SIZE (4*1024)
/** This option effects only on high speed parts that need to test full speed activities */
#define USB_FORCED_FULLSPEED 0
/** Define USE_USB_ROM_STACK = 1 to use MCU's internal ROM stack, 0 if otherwise */
#define USE_USB_ROM_STACK 0
#endif /* NXPUSBLIB_CONFIG_H_ */
/**
* @}
*/

BIN
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf vendored Normal file
View file

Binary file not shown.

756
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cm3.h → FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSIS/Include/core_cm3.h vendored
View file

File diff suppressed because it is too large Load diff

101
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmFunc.h → FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSIS/Include/core_cmFunc.h vendored
View file

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@ -47,7 +47,7 @@
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
@ -60,20 +60,20 @@ static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
/** \brief Get IPSR Register
This function returns the content of the ISPR Register.
This function returns the content of the IPSR Register.
\return ISPR Register value
\return IPSR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
@ -86,7 +86,7 @@ static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
@ -99,7 +99,7 @@ static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
@ -112,7 +112,7 @@ static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
@ -125,7 +125,7 @@ static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
@ -138,7 +138,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack)
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
@ -151,7 +151,7 @@ static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
@ -164,7 +164,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack)
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
@ -177,7 +177,7 @@ static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
@ -208,7 +208,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
@ -221,7 +221,7 @@ static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
@ -234,7 +234,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri)
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
@ -247,7 +247,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
@ -264,7 +264,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@ -281,7 +281,7 @@ static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@ -297,6 +297,13 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
@ -305,7 +312,7 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
@ -316,7 +323,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
@ -328,7 +335,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
@ -343,19 +350,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
/** \brief Get IPSR Register
This function returns the content of the ISPR Register.
This function returns the content of the IPSR Register.
\return ISPR Register value
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
@ -370,7 +377,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
@ -385,7 +392,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
@ -400,7 +407,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
@ -415,7 +422,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
@ -427,7 +434,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
@ -442,7 +449,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
@ -454,7 +461,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
@ -469,7 +476,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
@ -482,7 +489,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
@ -493,7 +500,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
@ -505,7 +512,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
@ -520,7 +527,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
@ -532,7 +539,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
@ -547,7 +554,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
@ -563,7 +570,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
@ -582,7 +589,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );

87
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmInstr.h → FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSIS/Include/core_cmInstr.h vendored
View file

@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@ -111,7 +111,7 @@
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
@ -125,13 +125,24 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value)
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
@ -259,6 +270,12 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
@ -266,7 +283,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@ -277,7 +294,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@ -288,7 +305,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@ -298,7 +315,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@ -310,7 +327,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
@ -321,7 +338,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
@ -332,7 +349,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
@ -345,7 +362,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
@ -361,7 +378,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
@ -377,7 +394,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
@ -386,6 +403,22 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
@ -395,7 +428,7 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
@ -411,7 +444,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
@ -427,7 +460,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
@ -443,7 +476,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
@ -461,11 +494,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@ -479,11 +512,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@ -497,11 +530,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@ -511,7 +544,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
@ -556,7 +589,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;

BIN
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/CMSIS END USER LICENCE AGREEMENT.pdf vendored
View file

Binary file not shown.

44
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt vendored
View file

@ -1,44 +0,0 @@
CMSIS : Cortex Microcontroller Software Interface Standard
==========================================================
Introduction
~~~~~~~~~~~~
CMSIS defines for a Cortex-M Microcontroller System:
* A common way to access peripheral registers and a
common way to define exception vectors.
* The register names of the Core Peripherals and the
names of the Core Exception Vectors.
* An device independent interface for RTOS Kernels
including a debug channel.
By using CMSIS compliant software components, the user can
easier re-use template code. CMSIS is intended to enable the
combination of software components from multiple middleware
vendors.
This project contains appropriate files for this MCU family
taken from CMSIS. A full copy of the CMSIS files, together
with additional information on CMSIS can be found at:
http://www.onarm.com/
http://www.arm.com/
Documentation
~~~~~~~~~~~~~
The standard CMSIS documentation can be found within the
Code Red IDE help system, via:
Help -> Help Contents -> Code Red Product Documentation -> CMSIS
More information on the use of CMSIS within the Code Red IDE
can be found in the Support area of the Code Red website at
http://www.code-red-tech.com/
At the time of writing, the CMSIS FAQ can be found directly
at:
http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS

325
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt vendored
View file

@ -1,325 +0,0 @@
RELEASE CMSIS for REV A 20111209
1/ New LPC18xx.h header file. Changes GPIO structure.
2/ Addition of lpc18xx_emc.c and lpc18xx_emc.h to configure memory on Hitex board.
3/ Addition of spifi_rom_api.h, spifi_drv_M3.lib and SPIFI_ROM_support.doc SPIFI driver package
4/ Updated SPIFI programming driver for Keil MDK which uses the SPIFI lib
5/ New BOOTFAST example shows how to boot from external flash or QSPI and ramp to 180 MHz
RELEASE CMSIS for REV A 20111130
1./ lpc18xx_lcd.h LCD_CFG_type add member pcd, lpc18xx_lcd.c add init pcd in LCD_Init function
2./ protect MAX and MIN macro in lpc_types.h
3./ Add getPC function to ARM,GNU, IAR startup_lpc18xx.s
4./ Add VTOR init in SystemInit function
5./ Change All ADC examples to use ADC port 0
6./ These example: CortexM3_Mpu, Pwr_DeepPowerDown, Timer_FreqMeasure, SCT_SimpleMatch and all USBDEV_ROM examples Keil project was adjusted
7./ SDRAM example and LCD example was changed not to use uint64_t in NS2CLK function
8./ Nvic_VectorTableRelocation.c
removed:
#if __RAM_MODE__//Run in RAM mode
memcpy((void *)VTOR_OFFSET, (const void *)0x10000000, 256*4);
#else
memcpy((void *)VTOR_OFFSET, (const void *)0x1C000000, 256*4);
#endif
added:
memcpy((void *)VTOR_OFFSET, (const void *)(getPC()& 0xFF000000), 256*4);
9./ Pwr_PowerDown change method for testing this feature
RELEASE CMSIS for REV A 20111028
1./ Add GNU support
2./ Addition of new Keil flash drivers for eFlash and SPIFI
3./ Change of Keil projects to support eFlash and SPIFI operation
PRE-RELEASE CMSIS for REV A 20111011
1/ PowerDown Example IAR issue fixed
2/ Upgraded CMSIS to version 2.10
3/ Upgraded Core header to Rev A
4/ lpc18xx_can.h remove all bitrates from 8Mhz, add bitrates from 12Mhz
/** Bitrate: 100K */
#define CAN_BITRATE100K12MHZ 0x00004509
/** Bitrate: 125K */
#define CAN_BITRATE125K12MHZ 0x00004507
/** Bitrate: 250K */
#define CAN_BITRATE250K12MHZ 0x00004503
/** Bitrate: 500K */
#define CAN_BITRATE500K12MHZ 0x00004501
/** Bitrate: 1000K */
#define CAN_BITRATE1000K12MHZ 0x00004500
5./ lpc18xx_cgu.* add PLL audio clock, modify alloc connect table and CGU_Entity_ControlReg_Offset
6./ lpc18xx_evrt.h
add EVRT_SRC_SDIO
7./ lpc18xx_i2s.h separate LPC_I2S0 and LPC_I2S1
8./ lpc18xx_scu.h
redefine, add pin modes and add pin functions 4->7
9./ debug_frmwrk.c
changed pin mode for UART RXD0 and UART RXD1
10./ lpc_can.c replace LPC_CAN by LPC_CAN0
11./ lpc18xx_i2c.* replace i2c pin configurations
12./ lpc18xx_ssp.c down default clock speed to 100kHz
13./ Examples\CCAN\CCan_SimpleTxRx\CCan_SimpleTxRx.c change RD pin mode to enable input buffer
14./ Examples\EMAC\Emac_EasyWeb\emac.c
replace MII and RMII pin setting by source from CodeBundle
15./ Examples\EMC\Emc_Sdram\SDRAM_Init.c and Examples\EMC\Emc_NorFlash\SST39VF320.c
replace EMC pin setting to be compatible with Rev A
16./ Examples\I2S\I2s_Audio\I2s_Audio.c
replace I2S pin setting to be compatible with Rev A
replace I2S to I2S0
17./ Examples\LCD\Lcd_Demo\IS42S16400D.c
replace EMC pin setting to be compatible with Rev A
18./ Examples\SSP\All SSP examples: replace SSP pin setting to be compatible with Rev A
19./ Timer_Capture and Timer_FreqMeasure: replace Capture input pin setting to be compatible with Rev A
20./ Examples\UART\All UART examples: replace UART pin setting to be compatible with Rev A
21./ Examples\USBDEV\USB_*\usbhw.c
replace USB pin setting to be compatible with Rev A
correct clock in Init function
RELEASE: LPC1800CMSIS_20110829
1./ Add GNU Support
modify pasting in can.c to be compatible with GCC
RELEASE: LPC1800CMSIS_20110729
1./ IAR flash support is moved to Tools folder
2./ ADC.h fixed macro ADC_CR_BITACC
3./ I2S.h fixed comment
from #endif /* LPC17XX_SSP_H_ */
to #endif /* LPC18XX_I2S_H_ */
4./ ADC.c fix ADC_Init Clock by rounding clk div value
5./ i2s.c fixed some comment
6./ EMC Nor Flash renamed file flash programing function
7./ SDRAM can run at MAX EMC Speed
8./ Removed flash programing support for LHF00L28
RELEASE: LPC1800CMSIS_20110627
1./ Fix abstract
2./ Fix I2S FreqConfig mistake
3./ Add DFU Driver and App
RELEASE: LPC1800CMSIS_20110613
1./ Add DSP Document
2./ Speed Up External FLash Mode
3./ Add IAR Flash Support
4./ Fix GPDMA Flash transfer issue in IAR
5./ Set default taget is EXFLASH(Keil only)
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110603
1./ Add DSP_lib into Core folder
2./ Update core_cmFunc.h and core_cmInstr.h for solving conflict with IAR EWARM version 6.20 or later
3./ add IAR startup file and IAR support files in Core\DeviceSupport\NXP\LPC18xx
4./ Modify SystemInit function to support RAM mode
#if (__RAM_MODE__)
SCB->VTOR = 0x10000000;
#endif
5./ Modify CCU1 and CCU2 struct in LPC18xx.h
6./ Fix bug in uart_set_divisors function
7./ Change UART clock source from XTAL to PLL1 in uart driver
8./ Fix RTC bugs
9./ Modify lpc18xx_GPDMA.c to support IAR compiler
10./ Modify lpc18xx_cgu.c to support IAR compiler
11./ Update lpc_types.h to support IAR compiler
12./ Fix bugs in I2S driver
13./ Remove Warnings
14./ Change new header, add more comments
15./ Standalize example, project, output names
16./ Support IAR EWARM (RAM mode)
17./ SUpport Hitex Board as default
18./ Modify hardware configuration in abstract files
19./ Set default Target to RAM mode
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110514
1./ Change all Keil example projects from device Cortex M3 to LPC1850
2./ change all examples to support Hitex board only
3./ Verify all project option
4./ separated CGU and PWR into 2 independent drivers
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110421
1./ Add CAN driver:
Drivers/include/lpc18xx_can.h
Drivers/source/lpc18xx_can.c
2./ Add CAN example for simple Transceiver
Examples\C_CAN\simpleTxRx
3./ Add 4 USB Rom examples:
USB_DFU
USB_HID
USB_MassStorage
USB_Composite
4./ Enable _printf function
debug_frmwrk.h:
uncomment _printf function declaration
debug_frmwrk.c:
uncomment _printf function
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110401
1./ Change all Keil example proiects from device NXP LPC1768 to ARM Cortex-M3
2./ Fix bug in I2C driver (customer feedback)
Problem description:
I2C_MasterTransferData() is not able to
(1) Send,
(2) doing a repeated Start and
(3) starting to receive with one function call.
Problem is that the repeated start is not generated, but a retransmission of the
last word is startet.
Solve: change
I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
I2Cx->I2CONSET = I2C_I2CONSET_STA;
to
I2Cx->I2CONSET = I2C_I2CONSET_STA;
I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
in function I2C_Start ()
3./ lpc18xx_timer.c:
Function TIM_ClearIntPending():
Change TIMx->IR |= TIM_IR_CLR(IntFlag);
To TIMx->IR = TIM_IR_CLR(IntFlag);
Function TIM_ClearIntCapturePending():
Change TIMx->IR |= (1<<(4+IntFlag));
To TIMx->IR = (1<<(4+IntFlag));
Function TIM_GetCaptureValue():
Add return 0;
4./ EMC - Nor Flash: remove example build target for FLASH mode as it only can run in RAM mode.
5./ SCT: update Fizzim tool to version 1.1
6./ Tools:
Update Flash burning for LHF00L28 and SST39X320X
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110324
1./ Current support hardwares:
- NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
- Hitex LPC1800 Board through definition 'BOARD_HITEX_LPC1800'
Some examples can run on LPC1800 Evaluation board, some can run on Hitex board...Please refer to abstract.txt
2./ Addin new flash support under Tools/Flash/SST39X320X
3./ lpc18xx_evrt.c:
Change EVRTx->SET_EN |= (1<<(uint8_t)EVRT_Src);
To EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);
Purpose: prevent clearing other set bits as writing '0' has no effect
4./ Fix ATIMER_WIC example:
- Configure 32KHZ osc in lpc18xx_atimer.c
- Call the configuration function in atimer_wic.c
5./ Fix RTC_Alarm example:
- Configure 32KHZ osc in lpc18xx_rtc.c
- Update Rtc_Alarm.c
6./ Add in PWR_PowerDown example
7./ Add in PWR_DeepPowerDown example
8./ All example in PWR are modified to wait for '1' sent from PC's COM port to start
9./ Fix LCD Logic4.3 example to run on Hitex LPC1800 Board
10./ Add in GPDMA Flash_2_Ram_Test example
11./ EMC EXT_SDRAM example: join IS42S16400D.c and MT48LC4M32B2.c into SDRAM_Init.c
12./ lpc18xx_i2s.c: update I2S_FreqConfig() function
************************************************************************************************************************************************
RELEASE: LPC1800CMSIS_20110311
1./ This package is compliant to CMSIS 2.0
2./ Add in 'Tools' folder which contains neccessary material for building project, examples like flash burning,..
3./ Examples are given in Keil uVision 4 project
4./ Current support hardwares:
- NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
5./ Examples can run:
- RAM (debug) mode
- ROM (Flash, stand alone) mode
+ External Nor Flash. Flash Part supporting:
1) LHF00L28
6./ Each example folder has an 'abstract.txt' file, this is where user can start
7./ Below is list of drivers and examples:
- ADC (lpc18xx_adc):
+ ADC_Interrupt
+ ADC_Polling
+ ADC_Burst
+ ADC_Dma
- ATIMER (lpc18xx_atimer):
+ ATIMER_interrupt
- PWR (lpc18xx_clkpwr):
+ CLKPWR_Sleep
+ CLKPWR_DeepSleep
- DAC (lpc18xx_dac):
+ DAC_WaveGenerator
+ DAC_Dma
- EMAC (lpc18xx_emac):
+ EMAC_EasyWeb
- EMC (no driver):
+ EXT_SDRAM
+ NOR_FLASH
- GPDMA (lpc18xx_gpdma):
+ GPDMA_Ram2Ram
+ GPDMA_LinkList
- GPIO (lpc18xx_gpio):
+ GPIO_LedBlinky
- I2C (lpc18xx_i2c):
+ I2C_Master
- I2S (lpc18xx_i2s):
+ I2S_Audio
- LCD (lpc18xx_lcd)
- MCPWM (lpc18xx_mcpwm):
+ MCPWM_Simple
- SCU (lpc18xx_scu)
- QEI (lpc18xx_qei):
+ QEI_Velo
- RIT (lpc18xx_rit):
+ RIT_Interrupt
- RTC (lpc18xx_rtc):
+ RTC_Calib
+ RTC_Alarm
- SSP (lpc18xx_ssp):
+ SSP_SPI
+ SSP_Microwire
+ SSP_TI
- TIMER (lpc18xx_timer):
+ TIMER_Capture
+ TIMER_MatchInterrupt
+ TIMER_FreqMeasure
- UART (lpc18xx_uart):
+ UART_Autobaud
+ UART_Dma
+ UART_Interrupt
+ UART_Polling
+ UART_RS485
- SCT(LPC18xx_SCT):
+ SCT_Capture
+ SCT_Match
- WWDT (lpc18xx_wwdt):
+ WWDT_Interrupt
- CORTEXM3 (no driver):
+ CORTEXM3_BitBanding
+ CORTEXM3_MPU
+ CORTEXM3_PriviledgeMode
- USBDEV (no driver):
+ USBDEV_VirtualCOM
+ USBDEV_MassStorage
- NVIC (no driver):
+ NVIC_Priority
+ NVIC_VecRelocation
- EVRT (lpc18xx_evrt)

9
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt vendored
View file

@ -1,9 +0,0 @@
NXP's documentation for their peripheral driver library can be found
as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx
CMSIS Standard Peripheral Driver Library download on NXP's website.
At the time of writing, this can be found at the following link:
http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103

32280
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/LPC18xx.h vendored
View file

File diff suppressed because it is too large Load diff

90
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/debug_frmwrk.h vendored
View file

@ -1,90 +0,0 @@
/**********************************************************************
* $Id$ debug_frmwrk.h 2011-06-02
*//**
* @file debug_frmwrk.h
* @brief Contains some utilities that used for debugging through UART
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef DEBUG_FRMWRK_H_
#define DEBUG_FRMWRK_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_uart.h"
#define VCOM_DEBUG_MESSEGES
//#define UART_DEBUG_MESSEGES
#define USED_UART_DEBUG_PORT 1
#if (USED_UART_DEBUG_PORT==0)
#define DEBUG_UART_PORT LPC_UART0
#elif (USED_UART_DEBUG_PORT==1)
#define DEBUG_UART_PORT LPC_UART1
#endif
#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBG_(x) _db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBC(x) _db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD(x) _db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD16(x) _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBD32(x) _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH(x) _db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH16(x) _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DBH32(x) _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
#define _DG _db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT)
void lpc_printf (const char *format, ...);
extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);
extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);
extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);
extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);
extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);
extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);
extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);
extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);
extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);
void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch);
void UARTPuts(LPC_USARTn_Type *UARTx, const void *str);
void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str);
void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum);
void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum);
void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum);
void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum);
void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum);
void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum);
uint8_t UARTGetChar (LPC_USARTn_Type *UARTx);
void debug_frmwrk_init(void);
#endif /* DEBUG_FRMWRK_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

295
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_adc.h vendored
View file

@ -1,295 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_adc.h 2011-06-02
*//**
* @file lpc18xx_adc.h
* @brief Contains all macro definitions and function prototypes
* support for ADC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ADC ADC (Analog to Digital Converter)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_ADC_H_
#define LPC18XX_ADC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for ADC control register
**********************************************************************/
/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CH_SEL(n) ((1UL << n))
/** The APB clock (PCLK) is divided by (this value plus one)
* to produce the clock for the A/D */
#define ADC_CR_CLKDIV(n) ((n<<8))
/** Repeated conversions A/D enable bit */
#define ADC_CR_BURST ((1UL<<16))
/** number of accuracy bits */
#define ADC_CR_BITACC(n) (((n)<<17))
/** ADC convert in power down mode */
#define ADC_CR_PDN ((1UL<<21))
/** Start mask bits */
#define ADC_CR_START_MASK ((7UL<<24))
/** Select Start Mode */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
/** Start conversion now */
#define ADC_CR_START_NOW ((1UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT15 ((2UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_CTOUT8 ((3UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG0 ((4UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_ADCTRIG1 ((5UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_START_MCOA2 ((6UL<<24))
/** Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_CR_EDGE ((1UL<<27))
/*********************************************************************//**
* Macro defines for ADC Global Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
/** These bits contain the channel from which the LS bits were converted */
#define ADC_GDR_CH(n) (((n>>24)&0x7))
/** This bit is 1 in burst mode if the results of one or
* more conversions was (were) lost */
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes */
#define ADC_GDR_DONE_FLAG ((1UL<<31))
/** This bits is used to mask for Channel */
#define ADC_GDR_CH_MASK ((7UL<<24))
/*********************************************************************//**
* Macro defines for ADC Interrupt register
**********************************************************************/
/** These bits allow control over which A/D channels generate
* interrupts for conversion completion */
#define ADC_INTEN_CH(n) ((1UL<<n))
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
#define ADC_INTEN_GLOBAL ((1UL<<8))
/*********************************************************************//**
* Macro defines for ADC Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_DR_RESULT(n) (((n>>6)&0x3FF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes. It is cleared
* when this register is read */
#define ADC_DR_DONE_FLAG ((1UL<<31))
/*********************************************************************//**
* Macro defines for ADC Status register
**********************************************************************/
/** These bits mirror the DONE status flags that appear in the result
* register for each A/D channel */
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
/** This bit is the A/D interrupt flag */
#define ADC_STAT_INT_FLAG ((1UL<<16))
/*********************************************************************//**
* Macro defines for ADC Trim register
**********************************************************************/
/** Offset trim bits for ADC operation */
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
/** Written to boot code*/
#define ADC_TRIM(n) (((n&0xF)<<8))
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
/** Check ADC parameter */
#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1))
/** Check ADC state parameter */
#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
/** Check ADC state parameter */
#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
/** Check ADC rate parameter */
#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
/** Check ADC bits accuracy parameter */
#define PARAM_ADC_BITSACC(x) ((x>=3)&&(x<=10))
/** Check ADC channel selection parameter */
#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
/** Check ADC start option parameter */
#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\
||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\
||(OPT == ADC_START_ON_MCOA2))
/** Check ADC interrupt type parameter */
#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
||(OPT == ADC_ADGINTEN))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup ADC_Public_Types ADC Public Types
* @{
*/
/*********************************************************************//**
* @brief ADC enumeration
**********************************************************************/
/** @brief Channel Selection */
typedef enum
{
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
ADC_CHANNEL_1, /*!< Channel 1 */
ADC_CHANNEL_2, /*!< Channel 2 */
ADC_CHANNEL_3, /*!< Channel 3 */
ADC_CHANNEL_4, /*!< Channel 4 */
ADC_CHANNEL_5, /*!< Channel 5 */
ADC_CHANNEL_6, /*!< Channel 6 */
ADC_CHANNEL_7 /*!< Channel 7 */
}ADC_CHANNEL_SELECTION;
/** @brief Type of start option */
typedef enum
{
ADC_START_CONTINUOUS =0, /*!< Continuous mode */
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected
* by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected
* by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected
* by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_OPT;
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
typedef enum
{
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
*on the selected CAP/MAT signal */
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
*on the selected CAP/MAT signal */
} ADC_START_ON_EDGE_OPT;
/** @brief* ADC type interrupt enum */
typedef enum
{
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
ADC_ADINTEN1, /*!< Interrupt channel 1 */
ADC_ADINTEN2, /*!< Interrupt channel 2 */
ADC_ADINTEN3, /*!< Interrupt channel 3 */
ADC_ADINTEN4, /*!< Interrupt channel 4 */
ADC_ADINTEN5, /*!< Interrupt channel 5 */
ADC_ADINTEN6, /*!< Interrupt channel 6 */
ADC_ADINTEN7, /*!< Interrupt channel 7 */
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
}ADC_TYPE_INT_OPT;
/** @brief ADC Data status */
typedef enum
{
ADC_DATA_BURST = 0, /*Burst bit*/
ADC_DATA_DONE /*Done bit*/
}ADC_DATA_STATUS;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ADC_Public_Functions ADC Public Functions
* @{
*/
/* Init/DeInit ADC peripheral ----------------*/
void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy);
void ADC_DeInit(LPC_ADCn_Type *ADCx);
/* Enable/Disable ADC functions --------------*/
void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode);
void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState);
/* Configure ADC functions -------------------*/
void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption);
void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
/* Get ADC information functions -------------------*/
uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel);
FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType);
uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx);
FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_ADC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

93
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_atimer.h vendored
View file

@ -1,93 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_atimer.h 2011-06-02
*//**
* @file lpc18xx_atimer.h
* @brief Contains all functions support for Alarm Timer firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ATIMER ATIMER (Alarm Timer)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_ATIMER_H_
#define __LPC18XX_ATIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros
* @{
*/
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid ALARM TIMER peripheral */
#define PARAM_ATIMERx(n) (((uint32_t *)n)==((uint32_t *)LPC_ATIMER))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ATIMER_Public_Functions ATIMER Public Functions
* @{
*/
/* Init/DeInit ATIMER functions -----------*/
void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue);
void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx);
/* ATIMER interrupt functions -------------*/
void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx);
void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx);
void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx);
/* ATIMER configuration functions --------*/
void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue);
uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_ATIMER_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

241
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_can.h vendored
View file

@ -1,241 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_can.h 2011-06-02
*//**
* @file lpc18xx_can.h
* @brief Contains all macro definitions and function prototypes
* support for CAN firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup C_CAN C_CAN (Controller Area Network)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_CAN_H
#define __LPC18XX_CAN_H
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Public_Macros C_CAN Public Macros
* @{
*/
/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer.
* If not BASIC_MODE use message objects and IF registers to communicate with message buffers
*/
#define BASIC_MODE 0
/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
* frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission
*/
#define SILENT_MODE 0
/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages
* and stores them (if they pass acceptance filtering) into a Receive Buffer.
*/
#define LOOPBACK_MODE 0
/** Enables receiving remote frame requests */
#define REMOTE_ENABLE 1
/**
* @}
*/
/* Private Macros -------------------------------------------------------------- */
/** @defgroup C_CAN_Private_Macros C_CAN Private Macros
* @{
*/
/** MAX CAN message obj */
#define CAN_MSG_OBJ_MAX 0x0020
/** MAX data length */
#define CAN_DLC_MAX 8
/********************************************************************//**
* BRP+1 = Fpclk/(CANBitRate * QUANTAValue)
* QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1)
* QUANTA value varies based on the Fpclk and sample point
* e.g. (1) sample point is 87.5%, Fpclk is 48Mhz
* the QUANTA should be 16
* (2) sample point is 90%, Fpclk is 12.5Mhz
* the QUANTA should be 10
* Fpclk = Fclk /APBDIV
* or
* BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1))
*/
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 8Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K12MHZ 0x00004509
/** Bitrate: 125K */
#define CAN_BITRATE125K12MHZ 0x00004507
/** Bitrate: 250K */
#define CAN_BITRATE250K12MHZ 0x00004503
/** Bitrate: 500K */
#define CAN_BITRATE500K12MHZ 0x00004501
/** Bitrate: 1000K */
#define CAN_BITRATE1000K12MHZ 0x00004500
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 16Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K16MHZ 0x00005809
/** Bitrate: 125K */
#define CAN_BITRATE125K16MHZ 0x00005807
/** Bitrate: 250K */
#define CAN_BITRATE250K16MHZ 0x00005803
/** Bitrate: 500K */
#define CAN_BITRATE500K16MHZ 0x00005801
/*********************************************************************//**
* @brief CAN Bit Timing Values definitions at 24Mhz
**********************************************************************/
/** Bitrate: 100K */
#define CAN_BITRATE100K24MHZ 0x00007E09
/** Bitrate: 125K */
#define CAN_BITRATE125K24MHZ 0x0000450F
/** Bitrate: 250K */
#define CAN_BITRATE250K24MHZ 0x00004507
/** Bitrate: 500K */
#define CAN_BITRATE500K24MHZ 0x00004503
/** Bitrate: 1000K */
#define CAN_BITRATE1000K24MHZ 0x00004501
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CAN_Public_Types CAN Public Types
* @{
*/
/*********************************************************************//**
* @brief CAN enumeration
**********************************************************************/
/**
* @brief CAN interface register type definition
*/
typedef enum CCAN_IFREG
{
CMDREQ = 0, /**< Command request */
CMDMSK = 1, /**< Command mask */
MSK1 = 2, /**< Mask 1 */
MSK2 = 3, /**< Mask 2 */
ARB1 = 4, /**< Arbitration 1 */
ARB2 = 5, /**< Arbitration 2 */
MCTRL = 6, /**< Message control */
DA1 = 7, /**< Data A1 */
DA2 = 8, /**< Data A2 */
DB1 = 9, /**< Data B1 */
DB2 = 10 /**< Data B2 */
}CCAN_IFREG_Type;
/**
* @brief CAN Clock division rate type definition
*/
typedef enum CCAN_CLKDIV
{
CLKDIV1 = 0,
CLKDIV2 = 1,
CLKDIV3 = 2,
CLKDIV5 = 3,
CLKDIV9 = 4,
CLKDIV17 = 5,
CLKDIV33 = 6,
CLKDIV65 = 7
}CCAN_CLKDIV_Type;
/********************************************************************//**
* @brief Data structure definition for a CAN message
**********************************************************************/
/**
* @brief CAN message object structure
*/
typedef struct
{
uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */
uint32_t dlc; /**< Message data length */
uint8_t data[8]; /**< Message data */
} message_object;
/**
* @brief CAN call-back function
*/
typedef void (*MSG_CB)(uint32_t msg_no);
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CAN_Public_Functions CAN Public Functions
* @{
*/
void CAN_IRQHandler (void);
void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb);
void CAN_ConfigureRxMessageObjects( void );
void CAN_RxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_TxInt_MessageProcess( uint8_t MsgObjNo );
void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr );
void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable);
void CAN_ReadMsg(uint32_t msg_no, message_object* buff);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_CAN_H */
/**
* @}
*/
/*****************************************************************************
** End Of File
******************************************************************************/

271
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_cgu.h vendored
View file

@ -1,271 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_cgu.h 2011-06-02
*//**
* @file llpc18xx_cgu.h
* @brief Contains all macro definitions and function prototypes
* support for Clock Generation and Clock Control firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CGU CGU (Clock Generation Unit)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_CGU_H_
#define LPC18XX_CGU_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros -------------------------------------------------------------- */
/** @defgroup CGU_Private_Macros CGU Private Macros
* @{
*/
/** Branch clocks from CGU_BASE_SAFE */
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
/** Check bit at specific position is clear or not */
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
/** Check bit at specific position is set or not */
#define ISBITSET(x,bit) (x&(1<<bit))
/** Set mask */
#define ISMASKSET(x,mask) (x&mask)
/** CGU number of clock source */
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
/*********************************************************************//**
* Macro defines for CGU control mask bit definitions
**********************************************************************/
/** CGU control enable mask bit */
#define CGU_CTRL_EN_MASK 1
/** CGU control clock-source mask bit */
#define CGU_CTRL_SRC_MASK (0xF<<24)
/** CGU control auto block mask bit */
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
/*********************************************************************//**
* Macro defines for CGU PLL1 mask bit definitions
**********************************************************************/
/** CGU PLL1 feedback select mask bit */
#define CGU_PLL1_FBSEL_MASK (1<<6)
/** CGU PLL1 Input clock bypass control mask bit */
#define CGU_PLL1_BYPASS_MASK (1<<1)
/** CGU PLL1 direct CCO output mask bit */
#define CGU_PLL1_DIRECT_MASK (1<<7)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup CGU_Public_Types CGU Public Types
* @{
*/
/*********************************************************************//**
* @brief CGU enumeration
**********************************************************************/
/*
* @brief CGU clock source enumerate definition
*/
typedef enum {
/* Clock Source */
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
CGU_CLKSRC_TCK, /**< TCK clock source */
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
CGU_CLKSRC_PLL0_AUDIO,
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
/* Base */
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
CGU_BASE_USB0, /**< USB0 base clock */
CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */
CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */
CGU_BASE_SPIFI, /**< SPIFI base clock */
//CGU_BASE_SPI,
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
CGU_BASE_LCD, /**< LCD base clock */
CGU_BASE_ENET_CSR,
CGU_BASE_SDIO, /**< SDIO base clock */
CGU_BASE_SSP0, /**< SSP0 base clock */
CGU_BASE_SSP1, /**< SSP1 base clock */
CGU_BASE_UART0, /**< UART0 base clock */
CGU_BASE_UART1, /**< UART1 base clock */
CGU_BASE_UART2, /**< UART2 base clock */
CGU_BASE_UART3, /**< UART3 base clock */
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
CGU_BASE_OUT0,
CGU_BASE_OUT1,
CGU_ENTITY_NUM /**< Number or clock source entity */
} CGU_ENTITY_T;
/*
* @brief CGU PPL0 mode enumerate definition
*/
typedef enum {
CGU_PLL0_MODE_1d = 0,
CGU_PLL0_MODE_1c,
CGU_PLL0_MODE_1b,
CGU_PLL0_MODE_1a
}CGU_PLL0_MODE;
/*
* @brief CGU peripheral enumerate definition
*/
typedef enum {
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
CGU_PERIPHERAL_ADC1, /**< ADC1 */
CGU_PERIPHERAL_AES, /**< AES */
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
CGU_PERIPHERAL_CAN, /**< CAN */
CGU_PERIPHERAL_CREG, /**< CREG */
CGU_PERIPHERAL_DAC, /**< DAC */
CGU_PERIPHERAL_DMA, /**< DMA */
CGU_PERIPHERAL_EMC, /**< EMC */
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
CGU_PERIPHERAL_GPIO, /**< GPIO */
CGU_PERIPHERAL_I2C0, /**< I2C0 */
CGU_PERIPHERAL_I2C1, /**< I2C1 */
CGU_PERIPHERAL_I2S, /**< I2S */
CGU_PERIPHERAL_LCD, /**< LCD */
CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */
CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
CGU_PERIPHERAL_QEI, /**< QEI */
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
CGU_PERIPHERAL_SCT, /**< SCT */
CGU_PERIPHERAL_SCU, /**< SCU */
CGU_PERIPHERAL_SDIO, /**< SDIO */
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
CGU_PERIPHERAL_SSP0, /**< SSP0 */
CGU_PERIPHERAL_SSP1, /**< SSP1 */
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
CGU_PERIPHERAL_UART0, /**< UART0 */
CGU_PERIPHERAL_UART1, /**< UART1 */
CGU_PERIPHERAL_UART2, /**< UART2 */
CGU_PERIPHERAL_UART3, /**< UART3 */
CGU_PERIPHERAL_USB0, /**< USB0 */
CGU_PERIPHERAL_USB1, /**< USB1 */
CGU_PERIPHERAL_WWDT, /**< WWDT */
CGU_PERIPHERAL_NUM
} CGU_PERIPHERAL_T;
/**
* @brief CGU error status enumerate definition
*/
typedef enum {
CGU_ERROR_SUCCESS = 0,
CGU_ERROR_CONNECT_TOGETHER,
CGU_ERROR_INVALID_ENTITY,
CGU_ERROR_INVALID_CLOCK_SOURCE,
CGU_ERROR_INVALID_PARAM,
CGU_ERROR_FREQ_OUTOF_RANGE
} CGU_ERROR;
/********************************************************************//**
* @brief CGU structure definitions
**********************************************************************/
/*
* @brief CGU peripheral clock structure
*/
typedef struct {
uint8_t RegBaseEntity; /**< Base register address */
uint16_t RegBranchOffset; /**< Branch register offset */
uint8_t PerBaseEntity; /**< Base peripheral address */
uint16_t PerBranchOffset; /**< Base peripheral offset */
uint8_t next; /**< Pointer to next structure */
} CGU_PERIPHERAL_S;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CGU_Public_Functions CGU Public Functions
* @{
*/
/** Clock generate initialize/de-initialize */
uint32_t CGU_Init(void);
uint32_t CGU_DeInit(void);
/** Clock Generator and Clock Control */
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
/** Clock Source and Base Clock operation */
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
uint32_t CGU_SetPLL0(void);
uint32_t CGU_SetPLL1(uint32_t mult);
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
void CGU_UpdateClock(void);
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_CGU_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

219
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_clkpwr.h vendored
View file

@ -1,219 +0,0 @@
/***********************************************************************//**
* @file lpc18xx_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on LPC18xx
* @version 1.0
* @date 14. Dec. 2010
* @author NXP MCU SW Application Team
**************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**************************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR CLKPWR
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_CLKPWR_H_
#define LPC18XX_CLKPWR_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
* @{
*/
typedef enum {
/* Clock Source */
CLKPWR_CLKSRC_32KHZ_OSC = 0,
CLKPWR_CLKSRC_IRC,
CLKPWR_CLKSRC_ENET_RX_CLK,
CLKPWR_CLKSRC_ENET_TX_CLK,
CLKPWR_CLKSRC_GP_CLKIN,
CLKPWR_CLKSRC_TCK,
CLKPWR_CLKSRC_XTAL_OSC,
CLKPWR_CLKSRC_PLL0,
CLKPWR_CLKSRC_PLL1,
CLKPWR_CLKSRC_IDIVA = CLKPWR_CLKSRC_PLL1 + 3,
CLKPWR_CLKSRC_IDIVB,
CLKPWR_CLKSRC_IDIVC,
CLKPWR_CLKSRC_IDIVD,
CLKPWR_CLKSRC_IDIVE,
/* Base */
CLKPWR_BASE_SAFE,
CLKPWR_BASE_USB0,
CLKPWR_BASE_USB1 = CLKPWR_BASE_USB0 + 2,
CLKPWR_BASE_M3,
CLKPWR_BASE_SPIFI,
//CLKPWR_BASE_SPI,
CLKPWR_BASE_PHY_RX = CLKPWR_BASE_SPIFI + 2,
CLKPWR_BASE_PHY_TX,
CLKPWR_BASE_APB1,
CLKPWR_BASE_APB3,
CLKPWR_BASE_LCD,
CLKPWR_BASE_SDIO = CLKPWR_BASE_LCD + 2,
CLKPWR_BASE_SSP0,
CLKPWR_BASE_SSP1,
CLKPWR_BASE_UART0,
CLKPWR_BASE_UART1,
CLKPWR_BASE_UART2,
CLKPWR_BASE_UART3,
CLKPWR_BASE_CLKOUT,
CLKPWR_ENTITY_NUM
} CLKPWR_ENTITY_T;
#define CLKPWR_CLKSRC_NUM (CLKPWR_CLKSRC_IDIVE+1)
typedef enum {
CLKPWR_PLL0_MODE_1d = 0,
CLKPWR_PLL0_MODE_1c,
CLKPWR_PLL0_MODE_1b,
CLKPWR_PLL0_MODE_1a,
}CLKPWR_PLL0_MODE;
typedef enum {
CLKPWR_PERIPHERAL_ADC0 = 0,
CLKPWR_PERIPHERAL_ADC1,
CLKPWR_PERIPHERAL_AES,
// CLKPWR_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
CLKPWR_PERIPHERAL_APB1_BUS,
CLKPWR_PERIPHERAL_APB3_BUS,
CLKPWR_PERIPHERAL_CAN,
CLKPWR_PERIPHERAL_CREG,
CLKPWR_PERIPHERAL_DAC,
CLKPWR_PERIPHERAL_DMA,
CLKPWR_PERIPHERAL_EMC,
CLKPWR_PERIPHERAL_ETHERNET,
CLKPWR_PERIPHERAL_ETHERNET_TX, //HIDE
CLKPWR_PERIPHERAL_GPIO,
CLKPWR_PERIPHERAL_I2C0,
CLKPWR_PERIPHERAL_I2C1,
CLKPWR_PERIPHERAL_I2S,
CLKPWR_PERIPHERAL_LCD,
CLKPWR_PERIPHERAL_M3CORE,
CLKPWR_PERIPHERAL_M3_BUS,
CLKPWR_PERIPHERAL_MOTOCON,
CLKPWR_PERIPHERAL_QEI,
CLKPWR_PERIPHERAL_RITIMER,
CLKPWR_PERIPHERAL_SCT,
CLKPWR_PERIPHERAL_SCU,
CLKPWR_PERIPHERAL_SDIO,
CLKPWR_PERIPHERAL_SPIFI,
CLKPWR_PERIPHERAL_SSP0,
CLKPWR_PERIPHERAL_SSP1,
CLKPWR_PERIPHERAL_TIMER0,
CLKPWR_PERIPHERAL_TIMER1,
CLKPWR_PERIPHERAL_TIMER2,
CLKPWR_PERIPHERAL_TIMER3,
CLKPWR_PERIPHERAL_UART0,
CLKPWR_PERIPHERAL_UART1,
CLKPWR_PERIPHERAL_UART2,
CLKPWR_PERIPHERAL_UART3,
CLKPWR_PERIPHERAL_USB0,
CLKPWR_PERIPHERAL_USB1,
CLKPWR_PERIPHERAL_WWDT,
CLKPWR_PERIPHERAL_NUM
} CLKPWR_PERIPHERAL_T;
//typedef CLKPWR_CLK_T CLKPWR_BASE_T;
typedef struct {
uint8_t RegBaseEntity;
uint16_t RegBranchOffset;
uint8_t PerBaseEntity;
uint16_t PerBranchOffset;
uint8_t next;
} CLKPWR_PERIPHERAL_S;
typedef enum {
CLKPWR_ERROR_SUCCESS = 0,
CLKPWR_ERROR_CONNECT_TOGETHER,
CLKPWR_ERROR_INVALID_ENTITY,
CLKPWR_ERROR_INVALID_CLOCK_SOURCE,
CLKPWR_ERROR_INVALID_PARAM,
CLKPWR_ERROR_FREQ_OUTOF_RANGE
} CLKPWR_ERROR;
/* Branch clocks from CLKPWR_BASE_SAFE */
#define CLKPWR_ENTITY_NONE CLKPWR_ENTITY_NUM
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
#define ISBITSET(x,bit) (x&(1<<bit))
#define ISMASKSET(x,mask) (x&mask)
#define CLKPWR_CTRL_EN_MASK 1
#define CLKPWR_CTRL_SRC_MASK (0xF<<24)
#define CLKPWR_CTRL_AUTOBLOCK_MASK (1<<11)
#define CLKPWR_PLL1_FBSEL_MASK (1<<6)
#define CLKPWR_PLL1_BYPASS_MASK (1<<1)
#define CLKPWR_PLL1_DIRECT_MASK (1<<7)
#define CLKPWR_SLEEP_MODE_DEEP_SLEEP 0x3F00AA
#define CLKPWR_SLEEP_MODE_POWER_DOWN 0x3FFCBA
#define CLKPWR_SLEEP_MODE_DEEP_POWER_DOWN 0x3FFF7F
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
* @{
*/
/* Clock Generator */
uint32_t CLKPWR_ConfigPWR (CLKPWR_PERIPHERAL_T PPType, FunctionalState en);
uint32_t CLKPWR_GetPCLKFrequency (CLKPWR_PERIPHERAL_T Clock);
/* Clock Source and Base Clock operation */
uint32_t CLKPWR_SetXTALOSC(uint32_t ClockFrequency);
uint32_t CLKPWR_SetDIV(CLKPWR_ENTITY_T SelectDivider, uint32_t divisor);
uint32_t CLKPWR_SetPLL0(void);
uint32_t CLKPWR_SetPLL1(uint32_t mult);
uint32_t CLKPWR_EnableEntity(CLKPWR_ENTITY_T ClockEntity, uint32_t en);
uint32_t CLKPWR_EntityConnect(CLKPWR_ENTITY_T ClockSource, CLKPWR_ENTITY_T ClockEntity);
uint32_t CLKPWR_GetBaseStatus(CLKPWR_ENTITY_T Base);
void CLKPWR_UpdateClock(void);
uint32_t CLKPWR_RealFrequencyCompare(CLKPWR_ENTITY_T Clock, CLKPWR_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
uint32_t CLKPWR_Init(void);
uint32_t CLKPWR_DeInit(void);
void CLKPWR_Sleep(void);
void CLKPWR_DeepSleep(void);
void CLKPWR_PowerDown(void);
void CLKPWR_DeepPowerDown(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_CLKPWR_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

149
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_dac.h vendored
View file

@ -1,149 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_dac.h 2011-06-02
*//**
* @file lpc18xx_dac.h
* @brief Contains all macro definitions and function prototypes
* support for DAC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DAC DAC (Digital to Analog Converter)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_DAC_H_
#define LPC18XX_DAC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
/** After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 × VREF */
#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
* and the maximum current is 700 microAmpere
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
* and the maximum current is 350 microAmpere */
#define DAC_BIAS_EN ((uint32_t)(1<<16))
/** Value to reload interrupt DMA counter */
#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
/** DCAR double buffering */
#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
/** DCAR Time out count enable */
#define DAC_CNT_ENA ((uint32_t)(1<<2))
/** DCAR DMA access */
#define DAC_DMA_ENA ((uint32_t)(1<<3))
/** DCAR DACCTRL mask bit */
#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
/** Macro to determine if it is valid DAC peripheral */
#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
/** Macro to check DAC current optional parameter */
#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
||(OPTION == DAC_MAX_CURRENT_350uA))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup DAC_Public_Types DAC Public Types
* @{
*/
/**
* @brief Current option in DAC configuration option */
typedef enum
{
DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
and the maximum current is 700 uA */
DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
and the maximum current is 350 uA */
} DAC_CURRENT_OPT;
/**
* @brief Configuration for DAC converter control register */
typedef struct
{
uint8_t DBLBUF_ENA; /**<
-0: Disable DACR double buffering
-1: when bit CNT_ENA, enable DACR double buffering feature
*/
uint8_t CNT_ENA; /*!<
-0: Time out counter is disable
-1: Time out conter is enable
*/
uint8_t DMA_ENA; /*!<
-0: DMA access is disable
-1: DMA burst request
*/
uint8_t RESERVED;
} DAC_CONVERTER_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup DAC_Public_Functions DAC Public Functions
* @{
*/
void DAC_Init(LPC_DAC_Type *DACx);
void DAC_UpdateValue (LPC_DAC_Type *DACx, uint32_t dac_value);
void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias);
void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
void DAC_SetDMATimeOut(LPC_DAC_Type *DACx,uint32_t time_out);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_DAC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

79
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_emc.h vendored
View file

@ -1,79 +0,0 @@
/**********************************************************************
* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
*//**
* @file lpc43xx_emc.h
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
#define __PLLMULT (15)
#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
#define __EMCDIV (2)
#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
void MemoryPinInit(void);
void EMCFlashInit(void);
/* SDRAM Address Base for DYCS0*/
#define SDRAM_BASE_ADDR 0x28000000
#define FLASH_BASE_ADDR 0x1C000000
#define EMC_SDRAM_WIDTH_8_BITS 0
#define EMC_SDRAM_WIDTH_16_BITS 1
#define EMC_SDRAM_WIDTH_32_BITS 2
#define EMC_SDRAM_SIZE_16_MBITS 0
#define EMC_SDRAM_SIZE_64_MBITS 1
#define EMC_SDRAM_SIZE_128_MBITS 2
#define EMC_SDRAM_SIZE_256_MBITS 3
#define EMC_SDRAM_SIZE_512_MBITS 4
#define EMC_SDRAM_DATA_BUS_16_BITS 0
#define EMC_SDRAM_DATA_BUS_32_BITS 1
#define EMC_B_ENABLE (1 << 19)
#define EMC_ENABLE (1 << 0)
#define EMC_CE_ENABLE (1 << 0)
#define EMC_CS_ENABLE (1 << 1)
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
#define EMC_INIT(i) ((i) << 7)
#define EMC_NORMAL (0)
#define EMC_MODE (1)
#define EMC_PRECHARGE_ALL (2)
#define EMC_NOP (3)
/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
#define SDRAM_COL_ADDR_BITS 8
#define CLK0_DELAY 0
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
void emc_WaitUS(volatile uint32_t us);
void emc_WaitMS(uint32_t ms);

146
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_evrt.h vendored
View file

@ -1,146 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_evrt.h 2011-06-02
*//**
* @file lpc18xx_evrt.h
* @brief Contains all macro definitions and function prototypes
* support for Event Router firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EVRT EVRT (Event Router)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_EVRT_H_
#define LPC18XX_EVRT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup EVRT_Private_Macros EVRT Private Macros
* @{
*/
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid EVRT peripheral */
#define PARAM_EVRTx(x) (((uint32_t *)x)==((uint32_t *)LPC_EVENTROUTER))
/* Macro check EVRT source */
#define PARAM_EVRT_SOURCE(n) ((n==EVRT_SRC_WAKEUP0) || (n==EVRT_SRC_WAKEUP1) \
|| (n==EVRT_SRC_WAKEUP2) || (n==EVRT_SRC_WAKEUP3) \
|| (n==EVRT_SRC_ATIMER) || (n==EVRT_SRC_RTC) \
|| (n==EVRT_SRC_BOD1) || (n==EVRT_SRC_WWDT) \
|| (n==EVRT_SRC_ETHERNET) || (n==EVRT_SRC_USB0) \
|| (n==EVRT_SRC_USB1) || (n==EVRT_SRC_CCAN) || (n==EVRT_SRC_SDIO) \
|| (n==EVRT_SRC_COMBINE_TIMER2) || (n==EVRT_SRC_COMBINE_TIMER6) \
|| (n==EVRT_SRC_QEI) || (n==EVRT_SRC_COMBINE_TIMER14) \
|| (n==EVRT_SRC_RESET)) \
/* Macro check EVRT source active type*/
#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n==EVRT_SRC_ACTIVE_LOW_LEVEL) || (n==EVRT_SRC_ACTIVE_HIGH_LEVEL) \
|| (n==EVRT_SRC_ACTIVE_FALLING_EDGE) || (n==EVRT_SRC_ACTIVE_RISING_EDGE))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup EVRT_Public_Types EVRT Public Types
* @{
*/
/** @brief EVRT input sources */
typedef enum {
EVRT_SRC_WAKEUP0, /**< WAKEUP0 event router source */
EVRT_SRC_WAKEUP1, /**< WAKEUP1 event router source */
EVRT_SRC_WAKEUP2, /**< WAKEUP2 event router source */
EVRT_SRC_WAKEUP3, /**< WAKEUP3 event router source */
EVRT_SRC_ATIMER, /**< Alarm timer event router source */
EVRT_SRC_RTC, /**< RTC event router source */
EVRT_SRC_BOD1, /**< BOD event router source */
EVRT_SRC_WWDT, /**< WWDT event router source */
EVRT_SRC_ETHERNET, /**< Ethernet event router source */
EVRT_SRC_USB0, /**< USB0 event router source */
EVRT_SRC_USB1, /**< USB1 event router source */
EVRT_SRC_SDIO, /**< Reserved */
EVRT_SRC_CCAN, /**< C_CAN event router source */
EVRT_SRC_COMBINE_TIMER2, /**< Combined timer 2 event router source */
EVRT_SRC_COMBINE_TIMER6, /**< Combined timer 6 event router source */
EVRT_SRC_QEI, /**< QEI event router source */
EVRT_SRC_COMBINE_TIMER14, /**< Combined timer 14 event router source */
EVRT_SRC_RESERVED1, /**< Reserved */
EVRT_SRC_RESERVED2, /**< Reserved */
EVRT_SRC_RESET /**< Reset event router source */
} EVRT_SRC_ENUM;
/** @brief EVRT input sources detecting type */
typedef enum {
EVRT_SRC_ACTIVE_LOW_LEVEL, /**< Active low level */
EVRT_SRC_ACTIVE_HIGH_LEVEL, /**< Active high level */
EVRT_SRC_ACTIVE_FALLING_EDGE, /**< Active falling edge */
EVRT_SRC_ACTIVE_RISING_EDGE /**< Active rising edge */
}EVRT_SRC_ACTIVE_TYPE;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup EVRT_Public_Functions EVRT Public Functions
* @{
*/
void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx);
void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx);
void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_EVRT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

468
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_gpdma.h vendored
View file

@ -1,468 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_gpdma.h 2011-06-02
*//**
* @file lpc18xx_gpdma.h
* @brief Contains all macro definitions and function prototypes
* support for GPDMA firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPDMA GPDMA (General Purpose DMA)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_GPDMA_H_
#define LPC18XX_GPDMA_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
* @{
*/
/** DMA Connection number definitions */
#define GPDMA_CONN_SPIFI ((0UL)) /**< SPIFI */
#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
#define GPDMA_CONN_I2S_Channel_0 ((20UL)) /**< I2S channel 0 */
#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
#define GPDMA_CONN_I2S_Channel_1 ((22UL)) /**< I2S channel 1 */
#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
#define GPDMA_CONN_DAC ((27UL)) /**< DAC */
/** GPDMA Transfer type definitions */
#define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA ((0UL)) /**< Memory to memory - DMA control */
#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA ((1UL)) /**< Memory to peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA ((2UL)) /**< Peripheral to memory - DMA control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL ((4UL)) /**< Source peripheral to destination peripheral - destination peripheral control */
#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL ((5UL)) /**< Memory to peripheral - peripheral control */
#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL ((6UL)) /**< Peripheral to memory - peripheral control */
#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */
/** Burst size in Source and Destination definitions */
#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
/** Width in Source transfer width and Destination transfer width definitions */
#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
/** LPC_GPDMA base addresses */
#define LPC_GPDMACH0_BASE 0x40002100
#define LPC_GPDMACH1_BASE 0x40002120
#define LPC_GPDMACH2_BASE 0x40002140
#define LPC_GPDMACH3_BASE 0x40002160
#define LPC_GPDMACH4_BASE 0x40002180
#define LPC_GPDMACH5_BASE 0x400021A0
#define LPC_GPDMACH6_BASE 0x400021C0
#define LPC_GPDMACH7_BASE 0x400021E0
/* LPC_GPDMA channels definitions */
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for DMA Interrupt Status register
**********************************************************************/
#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Status register
**********************************************************************/
#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Clear register
**********************************************************************/
#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Status register
**********************************************************************/
#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Clear register
**********************************************************************/
#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Interrupt Terminal Count Status register
**********************************************************************/
#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Error Interrupt Status register
**********************************************************************/
#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Enabled Channel register
**********************************************************************/
#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Software Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Single Request register
**********************************************************************/
#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Single Request register
**********************************************************************/
#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Configuration register
**********************************************************************/
#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
#define GPDMA_DMACConfig_M0 ((0x02)) /**< AHB Master 0 endianness configuration*/
#define GPDMA_DMACConfig_M1 ((0x04)) /**< AHB Master 1 endianness configuration*/
#define GPDMA_DMACConfig_BITMASK ((0x07))
/*********************************************************************//**
* Macro defines for DMA Synchronization register
**********************************************************************/
#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSync_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Channel Linked List Item registers
**********************************************************************/
/** DMA Channel Linked List Item registers bit mask*/
#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
/*********************************************************************//**
* Macro defines for DMA channel control registers
**********************************************************************/
#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL<<24)) /**< Source AHB master select*/
#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL<<25)) /**< Destination AHB master select*/
#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
/** DMA channel control registers bit mask */
#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
/*********************************************************************//**
* Macro defines for DMA Channel Configuration registers
**********************************************************************/
#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
/** DMA Channel Configuration registers bit mask */
#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macros check GPDMA channel */
#define PARAM_GPDMA_CHANNEL(n) (n<=7)
/* Macros check GPDMA connection type */
#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SPIFI) || (n==GPDMA_CONN_DAC) \
|| (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
|| (n==GPDMA_CONN_ADC_0) || (n==GPDMA_CONN_ADC_1) \
|| (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \
|| (n==GPDMA_CONN_SCT_0) || (n==GPDMA_CONN_SCT_1) \
|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
/* Macros check GPDMA burst size type */
#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
/* Macros check GPDMA width type */
#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
|| (n==GPDMA_WIDTH_WORD))
/* Macros check GPDMA status type */
#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
/* Macros check GPDMA transfer type */
#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \
||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\
||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\
||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))
/* Macros check GPDMA state clear type */
#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Types GPDMA Public Types
* @{
*/
/**
* @brief GPDMA Channel Registers
*/
typedef struct
{
__IO uint32_t CSrcAddr;
__IO uint32_t CDestAddr;
__IO uint32_t CLLI;
__IO uint32_t CControl;
__IO uint32_t CConfig;
} LPC_GPDMACH_TypeDef;
/**
* @brief GPDMA Status enumeration
*/
typedef enum {
GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
} GPDMA_Status_Type;
/**
* @brief GPDMA Interrupt clear status enumeration
*/
typedef enum{
GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
}GPDMA_StateClear_Type;
/**
* @brief GPDMA Channel configuration structure type definition
*/
typedef struct {
uint32_t ChannelNum; /**< DMA channel number, should be in
range from 0 to 7.
Note: DMA channel 0 has the highest priority
and DMA channel 7 the lowest priority.
*/
uint32_t TransferSize; /**< Length/Size of transfer */
uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
uint32_t TransferType; /**< Transfer Type, should be one of the following:
- GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control
- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control
- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control
- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control
- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control
- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: Source peripheral to destination peripheral - source peripheral control
*/
uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC_0: ADC0
- GPDMA_CONN_ADC_1: ADC1
- GPDMA_CONN_SCT_0: SCT0
- GPDMA_CONN_SCT_1: SCT1
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_SPIFI: SPIFI
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC_0: ADC0
- GPDMA_CONN_ADC_1: ADC1
- GPDMA_CONN_SCT_0: SCT0
- GPDMA_CONN_SCT_1: SCT1
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_SPIFI: SPIFI
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DMALLI; /**< Linker List Item structure data address
if there's no Linker List, set as '0'
*/
} GPDMA_Channel_CFG_Type;
/**
* @brief GPDMA Linker List Item structure type definition
*/
typedef struct {
uint32_t SrcAddr; /**< Source Address */
uint32_t DstAddr; /**< Destination address */
uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
uint32_t Control; /**< GPDMA Control of this LLI */
} GPDMA_LLI_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
* @{
*/
void GPDMA_Init(void);
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_GPDMA_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

186
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_gpio.h vendored
View file

@ -1,186 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_gpio.h 2011-06-02
*//**
* @file lpc18xx_gpio.h
* @brief Contains all macro definitions and function prototypes
* support for GPIO firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPIO GPIO (General Purpose I/O)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_GPIO_H_
#define LPC18XX_GPIO_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
#if 0
/** General LPC GPIO Base */
#define LPC_GPIO_BASE LPC_GPIO0_BASE
/** Fast GPIO port 0 byte accessible definition */
#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x00))
/** Fast GPIO port 1 byte accessible definition */
#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x20))
/** Fast GPIO port 2 byte accessible definition */
#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x40))
/** Fast GPIO port 3 byte accessible definition */
#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x60))
/** Fast GPIO port 4 byte accessible definition */
#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x80))
/** Fast GPIO port 0 half-word accessible definition */
#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x00))
/** Fast GPIO port 1 half-word accessible definition */
#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x20))
/** Fast GPIO port 2 half-word accessible definition */
#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x40))
/** Fast GPIO port 3 half-word accessible definition */
#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x60))
/** Fast GPIO port 4 half-word accessible definition */
#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x80))
#endif
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @brief Fast GPIO port byte type definition
*/
#if 0
typedef struct {
__IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */
uint32_t RESERVED0[3]; /**< Reserved */
__IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */
__IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */
__IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */
__O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */
} GPIO_Byte_TypeDef;
#endif
/**
* @brief Fast GPIO port half-word type definition
*/
#if 0
typedef struct {
__IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */
__IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */
uint32_t RESERVED0[3]; /**< Reserved */
__IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */
__IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */
__IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */
__IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */
__IO uint16_t FIOSETL; /**< FIO set register lower halfword part */
__IO uint16_t FIOSETU; /**< FIO set register upper halfword part */
__O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */
__O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */
} GPIO_HalfWord_TypeDef;
#endif
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPIO_Public_Functions GPIO Public Functions
* @{
*/
/* GPIO style ------------------------------- */
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t GPIO_ReadValue(uint8_t portNum);
#ifdef GPIO_INT
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
#endif
/* FIO (word-accessible) style ------------------------------- */
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t FIO_ReadValue(uint8_t portNum);
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
#ifdef GPIO_INT
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
#endif
#if 0
/* FIO (halfword-accessible) style ------------------------------- */
void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
/* FIO (byte-accessible) style ------------------------------- */
void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_GPIO_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

383
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_i2c.h vendored
View file

@ -1,383 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_i2c.h 2011-06-02
*//**
* @file lpc18xx_i2c.h
* @brief Contains all macro definitions and function prototypes
* support for I2C firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2C I2C (Inter-Integrated Circuit)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_I2C_H_
#define LPC18XX_I2C_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*******************************************************************//**
* I2C Control Set register description
*********************************************************************/
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
/*******************************************************************//**
* I2C Control Clear register description
*********************************************************************/
/** Assert acknowledge Clear bit */
#define I2C_I2CONCLR_AAC ((1<<2))
/** I2C interrupt Clear bit */
#define I2C_I2CONCLR_SIC ((1<<3))
/** START flag Clear bit */
#define I2C_I2CONCLR_STAC ((1<<5))
/** I2C interface Disable bit */
#define I2C_I2CONCLR_I2ENC ((1<<6))
/********************************************************************//**
* I2C Status Code definition (I2C Status register)
*********************************************************************/
/* Return Code in I2C status register */
#define I2C_STAT_CODE_BITMASK ((0xF8))
/* I2C return status code definitions ----------------------------- */
/** No relevant information */
#define I2C_I2STAT_NO_INF ((0xF8))
/* Master transmit mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_TX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))
/** SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
/** SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
/** Arbitration lost in SLA+R/W or Data bytes */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
/* Master receive mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_RX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))
/** Arbitration lost */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
/** SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
/** SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
/** Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
/** Data has been received, NACK has been return */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
/* Slave receive mode -------------------------------------------- */
/** Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
/** Own SLA+W has been received, ACK returned */
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
/** General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
/** General call address has been received, ACK has been returned */
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
/** Previously addressed with own SLV address;
* Data has been received, ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
/** Previously addressed with own SLA;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
/** Previously addressed with General Call;
* Data has been received and ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
/** Previously addressed with General Call;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
/** A STOP condition or repeated START condition has
* been received while still addressed as SLV/REC
* (Slave Receive) or SLV/TRX (Slave Transmit) */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
/** Slave transmit mode */
/** Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
/** Own SLA+R has been received, ACK has been returned */
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
/** Last data byte in I2DAT has been transmitted (AA = 0);
ACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
/** Time out in case of using I2C slave mode */
#define I2C_SLAVE_TIME_OUT 0x10000UL
/********************************************************************//**
* I2C Data register definition
*********************************************************************/
/** Mask for I2DAT register*/
#define I2C_I2DAT_BITMASK ((0xFF))
/** Idle data value will be send out in slave mode in case of the actual
* expecting data requested from the master is greater than its sending data
* length that can be supported */
#define I2C_I2DAT_IDLE_CHAR (0xFF)
/********************************************************************//**
* I2C Monitor mode control register description
*********************************************************************/
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/********************************************************************//**
* I2C Data buffer register description
*********************************************************************/
/** I2C Data buffer register bit mask */
#define I2DATA_BUFFER_BITMASK ((0xFF))
/********************************************************************//**
* I2C Slave Address registers definition
*********************************************************************/
/** General Call enable bit */
#define I2C_I2ADR_GC ((1<<0))
/** I2C Slave Address registers bit mask */
#define I2C_I2ADR_BITMASK ((0xFF))
/********************************************************************//**
* I2C Mask Register definition
*********************************************************************/
/** I2C Mask Register mask field */
#define I2C_I2MASK_MASK(n) ((n&0xFE))
/********************************************************************//**
* I2C SCL HIGH duty cycle Register definition
*********************************************************************/
/** I2C SCL HIGH duty cycle Register bit mask */
#define I2C_I2SCLH_BITMASK ((0xFFFF))
/********************************************************************//**
* I2C SCL LOW duty cycle Register definition
*********************************************************************/
/** I2C SCL LOW duty cycle Register bit mask */
#define I2C_I2SCLL_BITMASK ((0xFFFF))
/* I2C status values */
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
/*********************************************************************//**
* I2C monitor control configuration defines
**********************************************************************/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macros check I2C slave address */
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
/** Macro to determine if it is valid SSP port number */
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
/* Macros check I2C monitor configuration type */
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2C_Public_Types I2C Public Types
* @{
*/
/**
* @brief I2C Own slave address setting structure
*/
typedef struct {
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
should be in range from 0..3
*/
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
when I2C control being in Slave mode, should be:
- ENABLE: Enable General Call function.
- DISABLE: Disable General Call function.
*/
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
which is set to '1' will cause an automatic compare on
the corresponding bit of the received address when it
is compared to the SlaveAddr_7bit value associated with this
mask register. In other words, bits in SlaveAddr_7bit value
which are masked are not taken into account in determining
an address match
*/
} I2C_OWNSLAVEADDR_CFG_Type;
/**
* @brief Master transfer setup data structure definitions
*/
typedef struct
{
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
is not used*/
uint32_t tx_count; /**< Current Transmit data counter */
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is
not used */
uint32_t rx_count; /**< Current Receive data counter */
uint32_t retransmissions_max; /**< Max Re-Transmission value */
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to Call back function when transmission complete
used in interrupt transfer mode */
} I2C_M_SETUP_Type;
/**
* @brief Slave transfer setup data structure definitions
*/
typedef struct
{
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
uint32_t tx_count; /**< Current transmit data counter */
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
uint32_t rx_count; /**< Current receive data counter */
uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to call-back function when transmission complete
used by interrupt transfer mode */
} I2C_S_SETUP_Type;
/**
* @brief Transfer option type definitions
*/
typedef enum {
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
} I2C_TRANSFER_OPT_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2C_Public_Functions I2C Public Functions
* @{
*/
/* I2C Init/DeInit functions ---------- */
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
/* I2C transfer data functions -------- */
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
/* I2C Monitor functions ---------------*/
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
/* I2C Interrupt handler functions ------*/
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_I2C_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

369
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_i2s.h vendored
View file

@ -1,369 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_i2s.h 2011-06-02
*//**
* @file lpc18xx_i2s.h
* @brief Contains all macro definitions and function prototypes
* support for I2S firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2S I2S (Inter-IC Sound)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_I2S_H_
#define LPC18XX_I2S_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/*********************************************************************//**
* I2S configuration parameter defines
**********************************************************************/
/** I2S Wordwidth bit */
#define I2S_WORDWIDTH_8 ((uint32_t)(0))
#define I2S_WORDWIDTH_16 ((uint32_t)(1))
#define I2S_WORDWIDTH_32 ((uint32_t)(3))
/** I2S Channel bit */
#define I2S_STEREO ((uint32_t)(0))
#define I2S_MONO ((uint32_t)(1))
/** I2S Master/Slave mode bit */
#define I2S_MASTER_MODE ((uint8_t)(0))
#define I2S_SLAVE_MODE ((uint8_t)(1))
/** I2S Stop bit */
#define I2S_STOP_ENABLE ((uint8_t)(1))
#define I2S_STOP_DISABLE ((uint8_t)(0))
/** I2S Reset bit */
#define I2S_RESET_ENABLE ((uint8_t)(1))
#define I2S_RESET_DISABLE ((uint8_t)(0))
/** I2S Mute bit */
#define I2S_MUTE_ENABLE ((uint8_t)(1))
#define I2S_MUTE_DISABLE ((uint8_t)(0))
/** I2S Transmit/Receive bit */
#define I2S_TX_MODE ((uint8_t)(0))
#define I2S_RX_MODE ((uint8_t)(1))
/** I2S Clock Select bit */
#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
#define I2S_CLKSEL_MCLK ((uint8_t)(2))
/** I2S 4-pin Mode bit */
#define I2S_4PIN_ENABLE ((uint8_t)(1))
#define I2S_4PIN_DISABLE ((uint8_t)(0))
/** I2S MCLK Enable bit */
#define I2S_MCLK_ENABLE ((uint8_t)(1))
#define I2S_MCLK_DISABLE ((uint8_t)(0))
/** I2S select DMA bit */
#define I2S_DMA_1 ((uint8_t)(0))
#define I2S_DMA_2 ((uint8_t)(1))
/*********************************************************************//**
* Macro defines for DAO-Digital Audio Output register
**********************************************************************/
/** I2S wordwide - the number of bytes in data*/
#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
/** I2S control mono or stereo format */
#define I2S_DAO_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAO_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAO_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one */
#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
/** I2S control mute mode */
#define I2S_DAO_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for DAI-Digital Audio Input register
**********************************************************************/
/** I2S wordwide - the number of bytes in data*/
#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
/** I2S control mono or stereo format */
#define I2S_DAI_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAI_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAI_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one (9 bits)*/
#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
/** I2S control mute mode */
#define I2S_DAI_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for STAT register (Status Feedback register)
**********************************************************************/
/** I2S Status Receive or Transmit Interrupt */
#define I2S_STATE_IRQ ((uint32_t)(1))
/** I2S Status Receive or Transmit DMA1 */
#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
/** I2S Status Receive or Transmit DMA2 */
#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
/** I2S Status Current level of the Receive FIFO (5 bits)*/
#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
/** I2S Status Current level of the Transmit FIFO (5 bits)*/
#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
/*********************************************************************//**
* Macro defines for DMA1 register (DMA1 Configuration register)
**********************************************************************/
/** I2S control DMA1 for I2S receive */
#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for DMA2 register (DMA2 Configuration register)
**********************************************************************/
/** I2S control DMA2 for I2S receive */
#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for IRQ register (Interrupt Request Control register)
**********************************************************************/
/** I2S control I2S receive interrupt */
#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
/** I2S control I2S transmit interrupt */
#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/********************************************************************************//**
* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
*********************************************************************************/
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/*************************************************************************************//**
* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
**************************************************************************************/
#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
/**********************************************************************************//**
* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
************************************************************************************/
/** I2S Transmit select clock source (2 bits)*/
#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Transmit control 4-pin mode */
#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Transmit control the TX_MCLK output */
#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
/** I2S Receive select clock source */
#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Receive control 4-pin mode */
#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Receive control the TX_MCLK output */
#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid I2S peripheral */
#define PARAM_I2Sx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2S0)) || (((uint32_t *)n)==((uint32_t *)LPC_I2S1)))
/** Macro to check Data to send valid */
#define PRAM_I2S_FREQ(freq) ((freq>=8000)&&(freq <= 96000))
/* Macro check I2S word width type */
#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
||(n==I2S_WORDWIDTH_32))
/* Macro check I2S channel type */
#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
/* Macro check I2S master/slave mode */
#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
/* Macro check I2S stop mode */
#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
/* Macro check I2S reset mode */
#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
/* Macro check I2S reset mode */
#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
/* Macro check I2S transmit/receive mode */
#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
/* Macro check I2S clock select mode */
#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
/* Macro check I2S 4-pin mode */
#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
/* Macro check I2S MCLK mode */
#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
/* Macro check I2S DMA mode */
#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
/* Macro check I2S DMA depth value */
#define PARAM_I2S_DMA_DEPTH(n) ((n<=31))
/* Macro check I2S irq level value */
#define PARAM_I2S_IRQ_LEVEL(n) ((n<=31))
/* Macro check I2S half-period value */
#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
/* Macro check I2S bit-rate value */
#define PARAM_I2S_BITRATE(n) ((n<=63))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2S_Public_Types I2S Public Types
* @{
*/
/**
* @brief I2S configuration structure definition
*/
typedef struct {
uint8_t wordwidth; /** the number of bytes in data as follow:
-I2S_WORDWIDTH_8: 8 bit data
-I2S_WORDWIDTH_16: 16 bit data
-I2S_WORDWIDTH_32: 32 bit data */
uint8_t mono; /** Set mono/stereo mode, should be:
- I2S_STEREO: stereo mode
- I2S_MONO: mono mode */
uint8_t stop; /** Disables accesses on FIFOs, should be:
- I2S_STOP_ENABLE: enable stop mode
- I2S_STOP_DISABLE: disable stop mode */
uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
- I2S_RESET_ENABLE: enable reset mode
- I2S_RESET_DISABLE: disable reset mode */
uint8_t ws_sel; /** Set Master/Slave mode, should be:
- I2S_MASTER_MODE: I2S master mode
- I2S_SLAVE_MODE: I2S slave mode */
uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
- I2S_MUTE_ENABLE: enable mute mode
- I2S_MUTE_DISABLE: disable mute mode */
uint8_t Reserved0[2];
} I2S_CFG_Type;
/**
* @brief I2S DMA configuration structure definition
*/
typedef struct {
uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
- I2S_DMA_1: DMA1
- I2S_DMA_2: DMA2 */
uint8_t depth; /** FIFO level that triggers a DMA request */
uint8_t Reserved0[2];
}I2S_DMAConf_Type;
/**
* @brief I2S mode configuration structure definition
*/
typedef struct{
uint8_t clksel; /** Clock source selection, should be:
- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
uint8_t fpin; /** Select four pin mode, should be:
- I2S_4PIN_ENABLE: 4-pin enable
- I2S_4PIN_DISABLE: 4-pin disable */
uint8_t mcena; /** Select MCLK mode, should be:
- I2S_MCLK_ENABLE: MCLK enable for output
- I2S_MCLK_DISABLE: MCLK disable for output */
uint8_t Reserved;
}I2S_MODEConf_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2S_Public_Functions I2S Public Functions
* @{
*/
/* I2S Init/DeInit functions ---------*/
void I2S_Init(LPC_I2Sn_Type *I2Sx);
void I2S_DeInit(LPC_I2Sn_Type *I2Sx);
/* I2S configuration functions --------*/
void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode);
void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode);
void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
/* I2S operate functions -------------*/
void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData);
uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx);
void I2S_Start(LPC_I2Sn_Type *I2Sx);
void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
/* I2S DMA functions ----------------*/
void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
/* I2S IRQ functions ----------------*/
void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState);
void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level);
FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_I2S_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

224
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_lcd.h vendored
View file

@ -1,224 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_lcd.h 2011-06-02
*//**
* @file lpc18xx_lcd.h
* @brief Contains all macro definitions and function prototypes
* support for LCD Driver
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup LCD LCD
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_LCD_H_
#define __LPC18XX_LCD_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup LCD_Private_Macros LCD Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* LCD control enable bit */
#define CLCDC_LCDCTRL_ENABLE _BIT(0)
/* LCD control power enable bit */
#define CLCDC_LCDCTRL_PWR _BIT(11)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup LCD_Public_Types LCD Public Types
* @{
*/
/*********************************************************************//**
* @brief LCD enumeration
**********************************************************************/
/** @brief LCD Interrupt Source */
typedef enum{
LCD_INT_FUF = _BIT(1), /* FIFO underflow bit */
LCD_INT_LNBU = _BIT(2), /* LCD next base address update bit */
LCD_INT_VCOMP = _BIT(3), /* vertical compare bit */
LCD_INT_BER = _BIT(4) /* AHB master error interrupt bit */
} LCD_INT_SRC;
/** @brief LCD signal polarity */
typedef enum {
LCD_SIGNAL_ACTIVE_HIGH = 0,
LCD_SIGNAL_ACTIVE_LOW = 1
} LCD_SIGNAL_POLARITY_OPT;
/** @brief LCD clock edge polarity */
typedef enum {
LCD_CLK_RISING = 0,
LCD_CLK_FALLING= 1
} LCD_CLK_EDGE_OPT;
/** @brief LCD bits per pixel and pixel format */
typedef enum {
LCD_BPP1 = 0,
LCD_BPP2,
LCD_BPP4,
LCD_BPP8,
LCD_BPP16,
LCD_BPP24,
LCD_BPP16_565,
LCD_BPP12_444
}LCD_PIXEL_FORMAT_OPT;
/** @brief LCD color format */
typedef enum {
LCD_COLOR_FORMAT_RGB = 0,
LCD_COLOR_FORMAT_BGR
}LCD_COLOR_FORMAT_OPT;
/*********************************************************************//**
* @brief LCD structure definitions
**********************************************************************/
/** @brief LCD Palette entry format */
typedef struct
{
uint32_t Rl:5;
uint32_t Gl:5;
uint32_t Bl:5;
uint32_t Il:1;
uint32_t Ru:5;
uint32_t Gu:5;
uint32_t Bu:5;
uint32_t Iu:1;
} LCD_PALETTE_ENTRY_Type;
/** @brief LCD cursor format in 1 byte LBBP */
typedef struct
{
uint8_t Pixel3:2;
uint8_t Pixel2:2;
uint8_t Pixel1:2;
uint8_t Pixel0:2;
} LCD_CURSOR_PIXEL_Type;
/** @brief LCD cursor size */
typedef enum
{
LCD_CURSOR_32x32 = 0,
LCD_CURSOR_64x64
} LCD_CURSOR_SIZE_OPT;
/** @brief LCD panel type */
typedef enum
{
LCD_TFT = 0x02, /* standard TFT */
LCD_MONO_4 = 0x01, /* 4-bit STN mono */
LCD_MONO_8 = 0x05, /* 8-bit STN mono */
LCD_CSTN = 0x00 /* color STN */
} LCD_PANEL_OPT;
/** @brief LCD porch configuration structure */
typedef struct {
uint16_t front; /* front porch setting in clocks */
uint16_t back; /* back porch setting in clocks */
}LCD_PORCHCFG_Type;
/** @brief LCD configuration structure */
typedef struct {
uint16_t screen_width; /* Pixels per line */
uint16_t screen_height; /* Lines per panel */
LCD_PORCHCFG_Type horizontal_porch; /* porch setting for horizontal */
LCD_PORCHCFG_Type vertical_porch; /* porch setting for vertical */
uint16_t HSync_pulse_width; /* HSYNC pulse width in clocks */
uint16_t VSync_pulse_width; /* VSYNC pulse width in clocks */
uint8_t ac_bias_frequency; /* AC bias frequency in clocks */
LCD_SIGNAL_POLARITY_OPT HSync_pol; /* HSYNC polarity */
LCD_SIGNAL_POLARITY_OPT VSync_pol; /* VSYNC polarity */
LCD_CLK_EDGE_OPT panel_clk_edge; /* Panel Clock Edge Polarity */
LCD_SIGNAL_POLARITY_OPT OE_pol; /* Output Enable polarity */
uint32_t line_end_delay; /* 0 if not use */
LCD_PIXEL_FORMAT_OPT bits_per_pixel; /* Maximum bits per pixel the display supports */
LCD_PANEL_OPT lcd_panel_type; /* LCD panel type */
LCD_COLOR_FORMAT_OPT color_format; /* BGR or RGB */
Bool dual_panel; /* Dual panel, TRUE = dual panel display */
uint16_t pcd;
} LCD_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup LCD_Public_Functions LCD Public Functions
* @{
*/
void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct);
void LCD_DeInit(LPC_LCD_Type *LCDx);
void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff);
void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis);
void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette);
void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync);
void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image);
void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num);
void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff);
void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color);
void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color);
void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx);
void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
void LCD_Cursor_SetClipPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_LCD_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

192
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_libcfg_default.h vendored
View file

@ -1,192 +0,0 @@
/*
* Modified for Code Red tools to prevent redefinition of DEBUG macro
* 2011/12/29
*/
/**********************************************************************
* $Id$ lpc18xx_libcfg_default.h 2011-06-02
*//**
* @file lpc18xx_libcfg_default.h
* @brief Default Library configuration header file
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Library Configuration group ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_LIBCFG_DEFAULT_H_
#define LPC18XX_LIBCFG_DEFAULT_H_
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
* @{
*/
/************************** DEBUG MODE DEFINITIONS *********************************/
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
the "CHECK_PARAM" macro in the FW library code */
#ifndef __CODE_RED
#define DEBUG
#endif
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
/* Comment the line below to disable the specific peripheral inclusion */
/* GPIO ------------------------------- */
#define _GPIO
/* EXTI ------------------------------- */
#define _EXTI
/* UART ------------------------------- */
#define _UART
#define _UART0
#define _UART1
#define _UART2
#define _UART3
/* SPI ------------------------------- */
#define _SPI
/* SYSTICK --------------------------- */
#define _SYSTICK
/* SSP ------------------------------- */
#define _SSP
#define _SSP0
#define _SSP1
/* I2C ------------------------------- */
#define _I2C
#define _I2C0
#define _I2C1
#define _I2C2
/* TIMER ------------------------------- */
#define _TIM
/* WWDT ------------------------------- */
#define _WWDT
/* GPDMA ------------------------------- */
#define _GPDMA
/* DAC ------------------------------- */
#define _DAC
/* DAC ------------------------------- */
#define _ADC
/* PWM ------------------------------- */
#define _PWM
#define _PWM1
/* RTC ------------------------------- */
#define _RTC
/* I2S ------------------------------- */
#define _I2S
/* USB device ------------------------------- */
#define _USBDEV
#define _USB_DMA
/* QEI ------------------------------- */
#define _QEI
/* MCPWM ------------------------------- */
#define _MCPWM
/* CAN--------------------------------*/
#define _C_CAN
/* RIT ------------------------------- */
#define _RIT
/* EMAC ------------------------------ */
#define _EMAC
/* SCT ------------------------------ */
#define _SCT
/* LCD ------------------------------ */
#define _LCD
/* ATIMER ------------------------------ */
#define _ATIMER
/* RGU ------------------------------ */
#define _RGU
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
#ifdef DEBUG
/*******************************************************************************
* @brief The CHECK_PARAM macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* @param[in] expr - If expr is false, it calls check_failed() function
* which reports the name of the source file and the source
* line number of the call that failed.
* - If expr is true, it returns no value.
* @return None
*******************************************************************************/
#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
#else
#define CHECK_PARAM(expr)
#endif /* DEBUG */
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
* @{
*/
#ifdef DEBUG
void check_failed(uint8_t *file, uint32_t line);
#endif
/**
* @}
*/
#endif /* LPC18XX_LIBCFG_DEFAULT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

338
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_mcpwm.h vendored
View file

@ -1,338 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_mcpwm.h 2011-06-02
*//**
* @file lpc18xx_mcpwm.h
* @brief Contains all macro definitions and function prototypes
* support for Motor Control PWM firmware library on LPC18XX
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup MCPWM MCPWM (Motor Control PWM)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_MCPWM_H_
#define LPC18XX_MCPWM_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
* @{
*/
/** Edge aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
/** Center aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
* the six output pins under the control of the bits in this register */
#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/* Interrupt type in MCPWM */
/** Limit interrupt for channel (0) */
#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
/** Match interrupt for channel (0) */
#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
/** Capture interrupt for channel (0) */
#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
/** Limit interrupt for channel (1) */
#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
/** Match interrupt for channel (1) */
#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
/** Capture interrupt for channel (1) */
#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
/** Limit interrupt for channel (2) */
#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
/** Match interrupt for channel (2) */
#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
/** Capture interrupt for channel (2) */
#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
/** Fast abort interrupt */
#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
/*********************************************************************//**
* Macro defines for MCPWM Control register
**********************************************************************/
/* MCPWM Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Control read address
* - MCPWM Control set address
* - MCPWM Control clear address
*/
/**< Stops/starts timer channel n */
#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))
/**< Edge/center aligned operation for channel n */
#define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))
/**< Select polarity of the MCOAn and MCOBn pin */
#define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))
/**< Control the dead-time feature for channel n */
#define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))
/**< Enable/Disable update of functional register for channel n */
#define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))
/**< Control the polarity for all 3 channels */
#define MCPWM_CON_INVBDC ((uint32_t)(1<<29))
/**< 3-phase AC mode select */
#define MCPWM_CON_ACMODE ((uint32_t)(1<<30))
/**< 3-phase DC mode select */
#define MCPWM_CON_DCMODE (((uint32_t)1<<31))
/*********************************************************************//**
* Macro defines for MCPWM Capture Control register
**********************************************************************/
/* Capture Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Capture Control read address
* - MCPWM Capture Control set address
* - MCPWM Capture control clear address
*/
/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
/** TC(n) is reset by channel (n) capture event */
#define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
/** Hardware noise filter: channel (n) capture events are delayed */
#define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Interrupt register
**********************************************************************/
/* Interrupt registers, these macro definitions below can be applied for these
* register type:
* - MCPWM Interrupt Enable read address
* - MCPWM Interrupt Enable set address
* - MCPWM Interrupt Enable clear address
* - MCPWM Interrupt Flags read address
* - MCPWM Interrupt Flags set address
* - MCPWM Interrupt Flags clear address
*/
/** Limit interrupt for channel (n) */
#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
/** Match interrupt for channel (n) */
#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
/** Capture interrupt for channel (n) */
#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
/** Fast abort interrupt */
#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for MCPWM Count Control register
**********************************************************************/
/* MCPWM Count Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Count Control read address
* - MCPWM Count Control set address
* - MCPWM Count Control clear address
*/
/** Counter(tc) advances on a rising edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
/** Channel (n) is in counter mode */
#define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Dead-time register
**********************************************************************/
/** Dead time value x for channel n */
#define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Communication Pattern register
**********************************************************************/
#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/*********************************************************************//**
* Macro defines for MCPWM Capture clear address register
**********************************************************************/
/** Clear the MCCAP (n) register */
#define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1<<n)) : (0))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup MCPWM_Public_Types MCPWM Public Types
* @{
*/
/*********************************************************************//**
* @brief MCPWM enumeration
**********************************************************************/
/**
* @brief MCPWM channel identifier definition
*/
typedef enum
{
MCPWM_CHANNEL_0 = 0, /**< MCPWM channel 0 */
MCPWM_CHANNEL_1, /**< MCPWM channel 1 */
MCPWM_CHANNEL_2 /**< MCPWM channel 2 */
} en_MCPWM_Channel_Id;
/*********************************************************************//**
* @brief MCPWM structure definitions
**********************************************************************/
/**
* @brief Motor Control PWM Channel Configuration structure type definition
*/
typedef struct {
uint32_t channelType; /**< Edge/center aligned mode for this channel,
should be:
- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
*/
uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
*/
uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
uint32_t channelPeriodValue; /**< MCPWM Period value */
uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
} MCPWM_CHANNEL_CFG_Type;
/**
* @brief MCPWM Capture Configuration type definition
*/
typedef struct {
uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
- ENABLE.
- DISABLE.
*/
uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_CAPTURE_CFG_Type;
/**
* @brief MCPWM Count Control Configuration type definition
*/
typedef struct {
uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_COUNT_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
* @{
*/
void MCPWM_Init(LPC_MCPWM_Type *MCPWMx);
void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type * channelSetup);
void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type *channelSetup);
void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CAPTURE_CFG_Type *captureConfig);
void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
void MCPWM_Start(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx,uint32_t acMode);
void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,
uint32_t outputInvered, uint32_t outputPattern);
void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_MCPWM_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

68
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_nvic.h vendored
View file

@ -1,68 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_nvic.h 2011-06-02
*//**
* @file lpc18xx_nvic.h
* @brief Contains all macro definitions and function prototypes
* support for Nesting Vectored Interrupt firmware library
* on LPC18XX
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup NVIC NVIC (Nested Vector Interrupt Controller)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_NVIC_H_
#define LPC18XX_NVIC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Functions ----------------------------------------------------------- */
/** @defgroup NVIC_Public_Functions NVIC Public Functions
* @{
*/
void NVIC_SetVTOR(uint32_t offset);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_NVIC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

83
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_pwr.h vendored
View file

@ -1,83 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_pwr.h 2011-06-02
*//**
* @file lpc18xx_pwr.h
* @brief Contains all macro definitions and function prototypes
* support for Power Control firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PWR PWR (Power Control)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_PWR_H_
#define LPC18XX_PWR_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define PWR_SLEEP_MODE_DEEP_SLEEP 0x3F00AA
#define PWR_SLEEP_MODE_POWER_DOWN 0x30FCBA
#define PWR_SLEEP_MODE_DEEP_POWER_DOWN 0x3FFF7F
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PWR_Public_Functions PWR Public Functions
* @{
*/
/* Clock Generator */
void PWR_Sleep(void);
void PWR_DeepSleep(void);
void PWR_PowerDown(void);
void PWR_DeepPowerDown(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_PWR_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

426
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_qei.h vendored
View file

@ -1,426 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_qei.h 2011-06-02
*//**
* @file lpc18xx_qei.h
* @brief Contains all macro definitions and function prototypes
* support for QEI firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup QEI QEI (Quadrature Encoder Interface)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_QEI_H_
#define LPC18XX_QEI_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup QEI_Private_Macros QEI Private Macros
* @{
*/
/** QEI peripheral numver definition */
#define QEI_0 (0) /** Always 0 - because we just have only one QEI peripheral */
/** QEI Reset types */
#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
/** QEI Direction Invert Type Option */
#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
/** QEI Signal Mode Option */
#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
/** QEI Capture Mode Option */
#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
/** QEI Invert Index Signal Option */
#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
/** QEI timer reload option */
#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
/** QEI Flag Status type */
#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
/** QEI Compare Position channel option */
#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
/** QEI interrupt flag type */
#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
current position interrupt */
#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
index count interrupt */
#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* Quadrature Encoder Interface Control Register Definition --------------------- */
/*********************************************************************//**
* Macro defines for QEI Control register
**********************************************************************/
#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Configuration register
**********************************************************************/
#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Status register
**********************************************************************/
#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
/*********************************************************************//**
* Macro defines for QEI Interrupt Status register
**********************************************************************/
#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
index count */
#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
both the POS0_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
both the POS1_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
both the POS2_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Set register
**********************************************************************/
#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Clear register
**********************************************************************/
#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Clear register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable register
**********************************************************************/
#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Set register
**********************************************************************/
#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Clear register
**********************************************************************/
#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
current position */
#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
current position */
#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
current position */
#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
index count */
#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Enable Clear register bit-mask */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macro check QEI peripheral */
#define PARAM_QEIx(n) ((n==LPC_QEI))
/* Macro check QEI reset type */
#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
|| (n==QEI_RESET_POSOnIDX) \
|| (n==QEI_RESET_VEL) \
|| (n==QEI_RESET_IDX))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
/* Macro check QEI signal mode */
#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
/* Macro check QEI Capture mode */
#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
/* Macro check QEI Invert index mode */
#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
/* Macro check QEI status type */
#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
/* Macro check QEI combine position type */
#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
/* Macro check QEI interrupt flag type */
#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
|| (n==QEI_INTFLAG_TIM_Int) \
|| (n==QEI_INTFLAG_VELC_Int) \
|| (n==QEI_INTFLAG_DIR_Int) \
|| (n==QEI_INTFLAG_ERR_Int) \
|| (n==QEI_INTFLAG_ENCLK_Int) \
|| (n==QEI_INTFLAG_POS0_Int) \
|| (n==QEI_INTFLAG_POS1_Int) \
|| (n==QEI_INTFLAG_POS2_Int) \
|| (n==QEI_INTFLAG_REV_Int) \
|| (n==QEI_INTFLAG_POS0REV_Int) \
|| (n==QEI_INTFLAG_POS1REV_Int) \
|| (n==QEI_INTFLAG_POS2REV_Int))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup QEI_Public_Types QEI Public Types
* @{
*/
/*********************************************************************//**
* @brief QEI structure definitions
**********************************************************************/
/**
* @brief QEI Configuration structure type definition
*/
typedef struct {
uint32_t DirectionInvert :1; /**< Direction invert option:
- QEI_DIRINV_NONE: QEI Direction is normal
- QEI_DIRINV_CMPL: QEI Direction is complemented
*/
uint32_t SignalMode :1; /**< Signal mode Option:
- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
*/
uint32_t CaptureMode :1; /**< Capture Mode Option:
- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
*/
uint32_t InvertIndex :1; /**< Invert Index Option:
- QEI_INVINX_NONE: the sense of the index input is normal
- QEI_INVINX_EN: inverts the sense of the index input
*/
} QEI_CFG_Type;
/**
* @brief Timer Reload Configuration structure type definition
*/
typedef struct {
uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
*/
uint8_t Reserved[3];
uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
with Velocity Timer Reload Option
*/
} QEI_RELOADCFG_Type;
typedef struct
{
uint32_t PHA_FilterVal; /**< FILTERPHA register input */
uint32_t PHB_FilterVal; /**< FILTERPHB register input */
uint32_t INX_FilterVal; /**< FILTERINX register input */
} st_Qei_FilterCfg;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup QEI_Public_Functions QEI Public Functions
* @{
*/
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
void QEI_DeInit(uint8_t qeiId);
void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
uint32_t QEI_GetPosition(uint8_t qeiId);
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
uint32_t QEI_GetIndex(uint8_t qeiId);
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
uint32_t QEI_GetTimer(uint8_t qeiId);
uint32_t QEI_GetVelocity(uint8_t qeiId);
uint32_t QEI_GetVelocityCap(uint8_t qeiId);
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_QEI_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

139
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rgu.h vendored
View file

@ -1,139 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rgu.h 2011-06-02
*//**
* @file lpc18xx_rgu.h
* @brief Contains all macro definitions and function prototypes
* support for RGU firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RGU RGU (Reset Generation Unit)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_RGU_H_
#define LPC18XX_RGU_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Types --------------------------------------------------------------- */
/** @defgroup RGU_Public_Types RGU Public Types
* @{
*/
/*********************************************************************//**
* @brief RGU enumeration
**********************************************************************/
/** @brief Out Reset Signal Generated by RGU */
typedef enum
{
RGU_SIG_CORE = 0, /**< Core reset signal */
RGU_SIG_PERIPH, /**< Peripheral reset signal */
RGU_SIG_MASTER, /**< Master reset signal */
RGU_SIG_WWDT = 4, /**< WWDT reset signal */
RGU_SIG_CREG, /**< CREG reset signal */
RGU_SIG_BUS = 8, /**< Bus reset signal */
RGU_SIG_SCU, /**< SCU reset signal */
RGU_SIG_PINMUX, /**< Pin mux reset signal */
RGU_SIG_M3 = 13, /**< Cortex-M3 reset signal */
RGU_SIG_LCD = 16, /**< LCD reset signal */
RGU_SIG_USB0, /**< USB0 reset signal */
RGU_SIG_USB1, /**< USB1 reset signal */
RGU_SIG_DMA, /**< DMA reset signal */
RGU_SIG_SDIO, /**< SDIO reset signal */
RGU_SIG_EMC, /**< EMC reset signal */
RGU_SIG_ETHERNET, /**< Ethernet reset signal */
RGU_SIG_AES, /**< AES reset signal */
RGU_SIG_GPIO = 28, /**< GPIO reset signal */
RGU_SIG_TIMER0 = 32, /**< TIMER 0 reset signal */
RGU_SIG_TIMER1, /**< TIMER 1 reset signal */
RGU_SIG_TIMER2, /**< TIMER 2 reset signal */
RGU_SIG_TIMER3, /**< TIMER 3 reset signal */
RGU_SIG_RITIMER, /**< RIT timer reset signal */
RGU_SIG_SCT, /**< SCT reset signal */
RGU_SIG_MOTOCONPWM, /**< Motor control reset signal */
RGU_SIG_QEI, /**< QEI reset signal */
RGU_SIG_ADC0, /**< ADC0 reset signal */
RGU_SIG_ADC1, /**< ADC1 reset signal */
RGU_SIG_DAC, /**< DAC reset signal */
RGU_SIG_UART0 = 44, /**< UART0 reset signal */
RGU_SIG_UART1, /**< UART1 reset signal */
RGU_SIG_UART2, /**< UART2 reset signal */
RGU_SIG_UART3, /**< UART3 reset signal */
RGU_SIG_I2C0, /**< I2C0 reset signal */
RGU_SIG_I2C1, /**< I2C1 reset signal */
RGU_SIG_SSP0, /**< SSP0 reset signal */
RGU_SIG_SSP1, /**< SSP1 reset signal */
RGU_SIG_I2S, /**< I2S reset signal */
RGU_SIG_SPIFI, /**< SPIFI reset signal */
RGU_SIG_CAN = 55 /**< CAN reset signal */
}RGU_SIG;
/** @brief Reset Cause Source */
typedef enum {
RGU_SRC_NONE, /**< No source */
RGU_SRC_SOFT, /**< Software reset source */
RGU_SRC_EXT, /**< External reset source */
RGU_SRC_CORE, /**< Core reset source */
RGU_SRC_PERIPH, /**< Peripheral reset source*/
RGU_SRC_MASTER, /**< Master reset source */
RGU_SRC_BOD, /**< BOD reset source */
RGU_SRC_WWDT /**< WWDT reset source */
}RGU_SRC;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RGU_Public_Functions RGU Public Functions
* @{
*/
/* RGU peripheral control function ----------------*/
void RGU_SoftReset(RGU_SIG ResetSignal);
RGU_SRC RGU_GetSource(RGU_SIG ResetSignal);
Bool RGU_GetSignalStatus(RGU_SIG ResetSignal);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_RGU_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

106
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rit.h vendored
View file

@ -1,106 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rit.h 2011-06-02
*//**
* @file lpc18xx_rit.h
* @brief Contains all macro definitions and function prototypes
* support for RIT firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RIT RIT (Repetitive Interrupt Timer)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_RIT_H_
#define LPC18XX_RIT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup RIT_Private_Macros RIT Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for RIT control register
**********************************************************************/
/** Set interrupt flag when the counter value equals the masked compare value */
#define RIT_CTRL_INTEN ((uint32_t) (1))
/** Set timer enable clear to 0 when the counter value equals the masked compare value */
#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
/** Set timer enable on debug */
#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
/** Set timer enable */
#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
/** Macro to determine if it is valid RIT peripheral */
#define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RITIMER))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RIT_Public_Functions RIT Public Functions
* @{
*/
/* RIT Init/DeInit functions */
void RIT_Init(LPC_RITIMER_Type *RITx);
void RIT_DeInit(LPC_RITIMER_Type *RITx);
/* RIT config timer functions */
void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval);
/* Enable/Disable RIT functions */
void RIT_TimerClearCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
/* RIT Interrupt functions */
IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_RIT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

322
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rtc.h vendored
View file

@ -1,322 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rtc.h 2011-06-02
*//**
* @file lpc18xx_rtc.h
* @brief Contains all macro definitions and function prototypes
* support for RTC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RTC RTC (Real-Time Clock)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_RTC_H_
#define LPC18XX_RTC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/* ----------------------- BIT DEFINITIONS ----------------------------------- */
/* Miscellaneous register group --------------------------------------------- */
/**********************************************************************
* ILR register definitions
**********************************************************************/
/** ILR register mask */
#define RTC_ILR_BITMASK ((0x00000003))
/** Bit inform the source interrupt is counter increment*/
#define RTC_IRL_RTCCIF ((1<<0))
/** Bit inform the source interrupt is alarm match*/
#define RTC_IRL_RTCALF ((1<<1))
/**********************************************************************
* CCR register definitions
**********************************************************************/
/** CCR register mask */
#define RTC_CCR_BITMASK ((0x00000013))
/** Clock enable */
#define RTC_CCR_CLKEN ((1<<0))
/** Clock reset */
#define RTC_CCR_CTCRST ((1<<1))
/** Calibration counter enable */
#define RTC_CCR_CCALEN ((1<<4))
/**********************************************************************
* CIIR register definitions
**********************************************************************/
/** Counter Increment Interrupt bit for second */
#define RTC_CIIR_IMSEC ((1<<0))
/** Counter Increment Interrupt bit for minute */
#define RTC_CIIR_IMMIN ((1<<1))
/** Counter Increment Interrupt bit for hour */
#define RTC_CIIR_IMHOUR ((1<<2))
/** Counter Increment Interrupt bit for day of month */
#define RTC_CIIR_IMDOM ((1<<3))
/** Counter Increment Interrupt bit for day of week */
#define RTC_CIIR_IMDOW ((1<<4))
/** Counter Increment Interrupt bit for day of year */
#define RTC_CIIR_IMDOY ((1<<5))
/** Counter Increment Interrupt bit for month */
#define RTC_CIIR_IMMON ((1<<6))
/** Counter Increment Interrupt bit for year */
#define RTC_CIIR_IMYEAR ((1<<7))
/** CIIR bit mask */
#define RTC_CIIR_BITMASK ((0xFF))
/**********************************************************************
* AMR register definitions
**********************************************************************/
/** Counter Increment Select Mask bit for second */
#define RTC_AMR_AMRSEC ((1<<0))
/** Counter Increment Select Mask bit for minute */
#define RTC_AMR_AMRMIN ((1<<1))
/** Counter Increment Select Mask bit for hour */
#define RTC_AMR_AMRHOUR ((1<<2))
/** Counter Increment Select Mask bit for day of month */
#define RTC_AMR_AMRDOM ((1<<3))
/** Counter Increment Select Mask bit for day of week */
#define RTC_AMR_AMRDOW ((1<<4))
/** Counter Increment Select Mask bit for day of year */
#define RTC_AMR_AMRDOY ((1<<5))
/** Counter Increment Select Mask bit for month */
#define RTC_AMR_AMRMON ((1<<6))
/** Counter Increment Select Mask bit for year */
#define RTC_AMR_AMRYEAR ((1<<7))
/** AMR bit mask */
#define RTC_AMR_BITMASK ((0xFF))
/**********************************************************************
* RTC_AUX register definitions
**********************************************************************/
/** RTC Oscillator Fail detect flag */
#define RTC_AUX_RTC_OSCF ((1<<4))
/**********************************************************************
* RTC_AUXEN register definitions
**********************************************************************/
/** Oscillator Fail Detect interrupt enable*/
#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
/* Consolidated time register group ----------------------------------- */
/**********************************************************************
* Consolidated Time Register 0 definitions
**********************************************************************/
#define RTC_CTIME0_SECONDS_MASK ((0x3F))
#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
#define RTC_CTIME0_DOW_MASK ((0x7000000))
/**********************************************************************
* Consolidated Time Register 1 definitions
**********************************************************************/
#define RTC_CTIME1_DOM_MASK ((0x1F))
#define RTC_CTIME1_MONTH_MASK ((0xF00))
#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
/**********************************************************************
* Consolidated Time Register 2 definitions
**********************************************************************/
#define RTC_CTIME2_DOY_MASK ((0xFFF))
/**********************************************************************
* Time Counter Group and Alarm register group
**********************************************************************/
/** SEC register mask */
#define RTC_SEC_MASK (0x0000003F)
/** MIN register mask */
#define RTC_MIN_MASK (0x0000003F)
/** HOUR register mask */
#define RTC_HOUR_MASK (0x0000001F)
/** DOM register mask */
#define RTC_DOM_MASK (0x0000001F)
/** DOW register mask */
#define RTC_DOW_MASK (0x00000007)
/** DOY register mask */
#define RTC_DOY_MASK (0x000001FF)
/** MONTH register mask */
#define RTC_MONTH_MASK (0x0000000F)
/** YEAR register mask */
#define RTC_YEAR_MASK (0x00000FFF)
#define RTC_SECOND_MAX 59 /*!< Maximum value of second */
#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
#define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/
/**********************************************************************
* Calibration register
**********************************************************************/
/* Calibration register */
/** Calibration value */
#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
/** Calibration direction */
#define RTC_CALIBRATION_LIBDIR ((1<<17))
/** Calibration max value */
#define RTC_CALIBRATION_MAX ((0x20000))
/** Calibration definitions */
#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid RTC peripheral */
#define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))
/* Macro check RTC interrupt type */
#define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
/* Macro check RTC time type */
#define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
/* Macro check RTC calibration type */
#define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
/* Macro check RTC GPREG type */
#define PARAM_RTC_GPREG_CH(n) ((n<=63))
/* RTC GPREG base address*/
#define RTC_GPREG_BASE 0x40041000
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup RTC_Public_Types RTC Public Types
* @{
*/
/*********************************************************************//**
* @brief RTC enumeration
**********************************************************************/
/** @brief RTC interrupt source */
typedef enum {
RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
} RTC_INT_OPT;
/** @brief RTC time type option */
typedef enum {
RTC_TIMETYPE_SECOND = 0, /*!< Second */
RTC_TIMETYPE_MINUTE = 1, /*!< Month */
RTC_TIMETYPE_HOUR = 2, /*!< Hour */
RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */
RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */
RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */
RTC_TIMETYPE_MONTH = 6, /*!< Month */
RTC_TIMETYPE_YEAR = 7 /*!< Year */
} RTC_TIMETYPE_Num;
/*********************************************************************//**
* @brief RTC structure definitions
**********************************************************************/
/** @brief Time structure definitions for easy manipulate the data */
typedef struct {
uint32_t SEC; /*!< Seconds Register */
uint32_t MIN; /*!< Minutes Register */
uint32_t HOUR; /*!< Hours Register */
uint32_t DOM; /*!< Day of Month Register */
uint32_t DOW; /*!< Day of Week Register */
uint32_t DOY; /*!< Day of Year Register */
uint32_t MONTH; /*!< Months Register */
uint32_t YEAR; /*!< Years Register */
} RTC_TIME_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RTC_Public_Functions RTC Public Functions
* @{
*/
void RTC_Init (LPC_RTC_Type *RTCx);
void RTC_DeInit(LPC_RTC_Type *RTCx);
void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx);
void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState);
void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue);
uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype);
void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, FunctionalState NewState);
void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue);
uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype);
void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, FunctionalState NewState);
IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState);
void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir);
void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value);
uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_RTC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

142
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_sct.h vendored
View file

@ -1,142 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_sct.h 2011-06-02
*//**
* @file lpc18xx_sct.h
* @brief Contains all macro definitions and function prototypes
* support for SCT firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCT SCT (State Configurable Timer)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_SCT_H_
#define LPC18XX_SCT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for SCT configuration register
**********************************************************************/
/** Selects 16/32 bit counter */
#define SCT_CONFIG_16BIT_COUNTER 0x00000000
#define SCT_CONFIG_32BIT_COUNTER 0x00000001
/*********************************************************************//**
* Macro defines for SCT control register
**********************************************************************/
/** Stop low counter */
#define SCT_CTRL_STOP_L (1<<1)
/** Halt low counter */
#define SCT_CTRL_HALT_L (1<<2)
/** Clear low or unified counter */
#define SCT_CTRL_CLRCTR_L (1<<3)
/** Direction for low or unified counter */
#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
#define SCT_CTRL_BIDIR_L(x) (((x)&0x01)<<4)
/** Prescale clock for low or unified counter */
#define SCT_CTRL_PRE_L(x) (((x)&0xFF)<<5)
/** Stop high counter */
#define SCT_CTRL_STOP_H (1<<17)
/** Halt high counter */
#define SCT_CTRL_HALT_H (1<<18)
/** Clear high counter */
#define SCT_CTRL_CLRCTR_H (1<<19)
/** Direction for high counter */
#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
#define SCT_CTRL_BIDIR_H(x) (((x)&0x01)<<20)
/** Prescale clock for high counter */
#define SCT_CTRL_PRE_H(x) (((x)&0xFF)<<21)
/*********************************************************************//**
* Macro defines for SCT Conflict resolution register
**********************************************************************/
/** Define conflict solution */
#define SCT_RES_NOCHANGE (0)
#define SCT_RES_SET_OUTPUT (1)
#define SCT_RES_CLEAR_OUTPUT (2)
#define SCT_RES_TOGGLE_OUTPUT (3)
/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
/** Check SCT output number */
#define PARAM_SCT_OUTPUT_NUM(n) ((n)<= CONFIG_SCT_nOU )
/** Check SCT counter type */
#define PARAM_SCT_CONFIG_COUNTER_TYPE(n) ((n==SCT_CONFIG_16BIT_COUNTER)||(n==SCT_CONFIG_32BIT_COUNTER))
/** Check SCT conflict solution */
#define PARAM_SCT_RES(n) ((n==SCT_RES_NOCHANGE)||(n==SCT_RES_SET_OUTPUT)\
||(n==SCT_RES_CLEAR_OUTPUT)||(n==SCT_RES_TOGGLE_OUTPUT))
/** Check SCT event number */
#define PARAM_SCT_EVENT(n) ((n) <= 15)
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCT_Public_Functions SCT Public Functions
* @{
*/
void SCT_Config(uint32_t value);
void SCT_ControlSet(uint32_t value, FunctionalState ena);
void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value);
void SCT_EventFlagClear(uint8_t even_num);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_SCT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

101
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_scu.h vendored
View file

@ -1,101 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_scu.h 2011-06-02
*//**
* @file lpc18xx_scu.h
* @brief Contains all macro definitions and function prototypes
* support for SCU firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCU SCU (System Control Unit)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __SCU_H
#define __SCU_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/** Port offset definition */
#define PORT_OFFSET 0x80
/** Pin offset definition */
#define PIN_OFFSET 0x04
/* Pin modes */
#define MD_PUP (0x0<<3)
#define MD_BUK (0x1<<3)
#define MD_PLN (0x2<<3)
#define MD_PDN (0x3<<3)
#define MD_EHS (0x1<<5)
#define MD_EZI (0x1<<6)
#define MD_ZI (0x1<<7)
#define MD_EHD0 (0x1<<8)
#define MD_EHD1 (0x1<<8)
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
// 0xF0
/* Pin function */
#define FUNC0 0x0 /** Function 0 */
#define FUNC1 0x1 /** Function 1 */
#define FUNC2 0x2 /** Function 2 */
#define FUNC3 0x3 /** Function 3 */
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
/**
* @}
*/
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCU_Public_Functions SCU Public Functions
* @{
*/
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end __SCU_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

446
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_ssp.h vendored
View file

@ -1,446 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_ssp.h 2011-06-02
*//**
* @file lpc18xx_ssp.h
* @brief Contains all macro definitions and function prototypes
* support for SSP firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SSP SSP (Synchronous Serial Port)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_SSP_H_
#define LPC18XX_SSP_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup SSP_Private_Macros SSP Private Macros
* @{
*/
/*********************************************************************//**
* SSP configuration parameter defines
**********************************************************************/
/** Clock phase control bit */
#define SSP_CPHA_FIRST ((uint32_t)(0))
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI ((uint32_t)(0))
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE ((uint32_t)(0))
/** SSP data bit number defines */
#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
/** SSP Frame Format definition */
/** Motorola SPI mode */
#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
/** TI synchronous serial mode */
#define SSP_FRAME_TI SSP_CR0_FRF_TI
/** National Micro-wire mode */
#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
/*********************************************************************//**
* SSP Status defines
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
/** SSP status TX FIFO not full bit */
#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
/** SSP status RX FIFO not empty bit */
#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
/** SSP status RX FIFO full bit */
#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
/** SSP status SSP Busy bit */
#define SSP_STAT_BUSY SSP_SR_BSY
/*********************************************************************//**
* SSP Interrupt Configuration defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTCFG_ROR SSP_IMSC_ROR
/** Receive TimeOut */
#define SSP_INTCFG_RT SSP_IMSC_RT
/** Rx FIFO is at least half full */
#define SSP_INTCFG_RX SSP_IMSC_RX
/** Tx FIFO is at least half empty */
#define SSP_INTCFG_TX SSP_IMSC_TX
/*********************************************************************//**
* SSP Configured Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_ROR SSP_MIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RT SSP_MIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RX SSP_MIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_TX SSP_MIS_TX
/*********************************************************************//**
* SSP Raw Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
/*********************************************************************//**
* SSP Interrupt Clear defines
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_INTCLR_ROR SSP_ICR_ROR
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_INTCLR_RT SSP_ICR_RT
/*********************************************************************//**
* SSP DMA defines
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_TX SSP_DMA_RXDMA_EN
/** SSP bit for enabling TX DMA */
#define SSP_DMA_RX SSP_DMA_TXDMA_EN
/* SSP Status Implementation definitions */
#define SSP_STAT_DONE (1UL<<8) /**< Done */
#define SSP_STAT_ERROR (1UL<<9) /**< Error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for CR0 register
**********************************************************************/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
/*********************************************************************//**
* Macro defines for CR1 register
**********************************************************************/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro defines for DR register
**********************************************************************/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
/*********************************************************************//**
* Macro defines for SR register
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_SR_TFE ((uint32_t)(1<<0))
/** SSP status TX FIFO not full bit */
#define SSP_SR_TNF ((uint32_t)(1<<1))
/** SSP status RX FIFO not empty bit */
#define SSP_SR_RNE ((uint32_t)(1<<2))
/** SSP status RX FIFO full bit */
#define SSP_SR_RFF ((uint32_t)(1<<3))
/** SSP status SSP Busy bit */
#define SSP_SR_BSY ((uint32_t)(1<<4))
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t)(0x1F))
/*********************************************************************//**
* Macro defines for CPSR register
**********************************************************************/
/** SSP clock prescaler */
#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************//**
* Macro define for (IMSC) Interrupt Mask Set/Clear registers
**********************************************************************/
/** Receive Overrun */
#define SSP_IMSC_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_IMSC_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_IMSC_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_IMSC_TX ((uint32_t)(1<<3))
/** IMSC bit mask */
#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (RIS) Raw Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_RIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_RIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_RIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_RIS_TX ((uint32_t)(1<<3))
/** RIS bit mask */
#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (MIS) Masked Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_MIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_MIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_MIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_MIS_TX ((uint32_t)(1<<3))
/** MIS bit mask */
#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (ICR) Interrupt Clear registers
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_ICR_ROR ((uint32_t)(1<<0))
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_ICR_RT ((uint32_t)(1<<1))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t)(0x03))
/*********************************************************************//**
* Macro defines for DMACR register
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
/** SSP bit for enabling TX DMA */
#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
/** DMACR bit mask */
#define SSP_DMA_BITMASK ((uint32_t)(0x03))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid SSP port number */
#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
/** Macro check clock phase control mode */
#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
/** Macro check clock polarity mode */
#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
/* Macro check master/slave mode */
#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
/* Macro check databit value */
#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
|| (n==SSP_DATABIT_15))
/* Macro check frame type */
#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
|| (n==SSP_FRAME_MICROWIRE))
/* Macro check SSP status */
#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
|| (n==SSP_STAT_BUSY))
/* Macro check interrupt configuration */
#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
/* Macro check interrupt status value */
#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
/* Macro check interrupt status raw value */
#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
/* Macro check interrupt clear mode */
#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
/* Macro check DMA mode */
#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup SSP_Public_Types SSP Public Types
* @{
*/
/** @brief SSP configuration structure */
typedef struct {
uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
where x is in range from 4 - 16 */
uint32_t CPHA; /** Clock phase, should be:
- SSP_CPHA_FIRST: first clock edge
- SSP_CPHA_SECOND: second clock edge */
uint32_t CPOL; /** Clock polarity, should be:
- SSP_CPOL_HI: high level
- SSP_CPOL_LO: low level */
uint32_t Mode; /** SSP mode, should be:
- SSP_MASTER_MODE: Master mode
- SSP_SLAVE_MODE: Slave mode */
uint32_t FrameFormat; /** Frame Format:
- SSP_FRAME_SPI: Motorola SPI frame format
- SSP_FRAME_TI: TI frame format
- SSP_FRAME_MICROWIRE: National Microwire frame format */
uint32_t ClockRate; /** Clock rate,in Hz */
} SSP_CFG_Type;
/**
* @brief SSP Transfer Type definitions
*/
typedef enum {
SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
} SSP_TRANSFER_Type;
/**
* @brief SPI Data configuration structure definitions
*/
typedef struct {
void *tx_data; /**< Pointer to transmit data */
uint32_t tx_cnt; /**< Transmit counter */
void *rx_data; /**< Pointer to transmit data */
uint32_t rx_cnt; /**< Receive counter */
uint32_t length; /**< Length of transfer data */
uint32_t status; /**< Current status of SSP activity */
} SSP_DATA_SETUP_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SSP_Public_Functions SSP Public Functions
* @{
*/
void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
void SSP_DeInit(LPC_SSPn_Type* SSPx);
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);
uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);
int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
SSP_TRANSFER_Type xfType);
FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);
uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);
void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);
IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);
IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);
void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);
void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_SSP_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

352
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_timer.h vendored
View file

@ -1,352 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_timer.h 2011-06-02
*//**
* @file lpc18xx_timer.h
* @brief Contains all functions support for Timer firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup TIMER TIMER
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_TIMER_H_
#define __LPC18XX_TIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup TIMER_Private_Macros TIMER Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/**********************************************************************
** Interrupt information
**********************************************************************/
/** Macro to clean interrupt pending */
#define TIM_IR_CLR(n) _BIT(n)
/**********************************************************************
** Timer interrupt register definitions
**********************************************************************/
/** Macro for getting a timer match interrupt bit */
#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
/**********************************************************************
* Timer control register definitions
**********************************************************************/
/** Timer/counter enable bit */
#define TIM_ENABLE ((uint32_t)(1<<0))
/** Timer/counter reset bit */
#define TIM_RESET ((uint32_t)(1<<1))
/** Timer control bit mask */
#define TIM_TCR_MASKBIT ((uint32_t)(3))
/**********************************************************************
* Timer match control register definitions
**********************************************************************/
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
/** Timer Match control bit mask */
#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
/** Timer Match control bit mask for specific channel*/
#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer capture control register definitions
**********************************************************************/
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIM_CAP_RISING(n) (_BIT((n * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
/** Mask bit for rising and falling edge bit */
#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
/** Timer capture control bit mask */
#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
/** Timer Capture control bit mask for specific channel*/
#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer external match register definitions
**********************************************************************/
/** Bit location for output state change of MAT.n when external match
happens, n = 0 to 3 */
#define TIM_EM(n) _BIT(n)
/** Output state change of MAT.n when external match happens: no change */
#define TIM_EM_NOTHING ((uint8_t)(0x0))
/** Output state change of MAT.n when external match happens: low */
#define TIM_EM_LOW ((uint8_t)(0x1))
/** Output state change of MAT.n when external match happens: high */
#define TIM_EM_HIGH ((uint8_t)(0x2))
/** Output state change of MAT.n when external match happens: toggle */
#define TIM_EM_TOGGLE ((uint8_t)(0x3))
/** Macro for setting for the MAT.n change state bits */
#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
/** Mask for the MAT.n change state bits */
#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
/** Timer external match bit mask */
#define TIM_EMR_MASKBIT 0x0FFF
/**********************************************************************
* Timer Count Control Register definitions
**********************************************************************/
/** Mask to get the Counter/timer mode bits */
#define TIM_CTCR_MODE_MASK 0x3
/** Mask to get the count input select bits */
#define TIM_CTCR_INPUT_MASK 0xC
/** Timer Count control bit mask */
#define TIM_CTCR_MASKBIT 0xF
#define TIM_COUNTER_MODE ((uint8_t)(1))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to determine if it is valid TIMER peripheral */
#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIMER0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER1)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_TIMER2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER3)))
/* Macro check interrupt type */
#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\
||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\
||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)\
||(TYPE ==TIM_CR2_INT)||(TYPE ==TIM_CR3_INT))
/* Macro check TIMER mode */
#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\
|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))
/* Macro check TIMER prescale value */
#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))
/* Macro check TIMER counter intput mode */
#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)\
||(OPT == TIM_COUNTER_INCAP2)||(OPT == TIM_COUNTER_INCAP3))
/* Macro check TIMER external match mode */
#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\
||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))
/* Macro check TIMER external match mode */
#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \
||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup TIMER_Public_Types TIMER Public Types
* @{
*/
/***********************************************************************
* @brief Timer device enumeration
**********************************************************************/
/** @brief interrupt type */
typedef enum
{
TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
TIM_CR2_INT =6, /*!< interrupt for Capture channel 1*/
TIM_CR3_INT =7 /*!< interrupt for Capture channel 1*/
}TIM_INT_TYPE;
/** @brief Timer/counter operating mode */
typedef enum
{
TIM_TIMER_MODE = 0, /*!< Timer mode */
TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */
TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */
TIM_COUNTER_ANY_MODE /*!< Counter on both edges */
} TIM_MODE_OPT;
/** @brief Timer/Counter prescale option */
typedef enum
{
TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */
} TIM_PRESCALE_OPT;
/** @brief Counter input option */
typedef enum
{
TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */
TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */
TIM_COUNTER_INCAP2, /*!< CAPn.2 input pin for TIMERn */
TIM_COUNTER_INCAP3 /*!< CAPn.3 input pin for TIMERn */
} TIM_COUNTER_INPUT_OPT;
/** @brief Timer/Counter external match option */
typedef enum
{
TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */
TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */
TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */
TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */
}TIM_EXTMATCH_OPT;
/** @brief Timer/counter capture mode options */
typedef enum {
TIM_CAPTURE_NONE = 0, /*!< No Capture */
TIM_CAPTURE_RISING, /*!< Rising capture mode */
TIM_CAPTURE_FALLING, /*!< Falling capture mode */
TIM_CAPTURE_ANY /*!< On both edges */
} TIM_CAP_MODE_OPT;
/***********************************************************************
* @brief Timer structure definitions
**********************************************************************/
/** @brief Configuration structure in TIMER mode */
typedef struct
{
uint8_t PrescaleOption; /**< Timer Prescale option, should be:
- TIM_PRESCALE_TICKVAL: Prescale in absolute value
- TIM_PRESCALE_USVAL: Prescale in microsecond value
*/
uint8_t Reserved[3]; /**< Reserved */
uint32_t PrescaleValue; /**< Prescale value */
} TIM_TIMERCFG_Type;
/** @brief Configuration structure in COUNTER mode */
typedef struct {
uint8_t CounterOption; /**< Counter Option, should be:
- TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
- TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
*/
uint8_t CountInputSelect;
uint8_t Reserved[2];
} TIM_COUNTERCFG_Type;
/** @brief Match channel configuration structure */
typedef struct {
uint8_t MatchChannel; /**< Match channel, should be in range
from 0..3 */
uint8_t IntOnMatch; /**< Interrupt On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t StopOnMatch; /**< Stop On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ResetOnMatch; /**< Reset On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
- TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match
- TIM_EXTMATCH_LOW: Force external output pin to low if match
- TIM_EXTMATCH_HIGH: Force external output pin to high if match
- TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
*/
uint8_t Reserved[3]; /** Reserved */
uint32_t MatchValue; /** Match value */
} TIM_MATCHCFG_Type;
/** @brief Capture Input configuration structure */
typedef struct {
uint8_t CaptureChannel; /**< Capture channel, should be in range
from 0..1 */
uint8_t RisingEdge; /**< caption rising edge, should be:
- ENABLE: Enable rising edge.
- DISABLE: Disable this function.
*/
uint8_t FallingEdge; /**< caption falling edge, should be:
- ENABLE: Enable falling edge.
- DISABLE: Disable this function.
*/
uint8_t IntOnCaption; /**< Interrupt On caption, should be:
- ENABLE: Enable interrupt function.
- DISABLE: Disable this function.
*/
} TIM_CAPTURECFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup TIMER_Public_Functions TIMER Public Functions
* @{
*/
/* Init/DeInit TIM functions -----------*/
void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_DeInit(LPC_TIMERn_Type *TIMx);
/* TIM interrupt functions -------------*/
void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
/* TIM configuration functions --------*/
void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
void TIM_SetMatchExt(LPC_TIMERn_Type *TIMx,TIM_EXTMATCH_OPT ext_match );
void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState);
uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
void TIM_ResetCounter(LPC_TIMERn_Type *TIMx);
void TIM_Waitus(uint32_t time);
void TIM_Waitms(uint32_t time);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_TIMER_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

677
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_uart.h vendored
View file

@ -1,677 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_uart.h 2011-06-02
*//**
* @file lpc18xx_uart.h
* @brief Contains all macro definitions and function prototypes
* support for UART firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup UART UART
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC18XX_UART_H
#define __LPC18XX_UART_H
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup UART_Public_Macros UART Public Macros
* @{
*/
/** UART time-out definitions in case of using Read() and Write function
* with Blocking Flag mode
*/
#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
/* Accepted Error baud rate value (in percent unit) */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/*********************************************************************//**
* Macro defines for Macro defines for UART line control register
**********************************************************************/
#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 Modem Control Register
**********************************************************************/
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART line status register
**********************************************************************/
#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Modem (UART1 only) status register
**********************************************************************/
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART half duplex register
**********************************************************************/
#define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/
/*********************************************************************//**
* Macro defines for Macro defines for UART smart card interface control register
**********************************************************************/
#define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/
/*********************************************************************//**
* Macro defines for Macro defines for UART synchronous control register
**********************************************************************/
#define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/
#define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/
#define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/
/*********************************************************************//**
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
#define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
#define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
#define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */
#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS485 Control register
**********************************************************************/
#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
is disabled */
#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
(bit DCTRL = 1), pin DTR is used for direction control */
#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Address Match register
**********************************************************************/
#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Delay value register
**********************************************************************/
/* Macro defines for UART1 RS-485 Delay value register */
#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/** Macro to check the input UART_DATABIT parameters */
#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
/** Macro to check the input UART_STOPBIT parameters */
#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
/** Macro to check the input UART_PARITY parameters */
#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
|| (parity==UART_PARITY_SP_0))
/** Macro to check the input UART_FIFO parameters */
#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
|| (fifo==UART_FIFO_TRGLEV3))
/** Macro to check the input UART_INTCFG parameters */
#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
|| (IntCfg==UART_INTCFG_ABTO))
/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
/** Macro to check the input UART_AUTOBAUD_MODE parameters */
#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
(ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
/** Macro to check the input UART_IrDA_PULSEDIV parameters */
#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
/* Macro to check the input UART1_SignalState parameters */
#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
|| (x==UART1_MODEM_MODE_AUTO_CTS))
/** Macro to check the direction control pin type */
#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR))
/* Macro to determine if it is valid UART port number */
#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \
|| (((uint32_t *)x)==((uint32_t *)LPC_USART3)))
#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3))
#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
/** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */
#define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
/** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */
#define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/***********************************************************************
* @brief UART enumeration
**********************************************************************/
/**
* @brief UART Databit type definitions
*/
typedef enum {
UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
UART_DATABIT_6, /*!< UART 6 bit data mode */
UART_DATABIT_7, /*!< UART 7 bit data mode */
UART_DATABIT_8 /*!< UART 8 bit data mode */
} UART_DATABIT_Type;
/**
* @brief UART Stop bit type definitions
*/
typedef enum {
UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
UART_STOPBIT_2 /*!< UART Two Stop Bits Select */
} UART_STOPBIT_Type;
/**
* @brief UART Parity type definitions
*/
typedef enum {
UART_PARITY_NONE = 0, /*!< No parity */
UART_PARITY_ODD, /*!< Odd parity */
UART_PARITY_EVEN, /*!< Even parity */
UART_PARITY_SP_1, /*!< Forced "1" stick parity */
UART_PARITY_SP_0 /*!< Forced "0" stick parity */
} UART_PARITY_Type;
/**
* @brief FIFO Level type definitions
*/
typedef enum {
UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
} UART_FITO_LEVEL_Type;
/********************************************************************//**
* @brief UART Interrupt Type definitions
**********************************************************************/
typedef enum {
UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
UART_INTCFG_THRE, /*!< THR Interrupt enable*/
UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
} UART_INT_Type;
/**
* @brief UART Line Status Type definition
*/
typedef enum {
UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
} UART_LS_Type;
/**
* @brief UART Auto-baudrate mode type definition
*/
typedef enum {
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */
} UART_AB_MODE_Type;
/**
* @brief Auto Baudrate mode configuration type definition
*/
typedef struct {
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
FunctionalState AutoRestart; /**< Auto Restart state */
} UART_AB_CFG_Type;
/**
* @brief UART End of Auto-baudrate type definition
*/
typedef enum {
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
}UART_ABEO_Type;
/**
* UART IrDA Control type Definition
*/
typedef enum {
UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
} UART_IrDA_PULSE_Type;
/********************************************************************//**
* @brief UART1 Full modem - Signal states definition
**********************************************************************/
typedef enum {
INACTIVE = 0, /* In-active state */
ACTIVE = !INACTIVE /* Active state */
}UART1_SignalState;
/**
* @brief UART modem status type definition
*/
typedef enum {
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
} UART_MODEM_STAT_type;
/**
* @brief Modem output pin type definition
*/
typedef enum {
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
} UART_MODEM_PIN_Type;
/**
* @brief UART Modem mode type definition
*/
typedef enum {
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
} UART_MODEM_MODE_Type;
/**
* @brief UART Direction Control Pin type definition
*/
typedef enum {
UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
UART_RS485_DIRCTRL_DTR, /**< Pin DTR is used for direction control */
UART_RS485_DIRCTRL_DIR /**< Pin DIR is used for direction control */
} UART_RS485_DIRCTRL_PIN_Type;
/********************************************************************//**
* @brief UART Configuration Structure definition
**********************************************************************/
typedef struct {
uint32_t Baud_rate; /**< UART baud rate */
UART_PARITY_Type Parity; /**< Parity selection, should be:
- UART_PARITY_NONE: No parity
- UART_PARITY_ODD: Odd parity
- UART_PARITY_EVEN: Even parity
- UART_PARITY_SP_1: Forced "1" stick parity
- UART_PARITY_SP_0: Forced "0" stick parity
*/
UART_DATABIT_Type Databits; /**< Number of data bits, should be:
- UART_DATABIT_5: UART 5 bit data mode
- UART_DATABIT_6: UART 6 bit data mode
- UART_DATABIT_7: UART 7 bit data mode
- UART_DATABIT_8: UART 8 bit data mode
*/
UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
- UART_STOPBIT_1: UART 1 Stop Bits Select
- UART_STOPBIT_2: UART 2 Stop Bits Select
*/
} UART_CFG_Type;
/********************************************************************//**
* @brief UART FIFO Configuration Structure definition
**********************************************************************/
typedef struct {
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
- ENABLE: Reset Rx FIFO in UART
- DISABLE: Do not reset Rx FIFO in UART
*/
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
- ENABLE: Reset Tx FIFO in UART
- DISABLE: Do not reset Tx FIFO in UART
*/
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
- ENABLE: Enable DMA mode in UART
- DISABLE: Disable DMA mode in UART
*/
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
*/
} UART_FIFO_CFG_Type;
/********************************************************************//**
* @brief UART1 Full modem - RS485 Control configuration type
**********************************************************************/
typedef struct {
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
FunctionalState Rx_State; /*!< Receiver State:
- ENABLE: Enable Receiver.
- DISABLE: Disable Receiver. */
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
- ENABLE: ENABLE this function.
- DISABLE: Disable this function. */
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
- UART1_RS485_DIRCTRL_RTS:
pin RTS is used for direction control.
- UART1_RS485_DIRCTRL_DTR:
pin DTR is used for direction control. */
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
the RTS (or DTR) pin:
- RESET: The direction control pin will be driven
to logic "0" when the transmitter has data to be sent.
- SET: The direction control pin will be driven
to logic "1" when the transmitter has data to be sent. */
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
} UART_RS485_CTRLCFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup UART_Public_Functions UART Public Functions
* @{
*/
/* UART Init/DeInit functions --------------------------------------------------*/
void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct);
void UART_DeInit(LPC_USARTn_Type* UARTx);
void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
/* UART Send/Receive functions -------------------------------------------------*/
void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data);
uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx);
uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \
uint32_t buflen, TRANSFER_BLOCK_Type flag);
/* UART FIFO functions ----------------------------------------------------------*/
void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
/* UART operate functions -------------------------------------------------------*/
void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, \
FunctionalState NewState);
void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
FunctionalState NewState);
void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx);
FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx);
void UART_ForceBreak(LPC_USARTn_Type* UARTx);
/* UART1 FullModem functions ----------------------------------------------------*/
void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \
UART1_SignalState NewState);
void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \
FunctionalState NewState);
uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx);
/* UART RS485 functions ----------------------------------------------------------*/
void UART_RS485Config(LPC_USARTn_Type *UARTx, \
UART_RS485_CTRLCFG_Type *RS485ConfigStruct);
void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr);
uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size);
/* UART IrDA functions-------------------------------------------------------------*/
void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC18XX_UART_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

10
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_utils.h vendored
View file

@ -1,10 +0,0 @@
#ifndef _LPC18XX_UTILS_H
#define _LPC18XX_UTILS_H
#include "lpc_types.h"
extern uint32_t msec;
extern volatile uint32_t u32Milliseconds;
void SysTick_Handler (void);
int timer_delay_us( int cnt);
int timer_delay_ms( int cnt);
#endif

177
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_wwdt.h vendored
View file

@ -1,177 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_wwdt.h 2011-06-02
*//**
* @file lpc18xx_wwdt.h
* @brief Contains all macro definitions and function prototypes
* support for WWDT firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup WWDT WWDT (Windowed WatchDog Timer)
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC18XX_WWDT_H_
#define LPC18XX_WWDT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup WWDT_Public_Macros WWDT Public Macros
* @{
*/
/** WDT oscillator frequency value */
#define WDT_OSC (12000000UL) /* WWDT uses IRC clock */
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup WWDT_Private_Macros WWDT Private Macros
* @{
*/
// time is calculated by usec
#define WDT_GET_FROM_USEC(time) ((time*10)/((WWDT_US_INDEX *10 * 4)/WDT_OSC))
#define WDT_GET_USEC(counter) ((counter * ((WWDT_US_INDEX *10 * 4)/WDT_OSC))/10)
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t)(1<<0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t)(1<<1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t)(1<<2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t)(1<<3))
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t)(1<<4))
/** Define divider index for microsecond ( us ) */
#define WWDT_US_INDEX ((uint32_t)(1000000))
/** WWDT Time out minimum value */
#define WWDT_TIMEOUT_MIN ((uint32_t)(0xFF))
/** WWDT Time out maximum value */
#define WWDT_TIMEOUT_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT Warning minimum value */
#define WWDT_WARNINT_MIN ((uint32_t)(0xFF))
/** WWDT Warning maximum value */
#define WWDT_WARNINT_MAX ((uint32_t)(0x000003FF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MIN ((uint32_t)(0xFF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT timer constant register mask */
#define WWDT_WDTC_MASK ((uint32_t)(0x00FFFFFF))
/** WWDT warning value register mask */
#define WWDT_WDWARNINT_MASK ((uint32_t)(0x000003FF))
/** WWDT feed sequence register mask */
#define WWDT_WDFEED_MASK ((uint32_t)(0x000000FF))
/** WWDT flag */
#define WWDT_WARNINT_FLAG ((uint8_t)(0))
#define WWDT_TIMEOUT_FLAG ((uint8_t)(1))
/** WWDT mode definitions */
#define WWDT_PROTECT_MODE ((uint8_t)(0))
#define WWDT_RESET_MODE ((uint8_t)(1))
/* WWDT Timer value definition (us) */
#define WWDT_TIMEOUT_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds
#define WWDT_TIMEOUT_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))
#define WWDT_TIMEWARN_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))
#define WWDT_TIMEWARN_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))
#define WWDT_TIMEWINDOWED_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))
#define WWDT_TIMEWINDOWED_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup WWDT_Public_Types WWDT Public Types
* @{
*/
/********************************************************************//**
* @brief WWDT structure definitions
**********************************************************************/
typedef struct Wdt_Config
{
uint8_t wdtReset; /**< if ENABLE -> the Reset bit is enabled */
uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */
uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT (us) */
uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt (us) */
uint32_t wdtWindowVal; /**< Set a window vaule for WDT (us) */
}st_Wdt_Config;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup WWDT_Public_Functions WWDT Public Functions
* @{
*/
void WWDT_Init(void);
void WWDT_UpdateTimeOut(uint32_t TimeOut);
void WWDT_Feed (void);
void WWDT_SetWarning(uint32_t WarnTime);
void WWDT_SetWindow(uint32_t WindowedTime);
void WWDT_Configure(st_Wdt_Config wdtCfg);
void WWDT_Start(void);
FlagStatus WWDT_GetStatus (uint8_t Status);
void WWDT_ClearStatusFlag (uint8_t flag);
uint32_t WWDT_GetCurrentCount(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC18XX_WWDT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

211
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc_types.h vendored
View file

@ -1,211 +0,0 @@
/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Type group ----------------------------------------------------------- */
/** @defgroup LPC_Types LPC_Types
* @ingroup LPC1800CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC_TYPES_H
#define LPC_TYPES_H
/* Includes ------------------------------------------------------------------- */
#include <stdint.h>
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t(*PFI)();
/**
* @}
*/
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1<<(n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f,v) ((v)<<(f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void*) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility ------------------------------------------ */
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/** SMA type for character type */
typedef char CHAR;
/** SMA type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** SMA type for 8 bit signed value */
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;
/** SMA type for 64 bit unsigned value */
typedef uint64_t UNS_64;
/** 32 bit boolean type */
typedef Bool BOOL_32;
/** 16 bit boolean type */
typedef Bool BOOL_16;
/** 8 bit boolean type */
typedef Bool BOOL_8;
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
#endif /* LPC_TYPES_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

248
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/spifi_rom_api.h vendored
View file

@ -1,248 +0,0 @@
/***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef SPIFI_ROM_API_H
#define SPIFI_ROM_API_H
#include <stdint.h>
/* define the symbol TESTING in the environment if test output desired */
/* maintain LONGEST_PROT >= the length (in bytes) of the largest
protection block of any serial flash that this driver handles */
#define LONGEST_PROT 68
typedef uint8_t uc;
#ifndef NULL
#define NULL ((void *)0)
#endif
/* protection/sector descriptors */
typedef struct {
uint32_t base;
uc flags;
int8_t log2;
uint16_t rept;
} protEnt;
/* bits in the flags byte */
enum {RWPROT=1};
/* overall data structure includes # sectors, length of protection reg,
array of descriptors
typedef struct {
uint16_t sectors;
uint16_t protBytes;
protEnt *entries;
} protDesc; */
typedef union {
uint16_t hw;
uc byte[2];
}stat_t;
/* the object that init returns, and other routines use as an operand */
typedef struct {
uint32_t base, regbase, devSize, memSize;
uc mfger, devType, devID, busy;
stat_t stat;
uint16_t reserved;
uint16_t set_prot, write_prot;
uint32_t mem_cmd, prog_cmd;
uint16_t sectors, protBytes;
uint32_t opts, errCheck;
uc erase_shifts[4], erase_ops[4];
protEnt *protEnts;
char prot[LONGEST_PROT];
} SPIFIobj;
/* operands of program and erase */
typedef struct {
char *dest;
uint32_t length;
char *scratch;
int32_t protect;
uint32_t options;
} SPIFIopers;
/* instruction classes for wait_busy */
typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
/* bits in options operands (MODE3, RCVCLK, and FULLCLK
have the same relationship as in the Control register) */
#define S_MODE3 1
#define S_MODE0 0
#define S_MINIMAL 2
#define S_MAXIMAL 0
#define S_FORCE_ERASE 4
#define S_ERASE_NOT_REQD 8
#define S_CALLER_ERASE 8
#define S_ERASE_AS_REQD 0
#define S_VERIFY_PROG 0x10
#define S_VERIFY_ERASE 0x20
#define S_NO_VERIFY 0
#define S_RCVCLK 0x80
#define S_INTCLK 0
#define S_FULLCLK 0x40
#define S_HALFCLK 0
#define S_DUAL 0x100
#define S_CALLER_PROT 0x200
#define S_DRIVER_PROT 0
/* the following values in the first post-address memory command byte work
for all known quad devices that support "no opcode" operation */
#define NO_OPCODE_FOLLOWS 0xA5
#define OPCODE_FOLLOWS 0xFF
/* basic SPI commands for serial flash */
#define BASE_READ_CMD (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
#define BASE_PROG_CMD (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
/* the length of a standard program command is 256 on all devices */
#define PROG_SIZE 256
/* options in obj->opts (mostly for setMulti) */
/* used by Winbond: send 0xA3 command so hardware can read faster */
#define OPT_SEND_A3 1
/* used by SST: send 0x38 command to enable quad and allow full command set */
#define OPT_SEND_38 2
/* used by Winbond and others: read status reg 2, check it,
if necessary write it back with Quad Enable set */
#define OPT_35_OR02_01 4
/* used by Atmel: read Configuration register, if necessary set Quad Enable */
#define OPT_3F_OR80_3E 8
/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
#define OPT_65_CLR_C0_61 0x10
/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
to set # dummy bytes and allow XIP mode */
#define OPT_81 0x20
/* set for devices without full device erase command (Numonyx type 0x40) */
#define OPT_NO_DEV_ERASE 0x40
/* used by Macronix: status reg 2 includes selection between write-protect
in status reg and command-based */
#define OPT_WPSEL 0x80
/* set when protection data has been read into the SPIFI object */
#define OPT_PROT_READ 0x100
/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
#define OPT_4BAD 0x200
/* set if setMulti should set the Dual bit in Control reg */
#define OPT_DUAL 0x400
/* send "# dummy bits" in C0 command to Winbond */
#define OPT_C0 0x800
/* set QE for Chingis */
#define OPT_05_OR40_01 0x1000
/* write status does not go busy */
#define OPT_01_NO_BUSY 0x2000
/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */
#define OPT_PROT_STAT 0x4000
#define OPT_PROT_REG 0x8000
#define OPT_PROT_CMD3 0x10000
#define OPT_PROT_CMDE 0x20000
#define OPT_PROT_MASK 0x3C000
#define OPT_ALL_QUAD 0x40000
#ifndef OMIT_ROM_TABLE
/* interface to ROM API */
typedef struct {
int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options,
uint32_t mhz);
int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers);
/* mode switching */
void (*cancel_mem_mode)(SPIFIobj *obj);
void (*set_mem_mode) (SPIFIobj *obj);
/* mid level functions */
int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers);
int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change,
char *saveProt);
int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t check_program);
int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr);
uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length);
int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t *left_in_page);
uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length);
/* low level functions */
void(*setSize) (SPIFIobj *obj, int32_t value);
int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
uint32_t prog_cmd);
uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len);
uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value);
void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value);
int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase);
} SPIFI_RTNS;
#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
#endif /* OMIT_ROM_TABLE */
#ifdef USE_SPIFI_LIB
extern SPIFI_RTNS spifi_table;
#endif /* USE_SPIFI_LIB */
/* example of using this interface:
#include "spifi_rom_api.h"
#define CSHIGH 4
#define SPIFI_MHZ 80
#define source_data_ad (char *)1234
int32_t rc;
SPIFIopers opers;
define_spifi_romPtr(spifi);
SPIFIobj *obj = malloc(sizeof(SPIFIobj));
if (!obj) { can't allocate memory }
rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
if (rc) { investigate init error rc }
printf ("the serial flash contains %d bytes\n", obj->devSize);
opers.dest = where_to_program;
opers.length = how_many_bytes;
opers.scratch = NULL; // unprogrammed data is not saved/restored
opers.protect = -1; // save & restore protection
opers.options = S_VERIFY_PROG;
rc = spifi->spifi_program (obj, source_data_ad, &opers);
if (rc) { investigate program error rc }
*/
/* these are for normal users, including boot code */
int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
/* these are used by the manufacturer-specific init functions */
void setSize (SPIFIobj *obj, int32_t value);
int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
uint32_t read04(SPIFIobj *obj, uc op, uc len);
int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
/* needs to be defined for each platform */
void pullMISO(int high);
#ifdef TESTING
/* used by testing code */
unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
/* predeclare a debug routine */
void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
#endif
#endif /* SPIFI_ROM_API_H */

50
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/system_LPC18xx.h vendored
View file

@ -1,50 +0,0 @@
/**********************************************************************
* $Id$ system_LPC18xx.h 2011-06-02
*//**
* @file system_LPC18xx.h
* @brief Cortex-M3 Device System Header File for NXP LPC18xx Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_LPC18xx_H
#define __SYSTEM_LPC18xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC18xx_H */

326
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c vendored
View file

@ -1,326 +0,0 @@
/**********************************************************************
* $Id$ debug_frmwrk.c 2011-06-02
*//**
* @file debug_frmwrk.c
* @brief Contains some utilities that used for debugging through UART
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup DEBUG_FRMWRK
* @{
*/
#ifndef _DEBUG_FRMWRK_
#define _DEBUG_FRMWRK_
/* Includes ------------------------------------------------------------------- */
#include "debug_frmwrk.h"
#include "lpc18xx_scu.h"
#include <stdarg.h>
#include <stdio.h>
#ifdef CDC_DEBUG_MESSEGES
#include "usbhw.h"
#include "cdcuser.h"
#include "CDCdemo.h"
#include "lpc18xx_utils.h"
#include <string.h>
#endif
/* Debug framework */
void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);
void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);
void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);
void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);
void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);
void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);
void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);
void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);
void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);
uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);
/*********************************************************************//**
* @brief Puts a character to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] ch Character to put
* @return None
**********************************************************************/
void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch)
{
UART_Send(UARTx, &ch, 1, BLOCKING);
}
/*********************************************************************//**
* @brief Get a character to UART port
* @param[in] UARTx Pointer to UART peripheral
* @return character value that returned
**********************************************************************/
uint8_t UARTGetChar (LPC_USARTn_Type *UARTx)
{
uint8_t tmp = 0;
UART_Receive(UARTx, &tmp, 1, BLOCKING);
return(tmp);
}
/*********************************************************************//**
* @brief Puts a string to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] str string to put
* @return None
**********************************************************************/
void UARTPuts(LPC_USARTn_Type *UARTx, const void *str)
{
#ifdef CDC_DEBUG_MESSEGES
int num_of_bytes=0;
num_of_bytes = strlen(str);
timer_delay_us(num_of_bytes);
USB_WriteEP (CDC_DEP_IN, (unsigned char *)str, num_of_bytes);
#else
uint8_t *s = (uint8_t *) str;
while (*s)
{
UARTPutChar(UARTx, *s++);
}
#endif
}
/*********************************************************************//**
* @brief Puts a string to UART port and print new line
* @param[in] UARTx Pointer to UART peripheral
* @param[in] str String to put
* @return None
**********************************************************************/
void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str)
{
UARTPuts (UARTx, str);
UARTPuts (UARTx, "\n\r");
}
/*********************************************************************//**
* @brief Puts a decimal number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] decnum Decimal number (8-bit long)
* @return None
**********************************************************************/
void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum)
{
uint8_t c1=decnum%10;
uint8_t c2=(decnum/10)%10;
uint8_t c3=(decnum/100)%10;
UARTPutChar(UARTx, '0'+c3);
UARTPutChar(UARTx, '0'+c2);
UARTPutChar(UARTx, '0'+c1);
}
/*********************************************************************//**
* @brief Puts a decimal number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] decnum Decimal number (8-bit long)
* @return None
**********************************************************************/
void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum)
{
uint8_t c1=decnum%10;
uint8_t c2=(decnum/10)%10;
uint8_t c3=(decnum/100)%10;
uint8_t c4=(decnum/1000)%10;
uint8_t c5=(decnum/10000)%10;
UARTPutChar(UARTx, '0'+c5);
UARTPutChar(UARTx, '0'+c4);
UARTPutChar(UARTx, '0'+c3);
UARTPutChar(UARTx, '0'+c2);
UARTPutChar(UARTx, '0'+c1);
}
/*********************************************************************//**
* @brief Puts a decimal number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] decnum Decimal number (8-bit long)
* @return None
**********************************************************************/
void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum)
{
uint8_t c1=decnum%10;
uint8_t c2=(decnum/10)%10;
uint8_t c3=(decnum/100)%10;
uint8_t c4=(decnum/1000)%10;
uint8_t c5=(decnum/10000)%10;
uint8_t c6=(decnum/100000)%10;
uint8_t c7=(decnum/1000000)%10;
uint8_t c8=(decnum/10000000)%10;
uint8_t c9=(decnum/100000000)%10;
uint8_t c10=(decnum/1000000000)%10;
UARTPutChar(UARTx, '0'+c10);
UARTPutChar(UARTx, '0'+c9);
UARTPutChar(UARTx, '0'+c8);
UARTPutChar(UARTx, '0'+c7);
UARTPutChar(UARTx, '0'+c6);
UARTPutChar(UARTx, '0'+c5);
UARTPutChar(UARTx, '0'+c4);
UARTPutChar(UARTx, '0'+c3);
UARTPutChar(UARTx, '0'+c2);
UARTPutChar(UARTx, '0'+c1);
}
/*********************************************************************//**
* @brief Puts a hex number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] hexnum Hex number (8-bit long)
* @return None
**********************************************************************/
void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum)
{
uint8_t nibble, i;
UARTPuts(UARTx, "0x");
i = 1;
do {
nibble = (hexnum >> (4*i)) & 0x0F;
UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
} while (i--);
}
/*********************************************************************//**
* @brief Puts a hex number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] hexnum Hex number (16-bit long)
* @return None
**********************************************************************/
void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum)
{
uint8_t nibble, i;
UARTPuts(UARTx, "0x");
i = 3;
do {
nibble = (hexnum >> (4*i)) & 0x0F;
UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
} while (i--);
}
/*********************************************************************//**
* @brief Puts a hex number to UART port
* @param[in] UARTx Pointer to UART peripheral
* @param[in] hexnum Hex number (32-bit long)
* @return None
**********************************************************************/
void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum)
{
uint8_t nibble, i;
UARTPuts(UARTx, "0x");
i = 7;
do {
nibble = (hexnum >> (4*i)) & 0x0F;
UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
} while (i--);
}
/*********************************************************************//**
* @brief print function that supports format as same as printf()
* function of <stdio.h> library
* @param[in] format formated string to be print
* @return None
**********************************************************************/
void lpc_printf (const char *format, ...)
{
char buffer[512 + 1];
va_list vArgs;
va_start(vArgs, format);
vsprintf((char *)buffer, (char const *)format, vArgs);
va_end(vArgs);
_DBG(buffer);
}
/*********************************************************************//**
* @brief Initialize Debug frame work through initializing UART port
* @param[in] None
* @return None
**********************************************************************/
void debug_frmwrk_init(void)
{
#ifdef UART_DEBUG_MESSEGES
UART_CFG_Type UARTConfigStruct;
#if (USED_UART_DEBUG_PORT==0)
/*
* Initialize UART0 pin connect NGX board
*/
scu_pinmux(0xF ,10 , MD_PDN|MD_EZI, FUNC1); // P6.4 UART0_TXD
scu_pinmux(0xF ,11 , MD_PDN|MD_EZI, FUNC1); // P6.5 UART0_RXD
#elif (USED_UART_DEBUG_PORT==1)
/*
* Initialize UART1 pin connect
*/
scu_pinmux(0x1 ,13 , MD_PDN, FUNC1); // PC.13 : UART1_TXD
scu_pinmux(0x1 ,14 , MD_PLN|MD_EZI|MD_ZI, FUNC1); // PC.14 : UART1_RXD
#endif
/* Initialize UART Configuration parameter structure to default state:
* Baudrate = 9600bps
* 8 data bit
* 1 Stop bit
* None parity
*/
UART_ConfigStructInit(&UARTConfigStruct);
// Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter
UART_Init((LPC_USARTn_Type*)DEBUG_UART_PORT, &UARTConfigStruct);
// Enable UART Transmit
UART_TxCmd((LPC_USARTn_Type*)DEBUG_UART_PORT, ENABLE);
#endif
#ifdef CDC_DEBUG_MESSEGES
CDC_init(); //wait for usb enumeration
#endif
_db_msg = UARTPuts;
_db_msg_ = UARTPuts_;
_db_char = UARTPutChar;
_db_hex = UARTPutHex;
_db_hex_16 = UARTPutHex16;
_db_hex_32 = UARTPutHex32;
_db_dec = UARTPutDec;
_db_dec_16 = UARTPutDec16;
_db_dec_32 = UARTPutDec32;
_db_get_char = UARTGetChar;
}
#endif /* _DEBUG_FRMWRK_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

353
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c vendored
View file

@ -1,353 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_adc.c 2011-06-02
*//**
* @file lpc18xx_adc.c
* @brief Contains all functions support for ADC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup ADC
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_adc.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _ADC
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup ADC_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial for ADC
* + Set bit PCADC
* + Set clock for ADC
* + Set Clock Frequency
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] rate ADC conversion rate, should be <=200KHz
* @param[in] bits_accuracy number of bits accuracy, should be <=10 bits and >=3bits
* @return None
**********************************************************************/
void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy)
{
uint32_t temp, tmpreg, ADCbitrate;
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_RATE(rate));
// Turn on power and clock
//CGU_ConfigPPWR (CGU_PCONP_PCAD, ENABLE);
ADCx->CR = 0;
//Enable PDN bit
tmpreg = ADC_CR_PDN;
// Set clock frequency
if(ADCx == LPC_ADC0)
temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC0);
else if(ADCx == LPC_ADC1)
temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC1);
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
* A/D converter, which should be less than or equal to 13MHz.
* A fully conversion requires (bits_accuracy+1) of these clocks.
* ADC clock = PCLK_ADC0 / (CLKDIV + 1);
* ADC rate = ADC clock / (bits_accuracy+1);
*/
ADCbitrate = (rate * (bits_accuracy+1));
temp = ((temp*2 + ADCbitrate) / (ADCbitrate*2)) - 1;//get the round value by fomular: (2*A + B)/(2*B)
tmpreg |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(10 - bits_accuracy);
ADCx->CR = tmpreg;
}
/*********************************************************************//**
* @brief Close ADC
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @return None
**********************************************************************/
void ADC_DeInit(LPC_ADCn_Type *ADCx)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
// Clear PDN bit
ADCx->CR &= ~ADC_CR_PDN;
// Turn on power and clock
//CGU_ConfigPPWR (CGU_PCONP_PCAD, DISABLE);
}
///*********************************************************************//**
//* @brief Get Result conversion from A/D data register
//* @param[in] channel number which want to read back the result
//* @return Result of conversion
//*********************************************************************/
//uint32_t ADC_GetData(uint32_t channel)
//{
// uint32_t adc_value;
//
// CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
//
// adc_value = *(uint32_t *)((&LPC_ADC->DR0) + channel);
// return ADC_GDR_RESULT(adc_value);
//}
/*********************************************************************//**
* @brief Set start mode for ADC
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] start_mode Start mode choose one of modes in
* 'ADC_START_OPT' enumeration type definition, should be:
* - ADC_START_CONTINUOUS
* - ADC_START_NOW
* - ADC_START_ON_EINT0
* - ADC_START_ON_CAP01
* - ADC_START_ON_MAT01
* - ADC_START_ON_MAT03
* - ADC_START_ON_MAT10
* - ADC_START_ON_MAT11
* @return None
*********************************************************************/
void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_START_OPT(start_mode));
ADCx->CR &= ~ADC_CR_START_MASK;
ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode);
}
/*********************************************************************//**
* @brief ADC Burst mode setting
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] NewState
* - 1: Set Burst mode
* - 0: reset Burst mode
* @return None
**********************************************************************/
void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
ADCx->CR &= ~ADC_CR_BURST;
if (NewState){
ADCx->CR |= ADC_CR_BURST;
}
}
/*********************************************************************//**
* @brief Set AD conversion in power mode
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] NewState
* - 1: AD converter is optional
* - 0: AD Converter is in power down mode
* @return None
**********************************************************************/
void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
ADCx->CR &= ~ADC_CR_PDN;
if (NewState){
ADCx->CR |= ADC_CR_PDN;
}
}
/*********************************************************************//**
* @brief Set Edge start configuration
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING
* - 0: ADC_START_ON_RISING
* - 1: ADC_START_ON_FALLING
* @return None
**********************************************************************/
void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_START_ON_EDGE_OPT(EdgeOption));
ADCx->CR &= ~ADC_CR_EDGE;
if (EdgeOption){
ADCx->CR |= ADC_CR_EDGE;
}
}
/*********************************************************************//**
* @brief ADC interrupt configuration
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] IntType: type of interrupt, should be:
* - ADC_ADINTEN0: Interrupt channel 0
* - ADC_ADINTEN1: Interrupt channel 1
* ...
* - ADC_ADINTEN7: Interrupt channel 7
* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt
* @param[in] NewState:
* - SET : enable ADC interrupt
* - RESET: disable ADC interrupt
* @return None
**********************************************************************/
void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_TYPE_INT_OPT(IntType));
ADCx->INTEN &= ~ADC_INTEN_CH(IntType);
if (NewState){
ADCx->INTEN |= ADC_INTEN_CH(IntType);
}
}
/*********************************************************************//**
* @brief Enable/Disable ADC channel number
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] Channel channel number
* @param[in] NewState New state, should be:
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(Channel));
if (NewState == ENABLE) {
ADCx->CR |= ADC_CR_CH_SEL(Channel);
} else {
ADCx->CR &= ~ADC_CR_CH_SEL(Channel);
}
}
/*********************************************************************//**
* @brief Get ADC result
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] channel channel number, should be 0...7
* @return Converted data
**********************************************************************/
uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel)
{
uint32_t adc_value;
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
adc_value = *(uint32_t *) ((&(ADCx->DR[0])) + channel);
return ADC_DR_RESULT(adc_value);
}
/*********************************************************************//**
* @brief Get ADC Channel status from ADC data register
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] channel: channel number, should be 0..7
* @param[in] StatusType
* - 0: Burst status
* - 1: Done status
* @return Channel status, could be:
* - SET
* - RESET
**********************************************************************/
FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType)
{
uint32_t temp;
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));
temp = *(uint32_t *) ((&ADCx->DR[0]) + channel);
if (StatusType) {
temp &= ADC_DR_DONE_FLAG;
}else{
temp &= ADC_DR_OVERRUN_FLAG;
}
if (temp) {
return SET;
} else {
return RESET;
}
}
/*********************************************************************//**
* @brief Get ADC Data from AD Global register
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @return Result of conversion
**********************************************************************/
uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx)
{
CHECK_PARAM(PARAM_ADCx(ADCx));
return ((uint32_t)(ADCx->GDR));
}
/*********************************************************************//**
* @brief Get ADC Chanel status from AD global data register
* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC
* @param[in] StatusType
* - 0: Burst status
* - 1: Done status
* @return SET / RESET
**********************************************************************/
FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType)
{
uint32_t temp;
CHECK_PARAM(PARAM_ADCx(ADCx));
CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));
temp = ADCx->GDR;
if (StatusType){
temp &= ADC_DR_DONE_FLAG;
}else{
temp &= ADC_DR_OVERRUN_FLAG;
}
if (temp){
return SET;
}else{
return RESET;
}
}
/**
* @}
*/
#endif /* _ADC */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

170
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c vendored
View file

@ -1,170 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_atimer.c 2011-06-02
*//**
* @file lpc18xx_atimer.c
* @brief Contains all functions support for Alarm Timer firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup ATIMER
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_atimer.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _ATIMER
/* Private Functions ---------------------------------------------------------- */
/*********************************************************************//**
* @brief Initial Alarm Timer device
* @param[in] ATIMERx Timer selection, should be: LPC_ATIMER
* @param[in] PresetValue Count of 1/1024s for Alarm
* @return None
**********************************************************************/
void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
//set power
if (ATIMERx== LPC_ATIMER)
{
/*Set Clock Here */
CGU_EnableEntity(CGU_CLKSRC_32KHZ_OSC, ENABLE);
}
ATIMER_UpdatePresetValue(ATIMERx, PresetValue);
// Clear interrupt pending
ATIMER_ClearIntStatus(ATIMERx);
}
/*********************************************************************//**
* @brief Close ATIMER device
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @return None
**********************************************************************/
void ATIMER_DeInit (LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
// Disable atimer
ATIMER_ClearIntStatus(ATIMERx);
ATIMER_IntDisable(ATIMERx);
// Disable power
// if (ATIMERx== LPC_ATIMER0)
// CGU_ConfigPPWR (CGU_PCONP_PCATIMER0, DISABLE);
}
/*********************************************************************//**
* @brief Clear ATIMER Interrupt Status
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @return None
**********************************************************************/
void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
ATIMERx->CLR_STAT = 1;
while((ATIMERx->STATUS & 1) == 1);
}
/*********************************************************************//**
* @brief Set ATIMER Interrupt Status
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @return None
**********************************************************************/
void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
ATIMERx->SET_STAT = 1;
while((ATIMERx->STATUS & 1) == 0);
}
/*********************************************************************//**
* @brief Enable ATIMER Interrupt
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @return None
**********************************************************************/
void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
ATIMERx->SET_EN = 1;
while((ATIMERx->ENABLE & 1) == 0);
}
/*********************************************************************//**
* @brief Disable ATIMER Interrupt
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @return None
**********************************************************************/
void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
ATIMERx->CLR_EN = 1;
while((ATIMERx->ENABLE & 1) == 1);
}
/*********************************************************************//**
* @brief Update Preset value
* @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER
* @param[in] PresetValue updated preset value
* @return None
**********************************************************************/
void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
ATIMERx->PRESET = PresetValue;
}
/*********************************************************************//**
* @brief Read value of preset register
* @param[in] ATIMERx Pointer to timer/counter device, should be: LPC_ATIMER
* @return Value of capture register
**********************************************************************/
uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx)
{
CHECK_PARAM(PARAM_ATIMERx(ATIMERx));
return ATIMERx->PRESET;
}
/**
* @}
*/
#endif /* _ATIMER */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

561
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c vendored
View file

@ -1,561 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_can.c 2011-06-02
*//**
* @file lpc18xx_can.c
* @brief Contains all functions support for C CAN firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup C_CAN
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc18xx_can.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _C_CAN
/* Private Macros ---------------------------------------------------------- */
#ifndef __GNUC__
/* Macro for reading and writing to CCAN IF registers */
#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->##IFsel##_##reg)
#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->##IFsel##_##reg=val)
/* Macro for writing IF to specific RAM message object */
#define CAN_IF_readBuf(IFsel,msg) \
LPC_C_CAN0->##IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \
while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );
/* Macro for reading specific RAM message object to IF */
#define CAN_IF_writeBuf(IFsel,msg) \
LPC_C_CAN0->##IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \
while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );
#else
#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->IFsel##_##reg)
#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->IFsel ## _ ## reg = val)
/* Macro for writing IF to specific RAM message object */
#define CAN_IF_readBuf(IFsel,msg) \
LPC_C_CAN0->IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
LPC_C_CAN0->IFsel##_##CMDREQ=msg; \
while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );
/* Macro for reading specific RAM message object to IF */
#define CAN_IF_writeBuf(IFsel,msg) \
LPC_C_CAN0->IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \
LPC_C_CAN0->IFsel##_##CMDREQ=msg; \
while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );
#endif
#define IF1 0
#define IF2 1
#define CAN_STATUS_INTERRUPT 0x8000 /* 0x0001-0x0020 are the # of the message
object */
/* 0x8000 is the status interrupt */
/* CAN Message interface register definitions */
/* bit field of IF command request n register */
#define IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when
RD/WR done */
/* CAN CTRL register */
#define CTRL_INIT (1 << 0)
#define CTRL_IE (1 << 1)
#define CTRL_SIE (1 << 2)
#define CTRL_EIE (1 << 3)
#define CTRL_DAR (1 << 5)
#define CTRL_CCE (1 << 6)
#define CTRL_TEST (1 << 7)
/* CAN Test register */
#define TEST_BASIC (1 << 2)
#define TEST_SILENT (1 << 3)
#define TEST_LBACK (1 << 4)
/* CAN Status register */
#define STAT_LEC (0x7 << 0)
#define STAT_TXOK (1 << 3)
#define STAT_RXOK (1 << 4)
#define STAT_EPASS (1 << 5)
#define STAT_EWARN (1 << 6)
#define STAT_BOFF (1 << 7)
#define NO_ERR 0 // No Error
#define STUFF_ERR 1 // Stuff Error : More than 5 equal bits in a sequence have occurred in a part
// of a received message where this is not allowed.
#define FORM_ERR 2 // Form Error : A fixed format part of a received frame has the wrong format.
#define ACK_ERR 3 // AckError : The message this CAN Core transmitted was not acknowledged
// by another node.
#define BIT1_ERR 4 // Bit1Error : During the transmission of a message (with the exception of
// the arbitration field), the device wanted to send a recessive level (bit of
// logical value <20>1<EFBFBD>), but the monitored bus value was dominant.
#define BIT0_ERR 5 // Bit0Error : During the transmission of a message (or acknowledge bit,
// or active error flag, or overload flag), the device wanted to send a
// LOW/dominant level (data or identifier bit logical value <20>0<EFBFBD>), but the
// monitored Bus value was HIGH/recessive. During busoff recovery this
// status is set each time a
// sequence of 11 HIGH/recessive bits has been monitored. This enables
// the CPU to monitor the proceeding of the busoff recovery sequence
// (indicating the bus is not stuck at LOW/dominant or continuously
// disturbed).
#define CRC_ERR 6 // CRCError: The CRC checksum was incorrect in the message received.
/* bit field of IF command mask register */
#define DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */
#define DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */
#define NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */
#define CLRINTPND (1 << 3)
#define CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */
#define ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */
#define MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */
#define WR (1 << 7) /* 0 is READ, 1 is WRITE */
#define RD 0x0000
/* bit field of IF mask 2 register */
#define MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
#define MASK_MDIR (1 << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */
/* bit field of IF identifier 2 register */
#define ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
#define ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
#define ID_DIR (1 << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */
/* bit field of IF message control register */
#define NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
#define MLST (1 << 14) /* 1 indicates a message loss. */
#define INTP (1 << 13) /* 1 indicates message object is an interrupt source */
#define UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
#define TXIE (1 << 11) /* 1 is TX interrupt enabled */
#define RXIE (1 << 10) /* 1 is RX interrupt enabled */
#if REMOTE_ENABLE
#define RMTEN (1 << 9) /* 1 is remote frame enabled */
#else
#define RMTEN 0
#endif
#define TXRQ (1 << 8) /* 1 is TxRqst enabled */
#define EOB (1 << 7) /* End of buffer, always write to 1 */
#define DLC 0x000F /* bit mask for DLC */
#define ID_STD_MASK 0x07FF
#define ID_EXT_MASK 0x1FFFFFFF
#define DLC_MASK 0x0F
/* Private Variables ---------------------------------------------------------- */
/* Statistics of all the interrupts */
/* Buss off status counter */
volatile uint32_t BOffCnt = 0;
/* Warning status counter. At least one of the error counters
in the EML has reached the error warning limit of 96 */
volatile uint32_t EWarnCnt = 0;
/* More than 5 equal bits in a sequence in received message */
volatile uint32_t StuffErrCnt = 0;
/* Wrong format of fixed format part of a received frame */
volatile uint32_t FormErrCnt = 0;
/* Transmitted message not acknowledged. */
volatile uint32_t AckErrCnt = 0;
/* Send a HIGH/recessive level, but monitored LOW/dominant */
volatile uint32_t Bit1ErrCnt = 0;
/* Send a LOW/dominant level, but monitored HIGH/recessive */
volatile uint32_t Bit0ErrCnt = 0;
/* The CRC checksum was incorrect in the message received */
volatile uint32_t CRCErrCnt = 0;
/* Message object new data error counter */
volatile uint32_t ND1ErrCnt = 0;
MSG_CB TX_cb, RX_cb;
message_object can_buff[CAN_MSG_OBJ_MAX];
message_object recv_buff;
#if CAN_DEBUG
uint32_t CANStatusLog[100];
uint32_t CANStatusLogCount = 0;
#endif
//#ifdef __GNUC__
//uint32_t CAN_IF_Read(uint32_t reg,uint32_t IFsel){
// if(IFsel == IF1){
// return (LPC_C_CAN0->IF1_reg);
// }else{
// return (LPC_C_CAN0->IF2_reg);
// }
//}
//void CAN_IF_Write(uint32_t reg, uint32_t IFsel,uint32_t val){
// if(IFsel == IF1){
// (LPC_C_CAN0->IF1_reg=val);
// }else{
// (LPC_C_CAN0->IF2_reg=val);
// }
//}
//
///* Macro for writing IF to specific RAM message object */
//void CAN_IF_readBuf(uint32_t IFsel,uint32_t msg){
// if(IFsel == IF1){
// LPC_C_CAN0->IF1_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
// LPC_C_CAN0->IF1_CMDREQ=msg;
// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );
// }else{
// LPC_C_CAN0->IF2_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
// LPC_C_CAN0->IF2_CMDREQ=msg;
// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );
// }
//
//}
//
///* Macro for reading specific RAM message object to IF */
//void CAN_IF_writeBuf(uint32_t IFsel,uint32_t msg){
// if(IFsel == IF1){
// LPC_C_CAN0->IF1_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
// LPC_C_CAN0->IF1_CMDREQ=msg;
// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );
// }else{
// LPC_C_CAN0->IF2_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;
// LPC_C_CAN0->IF2_CMDREQ=msg;
// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );
// }
//}
//#endif
/*********************************************************************//**
* @brief Handle valid received message
* @param[in] msg_no Message Object number
* @return None
**********************************************************************/
void CAN_RxInt_MessageProcess( uint8_t msg_no )
{
uint32_t msg_id;
uint32_t *p_add;
uint32_t reg1, reg2;
/* Import message object to IF2 */
CAN_IF_readBuf(IF2, msg_no); /* Read the message into the IF registers */
p_add = (uint32_t *)&recv_buff;
if( CAN_IF_Read(ARB2, IF2) & ID_MTD ) /* bit 28-0 is 29 bit extended frame */
{
/* mask off MsgVal and Dir */
reg1 = CAN_IF_Read(ARB1, IF2);
reg2 = CAN_IF_Read(ARB2, IF2);
msg_id = (reg1|(reg2<<16));
}
else
{
/* bit 28-18 is 11-bit standard frame */
msg_id = (CAN_IF_Read(ARB2, IF2) &0x1FFF) >> 2;
}
p_add[0] = msg_id;
p_add[1] = CAN_IF_Read(MCTRL, IF2) & 0x000F; /* Get Msg Obj Data length */
p_add[2] = (CAN_IF_Read(DA2, IF2)<<16) | CAN_IF_Read(DA1, IF2);
p_add[3] = (CAN_IF_Read(DB2, IF2)<<16) | CAN_IF_Read(DB1, IF2);
/* Clear interrupt pending bit */
CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);
/* Save changes to message RAM */
CAN_IF_writeBuf(IF2, msg_no);
return;
}
/*********************************************************************//**
* @brief Handle valid transmit message
* @param[in] msg_no Message Object number
* @return None
**********************************************************************/
void CAN_TxInt_MessageProcess( uint8_t msg_no )
{
/* Clear interrupt pending bit */
CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);
/* Save changes to message RAM */
CAN_IF_writeBuf(IF2,msg_no);
return;
}
/*********************************************************************//**
* @brief CAN interrupt handler
* @param[in] None
* @return None
**********************************************************************/
volatile uint32_t nd_tmp;
void CAN_IRQHandler(void)
{
uint32_t canstat = 0;
uint32_t can_int, msg_no;
while ( (can_int = LPC_C_CAN0->INT) != 0 ) /* While interrupt is pending */
{
canstat = LPC_C_CAN0->STAT; /* Read CAN status register */
if ( can_int & CAN_STATUS_INTERRUPT )
{
/* Passive state monitored frequently in main. */
if ( canstat & STAT_EWARN )
{
EWarnCnt++;
return;
}
if ( canstat & STAT_BOFF )
{
BOffCnt++;
return;
}
switch (canstat&STAT_LEC) /* LEC Last Error Code (Type of the last error to occur on the CAN bus) */
{
case NO_ERR:
break;
case STUFF_ERR:
StuffErrCnt++;
break;
case FORM_ERR:
FormErrCnt++;
break;
case ACK_ERR:
AckErrCnt++;
break;
case BIT1_ERR:
Bit1ErrCnt++;
break;
case BIT0_ERR:
Bit0ErrCnt++;
break;
case CRC_ERR:
CRCErrCnt++;
break;
default:
break;
}
/* Clear all warning/error states except RXOK/TXOK */
LPC_C_CAN0->STAT &= STAT_RXOK|STAT_TXOK;
}
else
{
if ( (canstat & STAT_LEC) == 0 ) /* NO ERROR */
{
msg_no = can_int & 0x7FFF;
if((msg_no >= 1 ) && (msg_no <= 16))
{
LPC_C_CAN0->STAT &= ~STAT_RXOK;
/* Check if message number is correct by reading NEWDAT registers.
By reading out the NEWDAT bits, the CPU can check for which Message
Object the data portion was updated
Only first 16 message object used for receive : only use ND1 */
if((1<<(msg_no-1)) != LPC_C_CAN0->ND1)
{
/* message object does not contain new data! */
ND1ErrCnt++;
break;
}
CAN_RxInt_MessageProcess(msg_no);
RX_cb(msg_no);
}
else
{
LPC_C_CAN0->STAT &= ~STAT_TXOK;
CAN_TxInt_MessageProcess(msg_no);
TX_cb(msg_no);
}
}
}
}
return;
}
/*********************************************************************//**
* @brief Initialize CAN peripheral
* @param[in] BitClk CAN bit clock setting
* @param[in] ClkDiv CAN bit clock setting
* @param[in] Tx_cb point to call-back function when transmitted
* @param[in] Rx_cb point to call-back function when received
* @return None
**********************************************************************/
void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb)
{
RX_cb = Rx_cb;
TX_cb = Tx_cb;
if ( !(LPC_C_CAN0->CNTL & CTRL_INIT) )
{
/* If it's in normal operation already, stop it, reconfigure
everything first, then restart. */
LPC_C_CAN0->CNTL |= CTRL_INIT; /* Default state */
}
LPC_C_CAN0->CLKDIV = ClkDiv; /* Divider for CAN VPB3 clock */
LPC_C_CAN0->CNTL |= CTRL_CCE; /* Start configuring bit timing */
LPC_C_CAN0->BT = BitClk;
LPC_C_CAN0->BRPE = 0x0000;
LPC_C_CAN0->CNTL &= ~CTRL_CCE; /* Stop configuring bit timing */
LPC_C_CAN0->CNTL &= ~CTRL_INIT; /* Initialization finished, normal operation now. */
while ( LPC_C_CAN0->CNTL & CTRL_INIT );
/* By default, auto TX is enabled, enable all related interrupts */
LPC_C_CAN0->CNTL |= (CTRL_IE|CTRL_SIE|CTRL_EIE);
return;
}
/*********************************************************************//**
* @brief Send a message to the CAN port
* @param[in] msg_no message object number
* @param[in] msg_ptr msg buffer pointer
* @return None
**********************************************************************/
void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr )
{
uint32_t tx_id, Length;
if(msg_ptr == NULL) return;
/* first is the ID, second is length, the next four are data */
tx_id = *msg_ptr++;
Length = *msg_ptr++;
if(Length>CAN_DLC_MAX)Length = CAN_DLC_MAX;
CAN_IF_Write(MCTRL, IF1, UMSK|TXIE|TXRQ|EOB|RMTEN|(Length & DLC_MASK));
CAN_IF_Write(DA1, IF1, *msg_ptr); /* Lower two bytes of message pointer */
CAN_IF_Write(DA2, IF1, (*msg_ptr++)>>16); /* Upper two bytes of message pointer */
CAN_IF_Write(DB1, IF1, *msg_ptr); /* Lower two bytes of message pointer */
CAN_IF_Write(DB2, IF1, (*msg_ptr)>>16); /* Upper two bytes of message pointer */
/* Configure arbitration */
if(!(tx_id & (0x1<<30))) /* bit 30 is 0, standard frame */
{
/* Mxtd: 0, Mdir: 1, Mask is 0x7FF */
CAN_IF_Write(MSK2, IF1, MASK_MDIR | (ID_STD_MASK << 2));
CAN_IF_Write(MSK1, IF1, 0x0000);
/* MsgVal: 1, Mtd: 0, Dir: 1, ID = 0x200 */
CAN_IF_Write(ARB1, IF1, 0x0000);
CAN_IF_Write(ARB2, IF1, ID_MVAL| ID_DIR | (tx_id << 2));
}
else /* Extended frame */
{
/* Mxtd: 1, Mdir: 1, Mask is 0x7FF */
CAN_IF_Write(MSK2, IF1, MASK_MXTD | MASK_MDIR | (ID_EXT_MASK >> 16));
CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0x0000FFFF);
/* MsgVal: 1, Mtd: 1, Dir: 1, ID = 0x200000 */
CAN_IF_Write(ARB1, IF1, tx_id & 0x0000FFFF);
CAN_IF_Write(ARB2, IF1, ID_MVAL|ID_MTD | ID_DIR | (tx_id >> 16));
}
/* Write changes to message RAM */
CAN_IF_writeBuf(IF1, msg_no);
return;
}
/*********************************************************************//**
* @brief Listen for a message on CAN bus
* @param[in] msg_no message object number
* @param[in] msg_ptr msg buffer pointer
* @param[in] RemoteEnable Enable/disable remote frame support, should be:
* - TRUE: enable
* - FALSE: disable
* @return None
**********************************************************************/
void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable)
{
uint32_t rx_id = *msg_ptr;
uint32_t rmten = 0;
if(RemoteEnable){
rmten = 1<<8;
}
if(!(rx_id & (0x1<<30))){ /* standard frame */
/* Mxtd: 0, Mdir: 0, Mask is 0x7FF */
CAN_IF_Write(MSK1, IF1, 0x0000);
CAN_IF_Write(MSK2, IF1, ID_STD_MASK << 2);
/* MsgVal: 1, Mtd: 0, Dir: 0 */
CAN_IF_Write(ARB1, IF1, 0x0000);
CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);
CAN_IF_Write(DA1, IF1, 0x0000);
CAN_IF_Write(DA2, IF1, 0x0000);
CAN_IF_Write(DB1, IF1, 0x0000);
CAN_IF_Write(DB2, IF1, 0x0000);
CAN_IF_Write(ARB2, IF1, ID_MVAL | ((rx_id) << 2));
/* Transfer data to message RAM */
CAN_IF_writeBuf(IF1, msg_no);
}
else{
rx_id &= (0x1<<30)-1 ; /* Mask ID bit */
/* Mxtd: 1, Mdir: 0, Mask is 0x1FFFFFFF */
CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0xFFFF);
CAN_IF_Write(MSK2, IF1, MASK_MXTD | (ID_EXT_MASK >> 16));
/* MsgVal: 1, Mtd: 1, Dir: 0 */
CAN_IF_Write(ARB1, IF1, (rx_id) & 0xFFFF);
CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);
CAN_IF_Write(DA1, IF1, 0x0000);
CAN_IF_Write(DA2, IF1, 0x0000);
CAN_IF_Write(DB1, IF1, 0x0000);
CAN_IF_Write(DB2, IF1, 0x0000);
CAN_IF_Write(ARB2, IF1, ID_MVAL | ID_MTD | ((rx_id) >> 16));
/* Transfer data to message RAM */
CAN_IF_writeBuf(IF1, msg_no);
}
return;
}
/*********************************************************************//**
* @brief Read a message from Message RAM to buffer
* @param[in] msg_no message object number
* @param[in] buff msg buffer pointer
* @return None
**********************************************************************/
void CAN_ReadMsg(uint32_t msg_no, message_object* buff){
int i;
buff->id = recv_buff.id;
buff->dlc = recv_buff.dlc;
if(recv_buff.dlc>CAN_DLC_MAX) recv_buff.dlc = CAN_DLC_MAX;
for(i=0;i<recv_buff.dlc;i++)
buff->data[i] = recv_buff.data[i];
}
#endif /* _C_CAN*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

916
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_cgu.c vendored
View file

@ -1,916 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_cgu.c 2011-06-02
*//**
* @file lpc18xx_cgu.c
* @brief Contains all functions support for Clock Generation and Control
* firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup CGU
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
#include "lpc18xx_scu.h"
#include "lpc18xx_cgu.h"
/** This define used to fix mistake when run with IAR compiler */
#ifdef __ICCARM__
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001
#else
#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01
#endif
/*TODO List:
* SET PLL0
* UPDATE Clock from PLL0
* SetDIV uncheck value
* GetBaseStatus BASE_SAFE
* */
/* Local definition */
#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))
/* Local Variable */
const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {
-1, //CGU_CLKSRC_32KHZ_OSC,
-1, //CGU_CLKSRC_IRC,
-1, //CGU_CLKSRC_ENET_RX_CLK,
-1, //CGU_CLKSRC_ENET_TX_CLK,
-1, //CGU_CLKSRC_GP_CLKIN,
-1, //CGU_CLKSRC_TCK,
0x18, //CGU_CLKSRC_XTAL_OSC,
0x20, //CGU_CLKSRC_PLL0,
0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**
0x44, //CGU_CLKSRC_PLL1,
-1, //CGU_CLKSRC_RESERVE,
-1, //CGU_CLKSRC_RESERVE,
0x48, //CGU_CLKSRC_IDIVA,,
0x4C, //CGU_CLKSRC_IDIVB,
0x50, //CGU_CLKSRC_IDIVC,
0x54, //CGU_CLKSRC_IDIVD,
0x58, //CGU_CLKSRC_IDIVE,
0x5C, //CGU_BASE_SAFE,
0x60, //CGU_BASE_USB0,
-1, //CGU_BASE_RESERVE,
0x68, //CGU_BASE_USB1,
0x6C, //CGU_BASE_M3,
0x70, //CGU_BASE_SPIFI,
-1, //CGU_BASE_RESERVE,
0x78, //CGU_BASE_PHY_RX,
0x7C, //CGU_BASE_PHY_TX,
0x80, //CGU_BASE_APB1,
0x84, //CGU_BASE_APB3,
0x88, //CGU_BASE_LCD,
0X8C, //CGU_BASE_ENET_CSR, **REV A**
0x90, //CGU_BASE_SDIO,
0x94, //CGU_BASE_SSP0,
0x98, //CGU_BASE_SSP1,
0x9C, //CGU_BASE_UART0,
0xA0, //CGU_BASE_UART1,
0xA4, //CGU_BASE_UART2,
0xA8, //CGU_BASE_UART3,
0xAC, //CGU_BASE_CLKOUT
-1,
-1,
-1,
-1,
0xC0, //CGU_BASE_APLL
0xC4, //CGU_BASE_OUT0
0xC8 //CGU_BASE_OUT1
};
const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {
// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O
// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U
// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/
{0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/
{0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/
{0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/
{0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
{0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/
{0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/
};
const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {
/* Register Clock | Peripheral Clock
| BASE | BRANCH | BASE | BRANCH */
{CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,
{CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,
{CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,
//// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
{CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,
{CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,
{CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,
{CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,
{CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,
{CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,
{CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC,
{CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,
{CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX
{CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,
{CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,
{CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,
{CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,
{CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,
{CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,
{CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,
{CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,
{CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,
{CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,
{CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,
{CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,
{CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,
{CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,
{CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,
{CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,
{CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,
{CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,
{CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,
{CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,
{CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,
{CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,
{CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,
{CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,
{CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,
{CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,
{CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,
};
uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0};
#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)
#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))
#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))
#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))
#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))
#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))
/*********************************************************************//**
* @brief Initialize default clock for LPC1800 Eval board
* @param[in] None
* @return Initialize status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_Init(void){
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// Disable PLL1 CPU hang???
//CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);
CGU_SetPLL1(10);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
CGU_UpdateClock();
return 0;
}
/*********************************************************************//**
* @brief Configure power for individual peripheral
* @param[in] PPType peripheral type, should be:
* - CGU_PERIPHERAL_ADC0 :ADC0
* - CGU_PERIPHERAL_ADC1 :ADC1
* - CGU_PERIPHERAL_AES :AES
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
* - CGU_PERIPHERAL_CAN :CAN
* - CGU_PERIPHERAL_CREG :CREG
* - CGU_PERIPHERAL_DAC :DAC
* - CGU_PERIPHERAL_DMA :DMA
* - CGU_PERIPHERAL_EMC :EMC
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
* - CGU_PERIPHERAL_GPIO :GPIO
* - CGU_PERIPHERAL_I2C0 :I2C0
* - CGU_PERIPHERAL_I2C1 :I2C1
* - CGU_PERIPHERAL_I2S :I2S
* - CGU_PERIPHERAL_LCD :LCD
* - CGU_PERIPHERAL_M3CORE :M3 core
* - CGU_PERIPHERAL_M3_BUS :M3 bus
* - CGU_PERIPHERAL_MOTOCON :Motor control
* - CGU_PERIPHERAL_QEI :QEI
* - CGU_PERIPHERAL_RITIMER :RIT timer
* - CGU_PERIPHERAL_SCT :SCT
* - CGU_PERIPHERAL_SCU :SCU
* - CGU_PERIPHERAL_SDIO :SDIO
* - CGU_PERIPHERAL_SPIFI :SPIFI
* - CGU_PERIPHERAL_SSP0 :SSP0
* - CGU_PERIPHERAL_SSP1 :SSP1
* - CGU_PERIPHERAL_TIMER0 :TIMER0
* - CGU_PERIPHERAL_TIMER1 :TIMER1
* - CGU_PERIPHERAL_TIMER2 :TIMER2
* - CGU_PERIPHERAL_TIMER3 :TIMER3
* - CGU_PERIPHERAL_UART0 :UART0
* - CGU_PERIPHERAL_UART1 :UART1
* - CGU_PERIPHERAL_UART2 :UART2
* - CGU_PERIPHERAL_UART3 :UART3
* - CGU_PERIPHERAL_USB0 :USB0
* - CGU_PERIPHERAL_USB1 :USB1
* - CGU_PERIPHERAL_WWDT :WWDT
* @param[in] en status, should be:
* - ENABLE: Enable power
* - DISABLE: Disable power
* @return Configure status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){
if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0)
return CGU_ERROR_INVALID_PARAM;
if(en == DISABLE){/* Going to disable clock */
/*Get Reg branch status */
if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 &&
CGU_REG_BRANCH_STATUS(PPType) & 1){
CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
while(CGU_REG_BRANCH_STATUS(PPType) & 1);
}
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) &&
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){
/* Disable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0);
}
/* Same for Peripheral */
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */
while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);
}
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) &&
CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){
/* Disable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0);
}
}else{
/* enable */
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){
/* Enable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);
}
/*Get Reg branch status */
if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
}
/* Same for Peripheral */
/* GetBase Status*/
if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&
(CGU_PER_BASE_CTRL(PPType) & 1)){
/* Enable Base */
CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);
}
/*Get Reg branch status */
if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){
CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */
while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));
}
}
if(CGU_PERIPHERAL_Info[PPType].next){
return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);
}
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Get peripheral clock frequency
* @param[in] Clock Peripheral type, should be:
* - CGU_PERIPHERAL_ADC0 :ADC0
* - CGU_PERIPHERAL_ADC1 :ADC1
* - CGU_PERIPHERAL_AES :AES
* - CGU_PERIPHERAL_APB1_BUS :APB1 bus
* - CGU_PERIPHERAL_APB3_BUS :APB3 bus
* - CGU_PERIPHERAL_CAN :CAN
* - CGU_PERIPHERAL_CREG :CREG
* - CGU_PERIPHERAL_DAC :DAC
* - CGU_PERIPHERAL_DMA :DMA
* - CGU_PERIPHERAL_EMC :EMC
* - CGU_PERIPHERAL_ETHERNET :ETHERNET
* - CGU_PERIPHERAL_GPIO :GPIO
* - CGU_PERIPHERAL_I2C0 :I2C0
* - CGU_PERIPHERAL_I2C1 :I2C1
* - CGU_PERIPHERAL_I2S :I2S
* - CGU_PERIPHERAL_LCD :LCD
* - CGU_PERIPHERAL_M3CORE :M3 core
* - CGU_PERIPHERAL_M3_BUS :M3 bus
* - CGU_PERIPHERAL_MOTOCON :Motor control
* - CGU_PERIPHERAL_QEI :QEI
* - CGU_PERIPHERAL_RITIMER :RIT timer
* - CGU_PERIPHERAL_SCT :SCT
* - CGU_PERIPHERAL_SCU :SCU
* - CGU_PERIPHERAL_SDIO :SDIO
* - CGU_PERIPHERAL_SPIFI :SPIFI
* - CGU_PERIPHERAL_SSP0 :SSP0
* - CGU_PERIPHERAL_SSP1 :SSP1
* - CGU_PERIPHERAL_TIMER0 :TIMER0
* - CGU_PERIPHERAL_TIMER1 :TIMER1
* - CGU_PERIPHERAL_TIMER2 :TIMER2
* - CGU_PERIPHERAL_TIMER3 :TIMER3
* - CGU_PERIPHERAL_UART0 :UART0
* - CGU_PERIPHERAL_UART1 :UART1
* - CGU_PERIPHERAL_UART2 :UART2
* - CGU_PERIPHERAL_UART3 :UART3
* - CGU_PERIPHERAL_USB0 :USB0
* - CGU_PERIPHERAL_USB1 :USB1
* - CGU_PERIPHERAL_WWDT :WWDT
* @return Return frequently value
**********************************************************************/
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){
uint32_t ClkSrc;
if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0)
return CGU_ERROR_INVALID_PARAM;
if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){
/* Get Base Clock Source */
ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
/* GetBase Status*/
if(CGU_PER_BASE_CTRL(Clock) & 1)
return 0;
/* check Branch if it is enabled */
if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
}else{
if(CGU_REG_BASE_CTRL(Clock) & 1) return 0;
ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;
/* check Branch if it is enabled */
if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;
}
return CGU_ClockSourceFrequency[ClkSrc];
}
/*********************************************************************//**
* @brief Update clock
* @param[in] None
* @return None
**********************************************************************/
void CGU_UpdateClock(void){
uint32_t ClkSrc;
uint32_t div;
uint32_t divisor;
int32_t RegOffset;
/* 32OSC */
if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3))
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;
else
CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;
/*PLL0*/
/* PLL1 */
if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */
&& (LPC_CGU->PLL1_STAT&1)){ /* Locked? */
ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *
(((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1);
}else
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;
/* DIV */
for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){
RegOffset = CGU_Entity_ControlReg_Offset[div];
if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){
ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24;
divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF;
divisor ++;
CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;
}else
CGU_ClockSourceFrequency[div] = 0;
}
}
/*********************************************************************//**
* @brief Set XTAL oscillator value
* @param[in] ClockFrequency XTAL Frequency value
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range
**********************************************************************/
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){
if(ClockFrequency < 15000000){
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);
}else if(ClockFrequency < 25000000){
LPC_CGU->XTAL_OSC_CTRL |= (1<<2);
}else
return CGU_ERROR_FREQ_OUTOF_RANGE;
CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Set clock divider
* @param[in] SelectDivider Clock source, should be:
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* @param[in] divisor Divisor value, should be: 0..255
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
**********************************************************************/
/* divisor number must >=1*/
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){
int32_t RegOffset;
uint32_t tempReg;
if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){
RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
tempReg &= ~(0xFF<<2);
tempReg |= ((divisor-1)&0xFF)<<2;
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
return CGU_ERROR_SUCCESS;
}
return CGU_ERROR_INVALID_ENTITY;
}
/*********************************************************************//**
* @brief Enable clock entity
* @param[in] ClockEntity Clock entity, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
* - CGU_CLKSRC_IRC :IRC clock
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] en status, should be:
* - ENABLE: Enable power
* - DISABLE: Disable power
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_ENTITY: Invalid entity
**********************************************************************/
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){
int32_t RegOffset;
int32_t i;
if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){
if(en){
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2));
LPC_CREG->CREG0 |= (1<<1)|(1<<0);
}else{
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0));
LPC_CREG->CREG0 |= (1<<3);
}
for(i = 0;i<1000000;i++);
}else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){
scu_pinmux(0xC ,0 , MD_PLN, FUNC3);
}else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){
scu_pinmux(0x1 ,19 , MD_PLN, FUNC0);
}else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){
}else if(ClockEntity == CGU_CLKSRC_TCK){
}else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){
if(!en)
LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;
else
LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;
/*Delay for stable clock*/
for(i = 0;i<1000000;i++);
}else{
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
if(!en){
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK;
}else{
CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK;
/*if PLL is selected check if it is locked */
if(ClockEntity == CGU_CLKSRC_PLL0){
while((LPC_CGU->PLL0USB_STAT&1) == 0x0);
}
if(ClockEntity == CGU_CLKSRC_PLL1){
while((LPC_CGU->PLL1_STAT&1) == 0x0);
/*post check lock status */
if(!(LPC_CGU->PLL1_STAT&1))
while(1);
}
}
}
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Connect entity clock source
* @param[in] ClockSource Clock source, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator
* - CGU_CLKSRC_IRC :IRC clock
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* @param[in] ClockEntity Clock entity, should be:
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together
* - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error
* - CGU_ERROR_INVALID_ENTITY: Invalid entity error
**********************************************************************/
/* Connect one entity into clock source */
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){
int32_t RegOffset;
uint32_t tempReg;
if(ClockSource > CGU_CLKSRC_IDIVE)
return CGU_ERROR_INVALID_CLOCK_SOURCE;
if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){
if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){
RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];
if(RegOffset != -1){
if(ClockEntity<=CGU_CLKSRC_IDIVE &&
ClockEntity>=CGU_CLKSRC_PLL0)
{
//RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;
if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity)
return CGU_ERROR_CONNECT_TOGETHER;
}
}
RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];
if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;
tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);
tempReg &= ~CGU_CTRL_SRC_MASK;
tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK;
CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;
return CGU_ERROR_SUCCESS;
}else
return CGU_ERROR_INVALID_CLOCK_SOURCE;
}else
return CGU_ERROR_INVALID_ENTITY;
}
/*********************************************************************//**
* @brief Get current USB PLL clock from XTAL
* @param[in] None
* @return Returned clock value
**********************************************************************/
uint32_t CGU_SetPLL0(void){
// Setup PLL550 to generate 480MHz from 12 MHz crystal
LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL
// P N
LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);
// SELP SELI SELR MDEC
LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);
LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4);
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Setting PLL1
* @param[in] mult Multiple value
* @return Setting status, could be:
* - CGU_ERROR_SUCCESS: successful
* - CGU_ERROR_INVALID_PARAM: Invalid parameter error
**********************************************************************/
uint32_t CGU_SetPLL1(uint32_t mult){
uint32_t msel=0, nsel=0, psel=0, pval=1;
uint32_t freq;
uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;
freq = CGU_ClockSourceFrequency[ClkSrc];
freq *= mult;
msel = mult-1;
LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |
CGU_PLL1_BYPASS_MASK |
CGU_PLL1_DIRECT_MASK |
(0x03<<8) | (0xFF<<16) | (0x03<<12));
if(freq<156000000){
//psel is encoded such that 0=1, 1=2, 2=4, 3=8
while(2*(pval)*freq < 156000000) {
psel++;
pval*=2;
}
// if(2*(pval)*freq > 320000000) {
// //THIS IS OUT OF RANGE!!!
// //HOW DO WE ASSERT IN SAMPLE CODE?
// //__breakpoint(0);
// return CGU_ERROR_INVALID_PARAM;
// }
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK;
}else if(freq<320000000){
LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;
}else
return CGU_ERROR_INVALID_PARAM;
return CGU_ERROR_SUCCESS;
}
/*********************************************************************//**
* @brief Get current base status
* @param[in] Base Base type, should be:
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* @return Always return 0
**********************************************************************/
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){
switch(Base){
/*CCU1*/
case CGU_BASE_APB3:
return LPC_CCU1->BASE_STAT & 1;
case CGU_BASE_APB1:
return (LPC_CCU1->BASE_STAT>>1) & 1;
case CGU_BASE_SPIFI:
return (LPC_CCU1->BASE_STAT>>2) & 1;
case CGU_BASE_M3:
return (LPC_CCU1->BASE_STAT>>3) & 1;
case CGU_BASE_USB0:
return (LPC_CCU1->BASE_STAT>>7) & 1;
case CGU_BASE_USB1:
return (LPC_CCU1->BASE_STAT>>8) & 1;
/*CCU2*/
case CGU_BASE_UART3:
return (LPC_CCU2->BASE_STAT>>1) & 1;
case CGU_BASE_UART2:
return (LPC_CCU2->BASE_STAT>>2) & 1;
case CGU_BASE_UART1:
return (LPC_CCU2->BASE_STAT>>3) & 1;
case CGU_BASE_UART0:
return (LPC_CCU2->BASE_STAT>>4) & 1;
case CGU_BASE_SSP1:
return (LPC_CCU2->BASE_STAT>>5) & 1;
case CGU_BASE_SSP0:
return (LPC_CCU2->BASE_STAT>>6) & 1;
case CGU_BASE_SDIO:
return (LPC_CCU2->BASE_STAT>>7) & 1;
/*BASE SAFE is used by WWDT and RGU*/
case CGU_BASE_SAFE:
break;
default:
break;
}
return 0;
}
/*********************************************************************//**
* @brief Compare one source clock to IRC clock
* @param[in] Clock Clock entity that will be compared to IRC, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] m Multiple value pointer
* @param[in] d Divider value pointer
* @return Compare status, could be:
* - (-1): fail
* - 0: successful
* @note Formula used to compare:
* FClock = F_IRC* m / d
**********************************************************************/
int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){
uint32_t n,c,temp;
int i;
/* Maximum allow RCOUNT number */
c= 511;
/* Check Source Clock Freq is larger or smaller */
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
while(LPC_CGU->FREQ_MON & (1 <<23));
for(i=0;i<10000;i++);
temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
if(temp == 0) /* too low F < 12000000/511*/
return -1;
if(temp > 511){ /* larger */
c = 511 - (LPC_CGU->FREQ_MON&0x1FF);
}else{
do{
c--;
LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;
while(LPC_CGU->FREQ_MON & (1 <<23));
for(i=0;i<10000;i++);
n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;
}while(n==temp);
c++;
}
*m = temp;
*d = c;
return 0;
}
/*********************************************************************//**
* @brief Compare one source clock to another source clock
* @param[in] Clock Clock entity that will be compared to second source, should be:
* - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator
* - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock
* - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock
* - CGU_CLKSRC_GP_CLKIN :General purpose input clock
* - CGU_CLKSRC_XTAL_OSC :Crystal oscillator
* - CGU_CLKSRC_PLL0 :PLL0 clock
* - CGU_CLKSRC_PLL1 :PLL1 clock
* - CGU_CLKSRC_IDIVA :Integer divider register A
* - CGU_CLKSRC_IDIVB :Integer divider register B
* - CGU_CLKSRC_IDIVC :Integer divider register C
* - CGU_CLKSRC_IDIVD :Integer divider register D
* - CGU_CLKSRC_IDIVE :Integer divider register E
* - CGU_BASE_SAFE :Base safe clock (always on)for WDT
* - CGU_BASE_USB0 :Base clock for USB0
* - CGU_BASE_USB1 :Base clock for USB1
* - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core
* and APB peripheral blocks #0 and #2
* - CGU_BASE_SPIFI :Base clock for SPIFI
* - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx
* - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx
* - CGU_BASE_APB1 :Base clock for APB peripheral block #1
* - CGU_BASE_APB3 :Base clock for APB peripheral block #3
* - CGU_BASE_LCD :Base clock for LCD
* - CGU_BASE_SDIO :Base clock for SDIO card reader
* - CGU_BASE_SSP0 :Base clock for SSP0
* - CGU_BASE_SSP1 :Base clock for SSP1
* - CGU_BASE_UART0 :Base clock for UART0
* - CGU_BASE_UART1 :Base clock for UART1
* - CGU_BASE_UART2 :Base clock for UART2
* - CGU_BASE_UART3 :Base clock for UART3
* - CGU_BASE_CLKOUT :Base clock for CLKOUT pin
* @param[in] CompareToClock Clock source that to be compared to first source, should be different
* to first source.
* @param[in] m Multiple value pointer
* @param[in] d Divider value pointer
* @return Compare status, could be:
* - (-1): fail
* - 0: successful
* @note Formula used to compare:
* FClock = m*FCompareToClock/d
**********************************************************************/
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){
uint32_t m1,m2,d1,d2;
/* Check Parameter */
if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE))
return CGU_ERROR_INVALID_PARAM;
/* Check for Clock Enable - Not yet implement
* The Comparator will hang if Clock has not been set*/
CGU_FrequencyMonitor(Clock, &m1, &d1);
CGU_FrequencyMonitor(CompareToClock, &m2, &d2);
*m= m1*d2;
*d= d1*m2;
return 0;
}
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

147
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c vendored
View file

@ -1,147 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_dac.c 2011-06-02
*//**
* @file lpc18xx_dac.c
* @brief Contains all functions support for DAC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup DAC
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_dac.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _DAC
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup DAC_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial ADC configuration
* - Maximum current is 700 uA
* - Value to AOUT is 0
* @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC
* @return None
***********************************************************************/
void DAC_Init(LPC_DAC_Type *DACx)
{
CHECK_PARAM(PARAM_DACx(DACx));
/* Set default clock divider for DAC */
//LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11); // ABP3 base clock use PLL1 and auto block
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3);
//Set maximum current output
DAC_SetBias(LPC_DAC,DAC_MAX_CURRENT_700uA);
}
/*********************************************************************//**
* @brief Update value to DAC
* @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC
* @param[in] dac_value value 10 bit to be converted to output
* @return None
***********************************************************************/
void DAC_UpdateValue (LPC_DAC_Type *DACx,uint32_t dac_value)
{
uint32_t tmp;
CHECK_PARAM(PARAM_DACx(DACx));
tmp = DACx->CR & DAC_BIAS_EN;
tmp |= DAC_VALUE(dac_value);
// Update value
DACx->CR = tmp;
}
/*********************************************************************//**
* @brief Set Maximum current for DAC
* @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC
* @param[in] bias Using Bias value, should be:
* - 0 is 700 uA
* - 1 is 350 uA
* @return None
***********************************************************************/
void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias)
{
CHECK_PARAM(PARAM_DAC_CURRENT_OPT(bias));
DACx->CR &=~DAC_BIAS_EN;
if (bias == DAC_MAX_CURRENT_350uA)
{
DACx->CR |= DAC_BIAS_EN;
}
}
/*********************************************************************//**
* @brief To enable the DMA operation and control DMA timer
* @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC
* @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type
* - DBLBUF_ENA :enable/disable DACR double buffering feature
* - CNT_ENA :enable/disable timer out counter
* - DMA_ENA :enable/disable DMA access
* @return None
***********************************************************************/
void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct)
{
CHECK_PARAM(PARAM_DACx(DACx));
DACx->CTRL &= ~DAC_DACCTRL_MASK;
if (DAC_ConverterConfigStruct->DBLBUF_ENA)
DACx->CTRL |= DAC_DBLBUF_ENA;
if (DAC_ConverterConfigStruct->CNT_ENA)
DACx->CTRL |= DAC_CNT_ENA;
if (DAC_ConverterConfigStruct->DMA_ENA)
DACx->CTRL |= DAC_DMA_ENA;
}
/*********************************************************************//**
* @brief Set reload value for interrupt/DMA counter
* @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC
* @param[in] time_out time out to reload for interrupt/DMA counter
* @return None
***********************************************************************/
void DAC_SetDMATimeOut(LPC_DAC_Type *DACx, uint32_t time_out)
{
CHECK_PARAM(PARAM_DACx(DACx));
DACx->CNTVAL = DAC_CCNT_VALUE(time_out);
}
/**
* @}
*/
#endif /* _DAC */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

233
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c vendored
View file

@ -1,233 +0,0 @@
/**********************************************************************
* $Id: lpc18xx_emc.c 8765 2011-12-08 00:51:21Z nxp21346 $ lpc18xx_emc.c 2011-12-07
*//**
* @file lpc18xx_emc.c
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc18xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include "LPC18xx.h"
#include "lpc18xx_emc.h"
#include "lpc18xx_scu.h"
#define M32(x) *((uint32_t *)x)
#define DELAYCYCLES(ns) (ns / ((1.0 / __EMCHZ) * 1E9))
void emc_WaitUS(volatile uint32_t us)
{
us *= (SystemCoreClock / 1000000) / 3;
while(us--);
}
void emc_WaitMS(uint32_t ms)
{
emc_WaitUS(ms * 1000);
}
void MemoryPinInit(void)
{
/* select correct functions on the GPIOs */
#if 1
/* DATA LINES 0..31 > D0..D31 */
/* P1_7 - EXTBUS_D0 — External memory data line 0 */
scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */
scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */
scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */
scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */
scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */
scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */
scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */
scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */
scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */
scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */
scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */
scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */
scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */
scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */
scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */
scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */
#if 0
scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */
scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */
scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */
scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */
scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */
scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */
scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */
scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */
scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */
scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */
scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */
scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */
scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */
scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */
scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */
scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */
#endif
/* ADDRESS LINES A0..A11 > A0..A11 */
scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 — External memory address line 0 */
scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 — External memory address line 1 */
scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 — External memory address line 2 */
scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 — External memory address line 3 */
scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 — External memory address line 4 */
scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 — External memory address line 5 */
scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 — External memory address line 6 */
scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 — External memory address line 7 */
scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 — External memory address line 8 */
scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 — External memory address line 9 */
scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 — External memory address line 10 */
scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 — External memory address line 11 */
scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 — External memory address line 12 */
scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 — External memory address line 13 */
scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */
scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */
scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */
scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */
scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */
scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */
scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */
scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */
scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */
scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */
/* BYTE ENABLES */
scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 — LOW active Byte Lane select signal 0 */
scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 — LOW active Byte Lane select signal 1 */
scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 — LOW active Byte Lane select signal 2 */
scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 — LOW active Byte Lane select signal 3 */
scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */
scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */
LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */
LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */
LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */
LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */
scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */
scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */
scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */
scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */
scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE
#endif
}
void EMCFlashInit(void)
{
// Hitex board SST39VF3201B Flash
// Read Cycle Time 70 nS minimum
// Chip Enable Access Time 70 ns maximum
// Address Access Time 70 ns max
// Toe 35 ns max
// CE/OE high to inactive output 16 ns
/* Set up EMC Controller */
LPC_EMC->STATICWAITRD0 = DELAYCYCLES(70)+1;
LPC_EMC->STATICWAITPAG0 = DELAYCYCLES(70)+1;
LPC_EMC->CONTROL = 0x01;
LPC_EMC->STATICCONFIG0 = (1UL<<7) | (1UL);
LPC_EMC->STATICWAITOEN0 = DELAYCYCLES(35)+1;
/*Enable Buffer for External Flash*/
LPC_EMC->STATICCONFIG0 |= 1<<19;
}
/* SDRAM refresh time to 16 clock num */
#define EMC_SDRAM_REFRESH(freq,time) \
(((uint64_t)((uint64_t)time * freq)/16000000000ull)+1)
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// adjust the CCU delaye for EMI (default to zero)
//LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
// Move all clock delays together
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
| (CLK0_DELAY << 4)
| (CLK0_DELAY << 8)
| (CLK0_DELAY << 12));
/* Initialize EMC to interface with SDRAM */
LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
LPC_EMC->CONFIG = 0;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
LPC_EMC->DYNAMICRAS = 3;
LPC_EMC->DYNAMICSREX = 5;
LPC_EMC->DYNAMICAPR = 0;
LPC_EMC->DYNAMICDAL = 4;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 5;
LPC_EMC->DYNAMICRFC = 5;
LPC_EMC->DYNAMICXSR = 5;
LPC_EMC->DYNAMICRRD = 1;
LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
emc_WaitUS(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
emc_WaitUS(100);
LPC_EMC->DYNAMICREFRESH = 50;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
if(u32DataBus == 0)
{
/* burst size 8 */
*((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
}
else
{
/* burst size 4 */
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
}
LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
}

258
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c vendored
View file

@ -1,258 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_evrt.c 2011-06-02
*//**
* @file lpc18xx_evrt.c
* @brief Contains all functions support for Event Router firmware
* library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup EVRT
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_evrt.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup EVRT_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initializes the EVRT peripheral.
* @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT
* @return None
*********************************************************************/
void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx)
{
uint8_t i=0;
CHECK_PARAM(PARAM_EVRTx(EVRTx));
// Clear all register to be default
EVRTx->HILO = 0x0000;
EVRTx->EDGE = 0x0000;
EVRTx->CLR_EN = 0xFFFF;
do
{
i++;
EVRTx->CLR_STAT = 0xFFFFF;
}while((EVRTx->STATUS != 0)&&(i<10));
}
/*********************************************************************//**
* @brief De-initializes the EVRT peripheral registers to their
* default reset values.
* @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT
* @return None
**********************************************************************/
void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx)
{
CHECK_PARAM(PARAM_EVRTx(EVRTx));
EVRTx->CLR_EN = 0xFFFF;
EVRTx->CLR_STAT = 0xFFFF;
}
/*********************************************************************//**
* @brief Setting up the type of interrupt sources to EVRT
* @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT
* @param[in] EVRT_Src EVRT source, should be:
* - EVRT_SRC_WAKEUP0 :WAKEUP0 event
* - EVRT_SRC_WAKEUP1 :WAKEUP1 event
* - EVRT_SRC_WAKEUP2 :WAKEUP2 event
* - EVRT_SRC_WAKEUP3 :WAKEUP3 event
* - EVRT_SRC_ATIMER :Alarm timer eveny
* - EVRT_SRC_RTC :RTC event
* - EVRT_SRC_BOD :BOD event
* - EVRT_SRC_WWDT :WWDT event
* - EVRT_SRC_ETHERNET :ETHERNET event
* - EVRT_SRC_USB0 :USB0 event
* - EVRT_SRC_USB1 :USB1 event
* - EVRT_SRC_CCAN :CCAN event
* - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event
* - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event
* - EVRT_SRC_QEI :QEI event
* - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event
* - EVRT_SRC_RESET :RESET event
* type Active type, should be:
* - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level
* - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level
* - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge
* - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge
* @param[in] type EVRT source active type, should be:
* - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level
* - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level
* - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge
* - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge
* @return None
**********************************************************************/
void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)
{
CHECK_PARAM(PARAM_EVRTx(EVRTx));
CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));
CHECK_PARAM(PARAM_EVRT_SOURCE_ACTIVE_TYPE(type));
switch (type)
{
case EVRT_SRC_ACTIVE_LOW_LEVEL:
EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src);
EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src);
break;
case EVRT_SRC_ACTIVE_HIGH_LEVEL:
EVRTx->HILO |= (1<<(uint8_t)EVRT_Src);
EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src);
break;
case EVRT_SRC_ACTIVE_FALLING_EDGE:
EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src);
EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src);
break;
case EVRT_SRC_ACTIVE_RISING_EDGE:
EVRTx->HILO |= (1<<(uint8_t)EVRT_Src);
EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src);
break;
default:
break;
}
}
/*********************************************************************//**
* @brief Enable or disable interrupt sources to EVRT
* @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT
* @param[in] EVRT_Src EVRT source, should be:
* - EVRT_SRC_WAKEUP0 :WAKEUP0 event
* - EVRT_SRC_WAKEUP1 :WAKEUP1 event
* - EVRT_SRC_WAKEUP2 :WAKEUP2 event
* - EVRT_SRC_WAKEUP3 :WAKEUP3 event
* - EVRT_SRC_ATIMER :Alarm timer eveny
* - EVRT_SRC_RTC :RTC event
* - EVRT_SRC_BOD :BOD event
* - EVRT_SRC_WWDT :WWDT event
* - EVRT_SRC_ETHERNET :ETHERNET event
* - EVRT_SRC_USB0 :USB0 event
* - EVRT_SRC_USB1 :USB1 event
* - EVRT_SRC_CCAN :CCAN event
* - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event
* - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event
* - EVRT_SRC_QEI :QEI event
* - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event
* - EVRT_SRC_RESET :RESET event
* @param[in] state ENABLE or DISABLE
* @return None
**********************************************************************/
void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state)
{
CHECK_PARAM(PARAM_EVRTx(EVRTx));
CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));
if(state == ENABLE)
EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);
else
EVRTx->CLR_EN = (1<<(uint8_t)EVRT_Src);
}
/*********************************************************************//**
* @brief Check if a source is sending interrupt to EVRT
* @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT
* @param[in] EVRT_Src EVRT source, should be:
* - EVRT_SRC_WAKEUP0 :WAKEUP0 event
* - EVRT_SRC_WAKEUP1 :WAKEUP1 event
* - EVRT_SRC_WAKEUP2 :WAKEUP2 event
* - EVRT_SRC_WAKEUP3 :WAKEUP3 event
* - EVRT_SRC_ATIMER :Alarm timer eveny
* - EVRT_SRC_RTC :RTC event
* - EVRT_SRC_BOD :BOD event
* - EVRT_SRC_WWDT :WWDT event
* - EVRT_SRC_ETHERNET :ETHERNET event
* - EVRT_SRC_USB0 :USB0 event
* - EVRT_SRC_USB1 :USB1 event
* - EVRT_SRC_CCAN :CCAN event
* - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event
* - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event
* - EVRT_SRC_QEI :QEI event
* - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event
* - EVRT_SRC_RESET :RESET event
* @return TRUE or FALSE
**********************************************************************/
Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src)
{
CHECK_PARAM(PARAM_EVRTx(EVRTx));
CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));
if(EVRTx->STATUS & (1<<(uint8_t)EVRT_Src))
return TRUE;
else return FALSE;
}
/*********************************************************************//**
* @brief Clear pending interrupt EVRT source
* @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT
* @param[in] EVRT_Src EVRT source, should be:
* - EVRT_SRC_WAKEUP0 :WAKEUP0 event
* - EVRT_SRC_WAKEUP1 :WAKEUP1 event
* - EVRT_SRC_WAKEUP2 :WAKEUP2 event
* - EVRT_SRC_WAKEUP3 :WAKEUP3 event
* - EVRT_SRC_ATIMER :Alarm timer eveny
* - EVRT_SRC_RTC :RTC event
* - EVRT_SRC_BOD :BOD event
* - EVRT_SRC_WWDT :WWDT event
* - EVRT_SRC_ETHERNET :ETHERNET event
* - EVRT_SRC_USB0 :USB0 event
* - EVRT_SRC_USB1 :USB1 event
* - EVRT_SRC_CCAN :CCAN event
* - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event
* - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event
* - EVRT_SRC_QEI :QEI event
* - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event
* - EVRT_SRC_RESET :RESET event
* @return none
**********************************************************************/
void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src)
{
CHECK_PARAM(PARAM_EVRTx(EVRTx));
CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));
EVRTx->CLR_STAT = (1<<(uint8_t)EVRT_Src);
}
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

567
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c vendored
View file

@ -1,567 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_gpdma.c 2011-06-02
*//**
* @file lpc18xx_gpdma.c
* @brief Contains all functions support for GPDMA firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup GPDMA
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_gpdma.h"
//#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _GPDMA
/** GPDMA Mux definitions */
#define DMAMUX_ADDRESS 0x4004311C
/* Private Functions ----------------------------------------------------------- */
/** @
* @{
*/
uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number);
/**
* @}
*/
/* Private Variables ---------------------------------------------------------- */
/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
* @{
*/
/**
* @brief Lookup Table of Connection Type matched with
* Peripheral Data (FIFO) register base address
*/
#ifdef __ICCARM__
volatile const void *GPDMA_LUTPerAddr[] = {
(&LPC_SPIFI->DAT), // SPIFI
(&LPC_TIMER0->MR), // MAT0.0
(&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx
((uint32_t*)&LPC_TIMER0->MR + 1), // MAT0.1
(&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx
(&LPC_TIMER1->MR), // MAT1.0
(&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
((uint32_t*)&LPC_TIMER1->MR + 1), // MAT1.1
(&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
(&LPC_TIMER2->MR), // MAT2.0
(&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx
((uint32_t*)&LPC_TIMER2->MR + 1), // MAT2.1
(&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx
(&LPC_TIMER3->MR), // MAT3.0
(&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx
0, // to be defined: SCT DMA request 0
((uint32_t*)&LPC_TIMER3->MR + 1), // MAT3.1
(&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx
0, // to be defined: SCT DMA request 1
(&LPC_SSP0->DR), // SSP0 Rx
(&LPC_I2S0->TXFIFO), // I2S channel 0
(&LPC_SSP0->DR), // SSP0 Tx
(&LPC_I2S0->RXFIFO), // I2S channel 1
(&LPC_SSP1->DR), // SSP1 Rx
(&LPC_SSP1->DR), // SSP1 Tx
(&LPC_ADC0->GDR), // ADC 0
(&LPC_ADC1->GDR), // ADC 1
(&LPC_DAC->CR) // DAC
};
#else
const uint32_t GPDMA_LUTPerAddr[] = {
// ((uint32_t)&LPC_SPIFI->DAT), // SPIFI
((uint32_t)0), // SPIFI
((uint32_t)&LPC_TIMER0->MR[0]), // MAT0.0
((uint32_t)&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx
((uint32_t)&LPC_TIMER0->MR[1]), // MAT0.1
((uint32_t)&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx
((uint32_t)&LPC_TIMER1->MR[0]), // MAT1.0
((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
((uint32_t)&LPC_TIMER1->MR[1]), // MAT1.1
((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
((uint32_t)&LPC_TIMER2->MR[0]), // MAT2.0
((uint32_t)&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx
((uint32_t)&LPC_TIMER2->MR[1]), // MAT2.1
((uint32_t)&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx
((uint32_t)&LPC_TIMER3->MR[0]), // MAT3.0
((uint32_t)&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx
0, // to be defined: SCT DMA request 0
((uint32_t)&LPC_TIMER3->MR[1]), // MAT3.1
((uint32_t)&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx
0, // to be defined: SCT DMA request 1
((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
((uint32_t)&LPC_I2S0->TXFIFO), // I2S channel 0
((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
((uint32_t)&LPC_I2S0->RXFIFO), // I2S channel 1
((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
((uint32_t)&LPC_ADC0->GDR), // ADC 0
((uint32_t)&LPC_ADC1->GDR), // ADC 1
((uint32_t)&LPC_DAC->CR) // DAC
};
#endif
/**
* @brief Lookup Table of GPDMA Channel Number matched with
* GPDMA channel pointer
*/
const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
LPC_GPDMACH0, // GPDMA Channel 0
LPC_GPDMACH1, // GPDMA Channel 1
LPC_GPDMACH2, // GPDMA Channel 2
LPC_GPDMACH3, // GPDMA Channel 3
LPC_GPDMACH4, // GPDMA Channel 4
LPC_GPDMACH5, // GPDMA Channel 5
LPC_GPDMACH6, // GPDMA Channel 6
LPC_GPDMACH7, // GPDMA Channel 7
};
/**
* @brief Optimized Peripheral Source and Destination burst size
*/
const uint8_t GPDMA_LUTPerBurst[] = {
GPDMA_BSIZE_4, // SPIFI
GPDMA_BSIZE_1, // MAT0.0
GPDMA_BSIZE_1, // UART0 Tx
GPDMA_BSIZE_1, // MAT0.1
GPDMA_BSIZE_1, // UART0 Rx
GPDMA_BSIZE_1, // MAT1.0
GPDMA_BSIZE_1, // UART1 Tx
GPDMA_BSIZE_1, // MAT1.1
GPDMA_BSIZE_1, // UART1 Rx
GPDMA_BSIZE_1, // MAT2.0
GPDMA_BSIZE_1, // UART2 Tx
GPDMA_BSIZE_1, // MAT2.1
GPDMA_BSIZE_1, // UART2 Rx
GPDMA_BSIZE_1, // MAT3.0
GPDMA_BSIZE_1, // UART3 Tx
0, // to be defined: SCT DMA request 0
GPDMA_BSIZE_1, // MAT3.1
GPDMA_BSIZE_1, // UART3 Rx
0, // to be defined: SCT DMA request 1
GPDMA_BSIZE_4, // SSP0 Rx
GPDMA_BSIZE_32, // I2S channel 0
GPDMA_BSIZE_4, // SSP0 Tx
GPDMA_BSIZE_32, // I2S channel 1
GPDMA_BSIZE_4, // SSP1 Rx
GPDMA_BSIZE_4, // SSP1 Tx
GPDMA_BSIZE_4, // ADC 0
GPDMA_BSIZE_4, // ADC 1
GPDMA_BSIZE_1, // DAC
};
/**
* @brief Optimized Peripheral Source and Destination transfer width
*/
const uint8_t GPDMA_LUTPerWid[] = {
GPDMA_WIDTH_WORD, // SPIFI
GPDMA_WIDTH_WORD, // MAT0.0
GPDMA_WIDTH_BYTE, // UART0 Tx
GPDMA_WIDTH_WORD, // MAT0.1
GPDMA_WIDTH_BYTE, // UART0 Rx
GPDMA_WIDTH_WORD, // MAT1.0
GPDMA_WIDTH_BYTE, // UART1 Tx
GPDMA_WIDTH_WORD, // MAT1.1
GPDMA_WIDTH_BYTE, // UART1 Rx
GPDMA_WIDTH_WORD, // MAT2.0
GPDMA_WIDTH_BYTE, // UART2 Tx
GPDMA_WIDTH_WORD, // MAT2.1
GPDMA_WIDTH_BYTE, // UART2 Rx
GPDMA_WIDTH_WORD, // MAT3.0
GPDMA_WIDTH_BYTE, // UART3 Tx
0, // to be defined: SCT DMA request 0
GPDMA_WIDTH_WORD, // MAT3.1
GPDMA_WIDTH_BYTE, // UART3 Rx
0, // to be defined: SCT DMA request 1
GPDMA_WIDTH_BYTE, // SSP0 Rx
GPDMA_WIDTH_WORD, // I2S channel 0
GPDMA_WIDTH_BYTE, // SSP0 Tx
GPDMA_WIDTH_WORD, // I2S channel 1
GPDMA_WIDTH_BYTE, // SSP1 Rx
GPDMA_WIDTH_BYTE, // SSP1 Tx
GPDMA_WIDTH_WORD, // ADC 0
GPDMA_WIDTH_WORD, // ADC 1
GPDMA_WIDTH_WORD, // DAC
};
/**
* @}
*/
/* Private Functions ----------------------------------------------------------- */
/** @
* @{
*/
/********************************************************************//**
* @brief Control which set of peripherals is connected to the
* DMA controller
* @param[in] gpdma_peripheral_connection_number GPDMA peripheral
* connection number, should be:
* - GPDMA_CONN_SPIFI :SPIFI
* - GPDMA_CONN_MAT0_0 :Timer 0, match channel 0
* - GPDMA_CONN_MAT0_1 :Timer 0, match channel 1
* - GPDMA_CONN_MAT1_0 :Timer 1, match channel 0
* - GPDMA_CONN_MAT1_1 :Timer 1, match channel 1
* - GPDMA_CONN_MAT2_0 :Timer 2, match channel 0
* - GPDMA_CONN_MAT2_1 :Timer 2, match channel 1
* - GPDMA_CONN_MAT3_0 :Timer 3, match channel 0
* - GPDMA_CONN_MAT3_1 :Timer 3, match channel 1
* - GPDMA_CONN_UART0_Tx :USART 0 transmit
* - GPDMA_CONN_UART0_Rx :USART 0 receive
* - GPDMA_CONN_UART1_Tx :USART 1 transmit
* - GPDMA_CONN_UART1_Rx :USART 1 receive
* - GPDMA_CONN_UART2_Tx :USART 2 transmit
* - GPDMA_CONN_UART2_Rx :USART 2 receive
* - GPDMA_CONN_UART3_Tx :USART 3 transmit
* - GPDMA_CONN_UART3_Rx :USART 3 receive
* - GPDMA_CONN_SCT_0 :SCT output 0
* - GPDMA_CONN_SCT_1 :SCT output 1
* - GPDMA_CONN_I2S_Channel_0 :I2S channel 0
* - GPDMA_CONN_I2S_Channel_1 :I2S channel 1
* - GPDMA_CONN_SSP0_Tx :SSP0 transmit
* - GPDMA_CONN_SSP0_Rx :SSP0 receive
* - GPDMA_CONN_SSP1_Tx :SSP1 transmit
* - GPDMA_CONN_SSP1_Rx :SSP1 receive
* - GPDMA_CONN_ADC_0 :ADC0
* - GPDMA_CONN_ADC_1 :ADC1
* - GPDMA_CONN_DAC :DAC
* @return channel number, could be in range: 0..16
*********************************************************************/
uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)
{
uint32_t *dmamux_reg = (uint32_t*)DMAMUX_ADDRESS;
uint8_t function, channel;
switch(gpdma_peripheral_connection_number)
{
case GPDMA_CONN_SPIFI: function = 0; channel = 0; break;
case GPDMA_CONN_MAT0_0: function = 0; channel = 1; break;
case GPDMA_CONN_UART0_Tx: function = 1; channel = 1; break;
case GPDMA_CONN_MAT0_1: function = 0; channel = 2; break;
case GPDMA_CONN_UART0_Rx: function = 1; channel = 2; break;
case GPDMA_CONN_MAT1_0: function = 0; channel = 3; break;
case GPDMA_CONN_UART1_Tx: function = 1; channel = 3; break;
case GPDMA_CONN_MAT1_1: function = 0; channel = 4; break;
case GPDMA_CONN_UART1_Rx: function = 1; channel = 4; break;
case GPDMA_CONN_MAT2_0: function = 0; channel = 5; break;
case GPDMA_CONN_UART2_Tx: function = 1; channel = 5; break;
case GPDMA_CONN_MAT2_1: function = 0; channel = 6; break;
case GPDMA_CONN_UART2_Rx: function = 1; channel = 6; break;
case GPDMA_CONN_MAT3_0: function = 0; channel = 7; break;
case GPDMA_CONN_UART3_Tx: function = 1; channel = 7; break;
case GPDMA_CONN_SCT_0: function = 2; channel = 7; break;
case GPDMA_CONN_MAT3_1: function = 0; channel = 8; break;
case GPDMA_CONN_UART3_Rx: function = 1; channel = 8; break;
case GPDMA_CONN_SCT_1: function = 2; channel = 8; break;
case GPDMA_CONN_SSP0_Rx: function = 0; channel = 9; break;
case GPDMA_CONN_I2S_Channel_0:function = 1; channel = 9; break;
case GPDMA_CONN_SSP0_Tx: function = 0; channel = 10; break;
case GPDMA_CONN_I2S_Channel_1:function = 1; channel = 10; break;
case GPDMA_CONN_SSP1_Rx: function = 0; channel = 11; break;
case GPDMA_CONN_SSP1_Tx: function = 0; channel = 12; break;
case GPDMA_CONN_ADC_0: function = 0; channel = 13; break;
case GPDMA_CONN_ADC_1: function = 0; channel = 14; break;
case GPDMA_CONN_DAC: function = 0; channel = 15; break;
default: function = 3; channel = 15; break;
}
//Set select function to dmamux register
*dmamux_reg &= ~(0x03<<(2*channel));
*dmamux_reg |= (function<<(2*channel));
return channel;
}
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup GPDMA_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initialize GPDMA controller
* @param[in] None
* @return None
*********************************************************************/
void GPDMA_Init(void)
{
/* to be defined Enable GPDMA clock */
// enabled default on reset
// Reset all channel configuration register
LPC_GPDMACH0->CConfig = 0;
LPC_GPDMACH1->CConfig = 0;
LPC_GPDMACH2->CConfig = 0;
LPC_GPDMACH3->CConfig = 0;
LPC_GPDMACH4->CConfig = 0;
LPC_GPDMACH5->CConfig = 0;
LPC_GPDMACH6->CConfig = 0;
LPC_GPDMACH7->CConfig = 0;
/* Clear all DMA interrupt and error flag */
LPC_GPDMA->INTTCCLEAR = 0xFF;
LPC_GPDMA->INTERRCLR = 0xFF;
}
/********************************************************************//**
* @brief Setup GPDMA channel peripheral according to the specified
* parameters in the GPDMAChannelConfig.
* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure
* that contains the configuration information for the specified
* GPDMA channel peripheral.
* @return Setup status, could be:
* - ERROR :if selected channel is enabled before
* - SUCCESS :if channel is configured successfully
*********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
LPC_GPDMACH_TypeDef *pDMAch;
uint8_t SrcPeripheral=0, DestPeripheral=0;
if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
// This channel is enabled, return ERROR, need to release this channel first
return ERROR;
}
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
// Reset the Interrupt status
LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
// Clear DMA configure
pDMAch->CControl = 0x00;
pDMAch->CConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
/* Set value to Channel Control Registers */
switch (GPDMAChannelConfig->TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
// Assign physical source and destination address
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
// Assign physical source
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
//to be defined
// Do not support any more transfer type, return ERROR
default:
return ERROR;
}
/* Enable DMA channels, little endian */
LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;
while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));
// Configure DMA Channel, enable Error Counter and Terminate counter
pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \
| GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);
return SUCCESS;
}
/*********************************************************************//**
* @brief Enable/Disable DMA channel
* @param[in] channelNum GPDMA channel, should be in range from 0 to 15
* @param[in] NewState New State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
**********************************************************************/
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
{
LPC_GPDMACH_TypeDef *pDMAch;
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
if (NewState == ENABLE) {
pDMAch->CConfig |= GPDMA_DMACCxConfig_E;
} else {
pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;
}
}
/*********************************************************************//**
* @brief Check if corresponding channel does have an active interrupt
* request or not
* @param[in] type type of status, should be:
* - GPDMA_STAT_INT :GPDMA Interrupt Status
* - GPDMA_STAT_INTTC :GPDMA Interrupt Terminal Count Request Status
* - GPDMA_STAT_INTERR :GPDMA Interrupt Error Status
* - GPDMA_STAT_RAWINTTC :GPDMA Raw Interrupt Terminal Count Status
* - GPDMA_STAT_RAWINTERR :GPDMA Raw Error Interrupt Status
* - GPDMA_STAT_ENABLED_CH :GPDMA Enabled Channel Status
* @param[in] channel GPDMA channel, should be in range from 0 to 7
* @return IntStatus status of DMA channel interrupt after masking
* Should be:
* - SET :the corresponding channel has no active interrupt request
* - RESET :the corresponding channel does have an active interrupt request
**********************************************************************/
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
{
CHECK_PARAM(PARAM_GPDMA_STAT(type));
CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
switch (type)
{
case GPDMA_STAT_INT: //check status of DMA channel interrupts
if (LPC_GPDMA->INTSTAT & (GPDMA_DMACIntStat_Ch(channel)))
return SET;
return RESET;
case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntTCClear_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
if (LPC_GPDMA->RAWINTERRSTAT & GPDMA_DMACRawIntTCStat_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
if (LPC_GPDMA->RAWINTTCSTAT & GPDMA_DMACRawIntErrStat_Ch(channel))
return SET;
return RESET;
default: //check enable status for DMA channels
if (LPC_GPDMA->ENBLDCHNS & GPDMA_DMACEnbldChns_Ch(channel))
return SET;
return RESET;
}
}
/*********************************************************************//**
* @brief Clear one or more interrupt requests on DMA channels
* @param[in] type type of interrupt request, should be:
* - GPDMA_STATCLR_INTTC :GPDMA Interrupt Terminal Count Request Clear
* - GPDMA_STATCLR_INTERR :GPDMA Interrupt Error Clear
* @param[in] channel GPDMA channel, should be in range from 0 to 15
* @return None
**********************************************************************/
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
{
CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(channel);
else // clear the error interrupt request
LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(channel);
}
/**
* @}
*/
#endif /* _GPDMA */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

816
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpio.c vendored
View file

@ -1,816 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_gpio.c 2011-06-02
*//**
* @file lpc18xx_gpio.c
* @brief Contains all functions support for GPIO firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup GPIO
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_gpio.h"
#include "lpc_types.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _GPIO
/* Private Functions ---------------------------------------------------------- */
//static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum);
//static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum);
//static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum);
#if 0
/*********************************************************************//**
* @brief Get pointer to GPIO peripheral due to GPIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to GPIO peripheral
**********************************************************************/
static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum)
{
LPC_GPIOn_Type *pGPIO = NULL;
switch (portNum)
{
case 0:
pGPIO = LPC_GPIO0;
break;
case 1:
pGPIO = LPC_GPIO1;
break;
case 2:
pGPIO = LPC_GPIO2;
break;
case 3:
pGPIO = LPC_GPIO3;
break;
case 4:
pGPIO = LPC_GPIO4;
break;
default:
break;
}
return pGPIO;
}
/*********************************************************************//**
* @brief Get pointer to FIO peripheral in halfword accessible style
* due to FIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to FIO peripheral
**********************************************************************/
static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum)
{
GPIO_HalfWord_TypeDef *pFIO = NULL;
switch (portNum)
{
case 0:
pFIO = GPIO0_HalfWord;
break;
case 1:
pFIO = GPIO1_HalfWord;
break;
case 2:
pFIO = GPIO2_HalfWord;
break;
case 3:
pFIO = GPIO3_HalfWord;
break;
case 4:
pFIO = GPIO4_HalfWord;
break;
default:
break;
}
return pFIO;
}
/*********************************************************************//**
* @brief Get pointer to FIO peripheral in byte accessible style
* due to FIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to FIO peripheral
**********************************************************************/
static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum)
{
GPIO_Byte_TypeDef *pFIO = NULL;
switch (portNum)
{
case 0:
pFIO = GPIO0_Byte;
break;
case 1:
pFIO = GPIO1_Byte;
break;
case 2:
pFIO = GPIO2_Byte;
break;
case 3:
pFIO = GPIO3_Byte;
break;
case 4:
pFIO = GPIO4_Byte;
break;
default:
break;
}
return pFIO;
}
#endif
/* End of Private Functions --------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup GPIO_Public_Functions
* @{
*/
/* GPIO ------------------------------------------------------------------------------ */
/*********************************************************************//**
* @brief Set Direction for GPIO port.
* @param[in] portNum Port Number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits to set direction,
* in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to set direction for bit 0 and bit 1.
* @param[in] dir Direction value, should be:
* - 0: Input.
* - 1: Output.
* @return None
*
* Note:
* All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
{
if (dir)
{
LPC_GPIO_PORT->DIR[portNum] |= bitValue;
} else
{
LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;
}
}
/*********************************************************************//**
* @brief Set Value for bits that have output direction on GPIO port.
* @param[in] portNum Port number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits on GPIO to set, should
* be in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to set bit 0 and bit 1.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
{
LPC_GPIO_PORT->SET[portNum] = bitValue;
}
/*********************************************************************//**
* @brief Clear Value for bits that have output direction on GPIO port.
* @param[in] portNum Port number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits on GPIO to clear, should
* be in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to clear bit 0 and bit 1.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
{
LPC_GPIO_PORT->CLR[portNum] = bitValue;
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* @param[in] portNum Port number to read value, in range from 0 to 4
* @return Current value of GPIO port.
*
* Note: Return value contain state of each port pin (bit) on that GPIO regardless
* its direction is input or output.
**********************************************************************/
uint32_t GPIO_ReadValue(uint8_t portNum)
{
return LPC_GPIO_PORT->PIN[portNum];
}
#ifdef GPIO_INT
/*********************************************************************//**
* @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] bitValue Value that contains all bits on GPIO to enable,
* should be in range from 0 to 0xFFFFFFFF.
* @param[in] edgeState state of edge, should be:
* - 0: Rising edge
* - 1: Falling edge
* @return None
**********************************************************************/
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
{
if((portNum == 0)&&(edgeState == 0))
LPC_GPIOINT->IO0IntEnR = bitValue;
else if ((portNum == 2)&&(edgeState == 0))
LPC_GPIOINT->IO2IntEnR = bitValue;
else if ((portNum == 0)&&(edgeState == 1))
LPC_GPIOINT->IO0IntEnF = bitValue;
else if ((portNum == 2)&&(edgeState == 1))
LPC_GPIOINT->IO2IntEnF = bitValue;
else
//Error
while(1);
}
/*********************************************************************//**
* @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13
* (with port 2)
* @param[in] edgeState state of edge, should be:
* - 0 :Rising edge
* - 1 :Falling edge
* @return Function status, could be:
* - ENABLE :Interrupt has been generated due to a rising edge on P0.0
* - DISABLE :A rising edge has not been detected on P0.0
**********************************************************************/
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
{
if((portNum == 0) && (edgeState == 0))//Rising Edge
return (((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1);
else if ((portNum == 2) && (edgeState == 0))
return (((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1);
else if ((portNum == 0) && (edgeState == 1))//Falling Edge
return (((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1);
else if ((portNum == 2) && (edgeState == 1))
return (((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1);
else
//Error
while(1);
}
/*********************************************************************//**
* @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] bitValue Value that contains all bits on GPIO to enable,
* should be in range from 0 to 0xFFFFFFFF.
* @return None
**********************************************************************/
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue)
{
if(portNum == 0)
LPC_GPIOINT->IO0IntClr = bitValue;
else if (portNum == 2)
LPC_GPIOINT->IO2IntClr = bitValue;
else
//Invalid portNum
while(1);
}
#endif
/* FIO word accessible ----------------------------------------------------------------- */
/* Stub function for FIO (word-accessible) style */
/**
* @brief The same with GPIO_SetDir()
*/
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
{
GPIO_SetDir(portNum, bitValue, dir);
}
/**
* @brief The same with GPIO_SetValue()
*/
void FIO_SetValue(uint8_t portNum, uint32_t bitValue)
{
GPIO_SetValue(portNum, bitValue);
}
/**
* @brief The same with GPIO_ClearValue()
*/
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
{
GPIO_ClearValue(portNum, bitValue);
}
/**
* @brief The same with GPIO_ReadValue()
*/
uint32_t FIO_ReadValue(uint8_t portNum)
{
return (GPIO_ReadValue(portNum));
}
#ifdef GPIO_INT
/**
* @brief The same with GPIO_IntCmd()
*/
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
{
GPIO_IntCmd(portNum, bitValue, edgeState);
}
/**
* @brief The same with GPIO_GetIntStatus()
*/
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
{
return (GPIO_GetIntStatus(portNum, pinNum, edgeState));
}
/**
* @brief The same with GPIO_ClearInt()
*/
void FIO_ClearInt(uint8_t portNum, uint32_t bitValue)
{
GPIO_ClearInt(portNum, bitValue);
}
#endif
/*********************************************************************//**
* @brief Set mask value for bits in FIO port
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] bitValue Value that contains all bits in to set, should be
* in range from 0 to 0xFFFFFFFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0 :not mask.
* - 1 :mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue)
{
if (maskValue)
{
LPC_GPIO_PORT->MASK[portNum] |= bitValue;
} else
{
LPC_GPIO_PORT->MASK[portNum] &= ~bitValue;
}
}
/* FIO halfword accessible ------------------------------------------------------------- */
#if 0
/*********************************************************************//**
* @brief Set direction for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set direction,
* in range from 0 to 0xFFFF.
* @param[in] dir Direction value, should be:
* - 0 :Input.
* - 1 :Output.
* @return None
*
* Note: All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Output direction
if (dir)
{
// Upper
if(halfwordNum)
{
pFIO->FIODIRU |= bitValue;
}
// lower
else
{
pFIO->FIODIRL |= bitValue;
}
}
// Input direction
else
{
// Upper
if(halfwordNum)
{
pFIO->FIODIRU &= ~bitValue;
}
// lower
else
{
pFIO->FIODIRL &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set mask value for bits in FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set,
* in range from 0 to 0xFFFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0: not mask.
* - 1: mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Mask
if (maskValue)
{
// Upper
if(halfwordNum)
{
pFIO->FIOMASKU |= bitValue;
}
// lower
else
{
pFIO->FIOMASKL |= bitValue;
}
}
// Un-mask
else
{
// Upper
if(halfwordNum)
{
pFIO->FIOMASKU &= ~bitValue;
}
// lower
else
{
pFIO->FIOMASKL &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set bits for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set, should be
* in range from 0 to 0xFFFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
pFIO->FIOSETU = bitValue;
}
// lower
else
{
pFIO->FIOSETL = bitValue;
}
}
}
/*********************************************************************//**
* @brief Clear bits for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to clear, should be
* in range from 0 to 0xFFFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
pFIO->FIOCLRU = bitValue;
}
// lower
else
{
pFIO->FIOCLRL = bitValue;
}
}
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* in halfword accessible style.
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @return Current value of FIO port pin of specified halfword.
* Note: Return value contain state of each port pin (bit) on that FIO regardless
* its direction is input or output.
**********************************************************************/
uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
return (pFIO->FIOPINU);
}
// lower
else
{
return (pFIO->FIOPINL);
}
}
return (0);
}
/* FIO Byte accessible ------------------------------------------------------------ */
/*********************************************************************//**
* @brief Set direction for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set direction,
* in range from 0 to 0xFF.
* @param[in] dir Direction value, should be:
* - 0: Input.
* - 1: Output.
* @return None
*
* Note: All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if(pFIO != NULL)
{
// Output direction
if (dir)
{
if (byteNum <= 3)
{
pFIO->FIODIR[byteNum] |= bitValue;
}
}
// Input direction
else
{
if (byteNum <= 3)
{
pFIO->FIODIR[byteNum] &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set mask value for bits in FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set mask, should
* be in range from 0 to 0xFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0: not mask.
* - 1: mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if(pFIO != NULL)
{
// Mask
if (maskValue)
{
if (byteNum <= 3)
{
pFIO->FIOMASK[byteNum] |= bitValue;
}
}
// Un-mask
else {
if (byteNum <= 3)
{
pFIO->FIOMASK[byteNum] &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set bits for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set, should
* be in range from 0 to 0xFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL) {
if (byteNum <= 3)
{
pFIO->FIOSET[byteNum] = bitValue;
}
}
}
/*********************************************************************//**
* @brief Clear bits for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to clear, should
* be in range from 0 to 0xFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL)
{
if (byteNum <= 3)
{
pFIO->FIOCLR[byteNum] = bitValue;
}
}
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* in byte accessible style.
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @return Current value of FIO port pin of specified byte part.
* Note: Return value contain state of each port pin (bit) on that FIO regardless
* its direction is input or output.
**********************************************************************/
uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL)
{
if (byteNum <= 3)
{
return (pFIO->FIOPIN[byteNum]);
}
}
return (0);
}
#endif
/**
* @}
*/
#endif /* _GPIO */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

1329
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c vendored
View file

File diff suppressed because it is too large Load diff

663
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c vendored
View file

@ -1,663 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_i2s.c 2011-06-02
*//**
* @file lpc18xx_i2s.c
* @brief Contains all functions support for I2S firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup I2S
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_i2s.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _I2S
/* Private Functions ---------------------------------------------------------- */
static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
/********************************************************************//**
* @brief Get I2S wordwidth value
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is the I2S mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return The wordwidth value, should be: 8,16 or 32
*********************************************************************/
static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {
uint8_t value;
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) {
value = (I2Sx->DAO) & 0x03; /* get wordwidth bit */
} else {
value = (I2Sx->DAI) & 0x03; /* get wordwidth bit */
}
switch (value) {
case I2S_WORDWIDTH_8:
return 8;
case I2S_WORDWIDTH_16:
return 16;
default:
return 32;
}
}
/********************************************************************//**
* @brief Get I2S channel value
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is the I2S mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return The channel value, should be: 1(mono) or 2(stereo)
*********************************************************************/
static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {
uint8_t value;
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) {
value = (I2Sx->DAO) & 0x04; /* get bit[2] */
} else {
value = (I2Sx->DAI) & 0x04; /* get bit[2] */
}
value >>= 2;
if(value == I2S_MONO) return 1;
return 2;
}
/* End of Private Functions --------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup I2S_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initialize I2S
* - Turn on power and clock
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_Init(LPC_I2Sn_Type *I2Sx) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
// Turn on power and clock
//CGU_ConfigPPWR(CGU_PCONP_PCI2S, ENABLE);
I2Sx->DAI = I2Sx->DAO = 0x00;
}
/********************************************************************//**
* @brief Configuration I2S, setting:
* - master/slave mode
* - wordwidth value
* - channel mode
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @param[in] ConfigStruct pointer to I2S_CFG_Type structure
* which will be initialized.
* @return none
*********************************************************************/
void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct)
{
uint32_t bps, config;
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_WORDWIDTH(ConfigStruct->wordwidth));
CHECK_PARAM(PARAM_I2S_CHANNEL(ConfigStruct->mono));
CHECK_PARAM(PARAM_I2S_STOP(ConfigStruct->stop));
CHECK_PARAM(PARAM_I2S_RESET(ConfigStruct->reset));
CHECK_PARAM(PARAM_I2S_WS_SEL(ConfigStruct->ws_sel));
CHECK_PARAM(PARAM_I2S_MUTE(ConfigStruct->mute));
/* Setup clock */
bps = (ConfigStruct->wordwidth +1)*8;
/* Calculate audio config */
config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 |
(ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth);
if(TRMode == I2S_RX_MODE){
I2Sx->DAI = config;
}else{
I2Sx->DAO = config;
}
}
/********************************************************************//**
* @brief DeInitial both I2S transmit or receive
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_DeInit(LPC_I2Sn_Type *I2Sx) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
// Turn off power and clock
//CGU_ConfigPPWR(CGU_PCONP_PCI2S, DISABLE);
}
/********************************************************************//**
* @brief Get I2S Buffer Level
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode Transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return current level of Transmit/Receive Buffer
*********************************************************************/
uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if(TRMode == I2S_TX_MODE)
{
return ((I2Sx->STATE >> 16) & 0xFF);
}
else
{
return ((I2Sx->STATE >> 8) & 0xFF);
}
}
/********************************************************************//**
* @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_Start(LPC_I2Sn_Type *I2Sx)
{
//Clear STOP,RESET and MUTE bit
I2Sx->DAO &= ~I2S_DAI_RESET;
I2Sx->DAI &= ~I2S_DAI_RESET;
I2Sx->DAO &= ~I2S_DAI_STOP;
I2Sx->DAI &= ~I2S_DAI_STOP;
I2Sx->DAO &= ~I2S_DAI_MUTE;
}
/********************************************************************//**
* @brief I2S Send data
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] BufferData pointer to uint32_t is the data will be send
* @return none
*********************************************************************/
void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
I2Sx->TXFIFO = BufferData;
}
/********************************************************************//**
* @brief I2S Receive Data
* @param[in] I2Sx pointer to LPC_I2Sn_Type, should be: LPC_I2S
* @return received value
*********************************************************************/
uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
return (I2Sx->RXFIFO);
}
/********************************************************************//**
* @brief I2S Pause
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO |= I2S_DAO_STOP;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_STOP;
}
}
/********************************************************************//**
* @brief I2S Mute
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO |= I2S_DAO_MUTE;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_MUTE;
}
}
/********************************************************************//**
* @brief I2S Stop
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO &= ~I2S_DAO_MUTE;
I2Sx->DAO |= I2S_DAO_STOP;
I2Sx->DAO |= I2S_DAO_RESET;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_STOP;
I2Sx->DAI |= I2S_DAI_RESET;
}
}
/********************************************************************//**
* @brief Set frequency for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] Freq is the frequency for I2S will be set. It can range
* from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz)
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return Status: ERROR or SUCCESS
*********************************************************************/
Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode) {
/* Calculate bit rate
* The formula is:
* bit_rate = channel*wordwidth - 1
* 48kHz sample rate for 16 bit stereo date requires
* a bit rate of 48000*16*2=1536MHz (MCLK)
*/
uint32_t i2sPclk;
uint64_t divider;
uint8_t bitrate, channel, wordwidth;
uint32_t x, y;
uint16_t dif;
uint16_t error;
uint16_t x_divide, y_divide;
uint16_t ErrorOptimal = 0xFFFF;
uint32_t N;
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PRAM_I2S_FREQ(Freq));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
//LPC_CGU->BASE_VPB1_CLK = 0x08<<24 | AUTO_BLOCK;
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);
i2sPclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_I2S);
if(TRMode == I2S_TX_MODE)
{
channel = i2s_GetChannel(I2Sx,I2S_TX_MODE);
wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE);
}
else
{
channel = i2s_GetChannel(I2Sx,I2S_RX_MODE);
wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE);
}
bitrate = 2 * wordwidth - 1;
/* Calculate X and Y divider
* The MCLK rate for the I2S transmitter is determined by the value
* in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE
* setting depends on the desired audio sample rate desired, the format
* (stereo/mono) used, and the data size.
* The formula is:
* I2S_MCLK = PCLK * (X/Y) / 2
* We have:
* I2S_MCLK = Freq * bit_rate * I2Sx->TXBITRATE;
* So: (X/Y) = (Freq * bit_rate * I2Sx->TXBITRATE)/PCLK*2
* We use a loop function to chose the most suitable X,Y value
*/
/* divider is a fixed point number with 16 fractional bits */
divider = ((uint64_t)(Freq *( bitrate+1) * 2)<<16) / i2sPclk;
/* find N that make x/y <= 1 -> divider <= 2^16 */
for(N=64;N>=0;N--){
if((divider*N) < (1<<16)) break;
}
if(N == 0) return ERROR;
divider *= N;
for (y = 255; y > 0; y--) {
x = y * divider;
if(x & (0xFF000000)) continue;
dif = x & 0xFFFF;
if(dif>0x8000) error = 0x10000-dif;
else error = dif;
if (error == 0)
{
y_divide = y;
break;
}
else if (error < ErrorOptimal)
{
ErrorOptimal = error;
y_divide = y;
}
}
x_divide = ((uint64_t)y_divide * Freq *( bitrate+1)* N * 2)/i2sPclk;
if(x_divide >= 256) x_divide = 0xFF;
if(x_divide == 0) x_divide = 1;
if (TRMode == I2S_TX_MODE)// Transmitter
{
I2Sx->TXBITRATE = N;
I2Sx->TXRATE = y_divide | (x_divide << 8);
} else //Receiver
{
I2Sx->RXBITRATE = N;
I2Sx->RXRATE = y_divide | (x_divide << 8);
}
return SUCCESS;
}
/********************************************************************//**
* @brief I2S set bitrate
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] bitrate value will be set, it can be calculate as follows:
* bitrate = channel * wordwidth - 1
* bitrate value should be in range: 0 .. 63
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_BITRATE(bitrate));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if(TRMode == I2S_TX_MODE)
{
I2Sx->TXBITRATE = bitrate;
}
else
{
I2Sx->RXBITRATE = bitrate;
}
}
/********************************************************************//**
* @brief Configuration operating mode for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to
* configure
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig,
uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_CLKSEL(ModeConfig->clksel));
CHECK_PARAM(PARAM_I2S_4PIN(ModeConfig->fpin));
CHECK_PARAM(PARAM_I2S_MCLK(ModeConfig->mcena));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_TX_MODE) {
I2Sx->TXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
I2Sx->TXMODE |= 0x02;
}
if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
I2Sx->TXMODE |= (1 << 2);
}
if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
I2Sx->TXMODE |= (1 << 3);
}
} else {
I2Sx->RXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
I2Sx->RXMODE |= 0x02;
}
if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
I2Sx->RXMODE |= (1 << 2);
}
if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
I2Sx->RXMODE |= (1 << 3);
}
}
}
/********************************************************************//**
* @brief Configure DMA operation for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return none
*********************************************************************/
void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig,
uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_DMA(DMAConfig->DMAIndex));
CHECK_PARAM(PARAM_I2S_DMA_DEPTH(DMAConfig->depth));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_RX_MODE) {
if (DMAConfig->DMAIndex == I2S_DMA_1) {
I2Sx->DMA1 = (DMAConfig->depth) << 8;
} else {
I2Sx->DMA2 = (DMAConfig->depth) << 8;
}
} else {
if (DMAConfig->DMAIndex == I2S_DMA_1) {
I2Sx->DMA1 = (DMAConfig->depth) << 16;
} else {
I2Sx->DMA2 = (DMAConfig->depth) << 16;
}
}
}
/********************************************************************//**
* @brief Enable/Disable DMA operation for I2S
* @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S
* @param[in] DMAIndex chose what DMA is used, should be:
* - I2S_DMA_1 = 0 :DMA1
* - I2S_DMA_2 = 1 :DMA2
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @param[in] NewState is new state of DMA operation, should be:
* - ENABLE
* - DISABLE
* @return none
*********************************************************************/
void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex, uint8_t TRMode,
FunctionalState NewState)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
CHECK_PARAM(PARAM_I2S_DMA(DMAIndex));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
if (TRMode == I2S_RX_MODE) {
if (DMAIndex == I2S_DMA_1) {
if (NewState == ENABLE)
I2Sx->DMA1 |= 0x01;
else
I2Sx->DMA1 &= ~0x01;
} else {
if (NewState == ENABLE)
I2Sx->DMA2 |= 0x01;
else
I2Sx->DMA2 &= ~0x01;
}
} else {
if (DMAIndex == I2S_DMA_1) {
if (NewState == ENABLE)
I2Sx->DMA1 |= 0x02;
else
I2Sx->DMA1 &= ~0x02;
} else {
if (NewState == ENABLE)
I2Sx->DMA2 |= 0x02;
else
I2Sx->DMA2 &= ~0x02;
}
}
}
/********************************************************************//**
* @brief Configure IRQ for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @param[in] level is the FIFO level that triggers IRQ request
* @return none
*********************************************************************/
void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_I2S_TRX(TRMode));
CHECK_PARAM(PARAM_I2S_IRQ_LEVEL(level));
if (TRMode == I2S_RX_MODE) {
I2Sx->IRQ |= (level << 8);
} else {
I2Sx->IRQ |= (level << 16);
}
}
/********************************************************************//**
* @brief Enable/Disable IRQ for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @param[in] NewState is new state of DMA operation, should be:
* - ENABLE
* - DISABLE
* @return none
*********************************************************************/
void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, FunctionalState NewState) {
CHECK_PARAM(PARAM_I2Sx(I2Sx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (TRMode == I2S_RX_MODE) {
if (NewState == ENABLE)
I2Sx->IRQ |= 0x01;
else
I2Sx->IRQ &= ~0x01;
//Enable DMA
} else {
if (NewState == ENABLE)
I2Sx->IRQ |= 0x02;
else
I2Sx->IRQ &= ~0x02;
}
}
/********************************************************************//**
* @brief Get I2S interrupt status
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return FunctionState should be:
* - ENABLE :interrupt is enable
* - DISABLE :interrupt is disable
*********************************************************************/
FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
if(TRMode == I2S_TX_MODE)
return (FunctionalState)((I2Sx->IRQ >> 1)&0x01);
else
return (FunctionalState)((I2Sx->IRQ)&0x01);
}
/********************************************************************//**
* @brief Get I2S interrupt depth
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0 :transmit mode
* - I2S_RX_MODE = 1 :receive mode
* @return depth of FIFO level on which to create an irq request
*********************************************************************/
uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode)
{
CHECK_PARAM(PARAM_I2Sx(I2Sx));
if(TRMode == I2S_TX_MODE)
return (((I2Sx->IRQ)>>16)&0xFF);
else
return (((I2Sx->IRQ)>>8)&0xFF);
}
/**
* @}
*/
#endif /* _I2S */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

467
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c vendored
View file

@ -1,467 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_lcd.c 2011-06-02
*//**
* @file lpc18xx_lcd.c
* @brief Contains all function support for LCD Driver
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup LCD
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h"
#include "lpc18xx_lcd.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _LCD
LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;
/* Private Functions ---------------------------------------------------------- */
/*********************************************************************//**
* @brief Init the LPC18xx LCD Controller
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] LCD_ConfigStruct point to LCD_CFG_Type that describe the LCD Panel
* @return None
**********************************************************************/
void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct){
uint32_t i, regValue, *pPal;
uint32_t pcd;
/* disable the display */
LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
/* Setting LCD_TIMH register */
regValue= ( ((((LCD_ConfigStruct->screen_width/16)-1)&0x3F) << 2)
| (( (LCD_ConfigStruct->HSync_pulse_width-1) &0xFF) << 8)
| (( (LCD_ConfigStruct->horizontal_porch.front-1) &0xFF) << 16)
| (( (LCD_ConfigStruct->horizontal_porch.back-1) &0xFF) << 24) );
LCDx->TIMH = regValue;
/* Setting LCD_TIMV register */
regValue =((((LCD_ConfigStruct->screen_height-1) &0x3FF) << 0)
| (((LCD_ConfigStruct->VSync_pulse_width-1) &0x03F) << 10)
| (((LCD_ConfigStruct->vertical_porch.front-1) &0x0FF) << 16)
| (((LCD_ConfigStruct->vertical_porch.back-1) &0x0FF) << 24) );
LCDx->TIMV = regValue;
/* Generate the clock and signal polarity control word */
regValue = 0;
regValue = (((LCD_ConfigStruct->ac_bias_frequency-1) & 0x1F) << 6);
regValue |= (LCD_ConfigStruct->OE_pol & 1)<< 14;
regValue |= (LCD_ConfigStruct->panel_clk_edge & 1)<< 13;
regValue |= (LCD_ConfigStruct->HSync_pol & 1)<< 12;
regValue |= (LCD_ConfigStruct->VSync_pol & 1)<< 11;
/* Compute clocks per line based on panel type */
switch(LCD_ConfigStruct->lcd_panel_type)
{
case LCD_MONO_4:
regValue |= ((((LCD_ConfigStruct->screen_width / 4)-1) & 0x3FF) << 16);
break;
case LCD_MONO_8:
regValue |= ((((LCD_ConfigStruct->screen_width / 8)-1) & 0x3FF) << 16);
break;
case LCD_CSTN:
regValue |= (((((LCD_ConfigStruct->screen_width * 3)/8)-1) & 0x3FF) << 16);
break;
case LCD_TFT:
default:
regValue |= 1<<26 | (((LCD_ConfigStruct->screen_width-1) & 0x3FF) << 16);
}
/* panel clock divisor */
pcd = LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK
pcd &= 0x3FF;
regValue |= ((pcd>>5)<<27) | ((pcd)&0x1F);
LCDx->POL = regValue;
/* configure line end control */
CHECK_PARAM(LCD_ConfigStruct->line_end_delay<=(1<<7));
if(LCD_ConfigStruct->line_end_delay)
LCDx->LE = (LCD_ConfigStruct->line_end_delay-1) | 1<<16;
else
LCDx->LE = 0;
/* disable interrupts */
LCDx->INTMSK = 0;
/* set bits per pixel */
regValue = LCD_ConfigStruct->bits_per_pixel << 1;
/* set color format BGR or RGB */
regValue |= LCD_ConfigStruct->color_format << 8;
regValue |= LCD_ConfigStruct->lcd_panel_type << 4;
if(LCD_ConfigStruct->dual_panel == 1)
{
regValue |= 1 << 7;
}
LCDx->CTRL = regValue;
/* clear palette */
pPal = (uint32_t*) (&(LCDx->PAL));
for(i = 0; i < 128; i++)
{
*pPal = 0;
pPal++;
}
}
/*********************************************************************//**
* @brief Deinit LCD controller
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @return None
**********************************************************************/
void LCD_DeInit(LPC_LCD_Type *LCDx);
/*********************************************************************//**
* @brief Power the LCD Panel
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] OnOff Turn on/off LCD
* - TRUE :Turn on
* - FALSE :Turn off
* @return None
**********************************************************************/
void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff){
int i;
if(OnOff){
LPC_LCD->CTRL |= CLCDC_LCDCTRL_PWR;
for(i=0;i<100000;i++);
LPC_LCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
}else{
LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_PWR;
for(i=0;i<100000;i++);
LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
}
}
/*********************************************************************//**
* @brief Enable/Disable the LCD Controller
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] EnDis Enable/disable status
* - TRUE :Enable
* - FALSE :Disable
* @return None
**********************************************************************/
void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis){
if (EnDis)
{
LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE;
}
else
{
LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
}
}
/*********************************************************************//**
* @brief Set LCD Frame Buffer for Single Panel or Upper Panel Frame
* Buffer for Dual Panel
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] buffer address of buffer
* @return None
**********************************************************************/
void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){
LCDx->UPBASE = (uint32_t)buffer;
}
/*********************************************************************//**
* @brief Set LCD Lower Panel Frame Buffer for Dual Panel
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] buffer address of buffer
* @return None
**********************************************************************/
void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){
LCDx->LPBASE = (uint32_t)buffer;
}
/*********************************************************************//**
* @brief Configure Cursor
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] cursor_size specify size of cursor
* - LCD_CURSOR_32x32 :cursor size is 32x32 pixels
* - LCD_CURSOR_64x64 :cursor size is 64x64 pixels
* @param[in] sync cursor sync mode
* - TRUE :cursor sync to the frame sync pulse
* - FALSE :cursor async mode
* @return None
**********************************************************************/
void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync){
LCD_Cursor_Size = cursor_size;
LCDx->CRSR_CFG = ((sync?1:0)<<1) | cursor_size;
}
/*********************************************************************//**
* @brief Write Cursor Image into Internal Cursor Image Buffer
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] cursor_num specify number of cursor is going to be written
* this param must < 4
* @param[in] Image point to Cursor Image Buffer
* @return None
**********************************************************************/
void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image){
int i,j;
uint8_t *fifoptr, *crsr_ptr = (uint8_t *)Image;
CHECK_PARAM(cursor_num<4);
/* Check if Cursor Size was configured as 32x32 or 64x64*/
if(LCD_Cursor_Size == LCD_CURSOR_32x32){
i = cursor_num * 256;
j = i + 256;
}else{
i = 0;
j = 1024;
}
fifoptr = (uint8_t*)&(LCDx->CRSR_IMG[0]);
/* Copy Cursor Image content to FIFO */
for(; i < j; i++)
{
fifoptr[i] = *(uint8_t *)crsr_ptr;
crsr_ptr++;
}
}
/*********************************************************************//**
* @brief Get Internal Cursor Image Buffer Address
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] cursor_num specify number of cursor is going to be written
* this param must < 4
* @return Cursor Image Buffer Address
**********************************************************************/
void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num){
CHECK_PARAM(cursor_num<4);
return (void*)&(LCDx->CRSR_IMG[cursor_num*64]);
}
/*********************************************************************//**
* @brief Enable Cursor
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] cursor_num specify number of cursor is going to be written
* this param must < 4
* @param[in] OnOff Turn on/off LCD
* - TRUE :Enable
* - FALSE :Disable
* @return None
**********************************************************************/
void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff){
CHECK_PARAM(cursor_num<4);
if (OnOff)
{
LCDx->CRSR_CTRL = (cursor_num<<4) | 1;
}
else
{
LCDx->CRSR_CTRL = (cursor_num<<4);
}
}
/*********************************************************************//**
* @brief Load LCD Palette
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] palette point to palette address
* @return None
**********************************************************************/
void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette){
LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;
uint8_t i, *pal_ptr;
/* This function supports loading of the color palette from
the C file generated by the bmp2c utility. It expects the
palette to be passed as an array of 32-bit BGR entries having
the following format:
2:0 - Not used
7:3 - Blue
10:8 - Not used
15:11 - Green
18:16 - Not used
23:19 - Red
31:24 - Not used
arg = pointer to input palette table address */
ptr_pal_entry = &pal_entry;
pal_ptr = (uint8_t *) palette;
/* 256 entry in the palette table */
for(i = 0; i < 256/2; i++)
{
pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */
pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */
pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */
pal_ptr++; /* skip over the unused byte */
/* do the most significant halfword of the palette */
pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */
pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */
pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */
pal_ptr++; /* skip over the unused byte */
LCDx->PAL[i] = *(uint32_t *)ptr_pal_entry;
}
}
/*********************************************************************//**
* @brief Load Cursor Palette
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] palette_color cursor palette 0 value
* @return None
**********************************************************************/
void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color){
/* 7:0 - Red
15:8 - Green
23:16 - Blue
31:24 - Not used*/
LCDx->CRSR_PAL0 = (uint32_t)palette_color;
}
/*********************************************************************//**
* @brief Load Cursor Palette
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] palette_color cursor palette 1 value
* @return None
**********************************************************************/
void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color){
/* 7:0 - Red
15:8 - Green
23:16 - Blue
31:24 - Not used*/
LCDx->CRSR_PAL1 = (uint32_t)palette_color;
}
/*********************************************************************//**
* @brief Set Interrupt
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] Int LCD Interrupt Source, should be:
* - LCD_INT_FUF :FIFO underflow
* - LCD_INT_LNBU :LCD next base address update bit
* - LCD_INT_VCOMP :Vertical compare bit
* - LCD_INT_BER :AHB master error interrupt bit
* @return None
**********************************************************************/
void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){
LCDx->INTMSK |= Int;
}
/*********************************************************************//**
* @brief Clear Interrupt
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] Int LCD Interrupt Source, should be:
* - LCD_INT_FUF :FIFO underflow
* - LCD_INT_LNBU :LCD next base address update bit
* - LCD_INT_VCOMP :Vertical compare bit
* - LCD_INT_BER :AHB master error interrupt bit
* @return None
**********************************************************************/
void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){
LCDx->INTCLR |= Int;
}
/*********************************************************************//**
* @brief Get LCD Interrupt Status
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @return None
**********************************************************************/
LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx){
return (LCD_INT_SRC)LCDx->INTRAW;
}
/*********************************************************************//**
* @brief Enable Cursor Interrupt
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @return None
**********************************************************************/
void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx){
LCDx->CRSR_INTMSK |= 1;
}
/*********************************************************************//**
* @brief Clear Cursor Interrupt
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @return None
**********************************************************************/
void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx){
LCDx->CRSR_INTCLR |= 1;
}
/*********************************************************************//**
* @brief Set Cursor Position
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] x horizontal position
* @param[in] y vertical position
* @return None
**********************************************************************/
void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){
LCDx->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);
}
/*********************************************************************//**
* @brief Set Cursor Clipping Position
* @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD
* @param[in] x horizontal position, should be in range: 0..63
* @param[in] y vertical position, should be in range: 0..63
* @return None
**********************************************************************/
void LCD_Cursor_SetClip(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){
LCDx->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);
}
#endif /* _LCD */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

64
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c vendored
View file

@ -1,64 +0,0 @@
/***********************************************************************//**
* @file lpc18xx_libcfg_default.c
* @brief Library configuration source file (default),
* used to build library without examples.
* @version 2.0
* @date 21. May. 2010
* @author NXP MCU SW Application Team
**************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**************************************************************************/
/* Library group ----------------------------------------------------------- */
/** @addtogroup LIBCFG_DEFAULT
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_libcfg_default.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup LIBCFG_DEFAULT_Public_Functions
* @{
*/
#ifndef __BUILD_WITH_EXAMPLE__
#ifdef DEBUG
/*******************************************************************************
* @brief Reports the name of the source file and the source line number
* where the CHECK_PARAM error has occurred.
* @param[in] file Pointer to the source file name
* @param[in] line assert_param error line source number
* @return None
*******************************************************************************/
void check_failed(uint8_t *file, uint32_t line)
{
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* Infinite loop */
while(1);
}
#endif /* DEBUG */
#endif /* __BUILD_WITH_EXAMPLE__ */
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

555
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c vendored
View file

@ -1,555 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_mcpwm.c 2011-06-02
*//**
* @file lpc18xx_mcpwm.c
* @brief Contains all functions support for Motor Control PWM firmware
* library on LPC18XX
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup MCPWM
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_mcpwm.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _MCPWM
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup MCPWM_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initializes the MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @return None
**********************************************************************/
void MCPWM_Init(LPC_MCPWM_Type *MCPWMx)
{
/* Turn On MCPWM PCLK */
//LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);
MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2);
MCPWMx->INTF_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
| MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
| MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
MCPWMx->INTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
| MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
| MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
}
/*********************************************************************//**
* @brief Configures each channel in MCPWM peripheral according to the
* specified parameters in the MCPWM_CHANNEL_CFG_Type.
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channelNum Channel number, should be: 0..2.
* @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
* that contains the configuration information for the specified
* MCPWM channel.
* @return None
**********************************************************************/
void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type * channelSetup)
{
if (channelNum <= 2)
{
if (channelNum == MCPWM_CHANNEL_0)
{
MCPWMx->TC[0] = channelSetup->channelTimercounterValue;
MCPWMx->LIM[0] = channelSetup->channelPeriodValue;
MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_1)
{
MCPWMx->TC[1] = channelSetup->channelTimercounterValue;
MCPWMx->LIM[1] = channelSetup->channelPeriodValue;
MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_2)
{
MCPWMx->TC[2] = channelSetup->channelTimercounterValue;
MCPWMx->LIM[2] = channelSetup->channelPeriodValue;
MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue;
}
else
{
return;
}
if (channelSetup->channelType == MCPWM_CHANNEL_CENTER_MODE)
{
MCPWMx->CON_SET = MCPWM_CON_CENTER(channelNum);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_CENTER(channelNum);
}
if (channelSetup->channelPolarity == MCPWM_CHANNEL_PASSIVE_HI)
{
MCPWMx->CON_SET = MCPWM_CON_POLAR(channelNum);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_POLAR(channelNum);
}
if (channelSetup->channelDeadtimeEnable == ENABLE)
{
MCPWMx->CON_SET = MCPWM_CON_DTE(channelNum);
MCPWMx->DT &= ~(MCPWM_DT(channelNum, 0x3FF));
MCPWMx->DT |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_DTE(channelNum);
}
if (channelSetup->channelUpdateEnable == ENABLE)
{
MCPWMx->CON_CLR = MCPWM_CON_DISUP(channelNum);
}
else
{
MCPWMx->CON_SET = MCPWM_CON_DISUP(channelNum);
}
}
}
/*********************************************************************//**
* @brief Write to MCPWM shadow registers - Update the value for period
* and pulse width in MCPWM peripheral.
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channelNum Channel Number, should be: 0..2.
* @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
* that contains the configuration information for the specified
* MCPWM channel.
* @return None
**********************************************************************/
void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type *channelSetup)
{
if (channelNum == MCPWM_CHANNEL_0)
{
MCPWMx->LIM[0] = channelSetup->channelPeriodValue;
MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_1)
{
MCPWMx->LIM[1] = channelSetup->channelPeriodValue;
MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_2)
{
MCPWMx->LIM[2] = channelSetup->channelPeriodValue;
MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue;
}
}
/*********************************************************************//**
* @brief Configures capture function in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channelNum MCI (Motor Control Input pin) number, should be: 0..2
* @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM capture.
* @return
**********************************************************************/
void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
MCPWM_CAPTURE_CFG_Type *captureConfig)
{
if ((channelNum <= MCPWM_CHANNEL_2))
{
if (captureConfig->captureFalling == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
}
if (captureConfig->captureRising == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
}
if (captureConfig->timerReset == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel);
}
if (captureConfig->hnfEnable == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum);
}
}
}
/*********************************************************************//**
* @brief Clears current captured value in specified capture channel
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] captureChannel Capture channel number, should be: 0..2
* @return None
**********************************************************************/
void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel)
{
MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(captureChannel);
}
/*********************************************************************//**
* @brief Get current captured value in specified capture channel
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] captureChannel Capture channel number, should be: 0..2
* @return None
**********************************************************************/
uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel)
{
if (captureChannel == MCPWM_CHANNEL_0)
{
return (MCPWMx->CAP[0]);
}
else if (captureChannel == MCPWM_CHANNEL_1)
{
return (MCPWMx->CAP[1]);
}
else if (captureChannel == MCPWM_CHANNEL_2)
{
return (MCPWMx->CAP[2]);
}
return (0);
}
/*********************************************************************//**
* @brief Configures Count control in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channelNum Channel number, should be: 0..2
* @param[in] countMode Count mode, should be:
* - ENABLE: Enables count mode.
* - DISABLE: Disable count mode, the channel is in timer mode.
* @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM count control.
* @return None
**********************************************************************/
void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig)
{
if ((channelNum <= 2))
{
if (countMode == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_CNTR(channelNum);
if (countConfig->countFalling == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
}
if (countConfig->countRising == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
}
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum);
}
}
}
/*********************************************************************//**
* @brief Start MCPWM activity for each MCPWM channel
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channel0 State of this command on channel 0:
* - ENABLE: 'Start' command will effect on channel 0
* - DISABLE: 'Start' command will not effect on channel 0
* @param[in] channel1 State of this command on channel 1:
* - ENABLE: 'Start' command will effect on channel 1
* - DISABLE: 'Start' command will not effect on channel 1
* @param[in] channel2 State of this command on channel 2:
* - ENABLE: 'Start' command will effect on channel 2
* - DISABLE: 'Start' command will not effect on channel 2
* @return None
**********************************************************************/
void MCPWM_Start(LPC_MCPWM_Type *MCPWMx, uint32_t channel0,
uint32_t channel1, uint32_t channel2)
{
uint32_t regVal = 0;
regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
| (channel2 ? MCPWM_CON_RUN(2) : 0);
MCPWMx->CON_SET = regVal;
}
/*********************************************************************//**
* @brief Stop MCPWM activity for each MCPWM channel
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] channel0 State of this command on channel 0:
* - ENABLE: 'Stop' command will effect on channel 0
* - DISABLE: 'Stop' command will not effect on channel 0
* @param[in] channel1 State of this command on channel 1:
* - ENABLE: 'Stop' command will effect on channel 1
* - DISABLE: 'Stop' command will not effect on channel 1
* @param[in] channel2 State of this command on channel 2:
* - ENABLE: 'Stop' command will effect on channel 2
* - DISABLE: 'Stop' command will not effect on channel 2
* @return None
**********************************************************************/
void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx, uint32_t channel0,
uint32_t channel1, uint32_t channel2)
{
uint32_t regVal = 0;
regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
| (channel2 ? MCPWM_CON_RUN(2) : 0);
MCPWMx->CON_CLR = regVal;
}
/*********************************************************************//**
* @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] acMode State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
**********************************************************************/
void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx, uint32_t acMode)
{
if (acMode)
{
MCPWMx->CON_SET = MCPWM_CON_ACMODE;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_ACMODE;
}
}
/*********************************************************************//**
* @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] dcMode State of this command, should be:
* - ENABLE.
* - DISABLE.
* @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels,
* should be:
* - ENABLE :The MCOB outputs have opposite polarity from the MCOA outputs.
* - DISABLE :The MCOB outputs have the same basic polarity as the MCOA outputs.
* @param[in] outputPattern A value contains bits that enables/disables the specified
* output pins route to the internal MCOA0 signal, should be:
* - MCPWM_PATENT_A0 :MCOA0 tracks internal MCOA0
* - MCPWM_PATENT_B0 :MCOB0 tracks internal MCOA0
* - MCPWM_PATENT_A1 :MCOA1 tracks internal MCOA0
* - MCPWM_PATENT_B1 :MCOB1 tracks internal MCOA0
* - MCPWM_PATENT_A2 :MCOA2 tracks internal MCOA0
* - MCPWM_PATENT_B2 :MCOB2 tracks internal MCOA0
* @return None
*
* Note: all these outputPatent values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,
uint32_t outputInvered, uint32_t outputPattern)
{
if (dcMode)
{
MCPWMx->CON_SET = MCPWM_CON_DCMODE;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_DCMODE;
}
if (outputInvered)
{
MCPWMx->CON_SET = MCPWM_CON_INVBDC;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_INVBDC;
}
MCPWMx->CCP = outputPattern;
}
/*********************************************************************//**
* @brief Configures the specified interrupt in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT :Fast abort interrupt
* @param[in] NewState New State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
*
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState)
{
if (NewState)
{
MCPWMx->INTEN_SET = ulIntType;
}
else
{
MCPWMx->INTEN_CLR = ulIntType;
}
}
/*********************************************************************//**
* @brief Sets/Forces the specified interrupt for MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT :Fast abort interrupt
* @return None
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)
{
MCPWMx->INTF_SET = ulIntType;
}
/*********************************************************************//**
* @brief Clear the specified interrupt pending for MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT :Fast abort interrupt
* @return None
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)
{
MCPWMx->INTF_CLR = ulIntType;
}
/*********************************************************************//**
* @brief Check whether if the specified interrupt in MCPWM is set or not
* @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT :Fast abort interrupt
* @return None
**********************************************************************/
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)
{
return ((MCPWMx->INTF & ulIntType) ? SET : RESET);
}
/**
* @}
*/
#endif /* _MCPWM */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

74
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c vendored
View file

@ -1,74 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_nvic.c 2011-06-02
*//**
* @file lpc18xx_nvic.c
* @brief Contains all expansion functions support for NVIC firmware
* library on LPC18XX. The main NVIC functions are defined in
* core_cm3.h
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup NVIC
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_nvic.h"
/* Private Macros ------------------------------------------------------------- */
/** @addtogroup NVIC_Private_Macros
* @{
*/
/* Vector table offset bit mask */
#define NVIC_VTOR_MASK 0x3FFFFF80
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup NVIC_Public_Functions
* @{
*/
/*****************************************************************************//**
* @brief Set Vector Table Offset value
* @param offset Offset value
* @return None
*******************************************************************************/
void NVIC_SetVTOR(uint32_t offset)
{
// SCB->VTOR = (offset & NVIC_VTOR_MASK);
SCB->VTOR = offset;
}
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

102
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c vendored
View file

@ -1,102 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_pwr.c 2011-06-02
*//**
* @file lpc18xx_pwr.c
* @brief Contains all functions support for Power Control
* firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup PWR
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
#include "lpc18xx_scu.h"
#include "lpc18xx_pwr.h"
/*********************************************************************//**
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void PWR_Sleep(void)
{
//LPC_PMC->SLEEP0_MODE = 0x00;
/* Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void PWR_DeepSleep(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_SLEEP;
/* Deep Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void PWR_PowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_POWER_DOWN;
/* Power Down Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void PWR_DeepPowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_POWER_DOWN;
/* Deep Power Down Mode*/
__WFI();
}
/**
* @}
*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

540
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c vendored
View file

@ -1,540 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_qei.c 2011-06-02
*//**
* @file lpc18xx_pwr.c
* @brief Contains all functions support for QEI firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup QEI
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_qei.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _QEI
/* Private Types -------------------------------------------------------------- */
/** @defgroup QEI_Private_Types QEI Private Types
* @{
*/
/**
* @brief QEI configuration union type definition
*/
typedef union {
QEI_CFG_Type bmQEIConfig;
uint32_t ulQEIConfig;
} QEI_CFGOPT_Type;
/**
* @}
*/
LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId);
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup QEI_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Get the point to typedef of QEI component
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return None
**********************************************************************/
LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId)
{
LPC_QEI_Type* pQei = NULL;
if(qeiId == 0)
{
pQei = LPC_QEI;
}
return pQei;
}
/*********************************************************************//**
* @brief Resets value for each type of QEI value, such as velocity,
* counter, position, etc..
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulResetType QEI Reset Type, should be one of the following:
* - QEI_RESET_POS :Reset Position Counter
* - QEI_RESET_POSOnIDX :Reset Position Counter on Index signal
* - QEI_RESET_VEL :Reset Velocity
* - QEI_RESET_IDX :Reset Index Counter
* @return None
**********************************************************************/
void QEI_Reset(uint8_t qeiId, uint32_t ulResetType)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->CON = ulResetType;
}
/*********************************************************************//**
* @brief Initializes the QEI peripheral according to the specified
* parameters in the QEI_ConfigStruct.
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure
* that contains the configuration information for the
* specified QEI peripheral
* @return None
**********************************************************************/
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
/* Set up clock and power for QEI module */
// Already enabled by BASE_M3_CLK
// Reset all remaining value in QEI peripheral
pQei->MAXPOS = 0x00;
pQei->CMPOS0 = 0x00;
pQei->CMPOS1 = 0x00;
pQei->CMPOS2 = 0x00;
pQei->INXCMP0 = 0x00;
pQei->VELCOMP = 0x00;
pQei->LOAD = 0x00;
pQei->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;
pQei->FILTERPHA = 0x00;
pQei->FILTERPHB = 0x00;
pQei->FILTERINX = 0x00;
// Disable all Interrupt
pQei->IEC = QEI_IECLR_BITMASK;
// Clear all Interrupt pending
pQei->CLR = QEI_INTCLR_BITMASK;
// Set QEI configuration value corresponding to its setting up value
pQei->CONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig;
}
/*********************************************************************//**
* @brief De-Initalize QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return None
**********************************************************************/
void QEI_DeInit(uint8_t qeiId)
{
/* Turn off clock and power for QEI module */
}
/*****************************************************************************//**
* @brief Fills each QIE_InitStruct member with its default value:
* - DirectionInvert = QEI_DIRINV_NONE
* - SignalMode = QEI_SIGNALMODE_QUAD
* - CaptureMode = QEI_CAPMODE_4X
* - InvertIndex = QEI_INVINX_NONE
* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure which will be
* initialized.
* @return None
*******************************************************************************/
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct)
{
QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X;
QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE;
QIE_InitStruct->InvertIndex = QEI_INVINX_NONE;
QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD;
}
/*********************************************************************//**
* @brief Check whether if specified flag status is set or not
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulFlagType Status Flag Type, should be one of the following:
* - QEI_STATUS_DIR: Direction Status
* @return New Status of this status flag (SET or RESET)
**********************************************************************/
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return ((pQei->STAT & ulFlagType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Get current position value in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return Current position value of QEI peripheral
**********************************************************************/
uint32_t QEI_GetPosition(uint8_t qeiId)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return (pQei->POS);
}
/*********************************************************************//**
* @brief Set max position value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulMaxPos Max position value to set
* @return None
**********************************************************************/
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->MAXPOS = ulMaxPos;
}
/*********************************************************************//**
* @brief Set position compare value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] bPosCompCh Compare Position channel, should be:
* - QEI_COMPPOS_CH_0 :QEI compare position channel 0
* - QEI_COMPPOS_CH_1 :QEI compare position channel 1
* - QEI_COMPPOS_CH_2 :QEI compare position channel 2
* @param[in] ulPosComp Compare Position value to set
* @return None
**********************************************************************/
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
uint32_t *tmp;
tmp = (uint32_t *) (&(pQei->CMPOS0) + bPosCompCh * 4);
*tmp = ulPosComp;
}
/*********************************************************************//**
* @brief Get current index counter of QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return Current value of QEI index counter
**********************************************************************/
uint32_t QEI_GetIndex(uint8_t qeiId)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return (pQei->INXCNT);
}
/*********************************************************************//**
* @brief Set value for index compare in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulIndexComp Compare Index Value to set
* @return None
**********************************************************************/
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->INXCMP0 = ulIndexComp;
}
/*********************************************************************//**
* @brief Set timer reload value for QEI peripheral. When the velocity timer is
* over-flow, the value that set for Timer Reload register will be loaded
* into the velocity timer for next period. The calculated velocity in RPM
* therefore will be affect by this value.
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] QEIReloadStruct QEI reload structure
* @return None
**********************************************************************/
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
uint64_t pclk;
if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL)
{
pQei->LOAD = QEIReloadStruct->ReloadValue - 1;
}
else
{
#if 1
pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);
pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1;
pQei->LOAD = (uint32_t)pclk;
#else
ld = M3Frequency;
if (ld/1000000 > 0)
{
ld /= 1000000;
ld *= QEIReloadStruct->ReloadValue;
ld -= 1;
}
else
{
ld *= QEIReloadStruct->ReloadValue;
ld /= 1000000;
ld -= 1;
}
pQei->LOAD = ld;
#endif
}
}
/*********************************************************************//**
* @brief Get current timer counter in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return Current timer counter in QEI peripheral
**********************************************************************/
uint32_t QEI_GetTimer(uint8_t qeiId)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return (pQei->TIME);
}
/*********************************************************************//**
* @brief Get current velocity pulse counter in current time period
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return Current velocity pulse counter value
**********************************************************************/
uint32_t QEI_GetVelocity(uint8_t qeiId)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return (pQei->VEL);
}
/*********************************************************************//**
* @brief Get the most recently measured velocity of the QEI. When
* the Velocity timer in QEI is over-flow, the current velocity
* value will be loaded into Velocity Capture register.
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @return The most recently measured velocity value
**********************************************************************/
uint32_t QEI_GetVelocityCap(uint8_t qeiId)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return (pQei->CAP);
}
/*********************************************************************//**
* @brief Set Velocity Compare value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulVelComp Compare Velocity value to set
* @return None
**********************************************************************/
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->VELCOMP = ulVelComp;
}
/*********************************************************************//**
* @brief Set value of sampling count for the digital filter in
* QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulSamplingPulse Value of sampling count to set
* @return None
**********************************************************************/
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->FILTERPHA = FilterVal.PHA_FilterVal;
pQei->FILTERPHB = FilterVal.PHB_FilterVal;
pQei->FILTERINX = FilterVal.INX_FilterVal;
}
/*********************************************************************//**
* @brief Check whether if specified interrupt flag status in QEI
* peripheral is set or not
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulIntType Interrupt Flag Status type, should be:
* - QEI_INTFLAG_INX_Int : index pulse was detected interrupt
* - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt
* - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt
* - QEI_INTFLAG_DIR_Int : Change of direction interrupt
* - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt
* - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt
* - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt
* - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt
* - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt
* - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt
* - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt
* @return New State of specified interrupt flag status (SET or RESET)
**********************************************************************/
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
return((pQei->INTSTAT & ulIntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Enable/Disable specified interrupt in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulIntType Interrupt Flag Status type, should be:
* - QEI_INTFLAG_INX_Int : index pulse was detected interrupt
* - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt
* - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt
* - QEI_INTFLAG_DIR_Int : Change of direction interrupt
* - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt
* - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt
* - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt
* - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt
* - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt
* - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt
* - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt
* @param[in] NewState New function state, should be:
* - DISABLE
* - ENABLE
* @return None
**********************************************************************/
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
if (NewState == ENABLE)
{
pQei->IES = ulIntType;
}
else
{
pQei->IEC = ulIntType;
}
}
/*********************************************************************//**
* @brief Sets (forces) specified interrupt in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulIntType Interrupt Flag Status type, should be:
* - QEI_INTFLAG_INX_Int : index pulse was detected interrupt
* - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt
* - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt
* - QEI_INTFLAG_DIR_Int : Change of direction interrupt
* - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt
* - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt
* - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt
* - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt
* - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt
* - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt
* - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt
* @return None
**********************************************************************/
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->SET = ulIntType;
}
/*********************************************************************//**
* @brief Clear (force) specified interrupt (pending) in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulIntType Interrupt Flag Status type, should be:
* - QEI_INTFLAG_INX_Int : index pulse was detected interrupt
* - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt
* - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt
* - QEI_INTFLAG_DIR_Int : Change of direction interrupt
* - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt
* - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt
* - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt
* - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt
* - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt
* - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt
* - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt
* - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt
* @return None
**********************************************************************/
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
pQei->CLR = ulIntType;
}
/*********************************************************************//**
* @brief Calculates the actual velocity in RPM passed via velocity
* capture value and Pulse Per Round (of the encoder) value
* parameter input.
* @param[in] qeiId The Id of the expected QEI component, should be: 0
* @param[in] ulVelCapValue Velocity capture input value that can be
* got from QEI_GetVelocityCap() function
* @param[in] ulPPR Pulse per round of encoder
* @return The actual value of velocity in RPM (Round per minute)
**********************************************************************/
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR)
{
LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);
uint64_t rpm, clock, Load, edges;
// Get current Clock rate for timer input
clock = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);
// Get Timer load value (velocity capture period)
Load = (uint64_t)(pQei->LOAD + 1);
// Get Edge
edges = (uint64_t)((pQei->CONF & QEI_CONF_CAPMODE) ? 4 : 2);
// Calculate RPM
rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges));
return (uint32_t)(rpm);
}
/**
* @}
*/
#endif /* _QEI */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

253
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rgu.c vendored
View file

@ -1,253 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rgu.c 2011-06-02
*//**
* @file lpc18xx_rgu.c
* @brief Contains all functions support for RGU firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup RGU
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_rgu.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _RGU
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup RGU_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Soft Reset a Signal
* @param[in] ResetSignal indicates which signal will be reset, should be:
* - RGU_SIG_CORE :Core
* - RGU_SIG_PERIPH :Peripheral
* - RGU_SIG_MASTER :Master
* - RGU_SIG_WWDT :WWDT
* - RGU_SIG_CREG :Configuration register block
* - RGU_SIG_BUS :Buses
* - RGU_SIG_SCU :System control unit
* - RGU_SIG_PINMUX :Pin mux
* - RGU_SIG_M3 :Cortex-M3 system
* - RGU_SIG_LCD :LCD controller
* - RGU_SIG_USB0 :USB0
* - RGU_SIG_USB1 :USB1
* - RGU_SIG_DMA :DMA
* - RGU_SIG_SDIO :SDIO
* - RGU_SIG_EMC :External memory controller
* - RGU_SIG_ETHERNET :Ethernet
* - RGU_SIG_AES :AES
* - RGU_SIG_GPIO :GPIO
* - RGU_SIG_TIMER0 :Timer 0
* - RGU_SIG_TIMER1 :Timer 1
* - RGU_SIG_TIMER2 :Timer 2
* - RGU_SIG_TIMER3 :Timer 3
* - RGU_SIG_RITIMER :Repetitive Interrupt Timer
* - RGU_SIG_SCT :State Configurable Timer
* - RGU_SIG_MOTOCONPWM:Motor Control PWM
* - RGU_SIG_QEI :QEI
* - RGU_SIG_ADC0 :ADC0
* - RGU_SIG_ADC1 :ADC1
* - RGU_SIG_DAC :DAC
* - RGU_SIG_UART0 :UART0
* - RGU_SIG_UART1 :UART1
* - RGU_SIG_UART2 :UART2
* - RGU_SIG_UART3 :UART3
* - RGU_SIG_I2C0 :I2C0
* - RGU_SIG_I2C1 :I2C1
* - RGU_SIG_SSP0 :SSP0
* - RGU_SIG_SSP1 :SSP1
* - RGU_SIG_I2S :I2S
* - RGU_SIG_SPIFI :SPIFI
* - RGU_SIG_CAN :CAN
* @return None
**********************************************************************/
void RGU_SoftReset(RGU_SIG ResetSignal)
{
if(ResetSignal < 32){
LPC_RGU->RESET_CTRL0 = 1 << ResetSignal;
LPC_RGU->RESET_CTRL0 = 0;
}else{
LPC_RGU->RESET_CTRL1 = 1 << (ResetSignal - 32);
LPC_RGU->RESET_CTRL1 = 0;
}
}
/*********************************************************************//**
* @brief Get source cause of a signal
* @param[in] ResetSignal reset signal, should be:
* - RGU_SIG_CORE :Core
* - RGU_SIG_PERIPH :Peripheral
* - RGU_SIG_MASTER :Master
* - RGU_SIG_WWDT :WWDT
* - RGU_SIG_CREG :Configuration register block
* - RGU_SIG_BUS :Buses
* - RGU_SIG_SCU :System control unit
* - RGU_SIG_PINMUX :Pin mux
* - RGU_SIG_M3 :Cortex-M3 system
* - RGU_SIG_LCD :LCD controller
* - RGU_SIG_USB0 :USB0
* - RGU_SIG_USB1 :USB1
* - RGU_SIG_DMA :DMA
* - RGU_SIG_SDIO :SDIO
* - RGU_SIG_EMC :External memory controller
* - RGU_SIG_ETHERNET :Ethernet
* - RGU_SIG_AES :AES
* - RGU_SIG_GPIO :GPIO
* - RGU_SIG_TIMER0 :Timer 0
* - RGU_SIG_TIMER1 :Timer 1
* - RGU_SIG_TIMER2 :Timer 2
* - RGU_SIG_TIMER3 :Timer 3
* - RGU_SIG_RITIMER :Repetitive Interrupt Timer
* - RGU_SIG_SCT :State Configurable Timer
* - RGU_SIG_MOTOCONPWM:Motor Control PWM
* - RGU_SIG_QEI :QEI
* - RGU_SIG_ADC0 :ADC0
* - RGU_SIG_ADC1 :ADC1
* - RGU_SIG_DAC :DAC
* - RGU_SIG_UART0 :UART0
* - RGU_SIG_UART1 :UART1
* - RGU_SIG_UART2 :UART2
* - RGU_SIG_UART3 :UART3
* - RGU_SIG_I2C0 :I2C0
* - RGU_SIG_I2C1 :I2C1
* - RGU_SIG_SSP0 :SSP0
* - RGU_SIG_SSP1 :SSP1
* - RGU_SIG_I2S :I2S
* - RGU_SIG_SPIFI :SPIFI
* - RGU_SIG_CAN :CAN
* @return Source cause of reset, could be:
* - RGU_SRC_NONE :No source
* - RGU_SRC_SOFT :Software reset source
* - RGU_SRC_EXT :External reset source
* - RGU_SRC_CORE :Core reset source
* - RGU_SRC_PERIPH :Peripheral reset source
* - RGU_SRC_MASTER :Master reset source
* - RGU_SRC_BOD :BOD reset source
* - RGU_SRC_WWDT :WWDT reset source
**********************************************************************/
RGU_SRC RGU_GetSource(RGU_SIG ResetSignal)
{
uint32_t i, temp, registercache;
if(ResetSignal < 16)
temp = 3 & (LPC_RGU->RESET_STATUS0 >> ResetSignal);
else if(ResetSignal < 32)
temp = 3 & (LPC_RGU->RESET_STATUS1 >> (ResetSignal - 16));
else if(ResetSignal < 48)
temp = 3 & (LPC_RGU->RESET_STATUS2 >> (ResetSignal - 32));
else
temp = 3 & (LPC_RGU->RESET_STATUS3 >> (ResetSignal - 48));
if(temp == 0) return RGU_SRC_NONE;
else if(temp == 3) return RGU_SRC_SOFT;
else if(temp == 1){
registercache = (((uint32_t*)&LPC_RGU->RESET_EXT_STAT0)[ResetSignal]);
for(i = 0; i < 6; i++){
if(registercache & (1<<i)){
return (RGU_SRC)(RGU_SRC_EXT + i);
}
}
}
return RGU_SRC_NONE;
}
/*********************************************************************//**
* @brief Get Current Status of Signal
* @param[in] ResetSignal Reset Signal, should be:
* - RGU_SIG_CORE :Core
* - RGU_SIG_PERIPH :Peripheral
* - RGU_SIG_MASTER :Master
* - RGU_SIG_WWDT :WWDT
* - RGU_SIG_CREG :Configuration register block
* - RGU_SIG_BUS :Buses
* - RGU_SIG_SCU :System control unit
* - RGU_SIG_PINMUX :Pin mux
* - RGU_SIG_M3 :Cortex-M3 system
* - RGU_SIG_LCD :LCD controller
* - RGU_SIG_USB0 :USB0
* - RGU_SIG_USB1 :USB1
* - RGU_SIG_DMA :DMA
* - RGU_SIG_SDIO :SDIO
* - RGU_SIG_EMC :External memory controller
* - RGU_SIG_ETHERNET :Ethernet
* - RGU_SIG_AES :AES
* - RGU_SIG_GPIO :GPIO
* - RGU_SIG_TIMER0 :Timer 0
* - RGU_SIG_TIMER1 :Timer 1
* - RGU_SIG_TIMER2 :Timer 2
* - RGU_SIG_TIMER3 :Timer 3
* - RGU_SIG_RITIMER :Repetitive Interrupt Timer
* - RGU_SIG_SCT :State Configurable Timer
* - RGU_SIG_MOTOCONPWM:Motor Control PWM
* - RGU_SIG_QEI :QEI
* - RGU_SIG_ADC0 :ADC0
* - RGU_SIG_ADC1 :ADC1
* - RGU_SIG_DAC :DAC
* - RGU_SIG_UART0 :UART0
* - RGU_SIG_UART1 :UART1
* - RGU_SIG_UART2 :UART2
* - RGU_SIG_UART3 :UART3
* - RGU_SIG_I2C0 :I2C0
* - RGU_SIG_I2C1 :I2C1
* - RGU_SIG_SSP0 :SSP0
* - RGU_SIG_SSP1 :SSP1
* - RGU_SIG_I2S :I2S
* - RGU_SIG_SPIFI :SPIFI
* - RGU_SIG_CAN :CAN
* @return Signal status, could be:
* - TRUE :reset is active
* - FALSE :reset is inactive
**********************************************************************/
Bool RGU_GetSignalStatus(RGU_SIG ResetSignal)
{
if(ResetSignal < 32)
return (Bool)!(LPC_RGU->RESET_ACTIVE_STATUS0 | (1 << ResetSignal));
else
return (Bool)!(LPC_RGU->RESET_ACTIVE_STATUS1 | (1 << (ResetSignal - 32)));
}
/**
* @}
*/
#endif /* _RGU */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

196
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c vendored
View file

@ -1,196 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rit.c 2011-06-02
*//**
* @file lpc18xx_rit.c
* @brief Contains all functions support for RIT firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup RIT
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_rit.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _RIT
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup RIT_Public_Functions
* @{
*/
/******************************************************************************//*
* @brief Initial for RIT
* - Turn on power and clock
* - Setup default register values
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @return None
*******************************************************************************/
void RIT_Init(LPC_RITIMER_Type *RITx)
{
CHECK_PARAM(PARAM_RITx(RITx));
//CGU_ConfigPPWR (CGU_PCONP_PCRIT, ENABLE);
//Set up default register values
RITx->COMPVAL = 0xFFFFFFFF;
RITx->MASK = 0x00000000;
RITx->CTRL = 0x0C;
RITx->COUNTER = 0x00000000;
// Turn on power and clock
}
/******************************************************************************//*
* @brief DeInitial for RIT
* - Turn off power and clock
* - ReSetup default register values
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @return None
*******************************************************************************/
void RIT_DeInit(LPC_RITIMER_Type *RITx)
{
CHECK_PARAM(PARAM_RITx(RITx));
// Turn off power and clock
//CGU_ConfigPPWR (CGU_PCONP_PCRIT, DISABLE);
//ReSetup default register values
RITx->COMPVAL = 0xFFFFFFFF;
RITx->MASK = 0x00000000;
RITx->CTRL = 0x0C;
RITx->COUNTER = 0x00000000;
}
/******************************************************************************//*
* @brief Set compare value, mask value and time counter value
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @param[in] time_interval timer interval value (ms)
* @return None
*******************************************************************************/
void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval)
{
uint32_t clock_rate, cmp_value;
CHECK_PARAM(PARAM_RITx(RITx));
// Get PCLK value of RIT
clock_rate = /*CGU_GetPCLK(CGU_PCLKSEL_RIT)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);
/* calculate compare value for RIT to generate interrupt at
* specified time interval
* COMPVAL = (RIT_PCLK * time_interval)/1000
* (with time_interval unit is millisecond)
*/
cmp_value = (clock_rate /1000) * time_interval;
RITx->COMPVAL = cmp_value;
/* Set timer enable clear bit to clear timer to 0 whenever
* counter value equals the contents of RICOMPVAL
*/
RITx->CTRL |= (1<<1);
}
/******************************************************************************//*
* @brief Enable/Disable Timer
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @param[in] NewState New State of this function
* -ENABLE :Enable Timer
* -DISABLE :Disable Timer
* @return None
*******************************************************************************/
void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_RITx(RITx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
//Enable or Disable Timer
if(NewState==ENABLE)
{
RITx->CTRL |= RIT_CTRL_TEN;
}
else
{
RITx->CTRL &= ~RIT_CTRL_TEN;
}
}
/******************************************************************************//*
* @brief Timer Enable/Disable on debug
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @param[in] NewState New State of this function
* -ENABLE :The timer is halted whenever a hardware break condition occurs
* -DISABLE :Hardware break has no effect on the timer operation
* @return None
*******************************************************************************/
void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_RITx(RITx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
//Timer Enable/Disable on break
if(NewState==ENABLE)
{
RITx->CTRL |= RIT_CTRL_ENBR;
}
else
{
RITx->CTRL &= ~RIT_CTRL_ENBR;
}
}
/******************************************************************************//*
* @brief Check whether interrupt flag is set or not
* @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
* @return Current interrupt status, could be
* - SET
* - RESET
*******************************************************************************/
IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx)
{
uint8_t result;
CHECK_PARAM(PARAM_RITx(RITx));
if((RITx->CTRL&RIT_CTRL_INTEN)==1) result= SET;
else return RESET;
//clear interrupt flag
RITx->CTRL |= RIT_CTRL_INTEN;
return (IntStatus)result;
}
/**
* @}
*/
#endif /* _RIT */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

760
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c vendored
View file

@ -1,760 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_rtc.c 2011-06-02
*//**
* @file lpc18xx_rtc.c
* @brief Contains all functions support for RTC firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup RTC
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_rtc.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _RTC
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup RTC_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initializes the RTC peripheral.
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
*********************************************************************/
void RTC_Init (LPC_RTC_Type *RTCx)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
// Configure clock to RTC
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Reset 32Khz oscillator
LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k and release reset
LPC_SCU->SFSCLK_0 = 1 | (0x3<<2); // function 1; CGU clk out, pull down
LPC_CGU->BASE_OUT_CLK = (CGU_CLKSRC_32KHZ_OSC<<24) |(1<<11); // base clock out use 32KHz crystal and auto block
do
{
/* Reset RTC clock*/
RTCx->CCR = RTC_CCR_CTCRST | RTC_CCR_CCALEN;
}
while(RTCx->CCR!=(RTC_CCR_CTCRST | RTC_CCR_CCALEN));
do
{
/* Finish resetting RTC clock*/
RTCx->CCR = RTC_CCR_CCALEN;
}
while(RTCx->CCR != RTC_CCR_CCALEN);
/* Clear counter increment and alarm interrupt */
RTCx->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF;
while(RTCx->ILR!=0);
// Clear all register to be default
RTCx->CIIR = 0x00;
RTCx->AMR = 0xFF;
RTCx->CALIBRATION = 0x00;
}
/*********************************************************************//**
* @brief De-initializes the RTC peripheral registers to their
* default reset values.
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
**********************************************************************/
void RTC_DeInit(LPC_RTC_Type *RTCx)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
RTCx->CCR = 0x00;
}
/*********************************************************************//**
* @brief Reset clock tick counter in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
**********************************************************************/
void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
RTCx->CCR |= RTC_CCR_CTCRST;
RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
}
/*********************************************************************//**
* @brief Start/Stop RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] NewState New State of this function, should be:
* - ENABLE :The time counters are enabled
* - DISABLE :The time counters are disabled
* @return None
**********************************************************************/
void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
do
{
RTCx->CCR |= RTC_CCR_CLKEN;
}
while((RTCx->CCR&RTC_CCR_CLKEN)==0);
}
else
{
RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable/Disable Counter increment interrupt for each time type
* in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] CntIncrIntType: Counter Increment Interrupt type,
* an increment of this type value below will generates
* an interrupt, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] NewState New State of this function, should be:
* - ENABLE: Counter Increment interrupt for this time type are enabled
* - DISABLE: Counter Increment interrupt for this time type are disabled
* @return None
**********************************************************************/
void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, \
FunctionalState NewState)
{
uint32_t tem;
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
CHECK_PARAM(PARAM_RTC_TIMETYPE(CntIncrIntType));
switch (CntIncrIntType)
{
case RTC_TIMETYPE_SECOND:
tem = RTC_CIIR_IMSEC;
break;
case RTC_TIMETYPE_MINUTE:
tem = RTC_CIIR_IMMIN;
break;
case RTC_TIMETYPE_HOUR:
tem = RTC_CIIR_IMHOUR;
break;
case RTC_TIMETYPE_DAYOFWEEK:
tem = RTC_CIIR_IMDOW;
break;
case RTC_TIMETYPE_DAYOFMONTH:
tem = RTC_CIIR_IMDOM;
break;
case RTC_TIMETYPE_DAYOFYEAR:
tem = RTC_CIIR_IMDOY;
break;
case RTC_TIMETYPE_MONTH:
tem = RTC_CIIR_IMMON;
break;
case RTC_TIMETYPE_YEAR:
tem = RTC_CIIR_IMYEAR;
break;
}
if (NewState == ENABLE)
{
//do
{
RTCx->CIIR |= tem;
}
//while((RTCx->CIIR & tem)== 0);
}
else
{
//do
{
RTCx->CIIR &= (~tem) & RTC_CIIR_BITMASK;
}
//while(RTCx->CIIR & tem);
}
}
/*********************************************************************//**
* @brief Enable/Disable Alarm interrupt for each time type
* in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] AlarmTimeType: Alarm Time Interrupt type,
* an matching of this type value below with current time
* in RTC will generates an interrupt, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] NewState New State of this function, should be:
* - ENABLE: Alarm interrupt for this time type are enabled
* - DISABLE: Alarm interrupt for this time type are disabled
* @return None
**********************************************************************/
void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, \
FunctionalState NewState)
{
uint32_t tem;
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
CHECK_PARAM(PARAM_RTC_TIMETYPE(AlarmTimeType));
switch (AlarmTimeType)
{
case RTC_TIMETYPE_SECOND:
tem = (RTC_AMR_AMRSEC);
break;
case RTC_TIMETYPE_MINUTE:
tem = (RTC_AMR_AMRMIN);
break;
case RTC_TIMETYPE_HOUR:
tem = (RTC_AMR_AMRHOUR);
break;
case RTC_TIMETYPE_DAYOFWEEK:
tem = (RTC_AMR_AMRDOW);
break;
case RTC_TIMETYPE_DAYOFMONTH:
tem = (RTC_AMR_AMRDOM);
break;
case RTC_TIMETYPE_DAYOFYEAR:
tem = (RTC_AMR_AMRDOY);
break;
case RTC_TIMETYPE_MONTH:
tem = (RTC_AMR_AMRMON);
break;
case RTC_TIMETYPE_YEAR:
tem = (RTC_AMR_AMRYEAR);
break;
}
if (NewState == ENABLE)
{
//do
{
RTCx->AMR &= (~tem) & RTC_AMR_BITMASK;
}
//while(RTCx->AMR & tem);
}
else
{
//do
{
RTCx->AMR |= (tem);
}
//while((RTCx->AMR & tem)== 0);
}
}
/*********************************************************************//**
* @brief Set current time value for each time type in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] TimeValue Time value to set
* @return None
**********************************************************************/
void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));
switch ( Timetype)
{
case RTC_TIMETYPE_SECOND:
CHECK_PARAM(TimeValue <= RTC_SECOND_MAX);
RTCx->SEC = TimeValue & RTC_SEC_MASK;
break;
case RTC_TIMETYPE_MINUTE:
CHECK_PARAM(TimeValue <= RTC_MINUTE_MAX);
RTCx->MIN = TimeValue & RTC_MIN_MASK;
break;
case RTC_TIMETYPE_HOUR:
CHECK_PARAM(TimeValue <= RTC_HOUR_MAX);
RTCx->HRS = TimeValue & RTC_HOUR_MASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
CHECK_PARAM(TimeValue <= RTC_DAYOFWEEK_MAX);
RTCx->DOW = TimeValue & RTC_DOW_MASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
CHECK_PARAM((TimeValue <= RTC_DAYOFMONTH_MAX) \
&& (TimeValue >= RTC_DAYOFMONTH_MIN));
RTCx->DOM = TimeValue & RTC_DOM_MASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
CHECK_PARAM((TimeValue >= RTC_DAYOFYEAR_MIN) \
&& (TimeValue <= RTC_DAYOFYEAR_MAX));
RTCx->DOY = TimeValue & RTC_DOY_MASK;
break;
case RTC_TIMETYPE_MONTH:
CHECK_PARAM((TimeValue >= RTC_MONTH_MIN) \
&& (TimeValue <= RTC_MONTH_MAX));
RTCx->MONTH = TimeValue & RTC_MONTH_MASK;
break;
case RTC_TIMETYPE_YEAR:
CHECK_PARAM(TimeValue <= RTC_YEAR_MAX);
RTCx->YEAR = TimeValue & RTC_YEAR_MASK;
break;
}
}
/*********************************************************************//**
* @brief Get current time value for each type time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @return Value of time according to specified time type
**********************************************************************/
uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
return (RTCx->SEC & RTC_SEC_MASK);
case RTC_TIMETYPE_MINUTE:
return (RTCx->MIN & RTC_MIN_MASK);
case RTC_TIMETYPE_HOUR:
return (RTCx->HRS & RTC_HOUR_MASK);
case RTC_TIMETYPE_DAYOFWEEK:
return (RTCx->DOW & RTC_DOW_MASK);
case RTC_TIMETYPE_DAYOFMONTH:
return (RTCx->DOM & RTC_DOM_MASK);
case RTC_TIMETYPE_DAYOFYEAR:
return (RTCx->DOY & RTC_DOY_MASK);
case RTC_TIMETYPE_MONTH:
return (RTCx->MONTH & RTC_MONTH_MASK);
case RTC_TIMETYPE_YEAR:
return (RTCx->YEAR & RTC_YEAR_MASK);
default:
return (0);
}
}
/*********************************************************************//**
* @brief Set full of time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* contains time value in full.
* @return None
**********************************************************************/
void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK;
RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK;
RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK;
RTCx->HRS = pFullTime->HOUR & RTC_HOUR_MASK;
RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK;
RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK;
RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK;
RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Get full of time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* will be stored time in full.
* @return None
**********************************************************************/
void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK;
pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK;
pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK;
pFullTime->HOUR = RTCx->HRS & RTC_HOUR_MASK;
pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK;
pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK;
pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK;
pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Set alarm time value for each time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] ALValue Alarm time value to set
* @return None
**********************************************************************/
void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
CHECK_PARAM(ALValue <= RTC_SECOND_MAX);
RTCx->ASEC = ALValue & RTC_SEC_MASK;
break;
case RTC_TIMETYPE_MINUTE:
CHECK_PARAM(ALValue <= RTC_MINUTE_MAX);
RTCx->AMIN = ALValue & RTC_MIN_MASK;
break;
case RTC_TIMETYPE_HOUR:
CHECK_PARAM(ALValue <= RTC_HOUR_MAX);
RTCx->AHRS = ALValue & RTC_HOUR_MASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
CHECK_PARAM(ALValue <= RTC_DAYOFWEEK_MAX);
RTCx->ADOW = ALValue & RTC_DOW_MASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
CHECK_PARAM((ALValue <= RTC_DAYOFMONTH_MAX) \
&& (ALValue >= RTC_DAYOFMONTH_MIN));
RTCx->ADOM = ALValue & RTC_DOM_MASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
CHECK_PARAM((ALValue >= RTC_DAYOFYEAR_MIN) \
&& (ALValue <= RTC_DAYOFYEAR_MAX));
RTCx->ADOY = ALValue & RTC_DOY_MASK;
break;
case RTC_TIMETYPE_MONTH:
CHECK_PARAM((ALValue >= RTC_MONTH_MIN) \
&& (ALValue <= RTC_MONTH_MAX));
RTCx->AMON = ALValue & RTC_MONTH_MASK;
break;
case RTC_TIMETYPE_YEAR:
CHECK_PARAM(ALValue <= RTC_YEAR_MAX);
RTCx->AYRS = ALValue & RTC_YEAR_MASK;
break;
}
}
/*********************************************************************//**
* @brief Get alarm time value for each time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @return Value of Alarm time according to specified time type
**********************************************************************/
uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype)
{
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
return (RTCx->ASEC & RTC_SEC_MASK);
case RTC_TIMETYPE_MINUTE:
return (RTCx->AMIN & RTC_MIN_MASK);
case RTC_TIMETYPE_HOUR:
return (RTCx->AHRS & RTC_HOUR_MASK);
case RTC_TIMETYPE_DAYOFWEEK:
return (RTCx->ADOW & RTC_DOW_MASK);
case RTC_TIMETYPE_DAYOFMONTH:
return (RTCx->ADOM & RTC_DOM_MASK);
case RTC_TIMETYPE_DAYOFYEAR:
return (RTCx->ADOY & RTC_DOY_MASK);
case RTC_TIMETYPE_MONTH:
return (RTCx->AMON & RTC_MONTH_MASK);
case RTC_TIMETYPE_YEAR:
return (RTCx->AYRS & RTC_YEAR_MASK);
default:
return (0);
}
}
/*********************************************************************//**
* @brief Set full of alarm time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* contains alarm time value in full.
* @return None
**********************************************************************/
void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
RTCx->ADOM = pFullTime->DOM & RTC_DOM_MASK;
RTCx->ADOW = pFullTime->DOW & RTC_DOW_MASK;
RTCx->ADOY = pFullTime->DOY & RTC_DOY_MASK;
RTCx->AHRS = pFullTime->HOUR & RTC_HOUR_MASK;
RTCx->AMIN = pFullTime->MIN & RTC_MIN_MASK;
RTCx->ASEC = pFullTime->SEC & RTC_SEC_MASK;
RTCx->AMON = pFullTime->MONTH & RTC_MONTH_MASK;
RTCx->AYRS = pFullTime->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Get full of alarm time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* will be stored alarm time in full.
* @return None
**********************************************************************/
void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
pFullTime->DOM = RTCx->ADOM & RTC_DOM_MASK;
pFullTime->DOW = RTCx->ADOW & RTC_DOW_MASK;
pFullTime->DOY = RTCx->ADOY & RTC_DOY_MASK;
pFullTime->HOUR = RTCx->AHRS & RTC_HOUR_MASK;
pFullTime->MIN = RTCx->AMIN & RTC_MIN_MASK;
pFullTime->SEC = RTCx->ASEC & RTC_SEC_MASK;
pFullTime->MONTH = RTCx->AMON & RTC_MONTH_MASK;
pFullTime->YEAR = RTCx->AYRS & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Check whether if specified Location interrupt in
* RTC peripheral is set or not
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] IntType Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
* - RTC_INT_ALARM: Alarm generated an interrupt.
* @return New state of specified Location interrupt in RTC peripheral
* - SET
* - RESET
**********************************************************************/
IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_INT(IntType));
return ((RTCx->ILR & IntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Clear specified Location interrupt pending in
* RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] IntType Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.
* - RTC_INT_ALARM :Clear alarm interrupt pending
* @return None
**********************************************************************/
void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_INT(IntType));
RTCx->ILR = IntType;
}
/*********************************************************************//**
* @brief Enable/Disable calibration counter in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] NewState New State of this function, should be:
* - ENABLE :The calibration counter is enabled and counting
* - DISABLE :The calibration counter is disabled and reset to zero
* @return None
**********************************************************************/
void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
do
{
RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
}while(RTCx->CCR&RTC_CCR_CCALEN);
}
else
{
RTCx->CCR |= RTC_CCR_CCALEN;
}
}
/*********************************************************************//**
* @brief Configures Calibration in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] CalibValue Calibration value, should be in range from
* 0 to 131,072
* @param[in] CalibDir Calibration Direction, should be:
* - RTC_CALIB_DIR_FORWARD :Forward calibration
* - RTC_CALIB_DIR_BACKWARD :Backward calibration
* @return None
**********************************************************************/
void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir)
{
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_CALIB_DIR(CalibDir));
CHECK_PARAM(CalibValue < RTC_CALIBRATION_MAX);
RTCx->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK) \
| ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
}
/*********************************************************************//**
* @brief Write value to General purpose registers
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Channel General purpose registers Channel number,
* should be in range from 0 to 63.
* @param[in] Value Value to write
* @return None
* Note: These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset.
**********************************************************************/
void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value)
{
uint32_t *preg;
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));
preg = (uint32_t *)RTC_GPREG_BASE;
preg += Channel;
*preg = Value;
}
/*********************************************************************//**
* @brief Read value from General purpose registers
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Channel General purpose registers Channel number,
* should be in range from 0 to 4.
* @return Read Value
* Note: These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset.
**********************************************************************/
uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel)
{
uint32_t *preg;
uint32_t value;
CHECK_PARAM(PARAM_RTCx(RTCx));
CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));
preg = (uint32_t *)RTC_GPREG_BASE;
preg += Channel;
value = *preg;
return (value);
}
/**
* @}
*/
#endif /* _RTC */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

140
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c vendored
View file

@ -1,140 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_sct.c 2011-06-02
*//**
* @file lpc18xx_sct.c
* @brief Contains all functions support for SCT firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup SCT
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_sct.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _SCT
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SCT_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Select 16/32 bit SCT counter
* @param[in] value configuration value for SCT
* - SCT_CONFIG_16BIT_COUNTER :16-bit counter
* - SCT_CONFIG_32BIT_COUNTER :32-bit counter
* @return None
**********************************************************************/
void SCT_Config(uint32_t value)
{
CHECK_PARAM(PARAM_SCT_CONFIG_COUNTER_TYPE(value));
LPC_SCT->CONFIG = value;
}
/*********************************************************************//**
* @brief Setting SCT control
* @param[in] value setting value
* @param[in] ena Enable/disable status
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void SCT_ControlSet(uint32_t value, FunctionalState ena)
{
uint32_t tem;
CHECK_PARAM(PARAM_FUNCTIONALSTATE(ena));
tem = LPC_SCT->CTRL_U;
if(ena == ENABLE)
{
tem |= value;
}
else
{
tem &= (~value);
}
LPC_SCT->CTRL_U = tem;
}
/*********************************************************************//**
* @brief Set start mode for ADC
* @param[in] outnum number of SCT output, should be: 0..15
* @param[in] value solution value, should be
* - SCT_RES_NOCHANGE :No change
* - SCT_RES_SET_OUTPUT :Set output
* - SCT_RES_CLEAR_OUTPUT :Clear output
* - SCT_RES_TOGGLE_OUTPUT :Toggle output
* @return None
*********************************************************************/
void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value)
{
uint32_t tem;
CHECK_PARAM(PARAM_SCT_OUTPUT_NUM(outnum));
CHECK_PARAM(PARAM_SCT_RES(value));
tem = LPC_SCT->RES;
tem &= ~(0x03 << (2*outnum));
tem |= (value << (2*outnum));
LPC_SCT->RES = tem;
}
/*********************************************************************//**
* @brief Clear SCT event generating interrupt request
* @param[in] even_num SCT event number, should be: 0..15
* @return None
*********************************************************************/
void SCT_EventFlagClear(uint8_t even_num)
{
CHECK_PARAM(PARAM_SCT_EVENT(even_num));
LPC_SCT->EVFLAG = (1 << (even_num));
}
/**
* @}
*/
#endif /* _SCT */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

62
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_scu.c vendored
View file

@ -1,62 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_scu.c 2011-06-02
*//**
* @file lpc18xx_scu.c
* @brief Contains all functions support for SCU firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup SCU
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "LPC18xx.h" /* LPC18xx definitions */
#include "lpc_types.h"
#include "lpc18xx_scu.h"
/*********************************************************************//**
* @brief Configure pin function
* @param[in] port Port number, should be: 0..15
* @param[in] pin Pin number, should be: 0..31
* @param[in] mode Pin mode, should be:
* - MD_PUP :Pull-up enabled
* - MD_BUK :Plain input
* - MD_PLN :Repeater mode
* - MD_PDN :Pull-down enabled
* @param[in] func Function mode, should be:
* - FUNC0 :Function 0
* - FUNC1 :Function 1
* - FUNC2 :Function 2
* - FUNC3 :Function 3
* @return None
**********************************************************************/
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)
{
uint32_t * scu_base=(uint32_t*)(LPC_SCU_BASE);
scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;
} /* scu_pinmux */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

644
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c vendored
View file

@ -1,644 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_ssp.c 2011-06-02
*//**
* @file lpc18xx_ssp.c
* @brief Contains all functions support for SSP firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup SSP
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_ssp.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _SSP
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SSP_Private_Functions
* @{
*/
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SSP_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initializes the SSPx peripheral according to the specified
* parameters in the SSP_ConfigStruct.
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure that
* contains the configuration information for the specified
* SSP peripheral.
* @return None
*********************************************************************/
void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct)
{
uint32_t tmp;
uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
CHECK_PARAM(PARAM_SSPx(SSPx));
if(SSPx == LPC_SSP0) {
/* Set up clock and power for SSP0 module */
//LPC_CGU->BASE_SSP0_CLK = (SRC_PL160M_0<<24) | (1<<11);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP0);
} else if(SSPx == LPC_SSP1) {
/* Set up clock and power for SSP1 module */
//LPC_CGU->BASE_SSP1_CLK = (SRC_PL160M_0<<24) | (1<<11);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP1);
} else {
return;
}
/* Configure SSP, interrupt is disable, LoopBack mode is disable,
* SSP is disable, Slave output is disable as default
*/
tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \
| (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit))
& SSP_CR0_BITMASK;
// write back to SSP control register
SSPx->CR0 = tmp;
tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK;
// Write back to CR1
SSPx->CR1 = tmp;
// Set clock rate for SSP peripheral
if(SSPx == LPC_SSP0)
ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP0);
else
ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP1);
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > SSP_ConfigStruct->ClockRate)
{
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > SSP_ConfigStruct->ClockRate)
{
cr0_div++;
if (cr0_div > 0xFF)
{
cr0_div = 0;
prescale += 2;
}
}
}
/* Write computed prescaler and divider back to register */
SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
SSPx->CPSR = prescale & SSP_CPSR_BITMASK;
}
/*********************************************************************//**
* @brief De-initializes the SSPx peripheral registers to their
* default reset values.
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @return None
**********************************************************************/
void SSP_DeInit(LPC_SSPn_Type* SSPx)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
/* Disable SSP operation*/
SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
/*****************************************************************************//**
* @brief Get data size bit selected
* @param[in] SSPx pointer to LPC_SSPn_Type structure, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @return Data size, could be:
* - SSP_DATABIT_4 :4 bit transfer
* - SSP_DATABIT_5 :5 bit transfer
* ...
* - SSP_DATABIT_16 :16 bit transfer
*******************************************************************************/
uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
return (SSPx->CR0 & (0xF));
}
/*****************************************************************************//**
* @brief Fills each SSP_InitStruct member with its default value:
* - CPHA = SSP_CPHA_FIRST
* - CPOL = SSP_CPOL_HI
* - ClockRate = 1000000
* - Databit = SSP_DATABIT_8
* - Mode = SSP_MASTER_MODE
* - FrameFormat = SSP_FRAME_SSP
* @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure which will be
* initialized.
* @return None
*******************************************************************************/
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct)
{
SSP_InitStruct->CPHA = SSP_CPHA_FIRST;
SSP_InitStruct->CPOL = SSP_CPOL_HI;
SSP_InitStruct->ClockRate = 100000;
SSP_InitStruct->Databit = SSP_DATABIT_8;
SSP_InitStruct->Mode = SSP_MASTER_MODE;
SSP_InitStruct->FrameFormat = SSP_FRAME_SPI;
}
/*********************************************************************//**
* @brief Enable or disable SSP peripheral's operation
* @param[in] SSPx SSP peripheral, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] NewState New State of SSPx peripheral's operation, should be:
* - ENABLE
* - DISABLE
* @return none
**********************************************************************/
void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
SSPx->CR1 |= SSP_CR1_SSP_EN;
}
else
{
SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable or disable Loop Back mode function in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] NewState New State of Loop Back mode, should be:
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
SSPx->CR1 |= SSP_CR1_LBM_EN;
}
else
{
SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable or disable Slave Output function in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] NewState New State of Slave Output function, should be:
* - ENABLE :Slave Output in normal operation
* - DISABLE :Slave Output is disabled. This blocks
* SSP controller from driving the transmit data line (MISO)
* Note: This function is available when SSP peripheral in Slave mode
* @return None
**********************************************************************/
void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK;
}
else
{
SSPx->CR1 |= SSP_CR1_SO_DISABLE;
}
}
/*********************************************************************//**
* @brief Transmit a single data through SSPx peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] Data Data to transmit (must be 16 or 8-bit long, this
* depend on SSP data bit number configured)
* @return none
**********************************************************************/
void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
SSPx->DR = SSP_DR_BITMASK(Data);
}
/*********************************************************************//**
* @brief Receive a single data from SSPx peripheral
* @param[in] SSPx SSP peripheral selected, should be
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @return Data received (16-bit long)
**********************************************************************/
uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR)));
}
/*********************************************************************//**
* @brief SSP Read write data function
* @param[in] SSPx Pointer to SSP peripheral, should be
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that
* contains specified information about transmit data
* configuration.
* @param[in] xfType Transfer type, should be:
* - SSP_TRANSFER_POLLING :Polling mode
* - SSP_TRANSFER_INTERRUPT :Interrupt mode
* @return Actual Data length has been transferred in polling mode.
* In interrupt mode, always return (0)
* Return (-1) if error.
* Note: This function can be used in both master and slave mode.
***********************************************************************/
int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
SSP_TRANSFER_Type xfType)
{
uint8_t *rdata8;
uint8_t *wdata8;
uint16_t *rdata16;
uint16_t *wdata16;
uint32_t stat;
uint32_t tmp;
int32_t dataword;
dataCfg->rx_cnt = 0;
dataCfg->tx_cnt = 0;
dataCfg->status = 0;
/* Clear all remaining data in RX FIFO */
while (SSPx->SR & SSP_SR_RNE){
tmp = (uint32_t) SSP_ReceiveData(SSPx);
}
// Clear status
SSPx->ICR = SSP_ICR_BITMASK;
if(SSP_GetDataSize(SSPx)>8)
dataword = 1;
else dataword = 0;
// Polling mode ----------------------------------------------------------------------
if (xfType == SSP_TRANSFER_POLLING){
if (dataword == 0){
rdata8 = (uint8_t *)dataCfg->rx_data;
wdata8 = (uint8_t *)dataCfg->tx_data;
} else {
rdata16 = (uint16_t *)dataCfg->rx_data;
wdata16 = (uint16_t *)dataCfg->tx_data;
}
while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){
if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt != dataCfg->length)){
// Write data to buffer
if(dataCfg->tx_data == NULL){
if (dataword == 0){
SSP_SendData(SSPx, 0xFF);
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, 0xFFFF);
dataCfg->tx_cnt += 2;
}
} else {
if (dataword == 0){
SSP_SendData(SSPx, *wdata8);
wdata8++;
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, *wdata16);
wdata16++;
dataCfg->tx_cnt += 2;
}
}
}
// Check overrun error
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
// save status and return
dataCfg->status = stat | SSP_STAT_ERROR;
return (-1);
}
// Check for any data available in RX FIFO
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
// Read data from SSP data
tmp = SSP_ReceiveData(SSPx);
// Store data to destination
if (dataCfg->rx_data != NULL)
{
if (dataword == 0){
*(rdata8) = (uint8_t) tmp;
rdata8++;
} else {
*(rdata16) = (uint16_t) tmp;
rdata16++;
}
}
// Increase counter
if (dataword == 0){
dataCfg->rx_cnt++;
} else {
dataCfg->rx_cnt += 2;
}
}
}
// save status
dataCfg->status = SSP_STAT_DONE;
if (dataCfg->tx_data != NULL){
return dataCfg->tx_cnt;
} else if (dataCfg->rx_data != NULL){
return dataCfg->rx_cnt;
} else {
return (0);
}
}
// Interrupt mode ----------------------------------------------------------------------
else if (xfType == SSP_TRANSFER_INTERRUPT){
while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){
// Write data to buffer
if(dataCfg->tx_data == NULL){
if (dataword == 0){
SSP_SendData(SSPx, 0xFF);
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, 0xFFFF);
dataCfg->tx_cnt += 2;
}
} else {
if (dataword == 0){
SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
dataCfg->tx_cnt += 2;
}
}
// Check error
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
// save status and return
dataCfg->status = stat | SSP_STAT_ERROR;
return (-1);
}
// Check for any data available in RX FIFO
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
// Read data from SSP data
tmp = SSP_ReceiveData(SSPx);
// Store data to destination
if (dataCfg->rx_data != NULL)
{
if (dataword == 0){
*(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp;
} else {
*(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp;
}
}
// Increase counter
if (dataword == 0){
dataCfg->rx_cnt++;
} else {
dataCfg->rx_cnt += 2;
}
}
}
// If there more data to sent or receive
if ((dataCfg->rx_cnt != dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){
// Enable all interrupt
SSPx->IMSC = SSP_IMSC_BITMASK;
} else {
// Save status
dataCfg->status = SSP_STAT_DONE;
}
return (0);
}
return (-1);
}
/*********************************************************************//**
* @brief Checks whether the specified SSP status flag is set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] FlagType Type of flag to check status, should be:
* - SSP_STAT_TXFIFO_EMPTY :TX FIFO is empty
* - SSP_STAT_TXFIFO_NOTFULL :TX FIFO is not full
* - SSP_STAT_RXFIFO_NOTEMPTY :RX FIFO is not empty
* - SSP_STAT_RXFIFO_FULL :RX FIFO is full
* - SSP_STAT_BUSY :SSP peripheral is busy
* @return New State of specified SSP status flag
**********************************************************************/
FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_STAT(FlagType));
return ((SSPx->SR & FlagType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Enable or disable specified interrupt type in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] IntType Interrupt type in SSP peripheral, should be:
* - SSP_INTCFG_ROR :Receive Overrun interrupt
* - SSP_INTCFG_RT :Receive Time out interrupt
* - SSP_INTCFG_RX :RX FIFO is at least half full interrupt
* - SSP_INTCFG_TX :TX FIFO is at least half empty interrupt
* @param[in] NewState New State of specified interrupt type, should be:
* - ENABLE :Enable this interrupt type
* - DISABLE :Disable this interrupt type
* @return None
**********************************************************************/
void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_INTCFG(IntType));
if (NewState == ENABLE)
{
SSPx->IMSC |= IntType;
}
else
{
SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK;
}
}
/*********************************************************************//**
* @brief Check whether the specified Raw interrupt status flag is
* set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] RawIntType Raw Interrupt Type, should be:
* - SSP_INTSTAT_RAW_ROR :Receive Overrun interrupt
* - SSP_INTSTAT_RAW_RT :Receive Time out interrupt
* - SSP_INTSTAT_RAW_RX :RX FIFO is at least half full interrupt
* - SSP_INTSTAT_RAW_TX :TX FIFO is at least half empty interrupt
* @return New State of specified Raw interrupt status flag in SSP peripheral
* Note: Enabling/Disabling specified interrupt in SSP peripheral does not
* effect to Raw Interrupt Status flag.
**********************************************************************/
IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_INTSTAT_RAW(RawIntType));
return ((SSPx->RIS & RawIntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Check whether the specified interrupt status flag is
* set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] IntType Raw Interrupt Type, should be:
* - SSP_INTSTAT_ROR :Receive Overrun interrupt
* - SSP_INTSTAT_RT :Receive Time out interrupt
* - SSP_INTSTAT_RX :RX FIFO is at least half full interrupt
* - SSP_INTSTAT_TX :TX FIFO is at least half empty interrupt
* @return New State of specified interrupt status flag in SSP peripheral
* Note: Enabling/Disabling specified interrupt in SSP peripheral effects
* to Interrupt Status flag.
**********************************************************************/
IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_INTSTAT(IntType));
return ((SSPx->MIS & IntType) ? SET :RESET);
}
/*********************************************************************//**
* @brief Clear specified interrupt pending in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] IntType Interrupt pending to clear, should be:
* - SSP_INTCLR_ROR :clears the "frame was received when
* RxFIFO was full" interrupt.
* - SSP_INTCLR_RT :clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt.
* @return None
**********************************************************************/
void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_INTCLR(IntType));
SSPx->ICR = IntType;
}
/*********************************************************************//**
* @brief Enable/Disable DMA function for SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0 :SSP0 peripheral
* - LPC_SSP1 :SSP1 peripheral
* @param[in] DMAMode Type of DMA, should be:
* - SSP_DMA_TX :DMA for the transmit FIFO
* - SSP_DMA_RX :DMA for the Receive FIFO
* @param[in] NewState New State of DMA function on SSP peripheral,
* should be:
* - ENALBE :Enable this function
* - DISABLE :Disable this function
* @return None
**********************************************************************/
void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState)
{
CHECK_PARAM(PARAM_SSPx(SSPx));
CHECK_PARAM(PARAM_SSP_DMA(DMAMode));
CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
if (NewState == ENABLE)
{
SSPx->DMACR |= DMAMode;
}
else
{
SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK;
}
}
/**
* @}
*/
#endif /* _SSP */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

611
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c vendored
View file

@ -1,611 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_timer.c 2011-06-02
*//**
* @file lpc18xx_timer.c
* @brief Contains all functions support for Timer firmware library on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup TIMER
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_timer.h"
#include "lpc18xx_cgu.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _TIM
/* Private Functions ---------------------------------------------------------- */
static uint32_t getPClock (uint32_t timernum);
static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec);
static uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx);
/*********************************************************************//**
* @brief Get peripheral clock of each timer controller
* @param[in] timernum Timer number, should be: 0..3
* @return Peripheral clock of timer
**********************************************************************/
extern uint32_t M3Frequency;
static uint32_t getPClock (uint32_t timernum)
{
uint32_t clkdlycnt;
switch (timernum)
{
case 0:
clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER0)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER0);
break;
case 1:
clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER1)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER1);
break;
case 2:
clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER2)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER2);
break;
case 3:
clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER3)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER3);
break;
}
return clkdlycnt;
}
/*********************************************************************//**
* @brief Convert a time to a timer count value
* @param[in] timernum Timer number, should be: 0..3
* @param[in] usec Time in microseconds
* @return The number of required clock ticks to give the time delay
**********************************************************************/
uint32_t converUSecToVal (uint32_t timernum, uint32_t usec)
{
uint64_t clkdlycnt;
// Get Pclock of timer
clkdlycnt = (uint64_t) getPClock(timernum);
clkdlycnt = (clkdlycnt * usec) / 1000000;
return (uint32_t) clkdlycnt;
}
/*********************************************************************//**
* @brief Convert a timer register pointer to a timer number
* @param[in] TIMx Pointer to LPC_TIMERn_Type, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @return The timer number (0 to 3) or -1 if register pointer is bad
**********************************************************************/
uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx)
{
uint32_t tnum = 0xFFFFFFFF;
if (TIMx == LPC_TIMER0)
{
tnum = 0;
}
else if (TIMx == LPC_TIMER1)
{
tnum = 1;
}
else if (TIMx == LPC_TIMER2)
{
tnum = 2;
}
else if (TIMx == LPC_TIMER3)
{
tnum = 3;
}
return tnum;
}
/* End of Private Functions ---------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup TIM_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Get Interrupt Status
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] IntFlag: interrupt type, should be:
* - TIM_MR0_INT :Interrupt for Match channel 0
* - TIM_MR1_INT :Interrupt for Match channel 1
* - TIM_MR2_INT :Interrupt for Match channel 2
* - TIM_MR3_INT :Interrupt for Match channel 3
* - TIM_CR0_INT :Interrupt for Capture channel 0
* - TIM_CR1_INT :Interrupt for Capture channel 1
* @return FlagStatus
* - SET :interrupt
* - RESET :no interrupt
**********************************************************************/
FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)
{
uint8_t temp;
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
temp = (TIMx->IR)& TIM_IR_CLR(IntFlag);
if (temp)
return SET;
return RESET;
}
/*********************************************************************//**
* @brief Get Capture Interrupt Status
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] IntFlag: interrupt type, should be:
* - TIM_MR0_INT :Interrupt for Match channel 0
* - TIM_MR1_INT :Interrupt for Match channel 1
* - TIM_MR2_INT :Interrupt for Match channel 2
* - TIM_MR3_INT :Interrupt for Match channel 3
* - TIM_CR0_INT :Interrupt for Capture channel 0
* - TIM_CR1_INT :Interrupt for Capture channel 1
* @return FlagStatus
* - SET :interrupt
* - RESET :no interrupt
**********************************************************************/
FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)
{
uint8_t temp;
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
temp = (TIMx->IR) & (1<<(4+IntFlag));
if(temp)
return SET;
return RESET;
}
/*********************************************************************//**
* @brief Clear Interrupt pending
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] IntFlag: interrupt type, should be:
* - TIM_MR0_INT :Interrupt for Match channel 0
* - TIM_MR1_INT :Interrupt for Match channel 1
* - TIM_MR2_INT :Interrupt for Match channel 2
* - TIM_MR3_INT :Interrupt for Match channel 3
* - TIM_CR0_INT :Interrupt for Capture channel 0
* - TIM_CR1_INT :Interrupt for Capture channel 1
* @return None
**********************************************************************/
void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
TIMx->IR = TIM_IR_CLR(IntFlag);
}
/*********************************************************************//**
* @brief Clear Capture Interrupt pending
* @param[in] TIMx Timer selection, should be
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] IntFlag interrupt type, should be:
* - TIM_MR0_INT :Interrupt for Match channel 0
* - TIM_MR1_INT :Interrupt for Match channel 1
* - TIM_MR2_INT :Interrupt for Match channel 2
* - TIM_MR3_INT :Interrupt for Match channel 3
* - TIM_CR0_INT :Interrupt for Capture channel 0
* - TIM_CR1_INT :Interrupt for Capture channel 1
* @return None
**********************************************************************/
void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
TIMx->IR = (1<<(4+IntFlag));
}
/*********************************************************************//**
* @brief Configuration for Timer at initial time
* @param[in] TimerCounterMode timer counter mode, should be:
* - TIM_TIMER_MODE :Timer mode
* - TIM_COUNTER_RISING_MODE :Counter rising mode
* - TIM_COUNTER_FALLING_MODE :Counter falling mode
* - TIM_COUNTER_ANY_MODE :Counter on both edges
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or
* TIM_COUNTERCFG_Type
* @return None
**********************************************************************/
void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
{
if (TimerCounterMode == TIM_TIMER_MODE )
{
TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL;
pTimeCfg->PrescaleValue = 1;
}
else
{
TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0;
}
}
/*********************************************************************//**
* @brief Initial Timer/Counter device
* Set Clock frequency for Timer
* Set initial configuration for Timer
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] TimerCounterMode Timer counter mode, should be:
* - TIM_TIMER_MODE :Timer mode
* - TIM_COUNTER_RISING_MODE :Counter rising mode
* - TIM_COUNTER_FALLING_MODE :Counter falling mode
* - TIM_COUNTER_ANY_MODE :Counter on both edges
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type
* that contains the configuration information for the
* specified Timer peripheral.
* @return None
**********************************************************************/
void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
{
TIM_TIMERCFG_Type *pTimeCfg;
TIM_COUNTERCFG_Type *pCounterCfg;
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode));
//set power
if (TIMx== LPC_TIMER0)
{
}
else if (TIMx== LPC_TIMER1)
{
}
else if (TIMx== LPC_TIMER2)
{
}
else if (TIMx== LPC_TIMER3)
{
}
TIMx->CCR &= ~TIM_CTCR_MODE_MASK;
TIMx->CCR |= TIM_TIMER_MODE;
TIMx->TC =0;
TIMx->PC =0;
TIMx->PR =0;
TIMx->TCR |= (1<<1); //Reset Counter
TIMx->TCR &= ~(1<<1); //release reset
if (TimerCounterMode == TIM_TIMER_MODE )
{
pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)
{
TIMx->PR = pTimeCfg->PrescaleValue -1 ;
}
else
{
TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;
}
}
else
{
pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
TIMx->CCR &= ~TIM_CTCR_INPUT_MASK;
if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)
TIMx->CCR |= _BIT(2);
}
// Clear interrupt pending
TIMx->IR = 0xFFFFFFFF;
}
/*********************************************************************//**
* @brief Close Timer/Counter device
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @return None
**********************************************************************/
void TIM_DeInit (LPC_TIMERn_Type *TIMx)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
// Disable timer/counter
TIMx->TCR = 0x00;
}
/*********************************************************************//**
* @brief Start/Stop Timer/Counter device
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] NewState
* - ENABLE :Set timer enable
* - DISABLE :Disable timer
* @return None
**********************************************************************/
void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
if (NewState == ENABLE)
{
TIMx->TCR |= TIM_ENABLE;
}
else
{
TIMx->TCR &= ~TIM_ENABLE;
}
}
/*********************************************************************//**
* @brief Reset Timer/Counter device,
* Make TC and PC are synchronously reset on the next
* positive edge of PCLK
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @return None
**********************************************************************/
void TIM_ResetCounter(LPC_TIMERn_Type *TIMx)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
TIMx->TCR |= TIM_RESET;
TIMx->TCR &= ~TIM_RESET;
}
/*********************************************************************//**
* @brief Configuration for Match register
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type
* - MatchChannel : choose channel 0 or 1
* - IntOnMatch : if SET, interrupt will be generated when MRxx match
* the value in TC
* - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match
* the value in TC
* - ResetOnMatch : if SET, Reset on MR0 when MRxx match
* the value in TC
* -ExtMatchOutputType: Select output for external match
* + 0: Do nothing for external output pin if match
* + 1: Force external output pin to low if match
* + 2: Force external output pin to high if match
* + 3: Toggle external output pin if match
* MatchValue: Set the value to be compared with TC value
* @return None
**********************************************************************/
void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_EXTMATCH_OPT(TIM_MatchConfigStruct->ExtMatchOutputType));
switch(TIM_MatchConfigStruct->MatchChannel)
{
case 0:
TIMx->MR[0] = TIM_MatchConfigStruct->MatchValue;
break;
case 1:
TIMx->MR[1] = TIM_MatchConfigStruct->MatchValue;
break;
case 2:
TIMx->MR[2] = TIM_MatchConfigStruct->MatchValue;
break;
case 3:
TIMx->MR[3] = TIM_MatchConfigStruct->MatchValue;
break;
default:
//Error match value
//Error loop
while(1);
}
//interrupt on MRn
TIMx->MCR &=~TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel);
if (TIM_MatchConfigStruct->IntOnMatch)
TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
//reset on MRn
if (TIM_MatchConfigStruct->ResetOnMatch)
TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
//stop on MRn
if (TIM_MatchConfigStruct->StopOnMatch)
TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
// match output type
TIMx->EMR &= ~TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel);
TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType);
}
/*********************************************************************//**
* @brief Update Match value
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] MatchChannel Match channel, should be: 0..3
* @param[in] MatchValue updated match value
* @return None
**********************************************************************/
void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
switch(MatchChannel)
{
case 0:
TIMx->MR[0] = MatchValue;
break;
case 1:
TIMx->MR[1] = MatchValue;
break;
case 2:
TIMx->MR[2] = MatchValue;
break;
case 3:
TIMx->MR[3] = MatchValue;
break;
default:
//Error Loop
while(1);
}
}
/*********************************************************************//**
* @brief Configuration for Capture register
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type
* @return None
**********************************************************************/
void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->RisingEdge)
TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->FallingEdge)
TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->IntOnCaption)
TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel);
}
/*********************************************************************//**
* @brief Read value of capture register in timer/counter device
* @param[in] TIMx Pointer to timer/counter device, should be:
* - LPC_TIM0 :TIMER0 peripheral
* - LPC_TIM1 :TIMER1 peripheral
* - LPC_TIM2 :TIMER2 peripheral
* - LPC_TIM3 :TIMER3 peripheral
* @param[in] CaptureChannel: capture channel number, should be:
* - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
* - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
* - TIM_COUNTER_INCAP1: CAPn.2 input pin for TIMERn
* - TIM_COUNTER_INCAP1: CAPn.3 input pin for TIMERn
* @return Value of capture register
**********************************************************************/
uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel)
{
CHECK_PARAM(PARAM_TIMx(TIMx));
CHECK_PARAM(PARAM_TIM_COUNTER_INPUT_OPT(CaptureChannel));
switch(CaptureChannel){
case 0: return TIMx->CR[0];
case 1: return TIMx->CR[1];
case 2: return TIMx->CR[2];
case 3: return TIMx->CR[3];
}
return 0;
}
/*---------------Advanced TIMER functions -----------------------------------------*/
/*********************************************************************//**
* @brief Timer wait (microseconds)
* @param[in] time number of microseconds waiting
* @return None
**********************************************************************/
void TIM_Waitus(uint32_t time)
{
TIM_MATCHCFG_Type MatchConfigStruct;
LPC_TIMER0->IR = 0xFFFFFFFF;
MatchConfigStruct.MatchChannel = 0;
MatchConfigStruct.IntOnMatch = ENABLE;
MatchConfigStruct.ResetOnMatch = ENABLE;
MatchConfigStruct.StopOnMatch = ENABLE;
MatchConfigStruct.ExtMatchOutputType = 0;
MatchConfigStruct.MatchValue = time;
TIM_ConfigMatch(LPC_TIMER0, &MatchConfigStruct);
TIM_Cmd(LPC_TIMER0,ENABLE);
//wait until interrupt flag occur
while(!(LPC_TIMER0->IR & 0x01));
TIM_ResetCounter(LPC_TIMER0);
}
/*********************************************************************//**
* @brief Timer wait (milliseconds)
* @param[in] time number of millisecond waiting
* @return None
**********************************************************************/
void TIM_Waitms(uint32_t time)
{
TIM_Waitus(time * 1000);
}
/**
* @}
*/
#endif /* _TIMER */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

1438
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c vendored
View file

File diff suppressed because it is too large Load diff

79
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c vendored
View file

@ -1,79 +0,0 @@
#include "lpc18xx_utils.h"
#include "lpc18xx_timer.h"
//timer init
TIM_TIMERCFG_Type TIM_ConfigStruct;
TIM_MATCHCFG_Type TIM_MatchConfigStruct;
/*********************************************************************//**
* @brief Main TIMER program body
* @param[in] None
* @return int
**********************************************************************/
int timer_delay_us( int cnt)
{
// Initialize timer 0, prescale count time of 1uS
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
TIM_ConfigStruct.PrescaleValue = 20;
// use channel 0, MR0
TIM_MatchConfigStruct.MatchChannel = 0;
// Disable interrupt when MR0 matches the value in TC register
TIM_MatchConfigStruct.IntOnMatch = TRUE;
//Enable reset on MR0: TIMER will reset if MR0 matches it
TIM_MatchConfigStruct.ResetOnMatch = TRUE;
//Stop on MR0 if MR0 matches it
TIM_MatchConfigStruct.StopOnMatch = TRUE;
TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING;
TIM_MatchConfigStruct.MatchValue = cnt;
// Set configuration for Tim_config and Tim_MatchConfig
TIM_Init(LPC_TIMER0, TIM_TIMER_MODE,&TIM_ConfigStruct);
TIM_ConfigMatch(LPC_TIMER0,&TIM_MatchConfigStruct);
TIM_Cmd(LPC_TIMER0,ENABLE);
while ( !(TIM_GetIntStatus(LPC_TIMER0,TIM_MR0_INT)));
TIM_ClearIntPending(LPC_TIMER0,(TIM_INT_TYPE)0);
return 0;
}
/*********************************************************************//**
* @brief Main TIMER program body
* @param[in] None
* @return int
**********************************************************************/
int timer_delay_ms( int cnt)
{
// Initialize timer 0, prescale count time of 1uS
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
TIM_ConfigStruct.PrescaleValue = 1000;
// use channel 0, MR0
TIM_MatchConfigStruct.MatchChannel = 1;
// Disable interrupt when MR0 matches the value in TC register
TIM_MatchConfigStruct.IntOnMatch = TRUE;
//Enable reset on MR0: TIMER will reset if MR0 matches it
TIM_MatchConfigStruct.ResetOnMatch = TRUE;
//Stop on MR0 if MR0 matches it
TIM_MatchConfigStruct.StopOnMatch = TRUE;
TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING;
TIM_MatchConfigStruct.MatchValue = cnt;
// Set configuration for Tim_config and Tim_MatchConfig
TIM_Init(LPC_TIMER1, TIM_TIMER_MODE,&TIM_ConfigStruct);
TIM_ConfigMatch(LPC_TIMER1,&TIM_MatchConfigStruct);
TIM_Cmd(LPC_TIMER1,ENABLE);
while ( !(TIM_GetIntStatus(LPC_TIMER1,TIM_MR1_INT)));
TIM_ClearIntPending(LPC_TIMER1,(TIM_INT_TYPE)1);
return 0;
}

268
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c vendored
View file

@ -1,268 +0,0 @@
/**********************************************************************
* $Id$ lpc18xx_wwdt.c 2011-06-02
*//**
* @file lpc18xx_wwdt.c
* @brief Contains all functions support for WDT firmware library
* on LPC18xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup WWDT
* @{
*/
/* Includes ------------------------------------------------------------------- */
#include "lpc18xx_wwdt.h"
/* If this source file built with example, the LPC18xx FW library configuration
* file in each example directory ("lpc18xx_libcfg.h") must be included,
* otherwise the default FW library configuration file must be included instead
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc18xx_libcfg.h"
#else
#include "lpc18xx_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _WWDT
void WWDT_SetTimeOut(uint32_t timeout);
/*********************************************************************//**
* @brief Update WDT timeout value and feed
* @param[in] timeout WDT timeout (us)
* @return none
**********************************************************************/
void WWDT_SetTimeOut(uint32_t timeout)
{
uint32_t timeoutVal;
timeoutVal = WDT_GET_FROM_USEC(timeout);
if(timeoutVal < WWDT_TIMEOUT_MIN)
{
timeoutVal = WWDT_TIMEOUT_MIN;
}
else if (timeoutVal > WWDT_TIMEOUT_MAX)
{
timeoutVal = WWDT_TIMEOUT_MAX;
}
LPC_WWDT->TC = timeoutVal;
}
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup WDT_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial for Watchdog function
* @param[in] none
* @return None
**********************************************************************/
void WWDT_Init(void)
{
LPC_WWDT->MOD = 0; // Clear time out and interrupt flags
LPC_WWDT->TC = WWDT_TIMEOUT_MIN; // Reset time out
LPC_WWDT->WARNINT= 0; // Reset warning value
LPC_WWDT->WINDOW = WWDT_WINDOW_MAX; // Reset window value
}
/********************************************************************//**
* @brief Update WDT timeout value and feed
* @param[in] TimeOut TimeOut value to be updated, should be in range:
* 2048 .. 134217728
* @return None
*********************************************************************/
void WDT_UpdateTimeOut(uint32_t TimeOut)
{
/* check WDPROTECT,
* if it is enable, wait until the counter is below the value of
* WDWARNINT and WDWINDOW
*/
if(LPC_WWDT->MOD & (1<<4))
{
while((LPC_WWDT->TV <(LPC_WWDT->WARNINT & WWDT_WDWARNINT_MASK))\
&&(LPC_WWDT->TV <(LPC_WWDT->WINDOW & WWDT_WDTC_MASK)));
}
WWDT_SetTimeOut(TimeOut);
}
/********************************************************************//**
* @brief After set WDTEN, call this function to start Watchdog
* or reload the Watchdog timer
* @param[in] None
* @return None
*********************************************************************/
void WWDT_Feed (void)
{
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55;
}
/********************************************************************//**
* @brief Update WDT timeout value and feed
* @param[in] WarnTime time to generate watchdog warning interrupt(us)
* should be in range: 2048 .. 8192
* @return None
*********************************************************************/
void WWDT_SetWarning(uint32_t WarnTime)
{
uint32_t warnVal;
warnVal = WDT_GET_FROM_USEC(WarnTime);
if(warnVal <= WWDT_WARNINT_MIN)
{
warnVal = WWDT_WARNINT_MIN;
}
else if (warnVal >= WWDT_WARNINT_MAX)
{
warnVal = WWDT_WARNINT_MAX;
}
LPC_WWDT->WARNINT = warnVal;
}
/********************************************************************//**
* @brief Update WDT timeout value and feed
* @param[in] WindowedTime expected time to set watchdog window event(us)
* @return none
*********************************************************************/
void WWDT_SetWindow(uint32_t WindowedTime)
{
uint32_t wndVal;
wndVal = WDT_GET_FROM_USEC(WindowedTime);
if(wndVal <= WWDT_WINDOW_MIN)
{
wndVal = WWDT_WINDOW_MIN;
}
else if (wndVal >= WWDT_WINDOW_MAX)
{
wndVal = WWDT_WINDOW_MAX;
}
LPC_WWDT->WINDOW = wndVal;
}
/*********************************************************************//**
* @brief Enable/Disable WWDT activity
* @param[in] None
* @return None
**********************************************************************/
void WWDT_Configure(st_Wdt_Config wdtCfg)
{
WWDT_SetTimeOut(wdtCfg.wdtTmrConst);
if(wdtCfg.wdtReset)
{
LPC_WWDT->MOD |= WWDT_WDMOD_WDRESET;
}
else
{
LPC_WWDT->MOD &= ~WWDT_WDMOD_WDRESET;
}
if(wdtCfg.wdtProtect)
{
LPC_WWDT->MOD |= WWDT_WDMOD_WDPROTECT;
}
else
{
LPC_WWDT->MOD &= ~WWDT_WDMOD_WDPROTECT;
}
}
/*********************************************************************//**
* @brief Enable WWDT activity
* @param[in] None
* @return None
**********************************************************************/
void WWDT_Start(void)
{
LPC_WWDT->MOD |= WWDT_WDMOD_WDEN;
WWDT_Feed();
}
/********************************************************************//**
* @brief Read WWDT status flag
* @param[in] Status kind of status flag that you want to get, should be:
* - WWDT_WARNINT_FLAG: watchdog interrupt flag
* - WWDT_TIMEOUT_FLAG: watchdog time-out flag
* @return Time out flag status of WDT
*********************************************************************/
FlagStatus WWDT_GetStatus (uint8_t Status)
{
if(Status == WWDT_WARNINT_FLAG)
{
return ((FlagStatus)(LPC_WWDT->MOD & (1<<3)));
}
else if (Status == WWDT_TIMEOUT_FLAG)
{
return ((FlagStatus)(LPC_WWDT->MOD & (1<<2)));
}
return (FlagStatus)RESET;
}
/********************************************************************//**
* @brief Read WWDT status flag
* @param[in] Status kind of status flag that you want to get, should be:
* - WWDT_WARNINT_FLAG: watchdog interrupt flag
* - WWDT_TIMEOUT_FLAG: watchdog time-out flag
* @return Time out flag status of WDT
*********************************************************************/
void WWDT_ClearStatusFlag (uint8_t flag)
{
if(flag == WWDT_WARNINT_FLAG)
{
// Write 1 to this bit to clear itself
LPC_WWDT->MOD |= WWDT_WDMOD_WDINT;
}
else if(flag == WWDT_TIMEOUT_FLAG)
{
// Write 0 to this bit to clear itself
LPC_WWDT->MOD &= ~ WWDT_WDMOD_WDTOF;
}
}
/********************************************************************//**
* @brief Get the current value of WDT
* @param[in] None
* @return current value of WDT
*********************************************************************/
uint32_t WWDT_GetCurrentCount(void)
{
return LPC_WWDT->TV;
}
/**
* @}
*/
#endif /* _WWDT */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

76
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/system_LPC18xx.c vendored
View file

@ -1,76 +0,0 @@
/*
* Modifications for use with Code Red's toolchain - 2011/11/24
*/
/**********************************************************************
* $Id$ system_LPC18xx.c 2011-06-02
*//**
* @file system_LPC18xx.c
* @brief Cortex-M3 Device System Source File for NXP LPC18xx Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include "LPC18xx.h"
#include "lpc18xx_cgu.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IRC (12000000UL) /* IRC Oscillator frequency */
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __IRC * 10UL; /*!< System Clock Frequency (Core Clock)*/
#ifndef __CODE_RED
extern uint32_t getPC(void);
#endif
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef __CODE_RED
// CodeRed startup code will modify VTOR register to match
// when code has been linked to run from.
// Check whether we are running from external flash
if (SCB->VTOR == 0x1C000000)
/*Enable Buffer for External Flash*/
LPC_EMC->STATICCONFIG0 |= 1<<19;
// Call clock initialisation code
CGU_Init();
#else
// Enable VTOR register to point to vector table
SCB->VTOR = getPC() & 0xFFF00000;
/*Enable Buffer for External Flash*/
LPC_EMC->STATICCONFIG0 |= 1<<19;
#endif
}

256
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Common/Attributes.h vendored Normal file
View file

@ -0,0 +1,256 @@
/*
* @brief Compilers's specific attributes
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_Common
* @defgroup Group_FuncVarAttributes Function/Variable Attributes
* @brief Special function/variable attribute macros.
*
* This module contains macros for applying specific attributes to functions and variables to control various
* optimizer and code generation features of the compiler. Attributes may be placed in the function prototype
* or variable declaration in any order, and multiple attributes can be specified for a single item via a space
* separated list.
*
* On incompatible versions of GCC or on other compilers, these macros evaluate to nothing unless they are
* critical to the code's function and thus must throw a compile error when used.
*
* @{
*/
#ifndef __LPCUSBlib_FUNCATTR_H__
#define __LPCUSBlib_FUNCATTR_H__
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_COMMON_H)
#error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
#if (__GNUC__ >= 3) || defined(__DOXYGEN__)
/** Indicates to the compiler that the function can not ever return, so that any stack restoring or
* return code may be omitted by the compiler in the resulting binary.
*/
#define ATTR_NO_RETURN __attribute__ ((noreturn))
/** Indicates that the function returns a value which should not be ignored by the user code. When
* applied, any ignored return value from calling the function will produce a compiler warning.
*/
#define ATTR_WARN_UNUSED_RESULT __attribute__ ((warn_unused_result))
/** Indicates that the specified parameters of the function are pointers which should never be \c NULL.
* When applied as a 1-based comma separated list the compiler will emit a warning if the specified
* parameters are known at compiler time to be \c NULL at the point of calling the function.
*/
#define ATTR_NON_NULL_PTR_ARG(...) __attribute__ ((nonnull (__VA_ARGS__)))
/** Removes any preamble or postamble from the function. When used, the function will not have any
* register or stack saving code. This should be used with caution, and when used the programmer
* is responsible for maintaining stack and register integrity.
*/
#define ATTR_NAKED __attribute__ ((naked))
/** Prevents the compiler from considering a specified function for in-lining. When applied, the given
* function will not be in-lined under any circumstances.
*/
#define ATTR_NO_INLINE __attribute__ ((noinline))
/** Forces the compiler to inline the specified function. When applied, the given function will be
* in-lined under all circumstances.
*/
#define PRAGMA_ALWAYS_INLINE
#define ATTR_ALWAYS_INLINE __attribute__ ((always_inline))
/** Indicates that the specified function is pure, in that it has no side-effects other than global
* or parameter variable access.
*/
#define ATTR_PURE __attribute__ ((pure))
/** Indicates that the specified function is constant, in that it has no side effects other than
* parameter access.
*/
#define ATTR_CONST __attribute__ ((const))
/** Marks a given function as deprecated, which produces a warning if the function is called. */
#define ATTR_DEPRECATED __attribute__ ((deprecated))
/** Marks a function as a weak reference, which can be overridden by other functions with an
* identical name (in which case the weak reference is discarded at link time).
*/
#define PRAGMA_WEAK(func,alias)
#define ATTR_WEAK __attribute__ ((weak))
/** Marks a function as an alias for another function.
*
* @param Func Name of the function which the given function name should alias.
*/
#define ATTR_ALIAS(Func) __attribute__ ((alias( #Func )))
/** Forces the compiler to not automatically zero the given global variable on startup, so that the
* current RAM contents is retained. Under most conditions this value will be random due to the
* behaviour of volatile memory once power is removed, but may be used in some specific circumstances,
* like the passing of values back after a system watchdog reset.
*/
#define ATTR_NO_INIT __attribute__ ((section (".noinit")))
/** Indicates the minimum alignment in bytes for a variable or struct element.
*
* @param Bytes Minimum number of bytes the item should be aligned to.
*/
#define PRAGMA_ALIGN_4096
#define PRAGMA_ALIGN_2048
#define PRAGMA_ALIGN_256
#define PRAGMA_ALIGN_128
#define PRAGMA_ALIGN_64
#define PRAGMA_ALIGN_48
#define PRAGMA_ALIGN_32
#define PRAGMA_ALIGN_4
#define ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
#define ATTR_DEPRECATED __attribute__ ((deprecated))
#if defined (__CC_ARM)
#define ATTR_ERROR(Message) //__attribute__ (( error(Message) ))
#else
#define ATTR_ERROR(Message) __attribute__ (( error(Message) ))
#endif
#define ATTR_WARNING(Message) __attribute__ (( warning(Message) ))
#define ATTR_IAR_PACKED
#define ATTR_PACKED __attribute__ ((packed))
#endif
#if defined(__ICCARM__)
/** Indicates to the compiler that the function can not ever return, so that any stack restoring or
* return code may be omitted by the compiler in the resulting binary.
*/
#define ATTR_NO_RETURN
/** Indicates that the function returns a value which should not be ignored by the user code. When
* applied, any ignored return value from calling the function will produce a compiler warning.
*/
#define ATTR_WARN_UNUSED_RESULT
/** Indicates that the specified parameters of the function are pointers which should never be \c NULL.
* When applied as a 1-based comma separated list the compiler will emit a warning if the specified
* parameters are known at compiler time to be \c NULL at the point of calling the function.
*/
#define ATTR_NON_NULL_PTR_ARG(...)
/** Removes any preamble or postamble from the function. When used, the function will not have any
* register or stack saving code. This should be used with caution, and when used the programmer
* is responsible for maintaining stack and register integrity.
*/
#define ATTR_NAKED __attribute__ ((naked))
/** Prevents the compiler from considering a specified function for in-lining. When applied, the given
* function will not be in-lined under any circumstances.
*/
#define ATTR_NO_INLINE __attribute__ ((noinline))
/** Forces the compiler to inline the specified function. When applied, the given function will be
* in-lined under all circumstances.
*/
#define PRAGMA_ALWAYS_INLINE _Pragma("inline=forced")
#define ATTR_ALWAYS_INLINE
/** Indicates that the specified function is pure, in that it has no side-effects other than global
* or parameter variable access.
*/
#define ATTR_PURE __attribute__ ((pure))
/** Indicates that the specified function is constant, in that it has no side effects other than
* parameter access.
*/
#define ATTR_CONST
/** Marks a given function as deprecated, which produces a warning if the function is called. */
#define ATTR_DEPRECATED// __attribute__ ((deprecated))
/** Marks a function as a weak reference, which can be overridden by other functions with an
* identical name (in which case the weak reference is discarded at link time).
*/
#define _PPTOSTR_(x) #x
#define PRAGMA_WEAK(name, vector) _Pragma(_PPTOSTR_(weak name=vector))
#define ATTR_WEAK
/** Marks a function as an alias for another function.
*
* @param Func Name of the function which the given function name should alias.
*/
#define ATTR_ALIAS(Func)
/** Forces the compiler to not automatically zero the given global variable on startup, so that the
* current RAM contents is retained. Under most conditions this value will be random due to the
* behaviour of volatile memory once power is removed, but may be used in some specific circumstances,
* like the passing of values back after a system watchdog reset.
*/
#define ATTR_NO_INIT __attribute__ ((section (".noinit")))
/** Indicates the minimum alignment in bytes for a variable or struct element.
*
* @param Bytes Minimum number of bytes the item should be aligned to.
*/
#define PRAGMA_ALIGN_4096 _Pragma("data_alignment=4096")
#define PRAGMA_ALIGN_2048 _Pragma("data_alignment=2048")
#define PRAGMA_ALIGN_256 _Pragma("data_alignment=256")
#define PRAGMA_ALIGN_128 _Pragma("data_alignment=128")
#define PRAGMA_ALIGN_64 _Pragma("data_alignment=64")
#define PRAGMA_ALIGN_48 _Pragma("data_alignment=48")
#define PRAGMA_ALIGN_32 _Pragma("data_alignment=32")
#define PRAGMA_ALIGN_4 _Pragma("data_alignment=4")
#define ATTR_ALIGNED(Bytes)
//#define ATTR_DEPRECATED __attribute__ ((deprecated))
#define ATTR_ERROR(Message)// __attribute__ (( error(Message) ))
#define ATTR_WARNING(Message) // __attribute__ (( warning(Message) ))
#define ATTR_IAR_PACKED __packed
#define ATTR_PACKED
#endif
/** Places the function in one of the initialization sections, which execute before the main function
* of the application. Refer to the avr-libc manual for more information on the initialization sections.
*
* @param SectionIndex Initialization section number where the function should be placed.
*/
#define ATTR_INIT_SECTION(SectionIndex) __attribute__ ((naked, section (".init" #SectionIndex )))
/** Marks a variable or struct element for packing into the smallest space available, omitting any
* alignment bytes usually added between fields to optimize field accesses.
*/
#endif
/** @} */

264
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Common/Common.h vendored Normal file
View file

@ -0,0 +1,264 @@
/*
* @brief LPCUSB library's common macros, definitions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @defgroup Group_Common Common Utility Headers - LPCUSBlib/Common/Common.h
* @ingroup LPCUSBlib
* @brief Common library convenience headers, macros and functions.
*
* Common utility headers containing macros, functions, enums and types which are common to all
* aspects of the library.
*
* @{
*/
/** @defgroup Group_GlobalInt Global Interrupt Macros
* @brief Convenience macros for the management of interrupts globally within the device.
*
* Macros and functions to create and control global interrupts within the device.
*/
#ifndef __LPCUSBlib_COMMON_H__
#define __LPCUSBlib_COMMON_H__
/* Macros: */
#define __INCLUDE_FROM_COMMON_H
/* Includes: */
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <stddef.h>
#if defined(USE_LUFA_CONFIG_HEADER)
#include "LUFAConfig.h"
#endif
#if 1 // TODO add control macros later
#include "../LPCUSBlibConfig.h"
#endif
#include "CompilerSpecific.h"
#include "Attributes.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Architecture specific utility includes: */
#if defined(__DOXYGEN__)
/** Type define for an unsigned integer the same width as the selected architecture's machine register.
* This is distinct from the non-specific standard int data type, whose width is machine dependant but
* which may not reflect the actual machine register width on some targets (e.g. LPC).
*/
typedef MACHINE_REG_t uint_reg_t;
#else
typedef uint32_t uint_reg_t;
#define ARCH_LITTLE_ENDIAN
#define PROGMEM const
#define pgm_read_byte(x) (*x)
#define memcmp_P(...) memcmp(__VA_ARGS__)
#define memcpy_P(...) memcpy(__VA_ARGS__)
#include "Endianness.h"
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** Macro for encasing other multi-statement macros. This should be used along with an opening brace
* before the start of any multi-statement macro, so that the macros contents as a whole are treated
* as a discrete block and not as a list of separate statements which may cause problems when used as
* a block (such as inline \c if statements).
*/
#define MACROS do
/** Macro for encasing other multi-statement macros. This should be used along with a preceding closing
* brace at the end of any multi-statement macro, so that the macros contents as a whole are treated
* as a discrete block and not as a list of separate statements which may cause problems when used as
* a block (such as inline \c if statements).
*/
#define MACROE while (0)
/** Convenience macro to determine the larger of two values.
*
* @note This macro should only be used with operands that do not have side effects from being evaluated
* multiple times.
*
* @param x First value to compare
* @param y First value to compare
*
* @return The larger of the two input parameters
*/
#if !defined(MAX) || defined(__DOXYGEN__)
#define MAX(x, y) (((x) > (y)) ? (x) : (y))
#endif
/** Convenience macro to determine the smaller of two values.
*
* @note This macro should only be used with operands that do not have side effects from being evaluated
* multiple times.
*
* @param x First value to compare
* @param y First value to compare
*
* @return The smaller of the two input parameters
*/
#if !defined(MIN) || defined(__DOXYGEN__)
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
#endif
#if !defined(STRINGIFY) || defined(__DOXYGEN__)
/** Converts the given input into a string, via the C Preprocessor. This macro puts literal quotation
* marks around the input, converting the source into a string literal.
*
* @param x Input to convert into a string literal.
*
* @return String version of the input.
*/
#define STRINGIFY(x) #x
/** Converts the given input into a string after macro expansion, via the C Preprocessor. This macro puts
* literal quotation marks around the expanded input, converting the source into a string literal.
*
* @param x Input to expand and convert into a string literal.
*
* @return String version of the expanded input.
*/
#define STRINGIFY_EXPANDED(x) STRINGIFY(x)
#endif
/* Inline Functions: */
/** Function to reverse the individual bits in a byte - i.e. bit 7 is moved to bit 0, bit 6 to bit 1,
* etc.
*
* @param Byte Byte of data whose bits are to be reversed.
*/
static inline uint8_t BitReverse(uint8_t Byte) ATTR_WARN_UNUSED_RESULT ATTR_CONST;
static inline uint8_t BitReverse(uint8_t Byte)
{
Byte = (((Byte & 0xF0) >> 4) | ((Byte & 0x0F) << 4));
Byte = (((Byte & 0xCC) >> 2) | ((Byte & 0x33) << 2));
Byte = (((Byte & 0xAA) >> 1) | ((Byte & 0x55) << 1));
return Byte;
}
/** Function to perform a blocking delay for a specified number of milliseconds. The actual delay will be
* at a minimum the specified number of milliseconds, however due to loop overhead and internal calculations
* may be slightly higher.
*
* @param Milliseconds Number of milliseconds to delay
*/
PRAGMA_ALWAYS_INLINE
static inline void Delay_MS(uint16_t Milliseconds) ATTR_ALWAYS_INLINE;
static inline void Delay_MS(uint16_t Milliseconds)
{
while (Milliseconds--)
{
volatile uint32_t i;
for (i = 0; i < (4 * 1000); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
;
}
}
}
/** Retrieves a mask which contains the current state of the global interrupts for the device. This
* value can be stored before altering the global interrupt enable state, before restoring the
* flag(s) back to their previous values after a critical section using @ref SetGlobalInterruptMask().
*
* @ingroup Group_GlobalInt
*
* @return Mask containing the current Global Interrupt Enable Mask bit(s).
*/
PRAGMA_ALWAYS_INLINE
static inline uint_reg_t GetGlobalInterruptMask(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;
static inline uint_reg_t GetGlobalInterruptMask(void)
{
GCC_MEMORY_BARRIER();
// TODO #warning GetGlobalInterruptMask() is not implemented under ARCH_LPC.
return 0;
//GCC_MEMORY_BARRIER();
}
/** Sets the global interrupt enable state of the microcontroller to the mask passed into the function.
* This can be combined with @ref GetGlobalInterruptMask() to save and restore the Global Interrupt Enable
* Mask bit(s) of the device after a critical section has completed.
*
* @ingroup Group_GlobalInt
*
* @param GlobalIntState Global Interrupt Enable Mask value to use
*/
PRAGMA_ALWAYS_INLINE
static inline void SetGlobalInterruptMask(const uint_reg_t GlobalIntState) ATTR_ALWAYS_INLINE;
static inline void SetGlobalInterruptMask(const uint_reg_t GlobalIntState)
{
GCC_MEMORY_BARRIER();
// TODO #warning SetGlobalInterruptMask() is not implemented under ARCH_LPC.
GCC_MEMORY_BARRIER();
}
/** Enables global interrupt handling for the device, allowing interrupts to be handled.
*
* @ingroup Group_GlobalInt
*/
PRAGMA_ALWAYS_INLINE
static inline void GlobalInterruptEnable(void) ATTR_ALWAYS_INLINE;
static inline void GlobalInterruptEnable(void)
{
GCC_MEMORY_BARRIER();
// TODO #warning GlobalInterruptEnable() is not implemented under ARCH_LPC.
GCC_MEMORY_BARRIER();
}
/** Disabled global interrupt handling for the device, preventing interrupts from being handled.
*
* @ingroup Group_GlobalInt
*/
PRAGMA_ALWAYS_INLINE
static inline void GlobalInterruptDisable(void) ATTR_ALWAYS_INLINE;
static inline void GlobalInterruptDisable(void)
{
GCC_MEMORY_BARRIER();
// TODO #warning GlobalInterruptDisable() is not implemented under ARCH_LPC.
GCC_MEMORY_BARRIER();
}
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

93
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Common/CompilerSpecific.h vendored Normal file
View file

@ -0,0 +1,93 @@
/*
* @brief Special compiler's definitions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_Common
* @defgroup Group_CompilerSpecific Compiler Specific Definitions
* @brief Compiler specific definitions for code optimization and correctness.
*
* Compiler specific definitions to expose certain compiler features which may increase the level of code optimization
* for a specific compiler, or correct certain issues that may be present such as memory barriers for use in conjunction
* with atomic variable access.
*
* Where possible, on alternative compilers, these macros will either have no effect, or default to returning a sane value
* so that they can be used in existing code without the need for extra compiler checks in the user application code.
*
* @{
*/
#ifndef __LPCUSBlib_COMPILERSPEC_H__
#define __LPCUSBlib_COMPILERSPEC_H__
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_COMMON_H)
#error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
#if defined(__GNUC__) || defined(__DOXYGEN__)
/** Forces GCC to use pointer indirection (via the device's pointer register pairs) when accessing the given
* struct pointer. In some cases GCC will emit non-optimal assembly code when accessing a structure through
* a pointer, resulting in a larger binary. When this macro is used on a (non \c const) structure pointer before
* use, it will force GCC to use pointer indirection on the elements rather than direct store and load
* instructions.
*
* @param StructPtr Pointer to a structure which is to be forced into indirect access mode.
*/
#define GCC_FORCE_POINTER_ACCESS(StructPtr) __asm__ __volatile__("" : "=b" (StructPtr) : "0" (StructPtr))
/** Forces GCC to create a memory barrier, ensuring that memory accesses are not reordered past the barrier point.
* This can be used before ordering-critical operations, to ensure that the compiler does not re-order the resulting
* assembly output in an unexpected manner on sections of code that are ordering-specific.
*/
#define GCC_MEMORY_BARRIER() // FIXME __asm__ __volatile__("" ::: "memory");
/** Evaluates to boolean true if the specified value can be determined at compile time to be a constant value
* when compiling under GCC.
*
* @param x Value to check compile time constantness of.
*
* @return Boolean true if the given value is known to be a compile time constant, false otherwise.
*/
#define GCC_IS_COMPILE_CONST(x) __builtin_constant_p(x)
#else
#define GCC_FORCE_POINTER_ACCESS(StructPtr)
#define GCC_MEMORY_BARRIER()
#define GCC_IS_COMPILE_CONST(x) 0
#endif
#endif
/** @} */

480
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Common/Endianness.h vendored Normal file
View file

@ -0,0 +1,480 @@
/*
* @brief Endianness declaration
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_Endianness
* @defgroup Group_ByteSwapping Byte Reordering
* @brief Macros and functions for forced byte reordering.
*/
/** @ingroup Group_Endianness
* @defgroup Group_EndianConversion Endianness Conversion
* @brief Macros and functions for automatic endianness conversion.
*/
/** @ingroup Group_Common
* @defgroup Group_Endianness Endianness and Byte Ordering
* @brief Convenience macros and functions relating to byte (re-)ordering
*
* Common library convenience macros and functions relating to byte (re-)ordering.
*
* @{
*/
#ifndef __LPCUSBlib_ENDIANNESS_H__
#define __LPCUSBlib_ENDIANNESS_H__
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_COMMON_H)
#error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.
#endif
#if !(defined(ARCH_BIG_ENDIAN) || defined(ARCH_LITTLE_ENDIAN))
#error ARCH_BIG_ENDIAN or ARCH_LITTLE_ENDIAN not set for the specified architecture.
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** Swaps the byte ordering of a 16-bit value at compile-time. Do not use this macro for swapping byte orderings
* of dynamic values computed at runtime, use @ref SwapEndian_16() instead. The result of this macro can be used
* inside struct or other variable initializers outside of a function, something that is not possible with the
* inline function variant.
*
* @ingroup Group_ByteSwapping
*
* @param x 16-bit value whose byte ordering is to be swapped.
*
* @return Input value with the byte ordering reversed.
*/
#define SWAPENDIAN_16(x) (uint16_t)((((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8))
/** Swaps the byte ordering of a 32-bit value at compile-time. Do not use this macro for swapping byte orderings
* of dynamic values computed at runtime- use @ref SwapEndian_32() instead. The result of this macro can be used
* inside struct or other variable initializers outside of a function, something that is not possible with the
* inline function variant.
*
* @ingroup Group_ByteSwapping
*
* @param x 32-bit value whose byte ordering is to be swapped.
*
* @return Input value with the byte ordering reversed.
*/
#define SWAPENDIAN_32(x) (uint32_t)((((x) & 0xFF000000UL) >> 24UL) | (((x) & 0x00FF0000UL) >> 8UL) | \
(((x) & 0x0000FF00UL) << 8UL) | (((x) & 0x000000FFUL) << 24UL))
#if defined(ARCH_BIG_ENDIAN) && !defined(le16_to_cpu)
#define le16_to_cpu(x) SwapEndian_16(x)
#define le32_to_cpu(x) SwapEndian_32(x)
#define be16_to_cpu(x) (x)
#define be32_to_cpu(x) (x)
#define cpu_to_le16(x) SwapEndian_16(x)
#define cpu_to_le32(x) SwapEndian_32(x)
#define cpu_to_be16(x) (x)
#define cpu_to_be32(x) (x)
#define LE16_TO_CPU(x) SWAPENDIAN_16(x)
#define LE32_TO_CPU(x) SWAPENDIAN_32(x)
#define BE16_TO_CPU(x) (x)
#define BE32_TO_CPU(x) (x)
#define CPU_TO_LE16(x) SWAPENDIAN_16(x)
#define CPU_TO_LE32(x) SWAPENDIAN_32(x)
#define CPU_TO_BE16(x) (x)
#define CPU_TO_BE32(x) (x)
#elif !defined(le16_to_cpu)
/** \name Run-time endianness conversion */
//@{
/** Performs a conversion between a Little Endian encoded 16-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref LE16_TO_CPU instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define le16_to_cpu(x) (x)
/** Performs a conversion between a Little Endian encoded 32-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref LE32_TO_CPU instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define le32_to_cpu(x) (x)
/** Performs a conversion between a Big Endian encoded 16-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref BE16_TO_CPU instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define be16_to_cpu(x) SwapEndian_16(x)
/** Performs a conversion between a Big Endian encoded 32-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref BE32_TO_CPU instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define be32_to_cpu(x) SwapEndian_32(x)
/** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it
* is in Little Endian format regardless of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref CPU_TO_LE16 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define cpu_to_le16(x) (x)
/** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it
* is in Little Endian format regardless of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref CPU_TO_LE32 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define cpu_to_le32(x) (x)
/** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it
* is in Big Endian format regardless of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref CPU_TO_BE16 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define cpu_to_be16(x) SwapEndian_16(x)
/** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it
* is in Big Endian format regardless of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for run-time conversion of data - for compile-time endianness
* conversion, use @ref CPU_TO_BE32 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define cpu_to_be32(x) SwapEndian_32(x)
//@}
/** \name Compile-time endianness conversion */
//@{
/** Performs a conversion between a Little Endian encoded 16-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run time endianness
* conversion, use @ref le16_to_cpu instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define LE16_TO_CPU(x) (x)
/** Performs a conversion between a Little Endian encoded 32-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run time endianness
* conversion, use @ref le32_to_cpu instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define LE32_TO_CPU(x) (x)
/** Performs a conversion between a Big Endian encoded 16-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref be16_to_cpu instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define BE16_TO_CPU(x) SWAPENDIAN_16(x)
/** Performs a conversion between a Big Endian encoded 32-bit piece of data and the
* Endianness of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref be32_to_cpu instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define BE32_TO_CPU(x) SWAPENDIAN_32(x)
/** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it
* is in Little Endian format regardless of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref cpu_to_le16 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define CPU_TO_LE16(x) (x)
/** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it
* is in Little Endian format regardless of the currently selected CPU architecture.
*
* On little endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref cpu_to_le32 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define CPU_TO_LE32(x) (x)
/** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it
* is in Big Endian format regardless of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref cpu_to_be16 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define CPU_TO_BE16(x) SWAPENDIAN_16(x)
/** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it
* is in Big Endian format regardless of the currently selected CPU architecture.
*
* On big endian architectures, this macro does nothing.
*
* @note This macro is designed for compile-time conversion of data - for run-time endianness
* conversion, use @ref cpu_to_be32 instead.
*
* @ingroup Group_EndianConversion
*
* @param x Data to perform the endianness conversion on.
*
* @return Endian corrected version of the input value.
*/
#define CPU_TO_BE32(x) SWAPENDIAN_32(x)
//! @}
#endif
/* Inline Functions: */
/** Function to reverse the byte ordering of the individual bytes in a 16 bit value.
*
* @ingroup Group_ByteSwapping
*
* @param Word Word of data whose bytes are to be swapped.
*/
static inline uint16_t SwapEndian_16(const uint16_t Word) ATTR_WARN_UNUSED_RESULT ATTR_CONST;
static inline uint16_t SwapEndian_16(const uint16_t Word)
{
if (GCC_IS_COMPILE_CONST(Word))
return SWAPENDIAN_16(Word);
uint8_t Temp;
union
{
uint16_t Word;
uint8_t Bytes[2];
} Data;
Data.Word = Word;
Temp = Data.Bytes[0];
Data.Bytes[0] = Data.Bytes[1];
Data.Bytes[1] = Temp;
return Data.Word;
}
/** Function to reverse the byte ordering of the individual bytes in a 32 bit value.
*
* @ingroup Group_ByteSwapping
*
* @param DWord Double word of data whose bytes are to be swapped.
*/
static inline uint32_t SwapEndian_32(const uint32_t DWord) ATTR_WARN_UNUSED_RESULT ATTR_CONST;
static inline uint32_t SwapEndian_32(const uint32_t DWord)
{
if (GCC_IS_COMPILE_CONST(DWord))
return SWAPENDIAN_32(DWord);
uint8_t Temp;
union
{
uint32_t DWord;
uint8_t Bytes[4];
} Data;
Data.DWord = DWord;
Temp = Data.Bytes[0];
Data.Bytes[0] = Data.Bytes[3];
Data.Bytes[3] = Temp;
Temp = Data.Bytes[1];
Data.Bytes[1] = Data.Bytes[2];
Data.Bytes[2] = Temp;
return Data.DWord;
}
/** Function to reverse the byte ordering of the individual bytes in a n byte value.
*
* @ingroup Group_ByteSwapping
*
* \param[in,out] Data Pointer to a number containing an even number of bytes to be reversed.
* @param Length Length of the data in bytes.
*/
static inline void SwapEndian_n(void* const Data,
uint8_t Length) ATTR_NON_NULL_PTR_ARG(1);
static inline void SwapEndian_n(void* const Data,
uint8_t Length)
{
uint8_t* CurrDataPos = (uint8_t*)Data;
while (Length > 1)
{
uint8_t Temp = *CurrDataPos;
*CurrDataPos = *(CurrDataPos + Length - 1);
*(CurrDataPos + Length - 1) = Temp;
CurrDataPos++;
Length -= 2;
}
}
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

73
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/AudioClass.h vendored Normal file
View file

@ -0,0 +1,73 @@
/*
* @brief Master include file for the library USB Audio 1.0 Class driver, for both host and device modes
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassDrivers
* @defgroup Group_USBClassAudio Audio 1.0 Class Driver
*
* @section Sec_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - LPCUSBlib/Drivers/USB/Class/Device/Audio.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>
* - LPCUSBlib/Drivers/USB/Class/Host/Audio.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>
*
* @section Sec_ModDescription Module Description
* Audio 1.0 Class Driver module. This module contains an internal implementation of the USB Audio 1.0 Class, for both
* Device and Host USB modes. User applications can use this class driver instead of implementing the Audio 1.0 class
* manually via the low-level nxpUSBlib APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Hosts or Devices using the USB Audio 1.0 Class.
*
* @{
*/
#ifndef _AUDIO_CLASS_H_
#define _AUDIO_CLASS_H_
/* Macros: */
#define __INCLUDE_FROM_USB_DRIVER
#define __INCLUDE_FROM_AUDIO_DRIVER
/* Includes: */
#include "../Core/USBMode.h"
#if defined(USB_CAN_BE_DEVICE)
#include "Device/AudioClassDevice.h"
#endif
#if defined(USB_CAN_BE_HOST)
#include "Host/AudioClassHost.h"
#endif
#endif
/** @} */

73
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/CDCClass.h vendored Normal file
View file

@ -0,0 +1,73 @@
/*
* @brief Master include file for the library USB CDC Class driver, for both host and device modes
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassDrivers
* @defgroup Group_USBClassCDC CDC-ACM (Virtual Serial) Class Driver
*
* @section Sec_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - LPCUSBlib/Drivers/USB/Class/Device/CDC.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>
* - LPCUSBlib/Drivers/USB/Class/Host/CDC.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>
*
* @section Sec_ModDescription Module Description
* CDC Class Driver module. This module contains an internal implementation of the USB CDC-ACM class Virtual Serial
* Ports, for both Device and Host USB modes. User applications can use this class driver instead of implementing the
* CDC class manually via the low-level nxpUSBlib APIs.
*
* This module is designed to simplify the user code by exposing only the required interface needed to interface with
* Hosts or Devices using the USB CDC Class.
*
* @{
*/
#ifndef _CDC_CLASS_H_
#define _CDC_CLASS_H_
/* Macros: */
#define __INCLUDE_FROM_USB_DRIVER
#define __INCLUDE_FROM_CDC_DRIVER
/* Includes: */
#include "../Core/USBMode.h"
#if defined(USB_CAN_BE_DEVICE)
#include "Device/CDCClassDevice.h"
#endif
#if defined(USB_CAN_BE_HOST)
#include "Host/CDCClassHost.h"
#endif
#endif
/** @} */

766
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/AudioClassCommon.h vendored Normal file
View file

@ -0,0 +1,766 @@
/*
* @brief Common definitions and declarations for the library USB Audio 1.0 Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassAudio
* @defgroup Group_USBClassAudioCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* Audio 1.0 Class.
*
* @{
*/
#ifndef _AUDIO_CLASS_COMMON_H_
#define _AUDIO_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_AUDIO_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** @name Audio Channel Masks */
//@{
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_LEFT_FRONT (1 << 0)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_RIGHT_FRONT (1 << 1)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_CENTER_FRONT (1 << 2)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_LOW_FREQ_ENHANCE (1 << 3)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_LEFT_SURROUND (1 << 4)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_RIGHT_SURROUND (1 << 5)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_LEFT_OF_CENTER (1 << 6)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_RIGHT_OF_CENTER (1 << 7)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_SURROUND (1 << 8)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_SIDE_LEFT (1 << 9)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_SIDE_RIGHT (1 << 10)
/** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_CHANNEL_TOP (1 << 11)
//@}
/** @name Audio Feature Masks */
//@{
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_MUTE (1 << 0)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_VOLUME (1 << 1)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_BASS (1 << 2)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_MID (1 << 3)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_TREBLE (1 << 4)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_GRAPHIC_EQUALIZER (1 << 5)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_AUTOMATIC_GAIN (1 << 6)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_DELAY (1 << 7)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_BASS_BOOST (1 << 8)
/** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */
#define AUDIO_FEATURE_BASS_LOUDNESS (1 << 9)
//@}
/** @name Audio Terminal Types */
//@{
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_UNDEFINED 0x0100
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_STREAMING 0x0101
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_VENDOR 0x01FF
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_UNDEFINED 0x0200
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_MIC 0x0201
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_DESKTOP_MIC 0x0202
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_PERSONAL_MIC 0x0203
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_OMNIDIR_MIC 0x0204
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_MIC_ARRAY 0x0205
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_PROCESSING_MIC 0x0206
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_IN_OUT_UNDEFINED 0x0300
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_SPEAKER 0x0301
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_HEADPHONES 0x0302
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_HEAD_MOUNTED 0x0303
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_DESKTOP 0x0304
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_ROOM 0x0305
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_COMMUNICATION 0x0306
/** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */
#define AUDIO_TERMINAL_OUT_LOWFREQ 0x0307
//@}
/** Convenience macro to fill a 24-bit @ref USB_Audio_SampleFreq_t structure with the given sample rate as a 24-bit number.
*
* @param freq Required audio sampling frequency in HZ
*/
#define AUDIO_SAMPLE_FREQ(freq) {.Byte1 = ((uint32_t)freq & 0xFF), .Byte2 = (((uint32_t)freq >> 8) & 0xFF), .Byte3 = (((uint32_t)freq >> 16) & 0xFF)}
/** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint
* accepts only filled endpoint packets of audio samples.
*/
#define AUDIO_EP_FULL_PACKETS_ONLY (1 << 7)
/** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint
* will accept partially filled endpoint packets of audio samples.
*/
#define AUDIO_EP_ACCEPTS_SMALL_PACKETS (0 << 7)
/** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint
* allows for sampling frequency adjustments to be made via control requests directed at the endpoint.
*/
#define AUDIO_EP_SAMPLE_FREQ_CONTROL (1 << 0)
/** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint
* allows for pitch adjustments to be made via control requests directed at the endpoint.
*/
#define AUDIO_EP_PITCH_CONTROL (1 << 1)
/* Enums: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Audio
* device class.
*/
enum Audio_Descriptor_ClassSubclassProtocol_t
{
AUDIO_CSCP_AudioClass = 0x01, /**< Descriptor Class value indicating that the device or
* interface belongs to the USB Audio 1.0 class.
*/
AUDIO_CSCP_ControlSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or
* interface belongs to the Audio Control subclass.
*/
AUDIO_CSCP_ControlProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or
* interface belongs to the Audio Control protocol.
*/
AUDIO_CSCP_AudioStreamingSubclass = 0x02, /**< Descriptor Subclass value indicating that the device or
* interface belongs to the MIDI Streaming subclass.
*/
AUDIO_CSCP_MIDIStreamingSubclass = 0x03, /**< Descriptor Subclass value indicating that the device or
* interface belongs to the Audio streaming subclass.
*/
AUDIO_CSCP_StreamingProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or
* interface belongs to the Streaming Audio protocol.
*/
};
/** Audio class specific interface description subtypes, for the Audio Control interface. */
enum Audio_CSInterface_AC_SubTypes_t
{
AUDIO_DSUBTYPE_CSInterface_Header = 0x01, /**< Audio class specific control interface header. */
AUDIO_DSUBTYPE_CSInterface_InputTerminal = 0x02, /**< Audio class specific control interface Input Terminal. */
AUDIO_DSUBTYPE_CSInterface_OutputTerminal = 0x03, /**< Audio class specific control interface Output Terminal. */
AUDIO_DSUBTYPE_CSInterface_Mixer = 0x04, /**< Audio class specific control interface Mixer Unit. */
AUDIO_DSUBTYPE_CSInterface_Selector = 0x05, /**< Audio class specific control interface Selector Unit. */
AUDIO_DSUBTYPE_CSInterface_Feature = 0x06, /**< Audio class specific control interface Feature Unit. */
AUDIO_DSUBTYPE_CSInterface_Processing = 0x07, /**< Audio class specific control interface Processing Unit. */
AUDIO_DSUBTYPE_CSInterface_Extension = 0x08, /**< Audio class specific control interface Extension Unit. */
};
/** Audio class specific interface description subtypes, for the Audio Streaming interface. */
enum Audio_CSInterface_AS_SubTypes_t
{
AUDIO_DSUBTYPE_CSInterface_General = 0x01, /**< Audio class specific streaming interface general descriptor. */
AUDIO_DSUBTYPE_CSInterface_FormatType = 0x02, /**< Audio class specific streaming interface format type descriptor. */
AUDIO_DSUBTYPE_CSInterface_FormatSpecific = 0x03, /**< Audio class specific streaming interface format information descriptor. */
};
/** Audio class specific endpoint description subtypes, for the Audio Streaming interface. */
enum Audio_CSEndpoint_SubTypes_t
{
AUDIO_DSUBTYPE_CSEndpoint_General = 0x01, /**< Audio class specific endpoint general descriptor. */
};
/** Enum for the Audio class specific control requests that can be issued by the USB bus host. */
enum Audio_ClassRequests_t
{
AUDIO_REQ_SetCurrent = 0x01, /**< Audio class-specific request to set the current value of a parameter within the device. */
AUDIO_REQ_SetMinimum = 0x02, /**< Audio class-specific request to set the minimum value of a parameter within the device. */
AUDIO_REQ_SetMaximum = 0x03, /**< Audio class-specific request to set the maximum value of a parameter within the device. */
AUDIO_REQ_SetResolution = 0x04, /**< Audio class-specific request to set the resolution value of a parameter within the device. */
AUDIO_REQ_SetMemory = 0x05, /**< Audio class-specific request to set the memory value of a parameter within the device. */
AUDIO_REQ_GetCurrent = 0x81, /**< Audio class-specific request to get the current value of a parameter within the device. */
AUDIO_REQ_GetMinimum = 0x82, /**< Audio class-specific request to get the minimum value of a parameter within the device. */
AUDIO_REQ_GetMaximum = 0x83, /**< Audio class-specific request to get the maximum value of a parameter within the device. */
AUDIO_REQ_GetResolution = 0x84, /**< Audio class-specific request to get the resolution value of a parameter within the device. */
AUDIO_REQ_GetMemory = 0x85, /**< Audio class-specific request to get the memory value of a parameter within the device. */
AUDIO_REQ_GetStatus = 0xFF, /**< Audio class-specific request to get the device status. */
};
/** Enum for Audio class specific Endpoint control modifiers which can be set and retrieved by a USB host, if the corresponding
* endpoint control is indicated to be supported in the Endpoint's Audio-class specific endpoint descriptor.
*/
enum Audio_EndpointControls_t
{
AUDIO_EPCONTROL_SamplingFreq = 0x01, /**< Sampling frequency adjustment of the endpoint. */
AUDIO_EPCONTROL_Pitch = 0x02, /**< Pitch adjustment of the endpoint. */
};
/* Type Defines: */
/** @brief Audio class-specific Input Terminal Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific input terminal descriptor. This indicates to the host that the device
* contains an input audio source, either from a physical terminal on the device, or a logical terminal (for example,
* a USB endpoint). See the USB Audio specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_InputTerminal_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_InputTerminal.
*/
uint8_t TerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */
uint16_t TerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */
uint8_t AssociatedOutputTerminal; /**< ID of associated output terminal, for physically grouped terminals
* such as the speaker and microphone of a phone handset.
*/
uint8_t TotalChannels; /**< Total number of separate audio channels within this interface (right, left, etc.) */
uint16_t ChannelConfig; /**< \c CHANNEL_* masks indicating what channel layout is supported by this terminal. */
uint8_t ChannelStrIndex; /**< Index of a string descriptor describing this channel within the device. */
uint8_t TerminalStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_Descriptor_InputTerminal_t;
/** @brief Audio class-specific Input Terminal Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific input terminal descriptor. This indicates to the host that the device
* contains an input audio source, either from a physical terminal on the device, or a logical terminal (for example,
* a USB endpoint). See the USB Audio specification for more details.
*
* @see @ref USB_Audio_Descriptor_InputTerminal_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_InputTerminal.
*/
uint8_t bTerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */
uint16_t wTerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */
uint8_t bAssocTerminal; /**< ID of associated output terminal, for physically grouped terminals
* such as the speaker and microphone of a phone handset.
*/
uint8_t bNrChannels; /**< Total number of separate audio channels within this interface (right, left, etc.) */
uint16_t wChannelConfig; /**< \c CHANNEL_* masks indicating what channel layout is supported by this terminal. */
uint8_t iChannelNames; /**< Index of a string descriptor describing this channel within the device. */
uint8_t iTerminal; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_StdDescriptor_InputTerminal_t;
/** @brief Audio class-specific Output Terminal Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific output terminal descriptor. This indicates to the host that the device
* contains an output audio sink, either to a physical terminal on the device, or a logical terminal (for example,
* a USB endpoint). See the USB Audio specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_OutputTerminal_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_OutputTerminal.
*/
uint8_t TerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */
uint16_t TerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */
uint8_t AssociatedInputTerminal; /**< ID of associated input terminal, for physically grouped terminals
* such as the speaker and microphone of a phone handset.
*/
uint8_t SourceID; /**< ID value of the unit this terminal's audio is sourced from. */
uint8_t TerminalStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_Descriptor_OutputTerminal_t;
/** @brief Audio class-specific Output Terminal Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific output terminal descriptor. This indicates to the host that the device
* contains an output audio sink, either to a physical terminal on the device, or a logical terminal (for example,
* a USB endpoint). See the USB Audio specification for more details.
*
* @see @ref USB_Audio_Descriptor_OutputTerminal_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_OutputTerminal.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AC_SubTypes_t enum.
*/
uint8_t bTerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */
uint16_t wTerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */
uint8_t bAssocTerminal; /**< ID of associated input terminal, for physically grouped terminals
* such as the speaker and microphone of a phone handset.
*/
uint8_t bSourceID; /**< ID value of the unit this terminal's audio is sourced from. */
uint8_t iTerminal; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_StdDescriptor_OutputTerminal_t;
/** @brief Audio class-specific Interface Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific interface descriptor. This follows a regular interface descriptor to
* supply extra information about the audio device's layout to the host. See the USB Audio specification for more
* details.
*
* @see @ref USB_Audio_StdDescriptor_Interface_AC_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.
*/
uint16_t ACSpecification; /**< Binary coded decimal value, indicating the supported Audio Class specification version. */
uint16_t TotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */
uint8_t InCollection; /**< Total number of Audio Streaming interfaces linked to this Audio Control interface (must be 1). */
uint8_t InterfaceNumber; /**< Interface number of the associated Audio Streaming interface. */
} ATTR_PACKED USB_Audio_Descriptor_Interface_AC_t;
/** @brief Audio class-specific Interface Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific interface descriptor. This follows a regular interface descriptor to
* supply extra information about the audio device's layout to the host. See the USB Audio specification for more
* details.
*
* @see @ref USB_Audio_Descriptor_Interface_AC_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype;/**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.
*/
uint16_t bcdADC; /**< Binary coded decimal value, indicating the supported Audio Class specification version. */
uint16_t wTotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */
uint8_t bInCollection; /**< Total number of Audio Streaming interfaces linked to this Audio Control interface (must be 1). */
uint8_t bInterfaceNumbers; /**< Interface number of the associated Audio Streaming interface. */
} ATTR_PACKED USB_Audio_StdDescriptor_Interface_AC_t;
/** @brief Audio class-specific Feature Unit Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific Feature Unit descriptor. This indicates to the host what features
* are present in the device's audio stream for basic control, such as per-channel volume. See the USB Audio
* specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_FeatureUnit_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_Feature.
*/
uint8_t UnitID; /**< ID value of this feature unit - must be a unique value within the device. */
uint8_t SourceID; /**< Source ID value of the audio source input into this feature unit. */
uint8_t ControlSize; /**< Size of each element in the \c ChannelControls array. */
uint8_t ChannelControls[3]; /**< Feature masks for the control channel, and each separate audio channel. */
uint8_t FeatureUnitStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_Descriptor_FeatureUnit_t;
/** @brief Audio class-specific Feature Unit Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific Feature Unit descriptor. This indicates to the host what features
* are present in the device's audio stream for basic control, such as per-channel volume. See the USB Audio
* specification for more details.
*
* @see @ref USB_Audio_Descriptor_FeatureUnit_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_Feature.
*/
uint8_t bUnitID; /**< ID value of this feature unit - must be a unique value within the device. */
uint8_t bSourceID; /**< Source ID value of the audio source input into this feature unit. */
uint8_t bControlSize; /**< Size of each element in the \c ChannelControls array. */
uint8_t bmaControls[3]; /**< Feature masks for the control channel, and each separate audio channel. */
uint8_t iFeature; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_Audio_StdDescriptor_FeatureUnit_t;
/** @brief Audio class-specific Streaming Audio Interface Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific streaming interface descriptor. This indicates to the host
* how audio streams within the device are formatted. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_Interface_AS_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.
*/
uint8_t TerminalLink; /**< ID value of the output terminal this descriptor is describing. */
uint8_t FrameDelay; /**< Delay in frames resulting from the complete sample processing from input to output. */
uint16_t AudioFormat; /**< Format of the audio stream, see Audio Device Formats specification. */
} ATTR_PACKED USB_Audio_Descriptor_Interface_AS_t;
/** @brief Audio class-specific Streaming Audio Interface Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific streaming interface descriptor. This indicates to the host
* how audio streams within the device are formatted. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_Descriptor_Interface_AS_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.
*/
uint8_t bTerminalLink; /**< ID value of the output terminal this descriptor is describing. */
uint8_t bDelay; /**< Delay in frames resulting from the complete sample processing from input to output. */
uint16_t wFormatTag; /**< Format of the audio stream, see Audio Device Formats specification. */
} ATTR_PACKED USB_Audio_StdDescriptor_Interface_AS_t;
/** @brief Audio class-specific Format Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific audio format descriptor. This is used to give the host full details
* about the number of channels, the sample resolution, acceptable sample frequencies and encoding method used
* in the device's audio streams. See the USB Audio specification for more details.
*
* @note This descriptor <b>must</b> be followed by one or more @ref USB_Audio_SampleFreq_t elements containing
* the continuous or discrete sample frequencies.
*
* @see @ref USB_Audio_StdDescriptor_Format_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_FormatType.
*/
uint8_t FormatType; /**< Format of the audio stream, see Audio Device Formats specification. */
uint8_t Channels; /**< Total number of discrete channels in the stream. */
uint8_t SubFrameSize; /**< Size in bytes of each channel's sample data in the stream. */
uint8_t BitResolution; /**< Bits of resolution of each channel's samples in the stream. */
uint8_t TotalDiscreteSampleRates; /**< Total number of discrete sample frequencies supported by the device. When
* zero, this must be followed by the lower and upper continuous sampling
* frequencies supported by the device; otherwise, this must be followed
* by the given number of discrete sampling frequencies supported.
*/
} ATTR_PACKED USB_Audio_Descriptor_Format_t;
/** @brief 24-Bit Audio Frequency Structure.
*
* Type define for a 24bit audio sample frequency structure. As GCC does not contain a built in 24-bit datatype,
* this this structure is used to build up the value instead. Fill this structure with the @ref AUDIO_SAMPLE_FREQ() macro.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t Byte1; /**< Lowest 8 bits of the 24-bit value. */
uint8_t Byte2; /**< Middle 8 bits of the 24-bit value. */
uint8_t Byte3; /**< Upper 8 bits of the 24-bit value. */
} ATTR_PACKED USB_Audio_SampleFreq_t;
/** @brief Audio class-specific Format Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific audio format descriptor. This is used to give the host full details
* about the number of channels, the sample resolution, acceptable sample frequencies and encoding method used
* in the device's audio streams. See the USB Audio specification for more details.
*
* @note This descriptor <b>must</b> be followed by one or more 24-bit integer elements containing the continuous
* or discrete sample frequencies.
*
* @see @ref USB_Audio_Descriptor_Format_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Sub type value used to distinguish between audio class-specific descriptors,
* must be @ref AUDIO_DSUBTYPE_CSInterface_FormatType.
*/
uint8_t bDescriptorSubtype;/**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.
*/
uint8_t bFormatType; /**< Format of the audio stream, see Audio Device Formats specification. */
uint8_t bNrChannels; /**< Total number of discrete channels in the stream. */
uint8_t bSubFrameSize; /**< Size in bytes of each channel's sample data in the stream. */
uint8_t bBitResolution; /**< Bits of resolution of each channel's samples in the stream. */
uint8_t bSampleFrequencyType; /**< Total number of sample frequencies supported by the device. When
* zero, this must be followed by the lower and upper continuous sampling
* frequencies supported by the device; otherwise, this must be followed
* by the given number of discrete sampling frequencies supported.
*/
} ATTR_PACKED USB_Audio_StdDescriptor_Format_t;
/** @brief Audio class-specific Streaming Endpoint Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific endpoint descriptor. This contains a regular endpoint
* descriptor with a few Audio-class-specific extensions. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_StreamEndpoint_Std_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Endpoint_t Endpoint; /**< Standard endpoint descriptor describing the audio endpoint. */
uint8_t Refresh; /**< Always set to zero for Audio class devices. */
uint8_t SyncEndpointNumber; /**< Endpoint address to send synchronization information to, if needed (zero otherwise). */
} ATTR_PACKED USB_Audio_Descriptor_StreamEndpoint_Std_t;
/** @brief Audio class-specific Streaming Endpoint Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific endpoint descriptor. This contains a regular endpoint
* descriptor with a few Audio-class-specific extensions. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_Descriptor_StreamEndpoint_Std_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a
* value given by the specific class.
*/
uint8_t bEndpointAddress; /**< Logical address of the endpoint within the device for the current
* configuration, including direction mask.
*/
uint8_t bmAttributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (\c EP_TYPE_*)
* and attributes (\c ENDPOINT_ATTR_*) masks.
*/
uint16_t wMaxPacketSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet size
* that the endpoint can receive at a time.
*/
uint8_t bInterval; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT or
* ISOCHRONOUS type.
*/
uint8_t bRefresh; /**< Always set to zero for Audio class devices. */
uint8_t bSynchAddress; /**< Endpoint address to send synchronization information to, if needed (zero otherwise). */
} ATTR_PACKED USB_Audio_StdDescriptor_StreamEndpoint_Std_t;
/** @brief Audio class-specific Extended Endpoint Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific extended endpoint descriptor. This contains extra information
* on the usage of endpoints used to stream audio in and out of the USB Audio device, and follows an Audio
* class-specific extended endpoint descriptor. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_StdDescriptor_StreamEndpoint_Spc_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSEndpoint_SubTypes_t enum.
*/
uint8_t Attributes; /**< Audio class-specific endpoint attributes, such as @ref AUDIO_EP_FULL_PACKETS_ONLY. */
uint8_t LockDelayUnits; /**< Units used for the LockDelay field, see Audio class specification. */
uint16_t LockDelay; /**< Time required to internally lock endpoint's internal clock recovery circuitry. */
} ATTR_PACKED USB_Audio_Descriptor_StreamEndpoint_Spc_t;
/** @brief Audio class-specific Extended Endpoint Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific extended endpoint descriptor. This contains extra information
* on the usage of endpoints used to stream audio in and out of the USB Audio device, and follows an Audio
* class-specific extended endpoint descriptor. See the USB Audio specification for more details.
*
* @see @ref USB_Audio_Descriptor_StreamEndpoint_Spc_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,
* a value from the @ref Audio_CSEndpoint_SubTypes_t enum.
*/
uint8_t bmAttributes; /**< Audio class-specific endpoint attributes, such as @ref AUDIO_EP_FULL_PACKETS_ONLY. */
uint8_t bLockDelayUnits; /**< Units used for the LockDelay field, see Audio class specification. */
uint16_t wLockDelay; /**< Time required to internally lock endpoint's internal clock recovery circuitry. */
} ATTR_PACKED USB_Audio_StdDescriptor_StreamEndpoint_Spc_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

379
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/CDCClassCommon.h vendored Normal file
View file

@ -0,0 +1,379 @@
/*
* @brief Common definitions and declarations for the library USB CDC Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassCDC
* @defgroup Group_USBClassCDCCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* CDC Class.
*
* @{
*/
#ifndef _CDC_CLASS_COMMON_H_
#define _CDC_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_CDC_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** @name Virtual Control Line Masks */
//@{
/** Mask for the DTR handshake line for use with the @ref CDC_REQ_SetControlLineState class-specific request
* from the host, to indicate that the DTR line state should be high.
*/
#define CDC_CONTROL_LINE_OUT_DTR (1 << 0)
/** Mask for the RTS handshake line for use with the @ref CDC_REQ_SetControlLineState class-specific request
* from the host, to indicate that the RTS line state should be high.
*/
#define CDC_CONTROL_LINE_OUT_RTS (1 << 1)
/** Mask for the DCD handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification
* from the device to the host, to indicate that the DCD line state is currently high.
*/
#define CDC_CONTROL_LINE_IN_DCD (1 << 0)
/** Mask for the DSR handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification
* from the device to the host, to indicate that the DSR line state is currently high.
*/
#define CDC_CONTROL_LINE_IN_DSR (1 << 1)
/** Mask for the BREAK handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification
* from the device to the host, to indicate that the BREAK line state is currently high.
*/
#define CDC_CONTROL_LINE_IN_BREAK (1 << 2)
/** Mask for the RING handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification
* from the device to the host, to indicate that the RING line state is currently high.
*/
#define CDC_CONTROL_LINE_IN_RING (1 << 3)
/** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,
* to indicate that a framing error has occurred on the virtual serial port.
*/
#define CDC_CONTROL_LINE_IN_FRAMEERROR (1 << 4)
/** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,
* to indicate that a parity error has occurred on the virtual serial port.
*/
#define CDC_CONTROL_LINE_IN_PARITYERROR (1 << 5)
/** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,
* to indicate that a data overrun error has occurred on the virtual serial port.
*/
#define CDC_CONTROL_LINE_IN_OVERRUNERROR (1 << 6)
//@}
/** Macro to define a CDC class-specific functional descriptor. CDC functional descriptors have a
* uniform structure but variable sized data payloads, thus cannot be represented accurately by
* a single typedef struct. A macro is used instead so that functional descriptors can be created
* easily by specifying the size of the payload. This allows \c sizeof() to work correctly.
*
* @param DataSize Size in bytes of the CDC functional descriptor's data payload.
*/
#define CDC_FUNCTIONAL_DESCRIPTOR(DataSize) \
struct \
{ \
USB_Descriptor_Header_t Header; \
uint8_t SubType; \
uint8_t Data[DataSize]; \
}
/* Enums: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the CDC
* device class.
*/
enum CDC_Descriptor_ClassSubclassProtocol_t
{
CDC_CSCP_CDCClass = 0x02, /**< Descriptor Class value indicating that the device or interface
* belongs to the CDC class.
*/
CDC_CSCP_NoSpecificSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface
* belongs to no specific subclass of the CDC class.
*/
CDC_CSCP_ACMSubclass = 0x02, /**< Descriptor Subclass value indicating that the device or interface
* belongs to the Abstract Control Model CDC subclass.
*/
CDC_CSCP_ATCommandProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the AT Command protocol of the CDC class.
*/
CDC_CSCP_NoSpecificProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface
* belongs to no specific protocol of the CDC class.
*/
CDC_CSCP_VendorSpecificProtocol = 0xFF, /**< Descriptor Protocol value indicating that the device or interface
* belongs to a vendor-specific protocol of the CDC class.
*/
CDC_CSCP_CDCDataClass = 0x0A, /**< Descriptor Class value indicating that the device or interface
* belongs to the CDC Data class.
*/
CDC_CSCP_NoDataSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface
* belongs to no specific subclass of the CDC data class.
*/
CDC_CSCP_NoDataProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface
* belongs to no specific protocol of the CDC data class.
*/
};
/** Enum for the CDC class specific control requests that can be issued by the USB bus host. */
enum CDC_ClassRequests_t
{
CDC_REQ_SendEncapsulatedCommand = 0x00, /**< CDC class-specific request to send an encapsulated command to the device. */
CDC_REQ_GetEncapsulatedResponse = 0x01, /**< CDC class-specific request to retrieve an encapsulated command response from the device. */
CDC_REQ_SetLineEncoding = 0x20, /**< CDC class-specific request to set the current virtual serial port configuration settings. */
CDC_REQ_GetLineEncoding = 0x21, /**< CDC class-specific request to get the current virtual serial port configuration settings. */
CDC_REQ_SetControlLineState = 0x22, /**< CDC class-specific request to set the current virtual serial port handshake line states. */
CDC_REQ_SendBreak = 0x23, /**< CDC class-specific request to send a break to the receiver via the carrier channel. */
};
/** Enum for the CDC class specific notification requests that can be issued by a CDC device to a host. */
enum CDC_ClassNotifications_t
{
CDC_NOTIF_SerialState = 0x20, /**< Notification type constant for a change in the virtual serial port
* handshake line states, for use with a @ref USB_Request_Header_t
* notification structure when sent to the host via the CDC notification
* endpoint.
*/
};
/** Enum for the CDC class specific interface descriptor subtypes. */
enum CDC_DescriptorSubtypes_t
{
CDC_DSUBTYPE_CSInterface_Header = 0x00, /**< CDC class-specific Header functional descriptor. */
CDC_DSUBTYPE_CSInterface_CallManagement = 0x01, /**< CDC class-specific Call Management functional descriptor. */
CDC_DSUBTYPE_CSInterface_ACM = 0x02, /**< CDC class-specific Abstract Control Model functional descriptor. */
CDC_DSUBTYPE_CSInterface_DirectLine = 0x03, /**< CDC class-specific Direct Line functional descriptor. */
CDC_DSUBTYPE_CSInterface_TelephoneRinger = 0x04, /**< CDC class-specific Telephone Ringer functional descriptor. */
CDC_DSUBTYPE_CSInterface_TelephoneCall = 0x05, /**< CDC class-specific Telephone Call functional descriptor. */
CDC_DSUBTYPE_CSInterface_Union = 0x06, /**< CDC class-specific Union functional descriptor. */
CDC_DSUBTYPE_CSInterface_CountrySelection = 0x07, /**< CDC class-specific Country Selection functional descriptor. */
CDC_DSUBTYPE_CSInterface_TelephoneOpModes = 0x08, /**< CDC class-specific Telephone Operation Modes functional descriptor. */
CDC_DSUBTYPE_CSInterface_USBTerminal = 0x09, /**< CDC class-specific USB Terminal functional descriptor. */
CDC_DSUBTYPE_CSInterface_NetworkChannel = 0x0A, /**< CDC class-specific Network Channel functional descriptor. */
CDC_DSUBTYPE_CSInterface_ProtocolUnit = 0x0B, /**< CDC class-specific Protocol Unit functional descriptor. */
CDC_DSUBTYPE_CSInterface_ExtensionUnit = 0x0C, /**< CDC class-specific Extension Unit functional descriptor. */
CDC_DSUBTYPE_CSInterface_MultiChannel = 0x0D, /**< CDC class-specific Multi-Channel Management functional descriptor. */
CDC_DSUBTYPE_CSInterface_CAPI = 0x0E, /**< CDC class-specific Common ISDN API functional descriptor. */
CDC_DSUBTYPE_CSInterface_Ethernet = 0x0F, /**< CDC class-specific Ethernet functional descriptor. */
CDC_DSUBTYPE_CSInterface_ATM = 0x10, /**< CDC class-specific Asynchronous Transfer Mode functional descriptor. */
};
/** Enum for the possible line encoding formats of a virtual serial port. */
enum CDC_LineEncodingFormats_t
{
CDC_LINEENCODING_OneStopBit = 0, /**< Each frame contains one stop bit. */
CDC_LINEENCODING_OneAndAHalfStopBits = 1, /**< Each frame contains one and a half stop bits. */
CDC_LINEENCODING_TwoStopBits = 2, /**< Each frame contains two stop bits. */
};
/** Enum for the possible line encoding parity settings of a virtual serial port. */
enum CDC_LineEncodingParity_t
{
CDC_PARITY_None = 0, /**< No parity bit mode on each frame. */
CDC_PARITY_Odd = 1, /**< Odd parity bit mode on each frame. */
CDC_PARITY_Even = 2, /**< Even parity bit mode on each frame. */
CDC_PARITY_Mark = 3, /**< Mark parity bit mode on each frame. */
CDC_PARITY_Space = 4, /**< Space parity bit mode on each frame. */
};
/* Type Defines: */
/** @brief CDC class-specific Functional Header Descriptor (nxpUSBlib naming conventions).
*
* Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device
* contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration.
* See the CDC class specification for more details.
*
* @see @ref USB_CDC_StdDescriptor_FunctionalHeader_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_Header.
*/
uint16_t CDCSpecification; /**< Version number of the CDC specification implemented by the device,
* encoded in BCD format.
*/
} ATTR_PACKED USB_CDC_Descriptor_FunctionalHeader_t;
/** @brief CDC class-specific Functional Header Descriptor (USB-IF naming conventions).
*
* Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device
* contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration.
* See the CDC class specification for more details.
*
* @see @ref USB_CDC_Descriptor_FunctionalHeader_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_Header.
*/
uint16_t bcdCDC; /**< Version number of the CDC specification implemented by the device, encoded in BCD format. */
} ATTR_PACKED USB_CDC_StdDescriptor_FunctionalHeader_t;
/** @brief CDC class-specific Functional ACM Descriptor (nxpUSBlib naming conventions).
*
* Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface
* supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details.
*
* @see @ref USB_CDC_StdDescriptor_FunctionalACM_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_ACM.
*/
uint8_t Capabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices,
* this should be set to a fixed value of 0x06 - for other capabilities, refer
* to the CDC ACM specification.
*/
} ATTR_PACKED USB_CDC_Descriptor_FunctionalACM_t;
/** @brief CDC class-specific Functional ACM Descriptor (USB-IF naming conventions).
*
* Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface
* supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details.
*
* @see @ref USB_CDC_Descriptor_FunctionalACM_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_ACM.
*/
uint8_t bmCapabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices,
* this should be set to a fixed value of 0x06 - for other capabilities, refer
* to the CDC ACM specification.
*/
} ATTR_PACKED USB_CDC_StdDescriptor_FunctionalACM_t;
/** @brief CDC class-specific Functional Union Descriptor (nxpUSBlib naming conventions).
*
* Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific
* CDC control and data interfaces are related. See the CDC class specification for more details.
*
* @see @ref USB_CDC_StdDescriptor_FunctionalUnion_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_Union.
*/
uint8_t MasterInterfaceNumber; /**< Interface number of the CDC Control interface. */
uint8_t SlaveInterfaceNumber; /**< Interface number of the CDC Data interface. */
} ATTR_PACKED USB_CDC_Descriptor_FunctionalUnion_t;
/** @brief CDC class-specific Functional Union Descriptor (USB-IF naming conventions).
*
* Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific
* CDC control and data interfaces are related. See the CDC class specification for more details.
*
* @see @ref USB_CDC_Descriptor_FunctionalUnion_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,
* must be @ref CDC_DSUBTYPE_CSInterface_Union.
*/
uint8_t bMasterInterface; /**< Interface number of the CDC Control interface. */
uint8_t bSlaveInterface0; /**< Interface number of the CDC Data interface. */
} ATTR_PACKED USB_CDC_StdDescriptor_FunctionalUnion_t;
/** @brief CDC Virtual Serial Port Line Encoding Settings Structure.
*
* Type define for a CDC Line Encoding structure, used to hold the various encoding parameters for a virtual
* serial port.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t BaudRateBPS; /**< Baud rate of the virtual serial port, in bits per second. */
uint8_t CharFormat; /**< Character format of the virtual serial port, a value from the
* @ref CDC_LineEncodingFormats_t enum.
*/
uint8_t ParityType; /**< Parity setting of the virtual serial port, a value from the
* @ref CDC_LineEncodingParity_t enum.
*/
uint8_t DataBits; /**< Bits of data per character of the virtual serial port. */
} ATTR_PACKED CDC_LineEncoding_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

649
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/HIDClassCommon.h vendored Normal file
View file

@ -0,0 +1,649 @@
/*
* @brief Common definitions and declarations for the library USB HID Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassHID
* @defgroup Group_USBClassHIDCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* HID Class.
*
* @{
*/
#ifndef _HID_CLASS_COMMON_H_
#define _HID_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
#include "HIDParser.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_HID_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** @name Keyboard Standard Report Modifier Masks */
//@{
/** Constant for a keyboard report modifier byte, indicating that the keyboard's left control key is currently pressed. */
#define HID_KEYBOARD_MODIFER_LEFTCTRL (1 << 0)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's left shift key is currently pressed. */
#define HID_KEYBOARD_MODIFER_LEFTSHIFT (1 << 1)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's left alt key is currently pressed. */
#define HID_KEYBOARD_MODIFER_LEFTALT (1 << 2)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's left GUI key is currently pressed. */
#define HID_KEYBOARD_MODIFER_LEFTGUI (1 << 3)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's right control key is currently pressed. */
#define HID_KEYBOARD_MODIFER_RIGHTCTRL (1 << 4)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's right shift key is currently pressed. */
#define HID_KEYBOARD_MODIFER_RIGHTSHIFT (1 << 5)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's right alt key is currently pressed. */
#define HID_KEYBOARD_MODIFER_RIGHTALT (1 << 6)
/** Constant for a keyboard report modifier byte, indicating that the keyboard's right GUI key is currently pressed. */
#define HID_KEYBOARD_MODIFER_RIGHTGUI (1 << 7)
//@}
/** @name Keyboard Standard Report LED Masks */
//@{
/** Constant for a keyboard output report LED byte, indicating that the host's NUM LOCK mode is currently set. */
#define HID_KEYBOARD_LED_NUMLOCK (1 << 0)
/** Constant for a keyboard output report LED byte, indicating that the host's CAPS LOCK mode is currently set. */
#define HID_KEYBOARD_LED_CAPSLOCK (1 << 1)
/** Constant for a keyboard output report LED byte, indicating that the host's SCROLL LOCK mode is currently set. */
#define HID_KEYBOARD_LED_SCROLLLOCK (1 << 2)
/** Constant for a keyboard output report LED byte, indicating that the host's KATANA mode is currently set. */
#define HID_KEYBOARD_LED_KATANA (1 << 3)
//@}
/** @name Keyboard Standard Report Key Scan-codes */
//@{
#define HID_KEYBOARD_SC_ERROR_ROLLOVER 0x01
#define HID_KEYBOARD_SC_POST_FAIL 0x02
#define HID_KEYBOARD_SC_ERROR_UNDEFINED 0x03
#define HID_KEYBOARD_SC_A 0x04
#define HID_KEYBOARD_SC_B 0x05
#define HID_KEYBOARD_SC_C 0x06
#define HID_KEYBOARD_SC_D 0x07
#define HID_KEYBOARD_SC_E 0x08
#define HID_KEYBOARD_SC_F 0x09
#define HID_KEYBOARD_SC_G 0x0A
#define HID_KEYBOARD_SC_H 0x0B
#define HID_KEYBOARD_SC_I 0x0C
#define HID_KEYBOARD_SC_J 0x0D
#define HID_KEYBOARD_SC_K 0x0E
#define HID_KEYBOARD_SC_L 0x0F
#define HID_KEYBOARD_SC_M 0x10
#define HID_KEYBOARD_SC_N 0x11
#define HID_KEYBOARD_SC_O 0x12
#define HID_KEYBOARD_SC_P 0x13
#define HID_KEYBOARD_SC_Q 0x14
#define HID_KEYBOARD_SC_R 0x15
#define HID_KEYBOARD_SC_S 0x16
#define HID_KEYBOARD_SC_T 0x17
#define HID_KEYBOARD_SC_U 0x18
#define HID_KEYBOARD_SC_V 0x19
#define HID_KEYBOARD_SC_W 0x1A
#define HID_KEYBOARD_SC_X 0x1B
#define HID_KEYBOARD_SC_Y 0x1C
#define HID_KEYBOARD_SC_Z 0x1D
#define HID_KEYBOARD_SC_1_AND_EXCLAMATION 0x1E
#define HID_KEYBOARD_SC_2_AND_AT 0x1F
#define HID_KEYBOARD_SC_3_AND_HASHMARK 0x20
#define HID_KEYBOARD_SC_4_AND_DOLLAR 0x21
#define HID_KEYBOARD_SC_5_AND_PERCENTAGE 0x22
#define HID_KEYBOARD_SC_6_AND_CARET 0x23
#define HID_KEYBOARD_SC_7_AND_AND_AMPERSAND 0x24
#define HID_KEYBOARD_SC_8_AND_ASTERISK 0x25
#define HID_KEYBOARD_SC_9_AND_OPENING_PARENTHESIS 0x26
#define HID_KEYBOARD_SC_0_AND_CLOSING_PARENTHESIS 0x27
#define HID_KEYBOARD_SC_ENTER 0x28
#define HID_KEYBOARD_SC_ESCAPE 0x29
#define HID_KEYBOARD_SC_BACKSPACE 0x2A
#define HID_KEYBOARD_SC_TAB 0x2B
#define HID_KEYBOARD_SC_SPACE 0x2C
#define HID_KEYBOARD_SC_MINUS_AND_UNDERSCORE 0x2D
#define HID_KEYBOARD_SC_EQUAL_AND_PLUS 0x2E
#define HID_KEYBOARD_SC_OPENING_BRACKET_AND_OPENING_BRACE 0x2F
#define HID_KEYBOARD_SC_CLOSING_BRACKET_AND_CLOSING_BRACE 0x30
#define HID_KEYBOARD_SC_BACKSLASH_AND_PIPE 0x31
#define HID_KEYBOARD_SC_NON_US_HASHMARK_AND_TILDE 0x32
#define HID_KEYBOARD_SC_SEMICOLON_AND_COLON 0x33
#define HID_KEYBOARD_SC_APOSTROPHE_AND_QUOTE 0x34
#define HID_KEYBOARD_SC_GRAVE_ACCENT_AND_TILDE 0x35
#define HID_KEYBOARD_SC_COMMA_AND_LESS_THAN_SIGN 0x36
#define HID_KEYBOARD_SC_DOT_AND_GREATER_THAN_SIGN 0x37
#define HID_KEYBOARD_SC_SLASH_AND_QUESTION_MARK 0x38
#define HID_KEYBOARD_SC_CAPS_LOCK 0x39
#define HID_KEYBOARD_SC_F1 0x3A
#define HID_KEYBOARD_SC_F2 0x3B
#define HID_KEYBOARD_SC_F3 0x3C
#define HID_KEYBOARD_SC_F4 0x3D
#define HID_KEYBOARD_SC_F5 0x3E
#define HID_KEYBOARD_SC_F6 0x3F
#define HID_KEYBOARD_SC_F7 0x40
#define HID_KEYBOARD_SC_F8 0x41
#define HID_KEYBOARD_SC_F9 0x42
#define HID_KEYBOARD_SC_F10 0x43
#define HID_KEYBOARD_SC_F11 0x44
#define HID_KEYBOARD_SC_F12 0x45
#define HID_KEYBOARD_SC_PRINT_SCREEN 0x46
#define HID_KEYBOARD_SC_SCROLL_LOCK 0x47
#define HID_KEYBOARD_SC_PAUSE 0x48
#define HID_KEYBOARD_SC_INSERT 0x49
#define HID_KEYBOARD_SC_HOME 0x4A
#define HID_KEYBOARD_SC_PAGE_UP 0x4B
#define HID_KEYBOARD_SC_DELETE 0x4C
#define HID_KEYBOARD_SC_END 0x4D
#define HID_KEYBOARD_SC_PAGE_DOWN 0x4E
#define HID_KEYBOARD_SC_RIGHT_ARROW 0x4F
#define HID_KEYBOARD_SC_LEFT_ARROW 0x50
#define HID_KEYBOARD_SC_DOWN_ARROW 0x51
#define HID_KEYBOARD_SC_UP_ARROW 0x52
#define HID_KEYBOARD_SC_NUM_LOCK 0x53
#define HID_KEYBOARD_SC_KEYPAD_SLASH 0x54
#define HID_KEYBOARD_SC_KEYPAD_ASTERISK 0x55
#define HID_KEYBOARD_SC_KEYPAD_MINUS 0x56
#define HID_KEYBOARD_SC_KEYPAD_PLUS 0x57
#define HID_KEYBOARD_SC_KEYPAD_ENTER 0x58
#define HID_KEYBOARD_SC_KEYPAD_1_AND_END 0x59
#define HID_KEYBOARD_SC_KEYPAD_2_AND_DOWN_ARROW 0x5A
#define HID_KEYBOARD_SC_KEYPAD_3_AND_PAGE_DOWN 0x5B
#define HID_KEYBOARD_SC_KEYPAD_4_AND_LEFT_ARROW 0x5C
#define HID_KEYBOARD_SC_KEYPAD_5 0x5D
#define HID_KEYBOARD_SC_KEYPAD_6_AND_RIGHT_ARROW 0x5E
#define HID_KEYBOARD_SC_KEYPAD_7_AND_HOME 0x5F
#define HID_KEYBOARD_SC_KEYPAD_8_AND_UP_ARROW 0x60
#define HID_KEYBOARD_SC_KEYPAD_9_AND_PAGE_UP 0x61
#define HID_KEYBOARD_SC_KEYPAD_0_AND_INSERT 0x62
#define HID_KEYBOARD_SC_KEYPAD_DOT_AND_DELETE 0x63
#define HID_KEYBOARD_SC_NON_US_BACKSLASH_AND_PIPE 0x64
#define HID_KEYBOARD_SC_POWER 0x66
#define HID_KEYBOARD_SC_EQUAL_SIGN 0x67
#define HID_KEYBOARD_SC_F13 0x68
#define HID_KEYBOARD_SC_F14 0x69
#define HID_KEYBOARD_SC_F15 0x6A
#define HID_KEYBOARD_SC_F16 0x6B
#define HID_KEYBOARD_SC_F17 0x6C
#define HID_KEYBOARD_SC_F18 0x6D
#define HID_KEYBOARD_SC_F19 0x6E
#define HID_KEYBOARD_SC_F20 0x6F
#define HID_KEYBOARD_SC_F21 0x70
#define HID_KEYBOARD_SC_F22 0x71
#define HID_KEYBOARD_SC_F23 0x72
#define HID_KEYBOARD_SC_F24 0x73
#define HID_KEYBOARD_SC_EXECUTE 0x74
#define HID_KEYBOARD_SC_HELP 0x75
#define HID_KEYBOARD_SC_MANU 0x76
#define HID_KEYBOARD_SC_SELECT 0x77
#define HID_KEYBOARD_SC_STOP 0x78
#define HID_KEYBOARD_SC_AGAIN 0x79
#define HID_KEYBOARD_SC_UNDO 0x7A
#define HID_KEYBOARD_SC_CUT 0x7B
#define HID_KEYBOARD_SC_COPY 0x7C
#define HID_KEYBOARD_SC_PASTE 0x7D
#define HID_KEYBOARD_SC_FIND 0x7E
#define HID_KEYBOARD_SC_MUTE 0x7F
#define HID_KEYBOARD_SC_VOLUME_UP 0x80
#define HID_KEYBOARD_SC_VOLUME_DOWN 0x81
#define HID_KEYBOARD_SC_LOCKING_CAPS_LOCK 0x82
#define HID_KEYBOARD_SC_LOCKING_NUM_LOCK 0x83
#define HID_KEYBOARD_SC_LOCKING_SCROLL_LOCK 0x84
#define HID_KEYBOARD_SC_KEYPAD_COMMA 0x85
#define HID_KEYBOARD_SC_KEYPAD_EQUAL_SIGN 0x86
#define HID_KEYBOARD_SC_INTERNATIONAL1 0x87
#define HID_KEYBOARD_SC_INTERNATIONAL2 0x88
#define HID_KEYBOARD_SC_INTERNATIONAL3 0x89
#define HID_KEYBOARD_SC_INTERNATIONAL4 0x8A
#define HID_KEYBOARD_SC_INTERNATIONAL5 0x8B
#define HID_KEYBOARD_SC_INTERNATIONAL6 0x8C
#define HID_KEYBOARD_SC_INTERNATIONAL7 0x8D
#define HID_KEYBOARD_SC_INTERNATIONAL8 0x8E
#define HID_KEYBOARD_SC_INTERNATIONAL9 0x8F
#define HID_KEYBOARD_SC_LANG1 0x90
#define HID_KEYBOARD_SC_LANG2 0x91
#define HID_KEYBOARD_SC_LANG3 0x92
#define HID_KEYBOARD_SC_LANG4 0x93
#define HID_KEYBOARD_SC_LANG5 0x94
#define HID_KEYBOARD_SC_LANG6 0x95
#define HID_KEYBOARD_SC_LANG7 0x96
#define HID_KEYBOARD_SC_LANG8 0x97
#define HID_KEYBOARD_SC_LANG9 0x98
#define HID_KEYBOARD_SC_ALTERNATE_ERASE 0x99
#define HID_KEYBOARD_SC_SISREQ 0x9A
#define HID_KEYBOARD_SC_CANCEL 0x9B
#define HID_KEYBOARD_SC_CLEAR 0x9C
#define HID_KEYBOARD_SC_PRIOR 0x9D
#define HID_KEYBOARD_SC_RETURN 0x9E
#define HID_KEYBOARD_SC_SEPARATOR 0x9F
#define HID_KEYBOARD_SC_OUT 0xA0
#define HID_KEYBOARD_SC_OPER 0xA1
#define HID_KEYBOARD_SC_CLEAR_AND_AGAIN 0xA2
#define HID_KEYBOARD_SC_CRSEL_ANDPROPS 0xA3
#define HID_KEYBOARD_SC_EXSEL 0xA4
#define HID_KEYBOARD_SC_KEYPAD_00 0xB0
#define HID_KEYBOARD_SC_KEYPAD_000 0xB1
#define HID_KEYBOARD_SC_THOUSANDS_SEPARATOR 0xB2
#define HID_KEYBOARD_SC_DECIMAL_SEPARATOR 0xB3
#define HID_KEYBOARD_SC_CURRENCY_UNIT 0xB4
#define HID_KEYBOARD_SC_CURRENCY_SUB_UNIT 0xB5
#define HID_KEYBOARD_SC_KEYPAD_OPENING_PARENTHESIS 0xB6
#define HID_KEYBOARD_SC_KEYPAD_CLOSING_PARENTHESIS 0xB7
#define HID_KEYBOARD_SC_KEYPAD_OPENING_BRACE 0xB8
#define HID_KEYBOARD_SC_KEYPAD_CLOSING_BRACE 0xB9
#define HID_KEYBOARD_SC_KEYPAD_TAB 0xBA
#define HID_KEYBOARD_SC_KEYPAD_BACKSPACE 0xBB
#define HID_KEYBOARD_SC_KEYPAD_A 0xBC
#define HID_KEYBOARD_SC_KEYPAD_B 0xBD
#define HID_KEYBOARD_SC_KEYPAD_C 0xBE
#define HID_KEYBOARD_SC_KEYPAD_D 0xBF
#define HID_KEYBOARD_SC_KEYPAD_E 0xC0
#define HID_KEYBOARD_SC_KEYPAD_F 0xC1
#define HID_KEYBOARD_SC_KEYPAD_XOR 0xC2
#define HID_KEYBOARD_SC_KEYPAD_CARET 0xC3
#define HID_KEYBOARD_SC_KEYPAD_PERCENTAGE 0xC4
#define HID_KEYBOARD_SC_KEYPAD_LESS_THAN_SIGN 0xC5
#define HID_KEYBOARD_SC_KEYPAD_GREATER_THAN_SIGN 0xC6
#define HID_KEYBOARD_SC_KEYPAD_AMP 0xC7
#define HID_KEYBOARD_SC_KEYPAD_AMP_AMP 0xC8
#define HID_KEYBOARD_SC_KEYPAD_PIPE 0xC9
#define HID_KEYBOARD_SC_KEYPAD_PIPE_PIPE 0xCA
#define HID_KEYBOARD_SC_KEYPAD_COLON 0xCB
#define HID_KEYBOARD_SC_KEYPAD_HASHMARK 0xCC
#define HID_KEYBOARD_SC_KEYPAD_SPACE 0xCD
#define HID_KEYBOARD_SC_KEYPAD_AT 0xCE
#define HID_KEYBOARD_SC_KEYPAD_EXCLAMATION_SIGN 0xCF
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_STORE 0xD0
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_RECALL 0xD1
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_CLEAR 0xD2
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_ADD 0xD3
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_SUBTRACT 0xD4
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_MULTIPLY 0xD5
#define HID_KEYBOARD_SC_KEYPAD_MEMORY_DIVIDE 0xD6
#define HID_KEYBOARD_SC_KEYPAD_PLUS_AND_MINUS 0xD7
#define HID_KEYBOARD_SC_KEYPAD_CLEAR 0xD8
#define HID_KEYBOARD_SC_KEYPAD_CLEAR_ENTRY 0xD9
#define HID_KEYBOARD_SC_KEYPAD_BINARY 0xDA
#define HID_KEYBOARD_SC_KEYPAD_OCTAL 0xDB
#define HID_KEYBOARD_SC_KEYPAD_DECIMAL 0xDC
#define HID_KEYBOARD_SC_KEYPAD_HEXADECIMAL 0xDD
#define HID_KEYBOARD_SC_LEFT_CONTROL 0xE0
#define HID_KEYBOARD_SC_LEFT_SHIFT 0xE1
#define HID_KEYBOARD_SC_LEFT_ALT 0xE2
#define HID_KEYBOARD_SC_LEFT_GUI 0xE3
#define HID_KEYBOARD_SC_RIGHT_CONTROL 0xE4
#define HID_KEYBOARD_SC_RIGHT_SHIFT 0xE5
#define HID_KEYBOARD_SC_RIGHT_ALT 0xE6
#define HID_KEYBOARD_SC_RIGHT_GUI 0xE7
//@}
/** @name Common HID Device Report Descriptors */
//@{
/** \hideinitializer
* A list of HID report item array elements that describe a typical HID USB Joystick. The resulting report
* descriptor is structured according to the following layout:
*
* \code
* struct
* {
* intB_t X; // Signed X axis value
* intB_t Y; // Signed Y axis value
* int8_t Z; // Signed Z axis value
* // Additional axis elements here
* uintA_t Buttons; // Pressed buttons bitmask
* } Joystick_Report;
* \endcode
*
* Where \c uintA_t is a type large enough to hold one bit per button, and \c intB_t is a type large enough to hold the
* ranges of the signed \c MinAxisVal and \c MaxAxisVal values.
*
* @param NumAxis Number of axis in the joystick (8-bit)
* @param MinAxisVal Minimum logical axis value (16-bit).
* @param MaxAxisVal Maximum logical axis value (16-bit).
* @param MinPhysicalVal Minimum physical axis value, for movement resolution calculations (16-bit).
* @param MaxPhysicalVal Maximum physical axis value, for movement resolution calculations (16-bit).
* @param Buttons Total number of buttons in the device (8-bit).
*/
#define HID_DESCRIPTOR_JOYSTICK(NumAxis, MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons) \
HID_RI_USAGE_PAGE(8, 0x01), \
HID_RI_USAGE(8, 0x04), \
HID_RI_COLLECTION(8, 0x01), \
HID_RI_USAGE(8, 0x01), \
HID_RI_COLLECTION(8, 0x00), \
HID_RI_USAGE_MINIMUM(8, 0x30), \
HID_RI_USAGE_MAXIMUM(8, (0x30 + (NumAxis - 1))), \
HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \
HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \
HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \
HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \
HID_RI_REPORT_COUNT(8, NumAxis), \
HID_RI_REPORT_SIZE(8, ((((MinAxisVal >= -0xFF) && (MaxAxisVal <= 0xFF)) ? 8 : 16))), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \
HID_RI_END_COLLECTION(0), \
HID_RI_USAGE_PAGE(8, 0x09), \
HID_RI_USAGE_MINIMUM(8, 0x01), \
HID_RI_USAGE_MAXIMUM(8, Buttons), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0x01), \
HID_RI_REPORT_SIZE(8, 0x01), \
HID_RI_REPORT_COUNT(8, Buttons), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \
HID_RI_REPORT_SIZE(8, (8 - (Buttons % 8))), \
HID_RI_REPORT_COUNT(8, 0x01), \
HID_RI_INPUT(8, HID_IOF_CONSTANT), \
HID_RI_END_COLLECTION(0)
/** \hideinitializer
* A list of HID report item array elements that describe a typical HID USB keyboard. The resulting report descriptor
* is compatible with @ref USB_KeyboardReport_Data_t when \c MaxKeys is equal to 6. For other values, the report will
* be structured according to the following layout:
*
* \code
* struct
* {
* uint8_t Modifier; // Keyboard modifier byte indicating pressed modifier keys (HID_KEYBOARD_MODIFER_* masks)
* uint8_t Reserved; // Reserved for OEM use, always set to 0.
* uint8_t KeyCode[MaxKeys]; // Length determined by the number of keys that can be reported
* } Keyboard_Report;
* \endcode
*
* @param MaxKeys Number of simultaneous keys that can be reported at the one time (8-bit).
*/
#define HID_DESCRIPTOR_KEYBOARD(MaxKeys) \
HID_RI_USAGE_PAGE(8, 0x01), \
HID_RI_USAGE(8, 0x06), \
HID_RI_COLLECTION(8, 0x01), \
HID_RI_USAGE_PAGE(8, 0x07), \
HID_RI_USAGE_MINIMUM(8, 0xE0), \
HID_RI_USAGE_MAXIMUM(8, 0xE7), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0x01), \
HID_RI_REPORT_SIZE(8, 0x01), \
HID_RI_REPORT_COUNT(8, 0x08), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \
HID_RI_REPORT_COUNT(8, 0x01), \
HID_RI_REPORT_SIZE(8, 0x08), \
HID_RI_INPUT(8, HID_IOF_CONSTANT), \
HID_RI_USAGE_PAGE(8, 0x08), \
HID_RI_USAGE_MINIMUM(8, 0x01), \
HID_RI_USAGE_MAXIMUM(8, 0x05), \
HID_RI_REPORT_COUNT(8, 0x05), \
HID_RI_REPORT_SIZE(8, 0x01), \
HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \
HID_RI_REPORT_COUNT(8, 0x01), \
HID_RI_REPORT_SIZE(8, 0x03), \
HID_RI_OUTPUT(8, HID_IOF_CONSTANT), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0x65), \
HID_RI_USAGE_PAGE(8, 0x07), \
HID_RI_USAGE_MINIMUM(8, 0x00), \
HID_RI_USAGE_MAXIMUM(8, 0x65), \
HID_RI_REPORT_COUNT(8, MaxKeys), \
HID_RI_REPORT_SIZE(8, 0x08), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_ARRAY | HID_IOF_ABSOLUTE), \
HID_RI_END_COLLECTION(0)
/** \hideinitializer
* A list of HID report item array elements that describe a typical HID USB mouse. The resulting report descriptor
* is compatible with @ref USB_MouseReport_Data_t if the \c MinAxisVal and \c MaxAxisVal values fit within a \c int8_t range
* and the number of Buttons is less than 8. For other values, the report is structured according to the following layout:
*
* \code
* struct
* {
* uintA_t Buttons; // Pressed buttons bitmask
* intB_t X; // X axis value
* intB_t Y; // Y axis value
* } Mouse_Report;
* \endcode
*
* Where \c intA_t is a type large enough to hold one bit per button, and \c intB_t is a type large enough to hold the
* ranges of the signed \c MinAxisVal and \c MaxAxisVal values.
*
* @param MinAxisVal Minimum X/Y logical axis value (16-bit).
* @param MaxAxisVal Maximum X/Y logical axis value (16-bit).
* @param MinPhysicalVal Minimum X/Y physical axis value, for movement resolution calculations (16-bit).
* @param MaxPhysicalVal Maximum X/Y physical axis value, for movement resolution calculations (16-bit).
* @param Buttons Total number of buttons in the device (8-bit).
* @param AbsoluteCoords Boolean true to use absolute X/Y coordinates (e.g. touchscreen).
*/
#define HID_DESCRIPTOR_MOUSE(MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons, AbsoluteCoords) \
HID_RI_USAGE_PAGE(8, 0x01), \
HID_RI_USAGE(8, 0x02), \
HID_RI_COLLECTION(8, 0x01), \
HID_RI_USAGE(8, 0x01), \
HID_RI_COLLECTION(8, 0x00), \
HID_RI_USAGE_PAGE(8, 0x09), \
HID_RI_USAGE_MINIMUM(8, 0x01), \
HID_RI_USAGE_MAXIMUM(8, Buttons), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0x01), \
HID_RI_REPORT_COUNT(8, Buttons), \
HID_RI_REPORT_SIZE(8, 0x01), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \
HID_RI_REPORT_COUNT(8, 0x01), \
HID_RI_REPORT_SIZE(8, (8 - (Buttons % 8))), \
HID_RI_INPUT(8, HID_IOF_CONSTANT), \
HID_RI_USAGE_PAGE(8, 0x01), \
HID_RI_USAGE(8, 0x30), \
HID_RI_USAGE(8, 0x31), \
HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \
HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \
HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \
HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \
HID_RI_REPORT_COUNT(8, 0x02), \
HID_RI_REPORT_SIZE(8, ((((MinAxisVal >= -0xFF) && (MaxAxisVal <= 0xFF)) ? 8 : 16))), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | (AbsoluteCoords ? HID_IOF_ABSOLUTE : HID_IOF_RELATIVE)), \
HID_RI_END_COLLECTION(0), \
HID_RI_END_COLLECTION(0)
/** \hideinitializer
* A list of HID report item array elements that describe a typical Vendor Defined byte array HID report descriptor,
* used for transporting arbitrary data between the USB host and device via HID reports. The resulting report should be
* a uint8_t byte array of the specified length in both Device to Host (IN) and Host to Device (OUT) directions.
*
* @param VendorPageNum Vendor Defined HID Usage Page index, ranging from 0x00 to 0xFF.
* @param CollectionUsage Vendor Usage for the encompassing report IN and OUT collection, ranging from 0x00 to 0xFF.
* @param DataINUsage Vendor Usage for the IN report data, ranging from 0x00 to 0xFF.
* @param DataOUTUsage Vendor Usage for the OUT report data, ranging from 0x00 to 0xFF.
* @param NumBytes Length of the data IN and OUT reports.
*/
#define HID_DESCRIPTOR_VENDOR(VendorPageNum, CollectionUsage, DataINUsage, DataOUTUsage, NumBytes) \
HID_RI_USAGE_PAGE(16, (0xFF00 | VendorPageNum)), \
HID_RI_USAGE(8, CollectionUsage), \
HID_RI_COLLECTION(8, 0x01), \
HID_RI_USAGE(8, DataINUsage), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \
HID_RI_REPORT_SIZE(8, 0x08), \
HID_RI_REPORT_COUNT(8, NumBytes), \
HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \
HID_RI_USAGE(8, DataOUTUsage), \
HID_RI_LOGICAL_MINIMUM(8, 0x00), \
HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \
HID_RI_REPORT_SIZE(8, 0x08), \
HID_RI_REPORT_COUNT(8, NumBytes), \
HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \
HID_RI_END_COLLECTION(0)
//@}
/* Type Defines: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the HID
* device class.
*/
enum HID_Descriptor_ClassSubclassProtocol_t
{
HID_CSCP_HIDClass = 0x03, /**< Descriptor Class value indicating that the device or interface
* belongs to the HID class.
*/
HID_CSCP_NonBootSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface
* does not implement a HID boot protocol.
*/
HID_CSCP_BootSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface
* implements a HID boot protocol.
*/
HID_CSCP_NonBootProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface
* does not belong to a HID boot protocol.
*/
HID_CSCP_KeyboardBootProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the Keyboard HID boot protocol.
*/
HID_CSCP_MouseBootProtocol = 0x02, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the Mouse HID boot protocol.
*/
};
/** Enum for the HID class specific control requests that can be issued by the USB bus host. */
enum HID_ClassRequests_t
{
HID_REQ_GetReport = 0x01, /**< HID class-specific Request to get the current HID report from the device. */
HID_REQ_GetIdle = 0x02, /**< HID class-specific Request to get the current device idle count. */
HID_REQ_GetProtocol = 0x03, /**< HID class-specific Request to get the current HID report protocol mode. */
HID_REQ_SetReport = 0x09, /**< HID class-specific Request to set the current HID report to the device. */
HID_REQ_SetIdle = 0x0A, /**< HID class-specific Request to set the device's idle count. */
HID_REQ_SetProtocol = 0x0B, /**< HID class-specific Request to set the current HID report protocol mode. */
};
/** Enum for the HID class specific descriptor types. */
enum HID_DescriptorTypes_t
{
HID_DTYPE_HID = 0x21, /**< Descriptor header type value, to indicate a HID class HID descriptor. */
HID_DTYPE_Report = 0x22, /**< Descriptor header type value, to indicate a HID class HID report descriptor. */
};
/** Enum for the different types of HID reports. */
enum HID_ReportItemTypes_t
{
HID_REPORT_ITEM_In = 0, /**< Indicates that the item is an IN report type. */
HID_REPORT_ITEM_Out = 1, /**< Indicates that the item is an OUT report type. */
HID_REPORT_ITEM_Feature = 2, /**< Indicates that the item is a FEATURE report type. */
};
/** @brief HID class-specific HID Descriptor (nxpUSBlib naming conventions).
*
* Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID
* specification for details on the structure elements.
*
* @see @ref USB_HID_StdDescriptor_HID_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint16_t HIDSpec; /**< BCD encoded version that the HID descriptor and device complies to. */
uint8_t CountryCode; /**< Country code of the localized device, or zero if universal. */
uint8_t TotalReportDescriptors; /**< Total number of HID report descriptors for the interface. */
uint8_t HIDReportType; /**< Type of HID report, set to @ref HID_DTYPE_Report. */
uint16_t HIDReportLength; /**< Length of the associated HID report descriptor, in bytes. */
} ATTR_PACKED USB_HID_Descriptor_HID_t;
/** @brief HID class-specific HID Descriptor (USB-IF naming conventions).
*
* Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID
* specification for details on the structure elements.
*
* @see @ref USB_HID_Descriptor_HID_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */
uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */
uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */
uint8_t bDescriptorType2; /**< Type of HID report, set to @ref HID_DTYPE_Report. */
uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */
} ATTR_PACKED USB_HID_StdDescriptor_HID_t;
/** @brief Standard HID Boot Protocol Mouse Report.
*
* Type define for a standard Boot Protocol Mouse report
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t Button; /**< Button mask for currently pressed buttons in the mouse. */
int8_t X; /**< Current delta X movement of the mouse. */
int8_t Y; /**< Current delta Y movement on the mouse. */
} ATTR_PACKED USB_MouseReport_Data_t;
/** @brief Standard HID Boot Protocol Keyboard Report.
*
* Type define for a standard Boot Protocol Keyboard report
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t Modifier; /**< Keyboard modifier byte, indicating pressed modifier keys (a combination of
* \c HID_KEYBOARD_MODIFER_* masks).
*/
uint8_t Reserved; /**< Reserved for OEM use, always set to 0. */
uint8_t KeyCode[6]; /**< Key codes of the currently pressed keys. */
} ATTR_PACKED USB_KeyboardReport_Data_t;
/** Type define for the data type used to store HID report descriptor elements. */
typedef uint8_t USB_Descriptor_HIDReport_Datatype_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

365
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/HIDParser.c_ vendored Normal file
View file

@ -0,0 +1,365 @@
/*
* @brief USB Human Interface Device (HID) Class report descriptor parser
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#define __INCLUDE_FROM_USB_DRIVER
#define __INCLUDE_FROM_HID_DRIVER
#include "HIDParser.h"
uint8_t USB_ProcessHIDReport(const uint8_t* ReportData,
uint16_t ReportSize,
HID_ReportInfo_t* const ParserData)
{
HID_StateTable_t StateTable[HID_STATETABLE_STACK_DEPTH];
HID_StateTable_t* CurrStateTable = &StateTable[0];
HID_CollectionPath_t* CurrCollectionPath = NULL;
HID_ReportSizeInfo_t* CurrReportIDInfo = &ParserData->ReportIDSizes[0];
uint16_t UsageList[HID_USAGE_STACK_DEPTH];
uint8_t UsageListSize = 0;
HID_MinMax_t UsageMinMax = {0, 0};
memset(ParserData, 0x00, sizeof(HID_ReportInfo_t));
memset(CurrStateTable, 0x00, sizeof(HID_StateTable_t));
memset(CurrReportIDInfo, 0x00, sizeof(HID_ReportSizeInfo_t));
ParserData->TotalDeviceReports = 1;
while (ReportSize)
{
uint8_t HIDReportItem = *ReportData;
uint32_t ReportItemData = 0;
ReportData++;
ReportSize--;
switch (HIDReportItem & HID_RI_DATA_SIZE_MASK)
{
case HID_RI_DATA_BITS_32:
ReportItemData = le32_to_cpu(*((uint32_t*)ReportData));
ReportSize -= 4;
ReportData += 4;
break;
case HID_RI_DATA_BITS_16:
ReportItemData = le16_to_cpu(*((uint16_t*)ReportData));
ReportSize -= 2;
ReportData += 2;
break;
case HID_RI_DATA_BITS_8:
ReportItemData = *((uint8_t*)ReportData);
ReportSize -= 1;
ReportData += 1;
break;
}
switch (HIDReportItem & (HID_RI_TYPE_MASK | HID_RI_TAG_MASK))
{
case HID_RI_PUSH(0):
if (CurrStateTable == &StateTable[HID_STATETABLE_STACK_DEPTH - 1])
return HID_PARSE_HIDStackOverflow;
memcpy((CurrStateTable + 1),
CurrStateTable,
sizeof(HID_ReportItem_t));
CurrStateTable++;
break;
case HID_RI_POP(0):
if (CurrStateTable == &StateTable[0])
return HID_PARSE_HIDStackUnderflow;
CurrStateTable--;
break;
case HID_RI_USAGE_PAGE(0):
if ((HIDReportItem & HID_RI_DATA_SIZE_MASK) == HID_RI_DATA_BITS_32)
CurrStateTable->Attributes.Usage.Page = (ReportItemData >> 16);
CurrStateTable->Attributes.Usage.Page = ReportItemData;
break;
case HID_RI_LOGICAL_MINIMUM(0):
CurrStateTable->Attributes.Logical.Minimum = ReportItemData;
break;
case HID_RI_LOGICAL_MAXIMUM(0):
CurrStateTable->Attributes.Logical.Maximum = ReportItemData;
break;
case HID_RI_PHYSICAL_MINIMUM(0):
CurrStateTable->Attributes.Physical.Minimum = ReportItemData;
break;
case HID_RI_PHYSICAL_MAXIMUM(0):
CurrStateTable->Attributes.Physical.Maximum = ReportItemData;
break;
case HID_RI_UNIT_EXPONENT(0):
CurrStateTable->Attributes.Unit.Exponent = ReportItemData;
break;
case HID_RI_UNIT(0):
CurrStateTable->Attributes.Unit.Type = ReportItemData;
break;
case HID_RI_REPORT_SIZE(0):
CurrStateTable->Attributes.BitSize = ReportItemData;
break;
case HID_RI_REPORT_COUNT(0):
CurrStateTable->ReportCount = ReportItemData;
break;
case HID_RI_REPORT_ID(0):
CurrStateTable->ReportID = ReportItemData;
if (ParserData->UsingReportIDs)
{
CurrReportIDInfo = NULL;
for (uint8_t i = 0; i < ParserData->TotalDeviceReports; i++)
{
if (ParserData->ReportIDSizes[i].ReportID == CurrStateTable->ReportID)
{
CurrReportIDInfo = &ParserData->ReportIDSizes[i];
break;
}
}
if (CurrReportIDInfo == NULL)
{
if (ParserData->TotalDeviceReports == HID_MAX_REPORT_IDS)
return HID_PARSE_InsufficientReportIDItems;
CurrReportIDInfo = &ParserData->ReportIDSizes[ParserData->TotalDeviceReports++];
memset(CurrReportIDInfo, 0x00, sizeof(HID_ReportSizeInfo_t));
}
}
ParserData->UsingReportIDs = true;
CurrReportIDInfo->ReportID = CurrStateTable->ReportID;
break;
case HID_RI_USAGE(0):
if (UsageListSize == HID_USAGE_STACK_DEPTH)
return HID_PARSE_UsageListOverflow;
UsageList[UsageListSize++] = ReportItemData;
break;
case HID_RI_USAGE_MINIMUM(0):
UsageMinMax.Minimum = ReportItemData;
break;
case HID_RI_USAGE_MAXIMUM(0):
UsageMinMax.Maximum = ReportItemData;
break;
case HID_RI_COLLECTION(0):
if (CurrCollectionPath == NULL)
{
CurrCollectionPath = &ParserData->CollectionPaths[0];
}
else
{
HID_CollectionPath_t* ParentCollectionPath = CurrCollectionPath;
CurrCollectionPath = &ParserData->CollectionPaths[1];
while (CurrCollectionPath->Parent != NULL)
{
if (CurrCollectionPath == &ParserData->CollectionPaths[HID_MAX_COLLECTIONS - 1])
return HID_PARSE_InsufficientCollectionPaths;
CurrCollectionPath++;
}
CurrCollectionPath->Parent = ParentCollectionPath;
}
CurrCollectionPath->Type = ReportItemData;
CurrCollectionPath->Usage.Page = CurrStateTable->Attributes.Usage.Page;
if (UsageListSize)
{
CurrCollectionPath->Usage.Usage = UsageList[0];
for (uint8_t i = 0; i < UsageListSize; i++)
UsageList[i] = UsageList[i + 1];
UsageListSize--;
}
else if (UsageMinMax.Minimum <= UsageMinMax.Maximum)
{
CurrCollectionPath->Usage.Usage = UsageMinMax.Minimum++;
}
break;
case HID_RI_END_COLLECTION(0):
if (CurrCollectionPath == NULL)
return HID_PARSE_UnexpectedEndCollection;
CurrCollectionPath = CurrCollectionPath->Parent;
break;
case HID_RI_INPUT(0):
case HID_RI_OUTPUT(0):
case HID_RI_FEATURE(0):
for (uint8_t ReportItemNum = 0; ReportItemNum < CurrStateTable->ReportCount; ReportItemNum++)
{
HID_ReportItem_t NewReportItem;
memcpy(&NewReportItem.Attributes,
&CurrStateTable->Attributes,
sizeof(HID_ReportItem_Attributes_t));
NewReportItem.ItemFlags = ReportItemData;
NewReportItem.CollectionPath = CurrCollectionPath;
NewReportItem.ReportID = CurrStateTable->ReportID;
if (UsageListSize)
{
NewReportItem.Attributes.Usage.Usage = UsageList[0];
for (uint8_t i = 0; i < UsageListSize; i++)
UsageList[i] = UsageList[i + 1];
UsageListSize--;
}
else if (UsageMinMax.Minimum <= UsageMinMax.Maximum)
{
NewReportItem.Attributes.Usage.Usage = UsageMinMax.Minimum++;
}
uint8_t ItemTypeTag = (HIDReportItem & (HID_RI_TYPE_MASK | HID_RI_TAG_MASK));
if (ItemTypeTag == HID_RI_INPUT(0))
NewReportItem.ItemType = HID_REPORT_ITEM_In;
else if (ItemTypeTag == HID_RI_OUTPUT(0))
NewReportItem.ItemType = HID_REPORT_ITEM_Out;
else
NewReportItem.ItemType = HID_REPORT_ITEM_Feature;
NewReportItem.BitOffset = CurrReportIDInfo->ReportSizeBits[NewReportItem.ItemType];
CurrReportIDInfo->ReportSizeBits[NewReportItem.ItemType] += CurrStateTable->Attributes.BitSize;
if (ParserData->LargestReportSizeBits < NewReportItem.BitOffset)
ParserData->LargestReportSizeBits = NewReportItem.BitOffset;
if (ParserData->TotalReportItems == HID_MAX_REPORTITEMS)
return HID_PARSE_InsufficientReportItems;
memcpy(&ParserData->ReportItems[ParserData->TotalReportItems],
&NewReportItem, sizeof(HID_ReportItem_t));
if (!(ReportItemData & HID_IOF_CONSTANT) && CALLBACK_HIDParser_FilterHIDReportItem(&NewReportItem))
ParserData->TotalReportItems++;
}
break;
}
if ((HIDReportItem & HID_RI_TYPE_MASK) == HID_RI_TYPE_MAIN)
{
UsageMinMax.Minimum = 0;
UsageMinMax.Maximum = 0;
UsageListSize = 0;
}
}
if (!(ParserData->TotalReportItems))
return HID_PARSE_NoUnfilteredReportItems;
return HID_PARSE_Successful;
}
bool USB_GetHIDReportItemInfo(const uint8_t* ReportData,
HID_ReportItem_t* const ReportItem)
{
if (ReportItem == NULL)
return false;
uint16_t DataBitsRem = ReportItem->Attributes.BitSize;
uint16_t CurrentBit = ReportItem->BitOffset;
uint32_t BitMask = (1 << 0);
if (ReportItem->ReportID)
{
if (ReportItem->ReportID != ReportData[0])
return false;
ReportData++;
}
ReportItem->PreviousValue = ReportItem->Value;
ReportItem->Value = 0;
while (DataBitsRem--)
{
if (ReportData[CurrentBit / 8] & (1 << (CurrentBit % 8)))
ReportItem->Value |= BitMask;
CurrentBit++;
BitMask <<= 1;
}
return true;
}
void USB_SetHIDReportItemInfo(uint8_t* ReportData,
HID_ReportItem_t* const ReportItem)
{
if (ReportItem == NULL)
return;
uint16_t DataBitsRem = ReportItem->Attributes.BitSize;
uint16_t CurrentBit = ReportItem->BitOffset;
uint32_t BitMask = (1 << 0);
if (ReportItem->ReportID)
{
ReportData[0] = ReportItem->ReportID;
ReportData++;
}
ReportItem->PreviousValue = ReportItem->Value;
while (DataBitsRem--)
{
if (ReportItem->Value & (1 << (CurrentBit % 8)))
ReportData[CurrentBit / 8] |= BitMask;
CurrentBit++;
BitMask <<= 1;
}
}
uint16_t USB_GetHIDReportSize(HID_ReportInfo_t* const ParserData,
const uint8_t ReportID,
const uint8_t ReportType)
{
for (uint8_t i = 0; i < HID_MAX_REPORT_IDS; i++)
{
uint16_t ReportSizeBits = ParserData->ReportIDSizes[i].ReportSizeBits[ReportType];
if (ParserData->ReportIDSizes[i].ReportID == ReportID)
return (ReportSizeBits / 8) + ((ReportSizeBits % 8) ? 1 : 0);
}
return 0;
}

358
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/HIDParser.h vendored Normal file
View file

@ -0,0 +1,358 @@
/*
* @brief USB Human Interface Device (HID) Class report descriptor parser
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USB
* @defgroup Group_HIDParser HID Report Parser
* @brief USB Human Interface Device (HID) Class report descriptor parser.
*
* @section Sec_Dependencies Module Source Dependencies
* The following files must be built with any user project that uses this module:
* - nxpUSBlib/Drivers/USB/Class/Host/HIDParser.c <i>(Makefile source module name: NXPUSBLIB_SRC_USB)</i>
*
* @section Sec_ModDescription Module Description
* Human Interface Device (HID) class report descriptor parser. This module implements a parser than is
* capable of processing a complete HID report descriptor, and outputting a flat structure containing the
* contents of the report in an a more friendly format. The parsed data may then be further processed and used
* within an application to process sent and received HID reports to and from an attached HID device.
*
* A HID report descriptor consists of a set of HID report items, which describe the function and layout
* of data exchanged between a HID device and a host, including both the physical encoding of each item
* (such as a button, key press or joystick axis) in the sent and received data packets - known as "reports" -
* as well as other information about each item such as the usages, data range, physical location and other
* characteristics. In this way a HID device can retain a high degree of flexibility in its capabilities, as it
* is not forced to comply with a given report layout or feature-set.
*
* This module also contains routines for the processing of data in an actual HID report, using the parsed report
* descriptor data as a guide for the encoding.
*
* @{
*/
#ifndef __HIDPARSER_H__
#define __HIDPARSER_H__
/* Includes: */
#include "../../../../Common/Common.h"
#include "HIDReportData.h"
#include "HIDClassCommon.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Macros: */
#if !defined(HID_STATETABLE_STACK_DEPTH) || defined(__DOXYGEN__)
/** Constant indicating the maximum stack depth of the state table. A larger state table
* allows for more PUSH/POP report items to be nested, but consumes more memory. By default
* this is set to 2 levels (allowing non-nested PUSH items) but this can be overridden by
* defining \c HID_STATETABLE_STACK_DEPTH to another value in the user project makefile, passing the
* define to the compiler using the -D compiler switch.
*/
#define HID_STATETABLE_STACK_DEPTH 2
#endif
#if !defined(HID_USAGE_STACK_DEPTH) || defined(__DOXYGEN__)
/** Constant indicating the maximum stack depth of the usage table. A larger usage table
* allows for more USAGE items to be indicated sequentially for REPORT COUNT entries of more than
* one, but requires more stack space. By default this is set to 8 levels (allowing for a report
* item with a count of 8) but this can be overridden by defining \c HID_USAGE_STACK_DEPTH to another
* value in the user project makefile, passing the define to the compiler using the -D compiler
* switch.
*/
#define HID_USAGE_STACK_DEPTH 8
#endif
#if !defined(HID_MAX_COLLECTIONS) || defined(__DOXYGEN__)
/** Constant indicating the maximum number of COLLECTION items (nested or unnested) that can be
* processed in the report item descriptor. A large value allows for more COLLECTION items to be
* processed, but consumes more memory. By default this is set to 10 collections, but this can be
* overridden by defining \c HID_MAX_COLLECTIONS to another value in the user project makefile, passing
* the define to the compiler using the -D compiler switch.
*/
#define HID_MAX_COLLECTIONS 10
#endif
#if !defined(HID_MAX_REPORTITEMS) || defined(__DOXYGEN__)
/** Constant indicating the maximum number of report items (IN, OUT or FEATURE) that can be processed
* in the report item descriptor and stored in the user HID Report Info structure. A large value allows
* for more report items to be stored, but consumes more memory. By default this is set to 20 items,
* but this can be overridden by defining \c HID_MAX_REPORTITEMS to another value in the user project
* makefile, and passing the define to the compiler using the -D compiler switch.
*/
#define HID_MAX_REPORTITEMS 20
#endif
#if !defined(HID_MAX_REPORT_IDS) || defined(__DOXYGEN__)
/** Constant indicating the maximum number of unique report IDs that can be processed in the report item
* descriptor for the report size information array in the user HID Report Info structure. A large value
* allows for more report ID report sizes to be stored, but consumes more memory. By default this is set
* to 10 items, but this can be overridden by defining \c HID_MAX_REPORT_IDS to another value in the user project
* makefile, and passing the define to the compiler using the -D compiler switch. Note that IN, OUT and FEATURE
* items sharing the same report ID consume only one size item in the array.
*/
#define HID_MAX_REPORT_IDS 10
#endif
/** Returns the value a given HID report item (once its value has been fetched via @ref USB_GetHIDReportItemInfo())
* left-aligned to the given data type. This allows for signed data to be interpreted correctly, by shifting the data
* leftwards until the data's sign bit is in the correct position.
*
* @param ReportItem HID Report Item whose retrieved value is to be aligned.
* @param Type Data type to align the HID report item's value to.
*
* @return Left-aligned data of the given report item's pre-retrieved value for the given datatype.
*/
#define HID_ALIGN_DATA(ReportItem, Type) ((Type)(ReportItem->Value << ((8 * sizeof(Type)) - ReportItem->Attributes.BitSize)))
/* Public Interface - May be used in end-application: */
/* Enums: */
/** Enum for the possible error codes in the return value of the @ref USB_ProcessHIDReport() function. */
enum HID_Parse_ErrorCodes_t
{
HID_PARSE_Successful = 0, /**< Successful parse of the HID report descriptor, no error. */
HID_PARSE_HIDStackOverflow = 1, /**< More than @ref HID_STATETABLE_STACK_DEPTH nested PUSHes in the report. */
HID_PARSE_HIDStackUnderflow = 2, /**< A POP was found when the state table stack was empty. */
HID_PARSE_InsufficientReportItems = 3, /**< More than @ref HID_MAX_REPORTITEMS report items in the report. */
HID_PARSE_UnexpectedEndCollection = 4, /**< An END COLLECTION item found without matching COLLECTION item. */
HID_PARSE_InsufficientCollectionPaths = 5, /**< More than @ref HID_MAX_COLLECTIONS collections in the report. */
HID_PARSE_UsageListOverflow = 6, /**< More than @ref HID_USAGE_STACK_DEPTH usages listed in a row. */
HID_PARSE_InsufficientReportIDItems = 7, /**< More than @ref HID_MAX_REPORT_IDS report IDs in the device. */
HID_PARSE_NoUnfilteredReportItems = 8, /**< All report items from the device were filtered by the filtering callback routine. */
};
/* Type Defines: */
/** @brief HID Parser Report Item Min/Max Structure.
*
* Type define for an attribute with both minimum and maximum values (e.g. Logical Min/Max).
*/
typedef struct
{
uint32_t Minimum; /**< Minimum value for the attribute. */
uint32_t Maximum; /**< Maximum value for the attribute. */
} HID_MinMax_t;
/** @brief HID Parser Report Item Unit Structure.
*
* Type define for the Unit attributes of a report item.
*/
typedef struct
{
uint32_t Type; /**< Unit type (refer to HID specifications for details). */
uint8_t Exponent; /**< Unit exponent (refer to HID specifications for details). */
} HID_Unit_t;
/** @brief HID Parser Report Item Usage Structure.
*
* Type define for the Usage attributes of a report item.
*/
typedef struct
{
uint16_t Page; /**< Usage page of the report item. */
uint16_t Usage; /**< Usage of the report item. */
} HID_Usage_t;
/** @brief HID Parser Report Item Collection Path Structure.
*
* Type define for a COLLECTION object. Contains the collection attributes and a reference to the
* parent collection if any.
*/
typedef struct HID_CollectionPath
{
uint8_t Type; /**< Collection type (e.g. "Generic Desktop"). */
HID_Usage_t Usage; /**< Collection usage. */
struct HID_CollectionPath* Parent; /**< Reference to parent collection, or \c NULL if root collection. */
} HID_CollectionPath_t;
/** @brief HID Parser Report Item Attributes Structure.
*
* Type define for all the data attributes of a report item, except flags.
*/
typedef struct
{
uint8_t BitSize; /**< Size in bits of the report item's data. */
HID_Usage_t Usage; /**< Usage of the report item. */
HID_Unit_t Unit; /**< Unit type and exponent of the report item. */
HID_MinMax_t Logical; /**< Logical minimum and maximum of the report item. */
HID_MinMax_t Physical; /**< Physical minimum and maximum of the report item. */
} HID_ReportItem_Attributes_t;
/** @brief HID Parser Report Item Details Structure.
*
* Type define for a report item (IN, OUT or FEATURE) layout attributes and other details.
*/
typedef struct
{
uint16_t BitOffset; /**< Bit offset in the IN, OUT or FEATURE report of the item. */
uint8_t ItemType; /**< Report item type, a value in @ref HID_ReportItemTypes_t. */
uint16_t ItemFlags; /**< Item data flags, a mask of HID_IOF_* constants. */
uint8_t ReportID; /**< Report ID this item belongs to, or 0x00 if device has only one report */
HID_CollectionPath_t* CollectionPath; /**< Collection path of the item. */
HID_ReportItem_Attributes_t Attributes; /**< Report item attributes. */
uint32_t Value; /**< Current value of the report item - use @ref HID_ALIGN_DATA() when processing
* a retrieved value so that it is aligned to a specific type.
*/
uint32_t PreviousValue; /**< Previous value of the report item. */
} HID_ReportItem_t;
/** @brief HID Parser Report Size Structure.
*
* Type define for a report item size information structure, to retain the size of a device's reports by ID.
*/
typedef struct
{
uint8_t ReportID; /**< Report ID of the report within the HID interface. */
uint16_t ReportSizeBits[3]; /**< Total number of bits in each report type for the given Report ID,
* indexed by the @ref HID_ReportItemTypes_t enum.
*/
} HID_ReportSizeInfo_t;
/** @brief HID Parser State Structure.
*
* Type define for a complete processed HID report, including all report item data and collections.
*/
typedef struct
{
uint8_t TotalReportItems; /**< Total number of report items stored in the \c ReportItems array. */
HID_ReportItem_t ReportItems[HID_MAX_REPORTITEMS]; /**< Report items array, including all IN, OUT
* and FEATURE items.
*/
HID_CollectionPath_t CollectionPaths[HID_MAX_COLLECTIONS]; /**< All collection items, referenced
* by the report items.
*/
uint8_t TotalDeviceReports; /**< Number of reports within the HID interface */
HID_ReportSizeInfo_t ReportIDSizes[HID_MAX_REPORT_IDS]; /**< Report sizes for each report in the interface */
uint16_t LargestReportSizeBits; /**< Largest report that the attached device will generate, in bits */
bool UsingReportIDs; /**< Indicates if the device has at least one REPORT ID
* element in its HID report descriptor.
*/
} HID_ReportInfo_t;
/* Function Prototypes: */
/** Function to process a given HID report returned from an attached device, and store it into a given
* @ref HID_ReportInfo_t structure.
*
* @param ReportData Buffer containing the device's HID report table.
* @param ReportSize Size in bytes of the HID report table.
* \param[out] ParserData Pointer to a @ref HID_ReportInfo_t instance for the parser output.
*
* @return A value in the @ref HID_Parse_ErrorCodes_t enum.
*/
uint8_t USB_ProcessHIDReport(const uint8_t* ReportData,
uint16_t ReportSize,
HID_ReportInfo_t* const ParserData) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);
/** Extracts the given report item's value out of the given HID report and places it into the Value
* member of the report item's @ref HID_ReportItem_t structure.
*
* When called on a report with an item that exists in that report, this copies the report item's \c Value
* to its \c PreviousValue element for easy checking to see if an item's value has changed before processing
* a report. If the given item does not exist in the report, the function does not modify the report item's
* data.
*
* @param ReportData Buffer containing an IN or FEATURE report from an attached device.
* \param[in,out] ReportItem Pointer to the report item of interest in a @ref HID_ReportInfo_t ReportItem array.
*
* \returns Boolean \c true if the item to retrieve was located in the given report, \c false otherwise.
*/
bool USB_GetHIDReportItemInfo(const uint8_t* ReportData,
HID_ReportItem_t* const ReportItem) ATTR_NON_NULL_PTR_ARG(1);
/** Retrieves the given report item's value out of the \c Value member of the report item's
* @ref HID_ReportItem_t structure and places it into the correct position in the HID report
* buffer. The report buffer is assumed to have the appropriate bits cleared before calling
* this function (i.e., the buffer should be explicitly cleared before report values are added).
*
* When called, this copies the report item's \c Value element to its \c PreviousValue element for easy
* checking to see if an item's value has changed before sending a report.
*
* If the device has multiple HID reports, the first byte in the report is set to the report ID of the given item.
*
* \param[out] ReportData Buffer holding the current OUT or FEATURE report data.
* @param ReportItem Pointer to the report item of interest in a @ref HID_ReportInfo_t ReportItem array.
*/
void USB_SetHIDReportItemInfo(uint8_t* ReportData,
HID_ReportItem_t* const ReportItem) ATTR_NON_NULL_PTR_ARG(1);
/** Retrieves the size of a given HID report in bytes from its Report ID.
*
* @param ParserData Pointer to a @ref HID_ReportInfo_t instance containing the parser output.
* @param ReportID Report ID of the report whose size is to be determined.
* @param ReportType Type of the report whose size is to be determined, a value from the
* @ref HID_ReportItemTypes_t enum.
*
* @return Size of the report in bytes, or \c 0 if the report does not exist.
*/
uint16_t USB_GetHIDReportSize(HID_ReportInfo_t* const ParserData,
const uint8_t ReportID,
const uint8_t ReportType) ATTR_CONST ATTR_NON_NULL_PTR_ARG(1);
/** Callback routine for the HID Report Parser. This callback <b>must</b> be implemented by the user code when
* the parser is used, to determine what report IN, OUT and FEATURE item's information is stored into the user
* @ref HID_ReportInfo_t structure. This can be used to filter only those items the application will be using, so that
* no RAM is wasted storing the attributes for report items which will never be referenced by the application.
*
* Report item pointers passed to this callback function may be cached by the user application for later use
* when processing report items. This provides faster report processing in the user application than would
* a search of the entire parsed report item table for each received or sent report.
*
* @param CurrentItem Pointer to the current report item for user checking.
*
* @return Boolean \c true if the item should be stored into the @ref HID_ReportInfo_t structure, \c false if
* it should be ignored.
*/
bool CALLBACK_HIDParser_FilterHIDReportItem(HID_ReportItem_t* const CurrentItem);
/* Private Interface - For use in library only: */
#if !defined(__DOXYGEN__)
/* Type Defines: */
typedef struct
{
HID_ReportItem_Attributes_t Attributes;
uint8_t ReportCount;
uint8_t ReportID;
} HID_StateTable_t;
#endif
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

122
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/HIDReportData.h vendored Normal file
View file

@ -0,0 +1,122 @@
/*
* @brief Constants for HID report item attributes
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_HIDParser
* @defgroup Group_HIDReportItemConst HID Report Descriptor Item Constants
*
* General HID constant definitions for HID Report Descriptor elements.
*
* @{
*/
#ifndef __HIDREPORTDATA_H__
#define __HIDREPORTDATA_H__
/* Private Interface - For use in library only: */
#if !defined(__DOXYGEN__)
/* Macros: */
#define HID_RI_DATA_SIZE_MASK 0x03
#define HID_RI_TYPE_MASK 0x0C
#define HID_RI_TAG_MASK 0xF0
#define HID_RI_TYPE_MAIN 0x00
#define HID_RI_TYPE_GLOBAL 0x04
#define HID_RI_TYPE_LOCAL 0x08
#define HID_RI_DATA_BITS_0 0x00
#define HID_RI_DATA_BITS_8 0x01
#define HID_RI_DATA_BITS_16 0x02
#define HID_RI_DATA_BITS_32 0x03
#define HID_RI_DATA_BITS(DataBits) HID_RI_DATA_BITS_ ## DataBits
#define _HID_RI_ENCODE_0(Data)
#define _HID_RI_ENCODE_8(Data) , (Data & 0xFF)
#define _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_8(Data) _HID_RI_ENCODE_8(Data >> 8)
#define _HID_RI_ENCODE_32(Data) _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_16(Data >> 16)
#define _HID_RI_ENCODE(DataBits, ...) _HID_RI_ENCODE_ ## DataBits(__VA_ARGS__)
#define _HID_RI_ENTRY(Type, Tag, DataBits, ...) \
(Type | Tag | HID_RI_DATA_BITS(DataBits)) _HID_RI_ENCODE(DataBits, (__VA_ARGS__))
#endif
/* Public Interface - May be used in end-application: */
/* Macros: */
/** @name HID Input, Output and Feature Report Descriptor Item Flags */
//@{
#define HID_IOF_CONSTANT (1 << 0)
#define HID_IOF_DATA (0 << 0)
#define HID_IOF_VARIABLE (1 << 1)
#define HID_IOF_ARRAY (0 << 1)
#define HID_IOF_RELATIVE (1 << 2)
#define HID_IOF_ABSOLUTE (0 << 2)
#define HID_IOF_WRAP (1 << 3)
#define HID_IOF_NO_WRAP (0 << 3)
#define HID_IOF_NON_LINEAR (1 << 4)
#define HID_IOF_LINEAR (0 << 4)
#define HID_IOF_NO_PREFERRED_STATE (1 << 5)
#define HID_IOF_PREFERRED_STATE (0 << 5)
#define HID_IOF_NULLSTATE (1 << 6)
#define HID_IOF_NO_NULL_POSITION (0 << 6)
#define HID_IOF_VOLATILE (1 << 7)
#define HID_IOF_NON_VOLATILE (0 << 7)
#define HID_IOF_BUFFERED_BYTES (1 << 8)
#define HID_IOF_BITFIELD (0 << 8)
//@}
/** @name HID Report Descriptor Item Macros */
//@{
#define HID_RI_INPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x80, DataBits, __VA_ARGS__)
#define HID_RI_OUTPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x90, DataBits, __VA_ARGS__)
#define HID_RI_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xA0, DataBits, __VA_ARGS__)
#define HID_RI_FEATURE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xB0, DataBits, __VA_ARGS__)
#define HID_RI_END_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xC0, DataBits, __VA_ARGS__)
#define HID_RI_USAGE_PAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x00, DataBits, __VA_ARGS__)
#define HID_RI_LOGICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x10, DataBits, __VA_ARGS__)
#define HID_RI_LOGICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x20, DataBits, __VA_ARGS__)
#define HID_RI_PHYSICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x30, DataBits, __VA_ARGS__)
#define HID_RI_PHYSICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x40, DataBits, __VA_ARGS__)
#define HID_RI_UNIT_EXPONENT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x50, DataBits, __VA_ARGS__)
#define HID_RI_UNIT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x60, DataBits, __VA_ARGS__)
#define HID_RI_REPORT_SIZE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x70, DataBits, __VA_ARGS__)
#define HID_RI_REPORT_ID(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x80, DataBits, __VA_ARGS__)
#define HID_RI_REPORT_COUNT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x90, DataBits, __VA_ARGS__)
#define HID_RI_PUSH(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xA0, DataBits, __VA_ARGS__)
#define HID_RI_POP(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xB0, DataBits, __VA_ARGS__)
#define HID_RI_USAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x00, DataBits, __VA_ARGS__)
#define HID_RI_USAGE_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x10, DataBits, __VA_ARGS__)
#define HID_RI_USAGE_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x20, DataBits, __VA_ARGS__)
//@}
/** @} */
#endif

302
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/MIDIClassCommon.h vendored Normal file
View file

@ -0,0 +1,302 @@
/*
* @brief Common definitions and declarations for the library USB MIDI Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassMIDI
* @defgroup Group_USBClassMIDICommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* MIDI Class.
*
* @{
*/
#ifndef _MIDI_CLASS_COMMON_H_
#define _MIDI_CLASS_COMMON_H_
/* Macros: */
#define __INCLUDE_FROM_AUDIO_DRIVER
/* Includes: */
#include "../../Core/StdDescriptors.h"
#include "AudioClassCommon.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_MIDI_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** @name MIDI Command Values */
//@{
/** MIDI command for a note on (activation) event. */
#define MIDI_COMMAND_NOTE_ON 0x90
/** MIDI command for a note off (deactivation) event. */
#define MIDI_COMMAND_NOTE_OFF 0x80
//@}
/** Standard key press velocity value used for all note events. */
#define MIDI_STANDARD_VELOCITY 64
/** Convenience macro. MIDI channels are numbered from 1-10 (natural numbers) however the logical channel
* addresses are zero-indexed. This converts a natural MIDI channel number into the logical channel address.
*
* @param channel MIDI channel number to address.
*/
#define MIDI_CHANNEL(channel) ((channel) - 1)
/* Enums: */
/** Enum for the possible MIDI jack types in a MIDI device jack descriptor. */
enum MIDI_JackTypes_t
{
MIDI_JACKTYPE_Embedded = 0x01, /**< MIDI class descriptor jack type value for an embedded (logical) MIDI input or output jack. */
MIDI_JACKTYPE_External = 0x02, /**< MIDI class descriptor jack type value for an external (physical) MIDI input or output jack. */
};
/* Type Defines: */
/** @brief MIDI class-specific Streaming Interface Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific MIDI streaming interface descriptor. This indicates to the host
* how MIDI the specification compliance of the device and the total length of the Audio class-specific descriptors.
* See the USB Audio specification for more details.
*
* @see @ref USB_MIDI_StdDescriptor_AudioInterface_AS_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint16_t AudioSpecification; /**< Binary coded decimal value, indicating the supported Audio Class
* specification version.
*/
uint16_t TotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */
} ATTR_PACKED USB_MIDI_Descriptor_AudioInterface_AS_t;
/** @brief MIDI class-specific Streaming Interface Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific MIDI streaming interface descriptor. This indicates to the host
* how MIDI the specification compliance of the device and the total length of the Audio class-specific descriptors.
* See the USB Audio specification for more details.
*
* @see @ref USB_MIDI_Descriptor_AudioInterface_AS_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint16_t bcdMSC; /**< Binary coded decimal value, indicating the supported MIDI Class specification version. */
uint16_t wTotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */
} ATTR_PACKED USB_MIDI_StdDescriptor_AudioInterface_AS_t;
/** @brief MIDI class-specific Input Jack Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific MIDI IN jack. This gives information to the host on a MIDI input, either
* a physical input jack, or a logical jack (receiving input data internally, or from the host via an endpoint).
*
* @see @ref USB_MIDI_StdDescriptor_InputJack_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t JackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */
uint8_t JackID; /**< ID value of this jack - must be a unique value within the device. */
uint8_t JackStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_MIDI_Descriptor_InputJack_t;
/** @brief MIDI class-specific Input Jack Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific MIDI IN jack. This gives information to the host on a MIDI input, either
* a physical input jack, or a logical jack (receiving input data internally, or from the host via an endpoint).
*
* @see @ref USB_MIDI_Descriptor_InputJack_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t bJackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */
uint8_t bJackID; /**< ID value of this jack - must be a unique value within the device. */
uint8_t iJack; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_MIDI_StdDescriptor_InputJack_t;
/** @brief MIDI class-specific Output Jack Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific MIDI OUT jack. This gives information to the host on a MIDI output, either
* a physical output jack, or a logical jack (sending output data internally, or to the host via an endpoint).
*
* @see @ref USB_MIDI_StdDescriptor_OutputJack_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t JackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */
uint8_t JackID; /**< ID value of this jack - must be a unique value within the device. */
uint8_t NumberOfPins; /**< Number of output channels within the jack, either physical or logical. */
uint8_t SourceJackID[1]; /**< ID of each output pin's source data jack. */
uint8_t SourcePinID[1]; /**< Pin number in the input jack of each output pin's source data. */
uint8_t JackStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_MIDI_Descriptor_OutputJack_t;
/** @brief MIDI class-specific Output Jack Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific MIDI OUT jack. This gives information to the host on a MIDI output, either
* a physical output jack, or a logical jack (sending output data internally, or to the host via an endpoint).
*
* @see @ref USB_MIDI_Descriptor_OutputJack_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t bJackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */
uint8_t bJackID; /**< ID value of this jack - must be a unique value within the device. */
uint8_t bNrInputPins; /**< Number of output channels within the jack, either physical or logical. */
uint8_t baSourceID[1]; /**< ID of each output pin's source data jack. */
uint8_t baSourcePin[1]; /**< Pin number in the input jack of each output pin's source data. */
uint8_t iJack; /**< Index of a string descriptor describing this descriptor within the device. */
} ATTR_PACKED USB_MIDI_StdDescriptor_OutputJack_t;
/** @brief Audio class-specific Jack Endpoint Descriptor (nxpUSBlib naming conventions).
*
* Type define for an Audio class-specific extended MIDI jack endpoint descriptor. This contains extra information
* on the usage of MIDI endpoints used to stream MIDI events in and out of the USB Audio device, and follows an Audio
* class-specific extended MIDI endpoint descriptor. See the USB Audio specification for more details.
*
* @see @ref USB_MIDI_StdDescriptor_Jack_Endpoint_t for the version of this type with standard element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */
uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t TotalEmbeddedJacks; /**< Total number of jacks inside this endpoint. */
uint8_t AssociatedJackID[1]; /**< IDs of each jack inside the endpoint. */
} ATTR_PACKED USB_MIDI_Descriptor_Jack_Endpoint_t;
/** @brief Audio class-specific Jack Endpoint Descriptor (USB-IF naming conventions).
*
* Type define for an Audio class-specific extended MIDI jack endpoint descriptor. This contains extra information
* on the usage of MIDI endpoints used to stream MIDI events in and out of the USB Audio device, and follows an Audio
* class-specific extended MIDI endpoint descriptor. See the USB Audio specification for more details.
*
* @see @ref USB_MIDI_Descriptor_Jack_Endpoint_t for the version of this type with non-standard nxpUSBlib specific
* element names.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t bLength; /**< Size of the descriptor, in bytes. */
uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value
* given by the specific class.
*/
uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */
uint8_t bNumEmbMIDIJack; /**< Total number of jacks inside this endpoint. */
uint8_t bAssocJackID[1]; /**< IDs of each jack inside the endpoint. */
} ATTR_PACKED USB_MIDI_StdDescriptor_Jack_Endpoint_t;
/** @brief MIDI Class Driver Event Packet.
*
* Type define for a USB MIDI event packet, used to encapsulate sent and received MIDI messages from a USB MIDI interface.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
unsigned Command : 4; /**< Upper nibble of the MIDI command being sent or received in the event packet. */
unsigned CableNumber : 4; /**< Virtual cable number of the event being sent or received in the given MIDI interface. */
uint8_t Data1; /**< First byte of data in the MIDI event. */
uint8_t Data2; /**< Second byte of data in the MIDI event. */
uint8_t Data3; /**< Third byte of data in the MIDI event. */
} ATTR_PACKED MIDI_EventPacket_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

358
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/MassStorageClassCommon.h vendored Normal file
View file

@ -0,0 +1,358 @@
/*
* @brief Common definitions and declarations for the library USB Mass Storage Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassMS
* @defgroup Group_USBClassMSCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* Mass Storage Class.
*
* @{
*/
#ifndef _MS_CLASS_COMMON_H_
#define _MS_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_MS_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** Magic signature for a Command Block Wrapper used in the Mass Storage Bulk-Only transport protocol. */
#define MS_CBW_SIGNATURE 0x43425355UL
/** Magic signature for a Command Status Wrapper used in the Mass Storage Bulk-Only transport protocol. */
#define MS_CSW_SIGNATURE 0x53425355UL
/** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from host-to-device. */
#define MS_COMMAND_DIR_DATA_OUT (0 << 7)
/** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from device-to-host. */
#define MS_COMMAND_DIR_DATA_IN (1 << 7)
/** @name SCSI Commands*/
//@{
/** SCSI Command Code for an INQUIRY command. */
#define SCSI_CMD_INQUIRY 0x12
/** SCSI Command Code for a REQUEST SENSE command. */
#define SCSI_CMD_REQUEST_SENSE 0x03
/** SCSI Command Code for a TEST UNIT READY command. */
#define SCSI_CMD_TEST_UNIT_READY 0x00
/** SCSI Command Code for a READ CAPACITY (10) command. */
#define SCSI_CMD_READ_CAPACITY_10 0x25
/** SCSI Command Code for a SEND DIAGNOSTIC command. */
#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D
/** SCSI Command Code for a PREVENT ALLOW MEDIUM REMOVAL command. */
#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
/** SCSI Command Code for a WRITE (10) command. */
#define SCSI_CMD_WRITE_10 0x2A
/** SCSI Command Code for a READ (10) command. */
#define SCSI_CMD_READ_10 0x28
/** SCSI Command Code for a WRITE (6) command. */
#define SCSI_CMD_WRITE_6 0x0A
/** SCSI Command Code for a READ (6) command. */
#define SCSI_CMD_READ_6 0x08
/** SCSI Command Code for a VERIFY (10) command. */
#define SCSI_CMD_VERIFY_10 0x2F
/** SCSI Command Code for a MODE SENSE (6) command. */
#define SCSI_CMD_MODE_SENSE_6 0x1A
/** SCSI Command Code for a MODE SENSE (10) command. */
#define SCSI_CMD_MODE_SENSE_10 0x5A
//@}
/** @name SCSI Sense Key Values */
//@{
/** SCSI Sense Code to indicate no error has occurred. */
#define SCSI_SENSE_KEY_GOOD 0x00
/** SCSI Sense Code to indicate that the device has recovered from an error. */
#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01
/** SCSI Sense Code to indicate that the device is not ready for a new command. */
#define SCSI_SENSE_KEY_NOT_READY 0x02
/** SCSI Sense Code to indicate an error whilst accessing the medium. */
#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03
/** SCSI Sense Code to indicate a hardware error has occurred. */
#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04
/** SCSI Sense Code to indicate that an illegal request has been issued. */
#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05
/** SCSI Sense Code to indicate that the unit requires attention from the host to indicate
* a reset event, medium removal or other condition.
*/
#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06
/** SCSI Sense Code to indicate that a write attempt on a protected block has been made. */
#define SCSI_SENSE_KEY_DATA_PROTECT 0x07
/** SCSI Sense Code to indicate an error while trying to write to a write-once medium. */
#define SCSI_SENSE_KEY_BLANK_CHECK 0x08
/** SCSI Sense Code to indicate a vendor specific error has occurred. */
#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09
/** SCSI Sense Code to indicate that an EXTENDED COPY command has aborted due to an error. */
#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A
/** SCSI Sense Code to indicate that the device has aborted the issued command. */
#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B
/** SCSI Sense Code to indicate an attempt to write past the end of a partition has been made. */
#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D
/** SCSI Sense Code to indicate that the source data did not match the data read from the medium. */
#define SCSI_SENSE_KEY_MISCOMPARE 0x0E
//@}
/** @name SCSI Additional Sense Codes */
//@{
/** SCSI Additional Sense Code to indicate no additional sense information is available. */
#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00
/** SCSI Additional Sense Code to indicate that the logical unit (LUN) addressed is not ready. */
#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04
/** SCSI Additional Sense Code to indicate an invalid field was encountered while processing the issued command. */
#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24
/** SCSI Additional Sense Code to indicate that a medium that was previously indicated as not ready has now
* become ready for use.
*/
#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28
/** SCSI Additional Sense Code to indicate that an attempt to write to a protected area was made. */
#define SCSI_ASENSE_WRITE_PROTECTED 0x27
/** SCSI Additional Sense Code to indicate an error whilst formatting the device medium. */
#define SCSI_ASENSE_FORMAT_ERROR 0x31
/** SCSI Additional Sense Code to indicate an invalid command was issued. */
#define SCSI_ASENSE_INVALID_COMMAND 0x20
/** SCSI Additional Sense Code to indicate a write to a block out outside of the medium's range was issued. */
#define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21
/** SCSI Additional Sense Code to indicate that no removable medium is inserted into the device. */
#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A
//@}
/** @name SCSI Additional Sense Key Code Qualifiers */
//@{
/** SCSI Additional Sense Qualifier Code to indicate no additional sense qualifier information is available. */
#define SCSI_ASENSEQ_NO_QUALIFIER 0x00
/** SCSI Additional Sense Qualifier Code to indicate that a medium format command failed to complete. */
#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01
/** SCSI Additional Sense Qualifier Code to indicate that an initializing command must be issued before the issued
* command can be executed.
*/
#define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02
/** SCSI Additional Sense Qualifier Code to indicate that an operation is currently in progress. */
#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07
//@}
/* Enums: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Mass
* Storage device class.
*/
enum MS_Descriptor_ClassSubclassProtocol_t
{
MS_CSCP_MassStorageClass = 0x08, /**< Descriptor Class value indicating that the device or interface
* belongs to the Mass Storage class.
*/
MS_CSCP_SCSITransparentSubclass = 0x06, /**< Descriptor Subclass value indicating that the device or interface
* belongs to the SCSI Transparent Command Set subclass of the Mass
* storage class.
*/
MS_CSCP_BulkOnlyTransportProtocol = 0x50, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the Bulk Only Transport protocol of the Mass Storage class.
*/
};
/** Enum for the Mass Storage class specific control requests that can be issued by the USB bus host. */
enum MS_ClassRequests_t
{
MS_REQ_GetMaxLUN = 0xFE, /**< Mass Storage class-specific request to retrieve the total number of Logical
* Units (drives) in the SCSI device.
*/
MS_REQ_MassStorageReset = 0xFF, /**< Mass Storage class-specific request to reset the Mass Storage interface,
* ready for the next command.
*/
};
/** Enum for the possible command status wrapper return status codes. */
enum MS_CommandStatusCodes_t
{
MS_SCSI_COMMAND_Pass = 0, /**< Command completed with no error */
MS_SCSI_COMMAND_Fail = 1, /**< Command failed to complete - host may check the exact error via a
* SCSI REQUEST SENSE command.
*/
MS_SCSI_COMMAND_PhaseError = 2, /**< Command failed due to being invalid in the current phase. */
};
/* Type Defines: */
/** @brief Mass Storage Class Command Block Wrapper.
*
* Type define for a Command Block Wrapper, used in the Mass Storage Bulk-Only Transport protocol.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t Signature; /**< Command block signature, must be @ref MS_CBW_SIGNATURE to indicate a valid Command Block. */
uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */
uint32_t DataTransferLength; /**< Length of the optional data portion of the issued command, in bytes. */
uint8_t Flags; /**< Command block flags, indicating command data direction. */
uint8_t LUN; /**< Logical Unit number this command is issued to. */
uint8_t SCSICommandLength; /**< Length of the issued SCSI command within the SCSI command data array. */
uint8_t SCSICommandData[16]; /**< Issued SCSI command in the Command Block. */
} ATTR_PACKED MS_CommandBlockWrapper_t;
/** @brief Mass Storage Class Command Status Wrapper.
*
* Type define for a Command Status Wrapper, used in the Mass Storage Bulk-Only Transport protocol.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t Signature; /**< Status block signature, must be @ref MS_CSW_SIGNATURE to indicate a valid Command Status. */
uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */
uint32_t DataTransferResidue; /**< Number of bytes of data not processed in the SCSI command. */
uint8_t Status; /**< Status code of the issued command - a value from the @ref MS_CommandStatusCodes_t enum. */
} ATTR_PACKED MS_CommandStatusWrapper_t;
/** @brief Mass Storage Class SCSI Sense Structure
*
* Type define for a SCSI Sense structure. Structures of this type are filled out by the
* device via the @ref MS_Host_RequestSense() function, indicating the current sense data of the
* device (giving explicit error codes for the last issued command). For details of the
* structure contents, refer to the SCSI specifications.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t ResponseCode;
uint8_t SegmentNumber;
unsigned SenseKey : 4;
unsigned Reserved : 1;
unsigned ILI : 1;
unsigned EOM : 1;
unsigned FileMark : 1;
uint8_t Information[4];
uint8_t AdditionalLength;
uint8_t CmdSpecificInformation[4];
uint8_t AdditionalSenseCode;
uint8_t AdditionalSenseQualifier;
uint8_t FieldReplaceableUnitCode;
uint8_t SenseKeySpecific[3];
} ATTR_PACKED SCSI_Request_Sense_Response_t;
/** @brief Mass Storage Class SCSI Inquiry Structure.
*
* Type define for a SCSI Inquiry structure. Structures of this type are filled out by the
* device via the @ref MS_Host_GetInquiryData() function, retrieving the attached device's
* information.
*
* For details of the structure contents, refer to the SCSI specifications.
*/
typedef ATTR_IAR_PACKED struct
{
unsigned DeviceType : 5;
unsigned PeripheralQualifier : 3;
unsigned Reserved : 7;
unsigned Removable : 1;
uint8_t Version;
unsigned ResponseDataFormat : 4;
unsigned Reserved2 : 1;
unsigned NormACA : 1;
unsigned TrmTsk : 1;
unsigned AERC : 1;
uint8_t AdditionalLength;
uint8_t Reserved3[2];
unsigned SoftReset : 1;
unsigned CmdQue : 1;
unsigned Reserved4 : 1;
unsigned Linked : 1;
unsigned Sync : 1;
unsigned WideBus16Bit : 1;
unsigned WideBus32Bit : 1;
unsigned RelAddr : 1;
uint8_t VendorID[8];
uint8_t ProductID[16];
uint8_t RevisionID[4];
} ATTR_PACKED SCSI_Inquiry_Response_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

112
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/PrinterClassCommon.h vendored Normal file
View file

@ -0,0 +1,112 @@
/*
* @brief Common definitions and declarations for the library USB Printer Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassPrinter
* @defgroup Group_USBClassPrinterCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* Printer Class.
*
* @{
*/
#ifndef _PRINTER_CLASS_COMMON_H_
#define _PRINTER_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_PRINTER_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** @name Virtual Printer Status Line Masks */
//@{
/** Port status mask for a printer device, indicating that an error has *not* occurred. */
#define PRNT_PORTSTATUS_NOTERROR (1 << 3)
/** Port status mask for a printer device, indicating that the device is currently selected. */
#define PRNT_PORTSTATUS_SELECT (1 << 4)
/** Port status mask for a printer device, indicating that the device is currently out of paper. */
#define PRNT_PORTSTATUS_PAPEREMPTY (1 << 5)
//@}
/* Enums: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Printer
* device class.
*/
enum PRNT_Descriptor_ClassSubclassProtocol_t
{
PRNT_CSCP_PrinterClass = 0x07, /**< Descriptor Class value indicating that the device or interface
* belongs to the Printer class.
*/
PRNT_CSCP_PrinterSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface
* belongs to the Printer subclass.
*/
PRNT_CSCP_BidirectionalProtocol = 0x02, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the Bidirectional protocol of the Printer class.
*/
};
/** Enum for the Printer class specific control requests that can be issued by the USB bus host. */
enum PRNT_ClassRequests_t
{
PRNT_REQ_GetDeviceID = 0x00, /**< Printer class-specific request to retrieve the Unicode ID
* string of the device, containing the device's name, manufacturer
* and supported printer languages.
*/
PRNT_REQ_GetPortStatus = 0x01, /**< Printer class-specific request to get the current status of the
* virtual printer port, for device selection and ready states.
*/
PRNT_REQ_SoftReset = 0x02, /**< Printer class-specific request to reset the device, ready for new
* printer commands.
*/
};
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

404
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/RNDISClassCommon.h vendored Normal file
View file

@ -0,0 +1,404 @@
/*
* @brief Common definitions and declarations for the library USB RNDIS Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassRNDIS
* @defgroup Group_USBClassRNDISCommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* RNDIS Class.
*
* @{
*/
#ifndef _RNDIS_CLASS_COMMON_H_
#define _RNDIS_CLASS_COMMON_H_
/* Macros: */
#define __INCLUDE_FROM_CDC_DRIVER
/* Includes: */
#include "../../Core/StdDescriptors.h"
#include "CDCClassCommon.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_RNDIS_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** Additional error code for RNDIS functions when a device returns a logical command failure. */
#define RNDIS_ERROR_LOGICAL_CMD_FAILED 0x80
/** Implemented RNDIS Version Major. */
#define REMOTE_NDIS_VERSION_MAJOR 0x01
/** Implemented RNDIS Version Minor. */
#define REMOTE_NDIS_VERSION_MINOR 0x00
/** @name RNDIS Message Values */
//@{
#define REMOTE_NDIS_PACKET_MSG 0x00000001UL
#define REMOTE_NDIS_INITIALIZE_MSG 0x00000002UL
#define REMOTE_NDIS_HALT_MSG 0x00000003UL
#define REMOTE_NDIS_QUERY_MSG 0x00000004UL
#define REMOTE_NDIS_SET_MSG 0x00000005UL
#define REMOTE_NDIS_RESET_MSG 0x00000006UL
#define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007UL
#define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008UL
//@}
/** @name RNDIS Response Values */
//@{
#define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002UL
#define REMOTE_NDIS_QUERY_CMPLT 0x80000004UL
#define REMOTE_NDIS_SET_CMPLT 0x80000005UL
#define REMOTE_NDIS_RESET_CMPLT 0x80000006UL
#define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008UL
//@}
/** @name RNDIS Status Values */
//@{
#define REMOTE_NDIS_STATUS_SUCCESS 0x00000000UL
#define REMOTE_NDIS_STATUS_FAILURE 0xC0000001UL
#define REMOTE_NDIS_STATUS_INVALID_DATA 0xC0010015UL
#define REMOTE_NDIS_STATUS_NOT_SUPPORTED 0xC00000BBUL
#define REMOTE_NDIS_STATUS_MEDIA_CONNECT 0x4001000BUL
#define REMOTE_NDIS_STATUS_MEDIA_DISCONNECT 0x4001000CUL
//@}
/** @name RNDIS Media States */
//@{
#define REMOTE_NDIS_MEDIA_STATE_CONNECTED 0x00000000UL
#define REMOTE_NDIS_MEDIA_STATE_DISCONNECTED 0x00000001UL
//@}
#define REMOTE_NDIS_MEDIUM_802_3 0x00000000UL
/** @name RNDIS Connection Types */
//@{
#define REMOTE_NDIS_DF_CONNECTIONLESS 0x00000001UL
#define REMOTE_NDIS_DF_CONNECTION_ORIENTED 0x00000002UL
//@}
/** @name RNDIS Packet Types */
//@{
#define REMOTE_NDIS_PACKET_DIRECTED 0x00000001UL
#define REMOTE_NDIS_PACKET_MULTICAST 0x00000002UL
#define REMOTE_NDIS_PACKET_ALL_MULTICAST 0x00000004UL
#define REMOTE_NDIS_PACKET_BROADCAST 0x00000008UL
#define REMOTE_NDIS_PACKET_SOURCE_ROUTING 0x00000010UL
#define REMOTE_NDIS_PACKET_PROMISCUOUS 0x00000020UL
#define REMOTE_NDIS_PACKET_SMT 0x00000040UL
#define REMOTE_NDIS_PACKET_ALL_LOCAL 0x00000080UL
#define REMOTE_NDIS_PACKET_GROUP 0x00001000UL
#define REMOTE_NDIS_PACKET_ALL_FUNCTIONAL 0x00002000UL
#define REMOTE_NDIS_PACKET_FUNCTIONAL 0x00004000UL
#define REMOTE_NDIS_PACKET_MAC_FRAME 0x00008000UL
//@}
/** @name RNDIS OID Values */
//@{
#define OID_GEN_SUPPORTED_LIST 0x00010101UL
#define OID_GEN_HARDWARE_STATUS 0x00010102UL
#define OID_GEN_MEDIA_SUPPORTED 0x00010103UL
#define OID_GEN_MEDIA_IN_USE 0x00010104UL
#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106UL
#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111UL
#define OID_GEN_LINK_SPEED 0x00010107UL
#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010AUL
#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010BUL
#define OID_GEN_VENDOR_ID 0x0001010CUL
#define OID_GEN_VENDOR_DESCRIPTION 0x0001010DUL
#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010EUL
#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111UL
#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114UL
#define OID_GEN_PHYSICAL_MEDIUM 0x00010202UL
#define OID_GEN_XMIT_OK 0x00020101UL
#define OID_GEN_RCV_OK 0x00020102UL
#define OID_GEN_XMIT_ERROR 0x00020103UL
#define OID_GEN_RCV_ERROR 0x00020104UL
#define OID_GEN_RCV_NO_BUFFER 0x00020105UL
#define OID_802_3_PERMANENT_ADDRESS 0x01010101UL
#define OID_802_3_CURRENT_ADDRESS 0x01010102UL
#define OID_802_3_MULTICAST_LIST 0x01010103UL
#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104UL
#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101UL
#define OID_802_3_XMIT_ONE_COLLISION 0x01020102UL
#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103UL
//@}
/** Maximum size in bytes of a RNDIS control message which can be sent or received. */
#define RNDIS_MESSAGE_BUFFER_SIZE 128
/** Maximum size in bytes of an Ethernet frame according to the Ethernet standard. */
#define ETHERNET_FRAME_SIZE_MAX 1500
/* Enums: */
/** Enum for the RNDIS class specific control requests that can be issued by the USB bus host. */
enum RNDIS_ClassRequests_t
{
RNDIS_REQ_SendEncapsulatedCommand = 0x00, /**< RNDIS request to issue a host-to-device NDIS command. */
RNDIS_REQ_GetEncapsulatedResponse = 0x01, /**< RNDIS request to issue a device-to-host NDIS response. */
};
/** Enum for the possible NDIS adapter states. */
enum RNDIS_States_t
{
RNDIS_Uninitialized = 0, /**< Adapter currently uninitialized. */
RNDIS_Initialized = 1, /**< Adapter currently initialized but not ready for data transfers. */
RNDIS_Data_Initialized = 2, /**< Adapter currently initialized and ready for data transfers. */
};
/** Enum for the RNDIS class specific notification requests that can be issued by a RNDIS device to a host. */
enum RNDIS_ClassNotifications_t
{
RNDIS_NOTIF_ResponseAvailable = 0x01, /**< Notification request value for a RNDIS Response Available notification. */
};
/** Enum for the NDIS hardware states. */
enum NDIS_Hardware_Status_t
{
NDIS_HardwareStatus_Ready, /**< Hardware Ready to accept commands from the host. */
NDIS_HardwareStatus_Initializing, /**< Hardware busy initializing. */
NDIS_HardwareStatus_Reset, /**< Hardware reset. */
NDIS_HardwareStatus_Closing, /**< Hardware currently closing. */
NDIS_HardwareStatus_NotReady /**< Hardware not ready to accept commands from the host. */
};
/* Type Defines: */
/** @brief MAC Address Structure.
*
* Type define for a physical MAC address of a device on a network.
*/
typedef ATTR_IAR_PACKED struct
{
uint8_t Octets[6]; /**< Individual bytes of a MAC address */
} ATTR_PACKED MAC_Address_t;
/** @brief RNDIS Common Message Header Structure.
*
* Type define for a RNDIS message header, sent before RNDIS messages.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType; /**< RNDIS message type, a \c REMOTE_NDIS_*_MSG constant */
uint32_t MessageLength; /**< Total length of the RNDIS message, in bytes */
} ATTR_PACKED RNDIS_Message_Header_t;
/** @brief RNDIS Message Structure.
*
* Type define for a RNDIS packet message, used to encapsulate Ethernet packets sent to and from the adapter.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t DataOffset;
uint32_t DataLength;
uint32_t OOBDataOffset;
uint32_t OOBDataLength;
uint32_t NumOOBDataElements;
uint32_t PerPacketInfoOffset;
uint32_t PerPacketInfoLength;
uint32_t VcHandle;
uint32_t Reserved;
} ATTR_PACKED RNDIS_Packet_Message_t;
/** @brief RNDIS Initialization Message Structure.
*
* Type define for a RNDIS Initialize command message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t MajorVersion;
uint32_t MinorVersion;
uint32_t MaxTransferSize;
} ATTR_PACKED RNDIS_Initialize_Message_t;
/** @brief RNDIS Initialize Complete Message Structure.
*
* Type define for a RNDIS Initialize Complete response message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Status;
uint32_t MajorVersion;
uint32_t MinorVersion;
uint32_t DeviceFlags;
uint32_t Medium;
uint32_t MaxPacketsPerTransfer;
uint32_t MaxTransferSize;
uint32_t PacketAlignmentFactor;
uint32_t AFListOffset;
uint32_t AFListSize;
} ATTR_PACKED RNDIS_Initialize_Complete_t;
/** @brief RNDIS Keep Alive Message Structure.
*
* Type define for a RNDIS Keep Alive command message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
} ATTR_PACKED RNDIS_KeepAlive_Message_t;
/** @brief RNDIS Keep Alive Complete Message Structure.
*
* Type define for a RNDIS Keep Alive Complete response message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Status;
} ATTR_PACKED RNDIS_KeepAlive_Complete_t;
/** @brief RNDIS Reset Complete Message Structure.
*
* Type define for a RNDIS Reset Complete response message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t Status;
uint32_t AddressingReset;
} ATTR_PACKED RNDIS_Reset_Complete_t;
/** @brief RNDIS OID Property Set Message Structure.
*
* Type define for a RNDIS OID Property Set command message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Oid;
uint32_t InformationBufferLength;
uint32_t InformationBufferOffset;
uint32_t DeviceVcHandle;
} ATTR_PACKED RNDIS_Set_Message_t;
/** @brief RNDIS OID Property Set Complete Message Structure.
*
* Type define for a RNDIS OID Property Set Complete response message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Status;
} ATTR_PACKED RNDIS_Set_Complete_t;
/** @brief RNDIS OID Property Query Message Structure.
*
* Type define for a RNDIS OID Property Query command message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Oid;
uint32_t InformationBufferLength;
uint32_t InformationBufferOffset;
uint32_t DeviceVcHandle;
} ATTR_PACKED RNDIS_Query_Message_t;
/** @brief RNDIS OID Property Query Complete Message Structure.
*
* Type define for a RNDIS OID Property Query Complete response message.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef ATTR_IAR_PACKED struct
{
uint32_t MessageType;
uint32_t MessageLength;
uint32_t RequestId;
uint32_t Status;
uint32_t InformationBufferLength;
uint32_t InformationBufferOffset;
} ATTR_PACKED RNDIS_Query_Complete_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

154
FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB/Class/Common/StillImageClassCommon.h vendored Normal file
View file

@ -0,0 +1,154 @@
/*
* @brief Common definitions and declarations for the library USB Still Image Class driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* Copyright(C) Dean Camera, 2011, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
/** @ingroup Group_USBClassSI
* @defgroup Group_USBClassSICommon Common Class Definitions
*
* @section Sec_ModDescription Module Description
* Constants, Types and Enum definitions that are common to both Device and Host modes for the USB
* Still Image Class.
*
* @{
*/
#ifndef _SI_CLASS_COMMON_H_
#define _SI_CLASS_COMMON_H_
/* Includes: */
#include "../../Core/StdDescriptors.h"
/* Enable C linkage for C++ Compilers: */
#if defined(__cplusplus)
extern "C" {
#endif
/* Preprocessor Checks: */
#if !defined(__INCLUDE_FROM_SI_DRIVER)
#error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.
#endif
/* Macros: */
/** Length in bytes of a given Unicode string's character length.
*
* @param Chars Total number of Unicode characters in the string.
*
* @return Number of bytes of the given unicode string.
*/
#define UNICODE_STRING_LENGTH(Chars) ((Chars) << 1)
/** Used in the DataLength field of a PIMA container, to give the total container size in bytes for
* a command container.
*
* @param Params Number of parameters which are to be sent in the \c Param field of the container.
*/
#define PIMA_COMMAND_SIZE(Params) ((sizeof(PIMA_Container_t) - 12) + ((Params) * sizeof(uint32_t)))
/** Used in the DataLength field of a PIMA container, to give the total container size in bytes for
* a data container.
*
* @param DataLen Length in bytes of the data in the container.
*/
#define PIMA_DATA_SIZE(DataLen) ((sizeof(PIMA_Container_t) - 12) + (DataLen))
/* Enums: */
/** Enum for the possible PIMA contains types. */
enum PIMA_Container_Types_t
{
PIMA_CONTAINER_Undefined = 0, /**< Undefined container type. */
PIMA_CONTAINER_CommandBlock = 1, /**< Command Block container type. */
PIMA_CONTAINER_DataBlock = 2, /**< Data Block container type. */
PIMA_CONTAINER_ResponseBlock = 3, /**< Response container type. */
PIMA_CONTAINER_EventBlock = 4, /**< Event Block container type. */
};
/* Enums: */
/** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the
* Still Image device class.
*/
enum SI_Descriptor_ClassSubclassProtocol_t
{
SI_CSCP_StillImageClass = 0x06, /**< Descriptor Class value indicating that the device or interface
* belongs to the Still Image class.
*/
SI_CSCP_StillImageSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface
* belongs to the Still Image subclass.
*/
SI_CSCP_BulkOnlyProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface
* belongs to the Bulk Only Transport protocol of the Still Image class.
*/
};
/** Enums for the possible status codes of a returned Response Block from an attached PIMA compliant Still Image device. */
enum PIMA_ResponseCodes_t
{
PIMA_RESPONSE_OK = 1, /**< Response code indicating no error in the issued command. */
PIMA_RESPONSE_GeneralError = 2, /**< Response code indicating a general error while processing the
* issued command.
*/
PIMA_RESPONSE_SessionNotOpen = 3, /**< Response code indicating that the sent command requires an open
* session before being issued.
*/
PIMA_RESPONSE_InvalidTransaction = 4, /**< Response code indicating an invalid transaction occurred. */
PIMA_RESPONSE_OperationNotSupported = 5, /**< Response code indicating that the issued command is not supported
* by the attached device.
*/
PIMA_RESPONSE_ParameterNotSupported = 6, /**< Response code indicating that one or more of the issued command's
* parameters are not supported by the device.
*/
};
/* Type Defines: */
/** @brief PIMA Still Image Device Command/Response Container.
*
* Type define for a PIMA container, use to send commands and receive responses to and from an
* attached Still Image device.
*
* @note Regardless of CPU architecture, these values should be stored as little endian.
*/
typedef struct
{
uint32_t DataLength; /**< Length of the container and data, in bytes. */
uint16_t Type; /**< Container type, a value from the @ref PIMA_Container_Types_t enum. */
uint16_t Code; /**< Command, event or response code of the container. */
uint32_t TransactionID; /**< Unique container ID to link blocks together. */
uint32_t Params[3]; /**< Block parameters to be issued along with the block code (command blocks only). */
} ATTR_PACKED PIMA_Container_t;
/* Disable C linkage for C++ Compilers: */
#if defined(__cplusplus)
}
#endif
#endif
/** @} */

Some files were not shown because too many files have changed in this diff Show more