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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-02 20:33:49 -04:00
Update demo projects for RX210, not yet complete, and not yet actually built.
This commit is contained in:
Richard Barry
parent
4883a72844
commit
5441cb959b
13 changed files with 300 additions and 382 deletions
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@ -41,8 +41,7 @@ Includes <System Includes> , "Project Includes"
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******************************************************************************/
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#include <stdint.h>
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#include "iodefine.h"
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//#include "r_ether.h"
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#include "rskrx62ndef.h"
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#include "rskrx210def.h"
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#include "hd44780.h" /* EZ-LCD include file */
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/******************************************************************************
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@ -101,7 +100,6 @@ void HardwareSetup(void)
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void EnablePeripheralModules(void)
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{
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/* Module standby clear */
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// SYSTEM.MSTPCRB.BIT.MSTPB15 = 0; /* EtherC, EDMAC */
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SYSTEM.MSTPCRA.BIT.MSTPA15 = 0; /* CMT0 */
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}
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@ -119,65 +117,6 @@ state changes on the external ports.
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Many peripheral modules will override the setting of the port registers. Ensure
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that the state is safe for external devices if the internal peripheral module is
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disabled or powered down. */
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#if(0)
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/* ==== MII/RMII Pins setting ==== */
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/*--------------------------------------*/
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/* Port Function Control Register */
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/*--------------------------------------*/
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#if ETH_MODE_SEL == ETH_MII_MODE
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/* EE=1, PHYMODE=1, ENETE3=1, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */
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IOPORT.PFENET.BYTE = 0x9A;
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#endif /* ETH_MODE_SEL */
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#if ETH_MODE_SEL == ETH_RMII_MODE
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/* EE=1, PHYMODE=0, ENETE3=0, ENETE2=0, ENETE1=1, ENETE0=0 (Ethernet) */
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IOPORT.PFENET.BYTE = 0x82;
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#endif /* ETH_MODE_SEL */
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/*-------------------------------------------*/
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/* Input Buffer Control Register (ICR) */
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/*-------------------------------------------*/
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#if ETH_MODE_SEL == ETH_MII_MODE
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/* P54=1 Set ET_LINKSTA input */
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PORT5.ICR.BIT.B4 = 1;
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/* P71=1 Set ET_MDIO input */
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PORT7.ICR.BIT.B1 = 1;
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/* P74=1 Set ET_ERXD1 input */
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PORT7.ICR.BIT.B4 = 1;
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/* P75=1 Set ET_ERXD0 input */
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PORT7.ICR.BIT.B5 = 1;
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/* P76=1 Set ET_RX_CLK input */
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PORT7.ICR.BIT.B6 = 1;
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/* P77=1 Set ET_RX_ER input */
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PORT7.ICR.BIT.B7 = 1;
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/* P83=1 Set ET_CRS input */
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PORT8.ICR.BIT.B3 = 1;
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/* PC0=1 Set ET_ERXD3 input */
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PORTC.ICR.BIT.B0 = 1;
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/* PC1=1 Set ET_ERXD2 input */
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PORTC.ICR.BIT.B1 = 1;
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/* PC2=1 Set ET_RX_DV input */
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PORTC.ICR.BIT.B2 = 1;
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/* PC4=1 Set EX_TX_CLK input */
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PORTC.ICR.BIT.B4 = 1;
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/* PC7=1 Set ET_COL input */
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PORTC.ICR.BIT.B7 = 1;
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#endif /* ETH_MODE_SEL */
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#if ETH_MODE_SEL == ETH_RMII_MODE
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/* P54=1 Set ET_LINKSTA input */
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PORT5.ICR.BIT.B4 = 1;
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/* P71=1 Set ET_MDIO input */
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PORT7.ICR.BIT.B1 = 1;
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/* P74=1 Set RMII_RXD1 input */
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PORT7.ICR.BIT.B4 = 1;
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/* P75=1 Set RMII_RXD0 input */
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PORT7.ICR.BIT.B5 = 1;
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/* P76=1 Set REF50CLK input */
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PORT7.ICR.BIT.B6 = 1;
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/* P77=1 Set RMII_RX_ER input */
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PORT7.ICR.BIT.B7 = 1;
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/* P83=1 Set RMII_CRS_DV input */
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PORT8.ICR.BIT.B3 = 1;
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#endif /* ETH_MODE_SEL */
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#endif
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/* Configure LED 0-4 pin settings */
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PORT1.PODR.BIT.B4 = 1;
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PORT1.PODR.BIT.B5 = 1;
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@ -215,50 +154,64 @@ void io_set_cpg(void)
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changes to the debugger and flash kernel BRR settings. */
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/* ==== CPG setting ==== */
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// SYSTEM.SCKCR.LONG = 0x00020100; /* Clockin = 12MHz */
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// /* I Clock = 96MHz, B Clock = 24MHz, */
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// /* P Clock = 48MHz */
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unsigned int i;
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SYSTEM.PRCR.WORD = 0xA503; /* Protect on */
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SYSTEM.PRCR.WORD = 0xA503; /* Protect off */
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// SYSTEM.SOSCCR.BYTE = 0x01; /* stop sub-clock */
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/* delete when you use sub-clock */
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// SYSTEM.HOCOPCR.BYTE = 0x01; /* HOCO power supply off */
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/* delete when you use HOCO */
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#if (CLK_SRC_HOCO == 1)
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SYSTEM.HOCOPCR.BYTE = 0x00; /* HOCO power supply on */
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SYSTEM.HOCOCR2.BYTE = 0x03; /* Select - 50MHz */
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SYSTEM.HOCOCR.BYTE = 0x01; /* HOCO is operating */
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SYSTEM.MOSCWTCR.BYTE = 0x0D; /* 131072 state */
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/* wait over 10ms @12.5MHz */
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for(i=0; i<10; i++){ /* wait over 60us */
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}
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#else
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SYSTEM.MOSCWTCR.BYTE = 0x0C; /* Main Clock Oscillator Wait Control Register */
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/* 65536 states */
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/* wait over 2 ms @20MHz */
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SYSTEM.PLLWTCR.BYTE = 0x0E; /* 2097152 state */
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/* wait over 12ms @PLL=100MHz(12.5MHz*8) */
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SYSTEM.PLLWTCR.BYTE = 0x0B; /* PLL Wait Control Register */
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/* 262144 states */
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/* wait over 2.1 ms @PLL = 80Hz */
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/* (20/2x8*8) */
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// SYSTEM.PLLCR.WORD = 0x0902; /* x10 @PLL */
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/* Input to PLL (EXTAL in) / 2 */
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SYSTEM.PLLCR.WORD = 0x0701; /* x8 @PLL */
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/* Input to PLL (EXTAL in) / 2 */
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/* Therefore:
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PLL = EXTAL / 2
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= 20M / 2
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= 10MHz
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PLL * 8 = 80Mhz */
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// SYSTEM.MOSCCR.BYTE = 0x02; /* EXTAL ON */
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SYSTEM.MOSCCR.BYTE = 0x02; /* EXTAL ON */
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/* External oscillation input selection */
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// SYSTEM.PLLCR2.BYTE = 0x00; /* PLL ON */
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SYSTEM.PLLCR2.BYTE = 0x00; /* PLL ON */
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// for(i = 0;i< 0x168;i++) /* wait over 12ms */
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// {
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// }
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for(i = 0; i<263; i++){ /* wait over 2.1ms */
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}
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#endif
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// SYSTEM.SCKCR.LONG = 0x21022222; /* ICK=PLL/2,FCK,PCK,BCL=PLL/4 */
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// SYSTEM.SCKCR3.WORD = 0x0400; /* LOCO -> PLL */
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// SYSTEM.SCKCR.LONG = 0x21823333; /* ICK=PLL/2,FCK,PCK,BCL=PLL/4 */
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/************************************************************************/
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/* If setting bits individually, rather than a single long write, */
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/* set the BCK value before that of ICK */
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/************************************************************************/
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SYSTEM.SCKCR.BIT.PCKD = 3; /* PLL/8 = 10MHz */
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SYSTEM.SCKCR.BIT.PCKC = 3; /* PLL/8 = 10MHz */
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SYSTEM.SCKCR.BIT.PCKB = 3; /* PLL/8 = 10MHz */
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SYSTEM.SCKCR.BIT.PCKA = 3; /* PLL/8 = 10MHz */
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SYSTEM.SCKCR.BIT.BCK = 3; /* PLL/8 = 10MHz */
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SYSTEM.SCKCR.BIT.PSTOP1 = 1; /* BUS CLK OUT Disabled */
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SYSTEM.SCKCR.BIT.ICK = 1; /* PLL/2 = 40MHz */
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SYSTEM.SCKCR.BIT.FCK = 2; /* PLL/4 = 20MHz */
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/*************************************************************************/
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/* Using HOCO set to 50MHz to run device */
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/* ICLK = 50MHz */
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/* PCLKD (12ADC) = 50MHz */
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/* All other clocks = CLK / 2 = 25MHz */
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/*************************************************************************/
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SYSTEM.HOCOCR2.BYTE = 0x03; /* 50MHz */
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SYSTEM.SCKCR.LONG = 0x10811110;
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SYSTEM.SCKCR3.WORD = 0x0100; /* LOCO -> HOCO */
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while(SYSTEM.OPCCR.BIT.OPCMTSF == 1);
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SYSTEM.OPCCR.BIT.OLPCM = 0;
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while(SYSTEM.OPCCR.BIT.OPCMTSF == 1);
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#if (CLK_SRC_HOCO == 1)
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SYSTEM.SCKCR3.WORD = 0x0100; /* LOCO -> HOCO */
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#else
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SYSTEM.SCKCR3.WORD = 0x0400; /* LOCO -> PLL */
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#endif
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}
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