mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Add M7/M4 AMP demo.
This commit is contained in:
Richard Barry
parent
0b1a025789
commit
53cb12e389
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/*
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* FreeRTOS Kernel V10.0.1
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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/* Ensure stdint is only used by the compiler, and not the assembler. */
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#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
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#include <stdint.h>
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extern uint32_t SystemD2Clock;
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void vGenerateM4ToM7Interrupt( void * xUpdatedMessageBuffer );
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#endif
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ ( SystemD2Clock )
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#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
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#define configMAX_PRIORITIES ( 7 )
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#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configQUEUE_REGISTRY_SIZE 8
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#define configCHECK_FOR_STACK_OVERFLOW 0
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#define configUSE_RECURSIVE_MUTEXES 1
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#define configUSE_MALLOC_FAILED_HOOK 0
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#define configUSE_APPLICATION_TASK_TAG 0
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configGENERATE_RUN_TIME_STATS 0
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Software timer definitions. */
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#define configUSE_TIMERS 0
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#define configTIMER_TASK_PRIORITY ( 2 )
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#define configTIMER_QUEUE_LENGTH 10
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#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 1
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_xQueueGetMutexHolder 1
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#define INCLUDE_xTaskGetSchedulerState 1
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#define INCLUDE_eTaskGetState 1
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/* Cortex-M specific definitions. */
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#ifdef __NVIC_PRIO_BITS
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/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#else
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#define configPRIO_BITS 4 /* 15 priority levels */
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#endif
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/* The lowest interrupt priority that can be used in a call to a "set priority"
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function. */
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
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/* The highest interrupt priority that can be used by any interrupt service
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routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
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INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
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PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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/* Normal assert() semantics without relying on the provision of an assert.h
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header file. */
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#ifndef __IASMARM__
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void vAssertCalled( const char *pcFile, const uint32_t ulLine );
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#endif /* __IASMARM__ */
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#define configASSERT( x ) if( ( x ) == 0 ) { vAssertCalled( __FILE__, __LINE__ ); }
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/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
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standard names. */
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#define vPortSVCHandler SVC_Handler
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#define xPortPendSVHandler PendSV_Handler
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#define xPortSysTickHandler SysTick_Handler
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/* Override the default implementation of sbRECEIVE_COMPLETED so the macro
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creates an interrupt in the M7 core. See the comments at the top of main.c. */
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#define sbRECEIVE_COMPLETED( pxStreamBuffer ) vGenerateM4ToM7Interrupt( pxStreamBuffer )
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#endif /* FREERTOS_CONFIG_H */
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@ -0,0 +1,422 @@
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/**
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******************************************************************************
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* @file FreeRTOS/FreeRTOS_HwSemaphoreCoreSync/CM4/Inc/stm32h7xx_hal_conf.h
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* @author MCD Application Team
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* @brief HAL configuration file for Cortex-M4.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32H7xx_HAL_CONF_H
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#define __STM32H7xx_HAL_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* ########################## Module Selection ############################## */
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/**
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* @brief This is the list of modules to be used in the HAL driver
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*/
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#define HAL_MODULE_ENABLED
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#define HAL_ADC_MODULE_ENABLED
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/* #define HAL_CEC_MODULE_ENABLED */
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/* #define HAL_COMP_MODULE_ENABLED */
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#define HAL_CORTEX_MODULE_ENABLED
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/* #define HAL_CRC_MODULE_ENABLED */
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/* #define HAL_CRYP_MODULE_ENABLED */
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/* #define HAL_DAC_MODULE_ENABLED */
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/* #define HAL_DCMI_MODULE_ENABLED */
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/* #define HAL_DFSDM_MODULE_ENABLED */
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#define HAL_DMA_MODULE_ENABLED
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/* #define HAL_DMA2D_MODULE_ENABLED */
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/* #define HAL_ETH_MODULE_ENABLED */
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/* #define HAL_EXTI_MODULE_ENABLED */
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/* #define HAL_FDCAN_MODULE_ENABLED */
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#define HAL_FLASH_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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/* #define HAL_HASH_MODULE_ENABLED */
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/* #define HAL_HCD_MODULE_ENABLED */
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/* #define HAL_HRTIM_MODULE_ENABLED */
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#define HAL_HSEM_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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/* #define HAL_I2S_MODULE_ENABLED */
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/* #define HAL_IRDA_MODULE_ENABLED */
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/* #define HAL_IWDG_MODULE_ENABLED */
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/* #define HAL_JPEG_MODULE_ENABLED */
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/* #define HAL_LPTIM_MODULE_ENABLED */
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/* #define HAL_LTDC_MODULE_ENABLED */
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/* #define HAL_MDIOS_MODULE_ENABLED */
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/* #define HAL_MDMA_MODULE_ENABLED */
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/* #define HAL_MMC_MODULE_ENABLED */
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/* #define HAL_NAND_MODULE_ENABLED */
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/* #define HAL_NOR_MODULE_ENABLED */
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/* #define HAL_OPAMP_MODULE_ENABLED */
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/* #define HAL_PCD_MODULE_ENABLED */
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#define HAL_PWR_MODULE_ENABLED
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/* #define HAL_QSPI_MODULE_ENABLED */
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/* #define HAL_RAMECC_MODULE_ENABLED */
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#define HAL_RCC_MODULE_ENABLED
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/* #define HAL_RNG_MODULE_ENABLED */
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/* #define HAL_RTC_MODULE_ENABLED */
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/* #define HAL_SAI_MODULE_ENABLED */
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/* #define HAL_SD_MODULE_ENABLED */
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/* #define HAL_SDRAM_MODULE_ENABLED */
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/* #define HAL_SMARTCARD_MODULE_ENABLED */
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/* #define HAL_SMBUS_MODULE_ENABLED */
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/* #define HAL_SPDIFRX_MODULE_ENABLED */
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/* #define HAL_SPI_MODULE_ENABLED */
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/* #define HAL_SRAM_MODULE_ENABLED */
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/* #define HAL_SWPMI_MODULE_ENABLED */
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/* #define HAL_TIM_MODULE_ENABLED */
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#define HAL_UART_MODULE_ENABLED
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/* #define HAL_USART_MODULE_ENABLED */
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/* #define HAL_WWDG_MODULE_ENABLED */
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/* ########################## Oscillator Values adaptation ####################*/
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
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* This value is used by the RCC HAL module to compute the system frequency
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
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#endif /* HSE_STARTUP_TIMEOUT */
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/**
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* @brief Internal oscillator (CSI) default value.
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* This value is the default CSI value after Reset.
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*/
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#if !defined (CSI_VALUE)
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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/**
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* @brief Internal High Speed oscillator (HSI) value.
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* This value is used by the RCC HAL module to compute the system frequency
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* (when HSI is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief External Low Speed oscillator (LSE) value.
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* This value is used by the UART, RTC HAL module to compute the system frequency
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*/
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#if !defined (LSE_VALUE)
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#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
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#endif /* LSE_VALUE */
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#if !defined (LSE_STARTUP_TIMEOUT)
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#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
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#endif /* LSE_STARTUP_TIMEOUT */
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#if !defined (LSI_VALUE)
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#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
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The real value may vary depending on the variations
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in voltage and temperature.*/
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/**
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* @brief External clock source for I2S peripheral
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* This value is used by the I2S HAL module to compute the I2S clock source
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* frequency, this source is inserted directly through I2S_CKIN pad.
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*/
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#if !defined (EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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=== you can define the HSE value in your toolchain compiler preprocessor. */
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/* ########################### System Configuration ######################### */
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/**
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* @brief This is the HAL system configuration section
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*/
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#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
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#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
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#define USE_RTOS 0
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#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
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/* ########################### Ethernet Configuration ######################### */
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#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
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#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
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#define ETH_MAC_ADDR0 ((uint8_t)0x02)
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#define ETH_MAC_ADDR1 ((uint8_t)0x00)
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#define ETH_MAC_ADDR2 ((uint8_t)0x00)
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#define ETH_MAC_ADDR3 ((uint8_t)0x00)
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#define ETH_MAC_ADDR4 ((uint8_t)0x00)
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#define ETH_MAC_ADDR5 ((uint8_t)0x00)
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/* ########################## Assert Selection ############################## */
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/**
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* @brief Uncomment the line below to expanse the "assert_param" macro in the
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* HAL drivers code
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*/
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/* #define USE_FULL_ASSERT 1 */
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/* Includes ------------------------------------------------------------------*/
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/**
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* @brief Include module's header file
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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#include "stm32h7xx_hal_rcc.h"
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#endif /* HAL_RCC_MODULE_ENABLED */
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#ifdef HAL_GPIO_MODULE_ENABLED
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#include "stm32h7xx_hal_gpio.h"
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#endif /* HAL_GPIO_MODULE_ENABLED */
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#ifdef HAL_DMA_MODULE_ENABLED
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#include "stm32h7xx_hal_dma.h"
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#endif /* HAL_DMA_MODULE_ENABLED */
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#ifdef HAL_MDMA_MODULE_ENABLED
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#include "stm32h7xx_hal_mdma.h"
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#endif /* HAL_MDMA_MODULE_ENABLED */
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#ifdef HAL_HASH_MODULE_ENABLED
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#include "stm32h7xx_hal_hash.h"
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#endif /* HAL_HASH_MODULE_ENABLED */
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#ifdef HAL_DCMI_MODULE_ENABLED
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#include "stm32h7xx_hal_dcmi.h"
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#endif /* HAL_DCMI_MODULE_ENABLED */
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#ifdef HAL_DMA2D_MODULE_ENABLED
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#include "stm32h7xx_hal_dma2d.h"
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#endif /* HAL_DMA2D_MODULE_ENABLED */
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#ifdef HAL_DFSDM_MODULE_ENABLED
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#include "stm32h7xx_hal_dfsdm.h"
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#endif /* HAL_DFSDM_MODULE_ENABLED */
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#ifdef HAL_ETH_MODULE_ENABLED
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#include "stm32h7xx_hal_eth.h"
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#endif /* HAL_ETH_MODULE_ENABLED */
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#ifdef HAL_EXTI_MODULE_ENABLED
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#include "stm32h7xx_hal_exti.h"
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#endif /* HAL_EXTI_MODULE_ENABLED */
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#ifdef HAL_CORTEX_MODULE_ENABLED
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#include "stm32h7xx_hal_cortex.h"
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#endif /* HAL_CORTEX_MODULE_ENABLED */
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#ifdef HAL_ADC_MODULE_ENABLED
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#include "stm32h7xx_hal_adc.h"
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#endif /* HAL_ADC_MODULE_ENABLED */
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#ifdef HAL_FDCAN_MODULE_ENABLED
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#include "stm32h7xx_hal_fdcan.h"
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#endif /* HAL_FDCAN_MODULE_ENABLED */
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#ifdef HAL_CEC_MODULE_ENABLED
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#include "stm32h7xx_hal_cec.h"
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#endif /* HAL_CEC_MODULE_ENABLED */
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#ifdef HAL_COMP_MODULE_ENABLED
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#include "stm32h7xx_hal_comp.h"
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#endif /* HAL_COMP_MODULE_ENABLED */
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#ifdef HAL_CRC_MODULE_ENABLED
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#include "stm32h7xx_hal_crc.h"
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#endif /* HAL_CRC_MODULE_ENABLED */
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#ifdef HAL_CRYP_MODULE_ENABLED
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#include "stm32h7xx_hal_cryp.h"
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#endif /* HAL_CRYP_MODULE_ENABLED */
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#ifdef HAL_DAC_MODULE_ENABLED
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#include "stm32h7xx_hal_dac.h"
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#endif /* HAL_DAC_MODULE_ENABLED */
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#ifdef HAL_FLASH_MODULE_ENABLED
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#include "stm32h7xx_hal_flash.h"
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#endif /* HAL_FLASH_MODULE_ENABLED */
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#ifdef HAL_HRTIM_MODULE_ENABLED
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#include "stm32h7xx_hal_hrtim.h"
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#endif /* HAL_HRTIM_MODULE_ENABLED */
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#ifdef HAL_HSEM_MODULE_ENABLED
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#include "stm32h7xx_hal_hsem.h"
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#endif /* HAL_HSEM_MODULE_ENABLED */
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#ifdef HAL_SRAM_MODULE_ENABLED
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#include "stm32h7xx_hal_sram.h"
|
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#endif /* HAL_SRAM_MODULE_ENABLED */
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#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMECC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ramecc.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SWPMI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_swpmi.h"
|
||||
#endif /* HAL_SWPMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM4/Inc/stm32h7xx_it.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the headers of the interrupt handlers for Cortex-M4.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H7xx_IT_H
|
||||
#define __STM32H7xx_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void EXTI0_IRQHandler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7xx_IT_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,492 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.2.0
|
||||
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage
|
||||
* instructions (TBD, not available at the time of writing).
|
||||
*
|
||||
* Behavior
|
||||
* --------
|
||||
*
|
||||
* This example stress tests a simple Asymmetric Multi Processing (AMP) core to
|
||||
* core communication mechanism implemented using FreeRTOS message buffers:
|
||||
* https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers
|
||||
* are used to pass an ASCII representation of an incrementing number (so "0",
|
||||
* followed by "1", followed by "2", etc.) from a single 'sending' task that
|
||||
* runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks
|
||||
* running on the Arm Cortex-M4 core (the M4 core). There are two data message
|
||||
* buffers, one for each receiving task. To distinguish between the receiving
|
||||
* tasks one is assigned the task number 0, and the other task number 1.
|
||||
*
|
||||
* The M7 task sits in a loop sending the ascii strings to each M4 task. If a
|
||||
* receiving task receives the next expected value in the sequence it prints its
|
||||
* task number to the UART. If a receiving task receives anything else, or its
|
||||
* attempt to receive data times out, then it hits an assert() that prints an
|
||||
* error message to the UART before stopping all further processing on the M4
|
||||
* core. If the example is running correctly you will see lots of "0"s (from
|
||||
* the receiving task assigned task number 0) and "1"s (from the receiving task
|
||||
* assigned task number 1) streaming from the UART. The time taken to output
|
||||
* characters from the UART is the only thing throttling the speed of the core
|
||||
* to core communication as it causes the message buffers to become full - which
|
||||
* would probably happen anyway as the M7 core is executing at twice the
|
||||
* frequency of the M4 core.
|
||||
*
|
||||
*
|
||||
* Implementation of sbSEND_COMPLETED()
|
||||
* ------------------------------------
|
||||
*
|
||||
* sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a
|
||||
* message buffer in case there was a task blocked on the message buffer waiting
|
||||
* for data to become available - in which case the waiting task would be
|
||||
* unblocked: https://www.freertos.org/RTOS-message-buffer-example.html
|
||||
* However, the default sbSEND_COMPLETED implementation assumes the sending task
|
||||
* (or interrupt) and the receiving task are under the control of the same
|
||||
* instance of the FreeRTOS kernel and run on the same MCU core. In this AMP
|
||||
* example the sending task and the receiving tasks are under the control of two
|
||||
* different instances of the FreeRTOS kernel, and run on different MCU cores,
|
||||
* so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS
|
||||
* kernel instance only knowns about the tasks under its control). AMP
|
||||
* scenarios therefore require the sbSEND_COMPLETED macro (and potentially the
|
||||
* sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by
|
||||
* simply providing your own implementation in the project's FreeRTOSConfig.h
|
||||
* file. Note this example has a FreeRTOSConfig.h file used by the application
|
||||
* that runs on the M7 core and a separate FreeRTOSConfig.h file used by the
|
||||
* application that runs on the M4 core. The implementation of sbSEND_COMPLETED
|
||||
* used by the M7 core simply triggers an interrupt in the M4 core. The
|
||||
* interrupt's handler (the ISR that was triggered by the M7 core but executes
|
||||
* on the M4 core) must then do the job that would otherwise be done by the
|
||||
* default implementation of sbSEND_COMPLETE - namely unblock a task if the task
|
||||
* was waiting to receive data from the message buffer that now contains data.
|
||||
* There are two data message buffers though, so first ISR must determine which
|
||||
* of the two contains data.
|
||||
*
|
||||
* This demo only has two data message buffers, so it would be reasonable to
|
||||
* have the ISR simply query both to see which contained data, but that solution
|
||||
* would not scale if there are many message buffers, or if the number of
|
||||
* message buffers was unknown. Therefore, to demonstrate a more scalable
|
||||
* solution, this example introduced a third message buffer - a 'control'
|
||||
* message buffer as opposed to a 'data' message buffer. After the task on the
|
||||
* M7 core writes to a data message buffer it writes the handle of the message
|
||||
* buffer that contains data to the control message buffer. The ISR running on
|
||||
* the M4 core then reads from the control message buffer to know which data
|
||||
* message buffer contains data.
|
||||
*
|
||||
* The above described scenario contains many implementation decisions.
|
||||
* Alternative methods of enabling the M4 core to know data message buffer
|
||||
* contains data include:
|
||||
*
|
||||
* 1) Using a different interrupt for each data message buffer.
|
||||
* 2) Passing all data from the M7 core to the M4 core through a single message
|
||||
* buffer, along with additional data that tells the ISR running on the M4
|
||||
* core which task to forward the data to.
|
||||
*
|
||||
*
|
||||
* Implementation of sbRECEIVE_COMPLETED()
|
||||
* ---------------------------------------
|
||||
*
|
||||
* sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro
|
||||
* called by FreeRTOS after data has been read from a message buffer in case
|
||||
* there was a task blocked on the message buffer waiting for space to become
|
||||
* available - in which case the waiting task would be unblocked so it can
|
||||
* complete its write to the buffer.
|
||||
*
|
||||
* In this example the M7 task writes to the message buffers faster than the M4
|
||||
* tasks read from them (in part because the M7 is running faster, and in part
|
||||
* because the M4 cores write to the UART), so the buffers become full, and the
|
||||
* M7 task enters the Blocked state to wait for space to become available. As
|
||||
* with the sbSEND_COMPLETED macro, the default implementation of the
|
||||
* sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the
|
||||
* control of the same instance of FreeRTOS and execute on the same core.
|
||||
* Therefore, just as the application that executes on the M7 core overrides
|
||||
* the default implementation of sbSEND_SOMPLETED(), the application that runs
|
||||
* on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()
|
||||
* to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()
|
||||
* executes on the M4 core and generates an interrupt on the M7 core. To keep
|
||||
* things simple the ISR that runs on the M7 core does not use a control
|
||||
* message buffer to know which data message buffer contains space, and instead
|
||||
* simply sends a notification to both data message buffers. Note however that
|
||||
* this overly simplistic implementation is only acceptable because it is
|
||||
* known that there is only one sending task, and that task cannot be blocked on
|
||||
* both message buffers at the same time. Also, sending the notification to the
|
||||
* data message buffer updates the receiving task's direct to task notification
|
||||
* state: https://www.freertos.org/RTOS-task-notifications.html which is only ok
|
||||
* because it is known the task is not using its notification state for any
|
||||
* other purpose.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include "stdio.h"
|
||||
#include "string.h"
|
||||
|
||||
/* STM32 includes. */
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "stm32h745i_discovery.h"
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "message_buffer.h"
|
||||
|
||||
/* Demo includes. */
|
||||
#include "MessageBufferLocations.h"
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Seen as an infinite block by the ST HAL. */
|
||||
#define mainHAL_MAX_TIMEOUT 0xFFFFFFFFUL
|
||||
|
||||
/* When the cores boot they very crudely wait for each other in a non chip
|
||||
specific way by waiting for the other core to start incrementing a shared
|
||||
variable within an array. mainINDEX_TO_TEST sets the index within the array to
|
||||
the variable this core tests to see if it is incrementing, and
|
||||
mainINDEX_TO_INCREMENT sets the index within the array to the variable this core
|
||||
increments to indicate to the other core that it is at the sync point. Note
|
||||
this is not a foolproof method and it is better to use a hardware specific
|
||||
solution, such as having one core boot the other core when it was ready, or
|
||||
using some kind of shared semaphore or interrupt. */
|
||||
#define mainINDEX_TO_TEST 1
|
||||
#define mainINDEX_TO_INCREMENT 0
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Implements the tasks that receive messages from the M7 core.
|
||||
*/
|
||||
static void prvM4CoreTasks( void *pvParameters );
|
||||
|
||||
/*
|
||||
* The interrupt triggered by the M7 core when there is data available in the
|
||||
* message buffer used for core to core communication.
|
||||
*/
|
||||
void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin );
|
||||
|
||||
/*
|
||||
* Just waits to see a variable being incremented by the M7 core to know when
|
||||
* the M7 has created the message buffers used for core to core communication.
|
||||
*/
|
||||
static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );
|
||||
|
||||
/*
|
||||
* Configures the hardware ready to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Handle to the UART used to output strings. */
|
||||
static UART_HandleTypeDef xUARTHandle = { 0 };
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main( void )
|
||||
{
|
||||
static const uint8_t pucBootMessage[] = "\r\nM4 started and waiting for the M7 to run.\r\n";
|
||||
static const uint8_t pucCreatingTasksMessage[] = "M4 core proceeding to create demo tasks.\r\n";
|
||||
uint32_t x;
|
||||
|
||||
/*** See the comments at the top of this page ***/
|
||||
|
||||
|
||||
/* Prep the hardware to run this demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* The M4 core task prints its status out at various places so you know what
|
||||
it is doing when debugging the M7 core. This messages is just to indicate
|
||||
it has booted and is about to wait for the M7 core. If the M7 is already
|
||||
running then reset the hardware so both cores start at once. */
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucBootMessage, sizeof( pucBootMessage ), mainHAL_MAX_TIMEOUT );
|
||||
prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );
|
||||
|
||||
/* By this point the M7 should have initialized the message buffers used to
|
||||
send data from the M7 to the M4 core. The message buffers are statically
|
||||
allocated at a known location so both cores know where they are. See
|
||||
MessageBufferLocations.h. */
|
||||
configASSERT( ( xControlMessageBuffer != NULL ) && ( xDataMessageBuffers[ 0 ] != NULL ) && ( xDataMessageBuffers[ 1 ] != NULL ) );
|
||||
|
||||
/* Everything seems as expected - print a message to say the M4 is about to
|
||||
create the tasks that receive data from the M7 core. */
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucCreatingTasksMessage, sizeof( pucCreatingTasksMessage ), mainHAL_MAX_TIMEOUT );
|
||||
|
||||
for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
|
||||
{
|
||||
/* Pass the loop counter into the created task using the task's
|
||||
parameter. The task then uses the value as an index into the
|
||||
xDataMessageBuffers arrays. */
|
||||
xTaskCreate( prvM4CoreTasks, /* Function that implements the task. */
|
||||
"AMPM4Core", /* Task name, for debugging only. */
|
||||
configMINIMAL_STACK_SIZE, /* Size of stack to allocate for this task - in words. */
|
||||
( void * ) x, /* Task parameter. */
|
||||
tskIDLE_PRIORITY + 1, /* Task priority. */
|
||||
NULL ); /* Task handle. Not used in this case. */
|
||||
}
|
||||
|
||||
/* Start scheduler */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Will not get here if the scheduler starts successfully. If you do end up
|
||||
here then there wasn't enough heap memory available to start either the idle
|
||||
task or the timer/daemon task. https://www.freertos.org/a00111.html */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvM4CoreTasks( void *pvParameters )
|
||||
{
|
||||
static const uint8_t pucTaskStartedMessage[] = "M4 task started.\r\n";
|
||||
BaseType_t xTaskNumber;
|
||||
size_t xReceivedBytes;
|
||||
uint32_t ulNextValue = 0;
|
||||
char cExpectedString[ 15 ];
|
||||
char cReceivedString[ 15 ];
|
||||
char cMessage;
|
||||
const TickType_t xShortBlockTime = pdMS_TO_TICKS( 5 );
|
||||
|
||||
/* This task is created more than once so the task's parameter is used to
|
||||
pass in a task number, which is then used as an index into the message
|
||||
buffer array. */
|
||||
xTaskNumber = ( BaseType_t ) pvParameters;
|
||||
configASSERT( xTaskNumber < mbaNUMBER_OF_CORE_2_TASKS );
|
||||
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
/* Message transmitted to indicate the task has started. */
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucTaskStartedMessage, sizeof( pucTaskStartedMessage ), mainHAL_MAX_TIMEOUT );
|
||||
}
|
||||
xTaskResumeAll();
|
||||
|
||||
/* The tasks print out a letter to indicate that the expected message was
|
||||
received from the other core. */
|
||||
if( xTaskNumber == 0 )
|
||||
{
|
||||
cMessage = '0';
|
||||
}
|
||||
else
|
||||
{
|
||||
cMessage = '1';
|
||||
}
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* The M7 core creates and sends to this core an ascii string of an
|
||||
incrementing number. Create the string that is expected to be received
|
||||
this time round the loop. */
|
||||
sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue );
|
||||
|
||||
/* Wait to receive the next message from core 1. */
|
||||
memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
|
||||
xReceivedBytes = xMessageBufferReceive( /* Handle of message buffer. */
|
||||
xDataMessageBuffers[ xTaskNumber ],
|
||||
/* Buffer into which received data is placed. */
|
||||
cReceivedString,
|
||||
/* Size of the receive buffer. */
|
||||
sizeof( cReceivedString ),
|
||||
/* Time to wait for data to arrive. */
|
||||
xShortBlockTime );
|
||||
|
||||
/* Check the number of bytes received was as expected. */
|
||||
configASSERT( xReceivedBytes == strlen( cExpectedString ) );
|
||||
|
||||
/* If the received string matches that expected then output the task
|
||||
number to give visible indication that the task is still running. */
|
||||
if( strcmp( cReceivedString, cExpectedString ) == 0 )
|
||||
{
|
||||
/* Also print out the task number to give a visual indication that
|
||||
the M4 core is receiving the expected data. */
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) &cMessage, sizeof( cMessage ), mainHAL_MAX_TIMEOUT );
|
||||
}
|
||||
xTaskResumeAll();
|
||||
}
|
||||
|
||||
/* Expect the next string in sequence the next time around. */
|
||||
ulNextValue++;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vGenerateM4ToM7Interrupt( void * xUpdatedMessageBuffer )
|
||||
{
|
||||
MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
|
||||
const char cMessage[] = "\r\nvGenerateM4ToM7Interrupt\r\n";
|
||||
|
||||
/* Called by the implementation of sbRECEIVE_COMPLETED() in FreeRTOSConfig.h.
|
||||
See the comments at the top of this file. Write the handle of the data
|
||||
message buffer to which data was written to the control message buffer. */
|
||||
#if 0
|
||||
if( xUpdatedBuffer != xControlMessageBuffer )
|
||||
{
|
||||
while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )
|
||||
{
|
||||
/* Nothing to do here. Note it is very bad to loop in an interrupt
|
||||
service routine. If a loop is really required then defer the
|
||||
routine to a task. */
|
||||
}
|
||||
|
||||
/* Generate interrupt in the M4 core. */
|
||||
HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );
|
||||
HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );
|
||||
HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Generate interrupt in the M7 core. */
|
||||
HAL_EXTI_D2_EventInputConfig( EXTI_LINE1, EXTI_MODE_IT, DISABLE );
|
||||
HAL_EXTI_D1_EventInputConfig( EXTI_LINE1, EXTI_MODE_IT, ENABLE );
|
||||
HAL_EXTI_GenerateSWInterrupt( EXTI_LINE1 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
|
||||
{
|
||||
MessageBufferHandle_t xUpdatedMessageBuffer;
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Avoid compiler warnings about unused parameters. */
|
||||
( void ) GPIO_Pin;
|
||||
|
||||
/* Clear interrupt. */
|
||||
HAL_EXTI_D2_ClearFlag( EXTI_LINE0 );
|
||||
|
||||
configASSERT( ( xControlMessageBuffer != NULL ) && ( xDataMessageBuffers[ 0 ] != NULL ) && ( xDataMessageBuffers[ 1 ] != NULL ) );
|
||||
|
||||
/* In this example there are mbaNUMBER_OF_CORE_2_TASKS receiving tasks that
|
||||
run on the M4 core. It would be possible for the M7 core to use a single
|
||||
message buffer to send to both tasks, but that would require additional data
|
||||
to be sent to the message buffer - namely an identifier to indicate which
|
||||
receiving task a message was intended for along with some arbitration in the
|
||||
ISR. As an alternative, this example uses one message buffer per receiving
|
||||
task and a control message buffer. The M7 core sends data to a receiving
|
||||
task using that task's dedicated message buffer, then sends the handle of
|
||||
the message buffer that it just sent data to to the control task. This
|
||||
interrupt service routine receives the handle from the control task then
|
||||
uses the handle to signal the message buffer that contains the data.
|
||||
|
||||
Receive the handle of the message buffer that contains data from the
|
||||
control message buffer. */
|
||||
while( xMessageBufferReceiveFromISR( xControlMessageBuffer,
|
||||
&xUpdatedMessageBuffer,
|
||||
sizeof( xUpdatedMessageBuffer ),
|
||||
&xHigherPriorityTaskWoken ) == sizeof( xUpdatedMessageBuffer ) )
|
||||
{
|
||||
/* Call the API function that sends a notification to any task that is
|
||||
blocked on the xUpdatedMessageBuffer message buffer waiting for data to
|
||||
arrive. */
|
||||
xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken );
|
||||
}
|
||||
|
||||
/* Normal FreeRTOS "yield from interrupt" semantics, where
|
||||
xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
|
||||
pdTRUE if the interrupt unblocks a task that has a priority above that of
|
||||
the currently executing task. */
|
||||
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )
|
||||
{
|
||||
volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];
|
||||
|
||||
/* When the cores boot they very crudely wait for each other in a non chip
|
||||
specific way by waiting for the other core to start incrementing a shared
|
||||
variable within an array. mainINDEX_TO_TEST sets the index within the array
|
||||
to the variable this core tests to see if it is incrementing, and
|
||||
mainINDEX_TO_INCREMENT sets the index within the array to the variable this
|
||||
core increments to indicate to the other core that it is at the sync point.
|
||||
Note this is not a foolproof method and it is better to use a hardware
|
||||
specific solution, such as having one core boot the other core when it was
|
||||
ready, or using some kind of shared semaphore or interrupt. */
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Indicate to the M7 core that this core is at the synchronisation
|
||||
point. */
|
||||
ulStartSyncCounters[ ulIndexToIncrement ]++;
|
||||
|
||||
/* Has the counter incremented by the other core changed? */
|
||||
if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* One more increment before exiting to avoid race. */
|
||||
ulStartSyncCounters[ ulIndexToIncrement ]++;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vAssertCalled( const char *pcFile, const uint32_t ulLine )
|
||||
{
|
||||
char pcLine[ 10 ];
|
||||
const uint8_t pucM4AssertFile[] = "M4 Assert hit in file ";
|
||||
const uint8_t pucM4AssertLine[] = "on line number ";
|
||||
|
||||
/* Assert disables interrupts so no other code can run, prints out the
|
||||
location of the offending assert(), then loops doing nothing waiting for
|
||||
the user to inspect or reset. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucM4AssertFile, sizeof( pucM4AssertFile ), mainHAL_MAX_TIMEOUT );
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pcFile, strlen( pcFile ), mainHAL_MAX_TIMEOUT );
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pucM4AssertLine, sizeof( pucM4AssertLine ), mainHAL_MAX_TIMEOUT );
|
||||
sprintf( pcLine, "%u\r\n", ulLine );
|
||||
HAL_UART_Transmit( &xUARTHandle, ( uint8_t * ) pcLine, strlen( pcLine ), mainHAL_MAX_TIMEOUT );
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
/* Prevent the HAL's initialisation of SysTick actually starting the systick
|
||||
interrupt as the kernel has not started yet. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
HAL_Init();
|
||||
BSP_LED_Init( LED2 );
|
||||
|
||||
/* This core uses the UART, so initialise it. */
|
||||
xUARTHandle.Instance = USART3;
|
||||
xUARTHandle.Init.BaudRate = 115200;
|
||||
xUARTHandle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
xUARTHandle.Init.StopBits = UART_STOPBITS_1;
|
||||
xUARTHandle.Init.Parity = UART_PARITY_NONE;
|
||||
xUARTHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
xUARTHandle.Init.Mode = UART_MODE_TX_RX;
|
||||
xUARTHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
xUARTHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
xUARTHandle.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
HAL_UART_Init( &xUARTHandle );
|
||||
HAL_UARTEx_SetRxFifoThreshold( &xUARTHandle, UART_RXFIFO_THRESHOLD_1_4 );
|
||||
HAL_UARTEx_EnableFifoMode( &xUARTHandle );
|
||||
|
||||
/* AIEC Common configuration: make CPU1 and CPU2 SWI line1 sensitive to
|
||||
rising edge. */
|
||||
HAL_EXTI_EdgeConfig( EXTI_LINE1, EXTI_RISING_EDGE );
|
||||
|
||||
/* Interrupt used for M7 to M4 notifications. */
|
||||
HAL_NVIC_SetPriority( EXTI0_IRQn, 0xFU, 0U );
|
||||
HAL_NVIC_EnableIRQ( EXTI0_IRQn );
|
||||
}
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file UART/UART_WakeUpFromStopUsingFIFO/CM7/Src/stm32h7xx_hal_msp.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL MSP module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "stm32h745i_discovery.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* User can use this section to tailor USARTx/UARTx instance used and associated
|
||||
resources */
|
||||
#define USARTx USART3
|
||||
#define USARTx_CLK_ENABLE() __HAL_RCC_USART3_CLK_ENABLE()
|
||||
#define USARTx_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
|
||||
#define USARTx_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
|
||||
|
||||
#define RCC_PERIPHCLK_USARTx RCC_PERIPHCLK_USART3
|
||||
#define RCC_USARTxCLKSOURCE_HSI RCC_USART3CLKSOURCE_HSI
|
||||
|
||||
#define USARTx_FORCE_RESET() __HAL_RCC_USART3_FORCE_RESET()
|
||||
#define USARTx_RELEASE_RESET() __HAL_RCC_USART3_RELEASE_RESET()
|
||||
|
||||
#define USARTx_IRQn USART3_IRQn
|
||||
#define USARTx_IRQHandler USART3_IRQHandler
|
||||
|
||||
#define USARTx_TX_PIN GPIO_PIN_10
|
||||
#define USARTx_TX_GPIO_PORT GPIOB
|
||||
#define USARTx_TX_AF GPIO_AF7_USART3
|
||||
#define USARTx_RX_PIN GPIO_PIN_11
|
||||
#define USARTx_RX_GPIO_PORT GPIOB
|
||||
#define USARTx_RX_AF GPIO_AF7_USART3
|
||||
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_MSP
|
||||
* @brief HAL MSP module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_MSP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief UART MSP Initialization
|
||||
* This function configures the hardware resources used in this example:
|
||||
* - Peripheral's clock enable
|
||||
* - Peripheral's GPIO Configuration
|
||||
* @param huart: UART handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef *huart)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
|
||||
|
||||
/*##-1- Enable peripherals and GPIO Clocks #################################*/
|
||||
/* Enable GPIO TX/RX clock */
|
||||
USARTx_TX_GPIO_CLK_ENABLE();
|
||||
USARTx_RX_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Select HSI as source of USARTx clocks */
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USARTx;
|
||||
RCC_PeriphClkInit.Usart234578ClockSelection = RCC_USARTxCLKSOURCE_HSI;
|
||||
HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
|
||||
|
||||
/* Enable USARTx clock */
|
||||
USARTx_CLK_ENABLE();
|
||||
|
||||
/*##-2- Configure peripheral GPIO ##########################################*/
|
||||
/* UART TX GPIO pin configuration */
|
||||
GPIO_InitStruct.Pin = USARTx_TX_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = USARTx_TX_AF;
|
||||
|
||||
HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct);
|
||||
|
||||
/* UART RX GPIO pin configuration */
|
||||
GPIO_InitStruct.Pin = USARTx_RX_PIN;
|
||||
GPIO_InitStruct.Alternate = USARTx_RX_AF;
|
||||
|
||||
HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct);
|
||||
|
||||
/* NVIC for USART */
|
||||
HAL_NVIC_SetPriority(USARTx_IRQn, 0, 1);
|
||||
HAL_NVIC_EnableIRQ(USARTx_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART MSP De-Initialization
|
||||
* This function frees the hardware resources used in this example:
|
||||
* - Disable the Peripheral's clock
|
||||
* - Revert GPIO and NVIC configuration to their default state
|
||||
* @param huart: UART handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/*##-1- Reset peripherals ##################################################*/
|
||||
USARTx_FORCE_RESET();
|
||||
USARTx_RELEASE_RESET();
|
||||
|
||||
/*##-2- Disable peripherals and GPIO Clocks ################################*/
|
||||
/* Configure UART Tx as alternate function */
|
||||
HAL_GPIO_DeInit(USARTx_TX_GPIO_PORT, USARTx_TX_PIN);
|
||||
/* Configure UART Rx as alternate function */
|
||||
HAL_GPIO_DeInit(USARTx_RX_GPIO_PORT, USARTx_RX_PIN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM4/Src/stm32h7xx_it.c
|
||||
* @author MCD Application Team
|
||||
* @brief Main Interrupt Service Routines for Cortex-M4.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_it.h"
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_IOToggle
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M4 Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Hard Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory Manage exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Memory Manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Bus Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Usage Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug Monitor exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32H7xx Peripherals Interrupt Handlers */
|
||||
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||
/* available peripheral interrupt handler's name please refer to the startup */
|
||||
/* file (startup_stm32h7xx.s). */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief This function handles EXTI0 interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI0_IRQHandler( void )
|
||||
{
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PPP interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
/*void PPP_IRQHandler(void)
|
||||
{
|
||||
}*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* Ensure stdint is only used by the compiler, and not the assembler. */
|
||||
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
|
||||
#include <stdint.h>
|
||||
extern uint32_t SystemCoreClock;
|
||||
void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer );
|
||||
#endif
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( SystemCoreClock )
|
||||
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
|
||||
#define configMAX_PRIORITIES ( 7 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 16 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configUSE_APPLICATION_TASK_TAG 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
|
||||
#define configSUPPORT_STATIC_ALLOCATION 1
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 0
|
||||
#define configTIMER_TASK_PRIORITY ( 2 )
|
||||
#define configTIMER_QUEUE_LENGTH 10
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xQueueGetMutexHolder 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
|
||||
/* Cortex-M specific definitions. */
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4 /* 15 priority levels */
|
||||
#endif
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
/* Override the default implementation of sbSEND_COMPLETED so the macro creates
|
||||
an interrupt in the M4 core. See the comments at the top of main.c. */
|
||||
#define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateM7ToM4Interrupt( pxStreamBuffer )
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
||||
|
|
@ -0,0 +1,422 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_HwSemaphoreCoreSync/CM7/Inc/stm32h7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file for Cortex-M7.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H7xx_HAL_CONF_H
|
||||
#define __STM32H7xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_COMP_MODULE_ENABLED */
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
/* #define HAL_EXTI_MODULE_ENABLED */
|
||||
/* #define HAL_FDCAN_MODULE_ENABLED */
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
/* #define HAL_HRTIM_MODULE_ENABLED */
|
||||
#define HAL_HSEM_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
/* #define HAL_MDIOS_MODULE_ENABLED */
|
||||
/* #define HAL_MDMA_MODULE_ENABLED */
|
||||
/* #define HAL_MMC_MODULE_ENABLED */
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_OPAMP_MODULE_ENABLED */
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
/* #define HAL_RAMECC_MODULE_ENABLED */
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_SMBUS_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
/* #define HAL_SWPMI_MODULE_ENABLED */
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal oscillator (CSI) default value.
|
||||
* This value is the default CSI value after Reset.
|
||||
*/
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
|
||||
|
||||
/* ########################### Ethernet Configuration ######################### */
|
||||
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
|
||||
|
||||
#define ETH_MAC_ADDR0 ((uint8_t)0x02)
|
||||
#define ETH_MAC_ADDR1 ((uint8_t)0x00)
|
||||
#define ETH_MAC_ADDR2 ((uint8_t)0x00)
|
||||
#define ETH_MAC_ADDR3 ((uint8_t)0x00)
|
||||
#define ETH_MAC_ADDR4 ((uint8_t)0x00)
|
||||
#define ETH_MAC_ADDR5 ((uint8_t)0x00)
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDMA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mdma.h"
|
||||
#endif /* HAL_MDMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HRTIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hrtim.h"
|
||||
#endif /* HAL_HRTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hsem.h"
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMECC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ramecc.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SWPMI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_swpmi.h"
|
||||
#endif /* HAL_SWPMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Inc/stm32h7xx_it.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the headers of the interrupt handlers for Cortex-M7.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H7xx_IT_H
|
||||
#define __STM32H7xx_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void EXTI1_IRQHandler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7xx_IT_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.2.0
|
||||
* Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage
|
||||
* instructions (TBD, not available at the time of writing).
|
||||
*
|
||||
* Behavior
|
||||
* --------
|
||||
*
|
||||
* This example stress tests a simple Asymmetric Multi Processing (AMP) core to
|
||||
* core communication mechanism implemented using FreeRTOS message buffers:
|
||||
* https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers
|
||||
* are used to pass an ASCII representation of an incrementing number (so "0",
|
||||
* followed by "1", followed by "2", etc.) from a single 'sending' task that
|
||||
* runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks
|
||||
* running on the Arm Cortex-M4 core (the M4 core). There are two data message
|
||||
* buffers, one for each receiving task. To distinguish between the receiving
|
||||
* tasks one is assigned the task number 0, and the other task number 1.
|
||||
*
|
||||
* The M7 task sits in a loop sending the ascii strings to each M4 task. If a
|
||||
* receiving task receives the next expected value in the sequence it prints its
|
||||
* task number to the UART. If a receiving task receives anything else, or its
|
||||
* attempt to receive data times out, then it hits an assert() that prints an
|
||||
* error message to the UART before stopping all further processing on the M4
|
||||
* core. If the example is running correctly you will see lots of "0"s (from
|
||||
* the receiving task assigned task number 0) and "1"s (from the receiving task
|
||||
* assigned task number 1) streaming from the UART. The time taken to output
|
||||
* characters from the UART is the only thing throttling the speed of the core
|
||||
* to core communication as it causes the message buffers to become full - which
|
||||
* would probably happen anyway as the M7 core is executing at twice the
|
||||
* frequency of the M4 core.
|
||||
*
|
||||
*
|
||||
* Implementation of sbSEND_COMPLETED()
|
||||
* ------------------------------------
|
||||
*
|
||||
* sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a
|
||||
* message buffer in case there was a task blocked on the message buffer waiting
|
||||
* for data to become available - in which case the waiting task would be
|
||||
* unblocked: https://www.freertos.org/RTOS-message-buffer-example.html
|
||||
* However, the default sbSEND_COMPLETED implementation assumes the sending task
|
||||
* (or interrupt) and the receiving task are under the control of the same
|
||||
* instance of the FreeRTOS kernel and run on the same MCU core. In this AMP
|
||||
* example the sending task and the receiving tasks are under the control of two
|
||||
* different instances of the FreeRTOS kernel, and run on different MCU cores,
|
||||
* so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS
|
||||
* kernel instance only knowns about the tasks under its control). AMP
|
||||
* scenarios therefore require the sbSEND_COMPLETED macro (and potentially the
|
||||
* sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by
|
||||
* simply providing your own implementation in the project's FreeRTOSConfig.h
|
||||
* file. Note this example has a FreeRTOSConfig.h file used by the application
|
||||
* that runs on the M7 core and a separate FreeRTOSConfig.h file used by the
|
||||
* application that runs on the M4 core. The implementation of sbSEND_COMPLETED
|
||||
* used by the M7 core simply triggers an interrupt in the M4 core. The
|
||||
* interrupt's handler (the ISR that was triggered by the M7 core but executes
|
||||
* on the M4 core) must then do the job that would otherwise be done by the
|
||||
* default implementation of sbSEND_COMPLETE - namely unblock a task if the task
|
||||
* was waiting to receive data from the message buffer that now contains data.
|
||||
* There are two data message buffers though, so first ISR must determine which
|
||||
* of the two contains data.
|
||||
*
|
||||
* This demo only has two data message buffers, so it would be reasonable to
|
||||
* have the ISR simply query both to see which contained data, but that solution
|
||||
* would not scale if there are many message buffers, or if the number of
|
||||
* message buffers was unknown. Therefore, to demonstrate a more scalable
|
||||
* solution, this example introduced a third message buffer - a 'control'
|
||||
* message buffer as opposed to a 'data' message buffer. After the task on the
|
||||
* M7 core writes to a data message buffer it writes the handle of the message
|
||||
* buffer that contains data to the control message buffer. The ISR running on
|
||||
* the M4 core then reads from the control message buffer to know which data
|
||||
* message buffer contains data.
|
||||
*
|
||||
* The above described scenario contains many implementation decisions.
|
||||
* Alternative methods of enabling the M4 core to know data message buffer
|
||||
* contains data include:
|
||||
*
|
||||
* 1) Using a different interrupt for each data message buffer.
|
||||
* 2) Passing all data from the M7 core to the M4 core through a single message
|
||||
* buffer, along with additional data that tells the ISR running on the M4
|
||||
* core which task to forward the data to.
|
||||
*
|
||||
*
|
||||
* Implementation of sbRECEIVE_COMPLETED()
|
||||
* ---------------------------------------
|
||||
*
|
||||
* sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro
|
||||
* called by FreeRTOS after data has been read from a message buffer in case
|
||||
* there was a task blocked on the message buffer waiting for space to become
|
||||
* available - in which case the waiting task would be unblocked so it can
|
||||
* complete its write to the buffer.
|
||||
*
|
||||
* In this example the M7 task writes to the message buffers faster than the M4
|
||||
* tasks read from them (in part because the M7 is running faster, and in part
|
||||
* because the M4 cores write to the UART), so the buffers become full, and the
|
||||
* M7 task enters the Blocked state to wait for space to become available. As
|
||||
* with the sbSEND_COMPLETED macro, the default implementation of the
|
||||
* sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the
|
||||
* control of the same instance of FreeRTOS and execute on the same core.
|
||||
* Therefore, just as the application that executes on the M7 core overrides
|
||||
* the default implementation of sbSEND_SOMPLETED(), the application that runs
|
||||
* on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()
|
||||
* to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()
|
||||
* executes on the M4 core and generates an interrupt on the M7 core. To keep
|
||||
* things simple the ISR that runs on the M7 core does not use a control
|
||||
* message buffer to know which data message buffer contains space, and instead
|
||||
* simply sends a notification to both data message buffers. Note however that
|
||||
* this overly simplistic implementation is only acceptable because it is
|
||||
* known that there is only one sending task, and that task cannot be blocked on
|
||||
* both message buffers at the same time. Also, sending the notification to the
|
||||
* data message buffer updates the receiving task's direct to task notification
|
||||
* state: https://www.freertos.org/RTOS-task-notifications.html which is only ok
|
||||
* because it is known the task is not using its notification state for any
|
||||
* other purpose.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include "stdio.h"
|
||||
#include "string.h"
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "message_buffer.h"
|
||||
#include "MessageBufferLocations.h"
|
||||
|
||||
/* ST includes. */
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "stm32h745i_discovery.h"
|
||||
|
||||
/* When the cores boot they very crudely wait for each other in a non chip
|
||||
specific way by waiting for the other core to start incrementing a shared
|
||||
variable within an array. mainINDEX_TO_TEST sets the index within the array to
|
||||
the variable this core tests to see if it is incrementing, and
|
||||
mainINDEX_TO_INCREMENT sets the index within the array to the variable this core
|
||||
increments to indicate to the other core that it is at the sync point. Note
|
||||
this is not a foolproof method and it is better to use a hardware specific
|
||||
solution, such as having one core boot the other core when it was ready, or
|
||||
using some kind of shared semaphore or interrupt. */
|
||||
#define mainINDEX_TO_TEST 0
|
||||
#define mainINDEX_TO_INCREMENT 1
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Implements the task that sends messages to the M7 core.
|
||||
*/
|
||||
static void prvM7CoreTasks( void *pvParameters );
|
||||
|
||||
/*
|
||||
* configSUPPORT_STATIC_ALLOCATION is set to 1, requiring this callback to
|
||||
* provide statically allocated data for use by the idle task, which is a task
|
||||
* created by the scheduler when it starts.
|
||||
*/
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
|
||||
|
||||
/*
|
||||
* Just waits to see a variable being incremented by the M4 core to know when
|
||||
* the M4 has created the message buffers used for core to core communication.
|
||||
*/
|
||||
static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );
|
||||
|
||||
/*
|
||||
* Setup the hardware ready to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static TaskHandle_t xM7AMPTask = NULL;
|
||||
|
||||
int main( void )
|
||||
{
|
||||
BaseType_t x;
|
||||
|
||||
/*** See the comments at the top of this page ***/
|
||||
|
||||
prvSetupHardware();
|
||||
|
||||
/* Create the control and data message buffers, as described at the top of
|
||||
this file. The message buffers are statically allocated at a known location
|
||||
as both cores need to know where they are. See MessageBufferLocations.h. */
|
||||
xControlMessageBuffer = xMessageBufferCreateStatic( /* The buffer size in bytes. */
|
||||
mbaCONTROL_MESSAGE_BUFFER_SIZE,
|
||||
/* Statically allocated buffer storage area. */
|
||||
ucControlBufferStorage,
|
||||
/* Message buffer handle. */
|
||||
&xControlMessageBufferStruct );
|
||||
for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
|
||||
{
|
||||
xDataMessageBuffers[ x ] = xMessageBufferCreateStatic( mbaTASK_MESSAGE_BUFFER_SIZE,
|
||||
&( ucDataBufferStorage[ x ][ 0 ] ),
|
||||
&( xDataMessageBufferStructs[ x ] ) );
|
||||
}
|
||||
|
||||
/* The message buffers have been initialised so it is safe for both cores to
|
||||
synchronise their startup. */
|
||||
prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );
|
||||
|
||||
/* Start the task that executes on the M7 core. */
|
||||
xTaskCreate( prvM7CoreTasks, /* Function that implements the task. */
|
||||
"AMPM7Core", /* Task name, for debugging only. */
|
||||
configMINIMAL_STACK_SIZE, /* Size of stack (in words) to allocate for this task. */
|
||||
NULL, /* Task parameter, not used in this case. */
|
||||
tskIDLE_PRIORITY, /* Task priority. */
|
||||
&xM7AMPTask ); /* Task handle, used to unblock task from interrupt. */
|
||||
|
||||
/* Start scheduler */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Will not get here if the scheduler starts successfully. If you do end up
|
||||
here then there wasn't enough heap memory available to start either the idle
|
||||
task or the timer/daemon task. https://www.freertos.org/a00111.html */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvM7CoreTasks( void *pvParameters )
|
||||
{
|
||||
BaseType_t x;
|
||||
uint32_t ulNextValue = 0;
|
||||
const TickType_t xDelay = pdMS_TO_TICKS( 25 );
|
||||
char cString[ 15 ];
|
||||
size_t xStringLength;
|
||||
|
||||
/* Remove warning about unused parameters. */
|
||||
( void ) pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Create the next string to send. The value is incremented on each
|
||||
loop iteration, and the length of the string changes as the number of
|
||||
digits in the value increases. */
|
||||
sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
|
||||
xStringLength = strlen( cString );
|
||||
|
||||
/* This task runs on the M7 core, use the message buffers to send the
|
||||
strings to the tasks running on the M4 core. This will result in
|
||||
sbSEND_COMPLETED() being executed, which in turn will write the handle
|
||||
of the message buffer written to into xControlMessageBuffer then
|
||||
generate an interrupt in M4 core. */
|
||||
for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
|
||||
{
|
||||
while( xMessageBufferSend( xDataMessageBuffers[ x ],
|
||||
( void * ) cString,
|
||||
xStringLength,
|
||||
portMAX_DELAY ) != xStringLength );
|
||||
|
||||
/* Delay before repeating */
|
||||
// vTaskDelay( xDelay );
|
||||
}
|
||||
|
||||
ulNextValue++;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer )
|
||||
{
|
||||
MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
|
||||
|
||||
/* Called by the implementation of sbSEND_COMPLETED() in FreeRTOSConfig.h.
|
||||
See the comments at the top of this file. Write the handle of the data
|
||||
message buffer to which data was written to the control message buffer. */
|
||||
if( xUpdatedBuffer != xControlMessageBuffer )
|
||||
{
|
||||
while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )
|
||||
{
|
||||
/* Nothing to do here. Note it is very bad to loop in an interrupt
|
||||
service routine. If a loop is really required then defer the
|
||||
routine to a task. */
|
||||
}
|
||||
|
||||
/* Generate interrupt in the M4 core. */
|
||||
HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );
|
||||
HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );
|
||||
HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
|
||||
{
|
||||
/* If the buffers to be provided to the Idle task are declared inside this
|
||||
function then they must be declared static - otherwise they will be allocated on
|
||||
the stack and so not exists after this function exits. */
|
||||
static StaticTask_t xIdleTaskTCB;
|
||||
static uint32_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
|
||||
|
||||
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide
|
||||
an implementation of vApplicationGetIdleTaskMemory() to provide the memory
|
||||
that is used by the Idle task.
|
||||
https://www.freertos.org/a00110.html#configSUPPORT_STATIC_ALLOCATION */
|
||||
|
||||
/* Pass out a pointer to the StaticTask_t structure in which the Idle task's
|
||||
state will be stored. */
|
||||
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
|
||||
|
||||
/* Pass out the array that will be used as the Idle task's stack. */
|
||||
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
|
||||
|
||||
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
|
||||
Note that, as the array is necessarily of type StackType_t,
|
||||
configMINIMAL_STACK_SIZE is specified in words, not bytes. */
|
||||
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )
|
||||
{
|
||||
volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ], x;
|
||||
const uint32_t ulCrudeLoopDelay = 0xfffffUL;
|
||||
|
||||
/* When the cores boot they very crudely wait for each other in a non chip
|
||||
specific way by waiting for the other core to start incrementing a shared
|
||||
variable within an array. mainINDEX_TO_TEST sets the index within the array
|
||||
to the variable this core tests to see if it is incrementing, and
|
||||
mainINDEX_TO_INCREMENT sets the index within the array to the variable this
|
||||
core increments to indicate to the other core that it is at the sync point.
|
||||
Note this is not a foolproof method and it is better to use a hardware
|
||||
specific solution, such as having one core boot the other core when it was
|
||||
ready, or using some kind of shared semaphore or interrupt. */
|
||||
|
||||
/* Wait for the other core to reach the synchronisation point. */
|
||||
while( ulStartSyncCounters[ ulIndexToTest ] == ulInitialCount );
|
||||
ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
ulStartSyncCounters[ ulIndexToIncrement ]++;
|
||||
if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )
|
||||
{
|
||||
ulStartSyncCounters[ ulIndexToIncrement ]++;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Unlike the M4 core, this core does not have direct access to the UART,
|
||||
so simply toggle an LED to show its status. */
|
||||
for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
|
||||
BSP_LED_Off( LED2 );
|
||||
for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
|
||||
BSP_LED_On( LED2 );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
|
||||
{
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
uint32_t x;
|
||||
|
||||
configASSERT( xM7AMPTask );
|
||||
|
||||
HAL_EXTI_D1_ClearFlag( EXTI_LINE1 );
|
||||
|
||||
/* Task can't be blocked on both so just send the notification to both. */
|
||||
for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
|
||||
{
|
||||
xMessageBufferReceiveCompletedFromISR( xDataMessageBuffers[ x ], &xHigherPriorityTaskWoken );
|
||||
}
|
||||
|
||||
/* Normal FreeRTOS "yield from interrupt" semantics, where
|
||||
xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
|
||||
pdTRUE if the interrupt unblocks a task that has a priority above that of
|
||||
the currently executing task. */
|
||||
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
MPU_Region_InitTypeDef MPU_InitStruct;
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* Configure the MPU attributes as Not Cachable for Internal D3SRAM. The
|
||||
Base Address is 0x38000000 (D3_SRAM_BASE), and the size is 64K. */
|
||||
HAL_MPU_Disable();
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.BaseAddress = D3_SRAM_BASE;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||
MPU_InitStruct.SubRegionDisable = 0x00;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
||||
|
||||
/* Enable I-Cache */
|
||||
SCB_EnableICache();
|
||||
|
||||
/* Enable D-Cache */
|
||||
SCB_EnableDCache();
|
||||
|
||||
HAL_Init();
|
||||
BSP_LED_Init(LED1);
|
||||
|
||||
|
||||
/*
|
||||
System Clock Configuration:
|
||||
System Clock source = PLL (HSE)
|
||||
SYSCLK(Hz) = 400000000 (Cortex-M7 CPU Clock)
|
||||
HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks)
|
||||
AHB Prescaler = 2
|
||||
D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
|
||||
D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
|
||||
D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
|
||||
D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
|
||||
HSE Frequency(Hz) = 25000000
|
||||
PLL_M = 5
|
||||
PLL_N = 160
|
||||
PLL_P = 2
|
||||
PLL_Q = 4
|
||||
PLL_R = 2
|
||||
VDD(V) = 3.3
|
||||
Flash Latency(WS) = 4
|
||||
*/
|
||||
|
||||
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the
|
||||
device is clocked below the maximum system frequency, to update the voltage
|
||||
scaling value regarding system frequency refer to product datasheet. */
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
while( !__HAL_PWR_GET_FLAG( PWR_FLAG_VOSRDY ) )
|
||||
{
|
||||
__asm volatile ( "NOP" );
|
||||
}
|
||||
|
||||
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
|
||||
RCC_OscInitStruct.PLL.PLLM = 5;
|
||||
RCC_OscInitStruct.PLL.PLLN = 160;
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
RCC_OscInitStruct.PLL.PLLP = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4;
|
||||
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
|
||||
configASSERT( HAL_RCC_OscConfig( &RCC_OscInitStruct ) == HAL_OK );
|
||||
|
||||
/* Select PLL as system clock source and configure bus clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
|
||||
RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 );
|
||||
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
||||
configASSERT( HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_4 ) == HAL_OK );
|
||||
|
||||
/* AIEC Common configuration: make CPU1 and CPU2 SWI line0 sensitive to
|
||||
rising edge. */
|
||||
HAL_EXTI_EdgeConfig( EXTI_LINE0, EXTI_RISING_EDGE );
|
||||
|
||||
/* Interrupt used for M4 to M7 notifications. */
|
||||
HAL_NVIC_SetPriority( EXTI1_IRQn, 0xFU, 0U );
|
||||
HAL_NVIC_EnableIRQ( EXTI1_IRQn );
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Src/stm32h7xx_hal_timebase_tim.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL time base based on the hardware TIM.
|
||||
*
|
||||
* This file overrides the native HAL time base functions (defined as weak)
|
||||
* the TIM time base:
|
||||
* + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
|
||||
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
TIM_HandleTypeDef TimHandle;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void TIM6_DAC_IRQHandler(void);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the TIM6 as a time base source.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||
* @param TickPriority: Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
|
||||
{
|
||||
RCC_ClkInitTypeDef clkconfig;
|
||||
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
|
||||
uint32_t uwPrescalerValue = 0U;
|
||||
uint32_t pFLatency;
|
||||
|
||||
/*Configure the TIM6 IRQ priority */
|
||||
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
|
||||
|
||||
/* Enable the TIM6 global Interrupt */
|
||||
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
||||
|
||||
/* Enable TIM6 clock */
|
||||
__HAL_RCC_TIM6_CLK_ENABLE();
|
||||
|
||||
/* Get clock configuration */
|
||||
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
||||
|
||||
/* Get APB1 prescaler */
|
||||
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
|
||||
|
||||
/* Compute TIM6 clock */
|
||||
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
|
||||
{
|
||||
uwTimclock = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
|
||||
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
||||
|
||||
/* Initialize TIM6 */
|
||||
TimHandle.Instance = TIM6;
|
||||
|
||||
/* Initialize TIMx peripheral as follow:
|
||||
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
|
||||
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
||||
+ ClockDivision = 0
|
||||
+ Counter direction = Up
|
||||
*/
|
||||
TimHandle.Init.Period = (1000000U / 1000U) - 1U;
|
||||
TimHandle.Init.Prescaler = uwPrescalerValue;
|
||||
TimHandle.Init.ClockDivision = 0;
|
||||
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
|
||||
{
|
||||
/* Start the TIM time Base generation in interrupt mode */
|
||||
return HAL_TIM_Base_Start_IT(&TimHandle);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note Disable the tick increment by disabling TIM6 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable TIM6 update Interrupt */
|
||||
__HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note Enable the tick increment by Enabling TIM6 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable TIM6 Update interrupt */
|
||||
__HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Period elapsed callback in non blocking mode
|
||||
* @note This function is called when TIM6 interrupt took place, inside
|
||||
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||
* a global variable "uwTick" used as application time base.
|
||||
* @param htim : TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
HAL_IncTick();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles TIM interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TIM6_DAC_IRQHandler(void)
|
||||
{
|
||||
HAL_TIM_IRQHandler(&TimHandle);
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file FreeRTOS/FreeRTOS_AMP_Dual_RTOS/CM7/Src/stm32h7xx_it.c
|
||||
* @author MCD Application Team
|
||||
* @brief Main Interrupt Service Routines.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_it.h"
|
||||
#include "stm32h7xx_hal.h"
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M7 Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Hard Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory Manage exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Memory Manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Bus Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Usage Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug Monitor exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32H7xx Peripherals Interrupt Handlers */
|
||||
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||
/* available peripheral interrupt handler's name please refer to the startup */
|
||||
/* file (startup_stm32h7xx.s). */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief This function handles EXTI0 interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI1_IRQHandler( void )
|
||||
{
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* FreeRTOS Kernel V10.0.0
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software. If you wish to use our Amazon
|
||||
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef MESSAGE_BUFFER_AMP_H
|
||||
#define MESSAGE_BUFFER_AMP_H
|
||||
|
||||
/* Enough four 4 8 byte strings, plus the additional 4 bytes per message
|
||||
overhead of message buffers. */
|
||||
#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 )
|
||||
|
||||
#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 )
|
||||
|
||||
/* The number of instances of prvM4CoreTasks that are created. */
|
||||
#define mbaNUMBER_OF_CORE_2_TASKS 2
|
||||
|
||||
/* A block time of 0 simply means, don't block. */
|
||||
#define mbaDONT_BLOCK 0
|
||||
|
||||
/* Place the message buffers at a fixed location so it is the same for both
|
||||
cores. */
|
||||
#pragma location = 0x38000000
|
||||
MessageBufferHandle_t xControlMessageBuffer;
|
||||
|
||||
#pragma location = 0x38000004
|
||||
MessageBufferHandle_t xDataMessageBuffers[ mbaNUMBER_OF_CORE_2_TASKS ];
|
||||
|
||||
#pragma location = 0x3800000c
|
||||
static volatile uint32_t ulStartSyncCounters[ mbaNUMBER_OF_CORE_2_TASKS ];
|
||||
|
||||
|
||||
/* The variable used to hold the stream buffer structure.*/
|
||||
#pragma location = 0x38000050
|
||||
StaticStreamBuffer_t xControlMessageBufferStruct;
|
||||
#pragma location = 0x380000A0
|
||||
StaticStreamBuffer_t xDataMessageBufferStructs[mbaNUMBER_OF_CORE_2_TASKS];
|
||||
/* Used to dimension the array used to hold the streams.*/
|
||||
/* Defines the memory that will actually hold the streams within the stream buffer.*/
|
||||
#pragma location = 0x38000100
|
||||
static uint8_t ucControlBufferStorage[ mbaCONTROL_MESSAGE_BUFFER_SIZE ];
|
||||
#pragma location = 0x38000200
|
||||
static uint8_t ucDataBufferStorage[mbaNUMBER_OF_CORE_2_TASKS][ mbaTASK_MESSAGE_BUFFER_SIZE ];
|
||||
|
||||
|
||||
#endif /* MESSAGE_BUFFER_AMP_H */
|
||||
2966
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewd
Normal file
2966
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewd
Normal file
File diff suppressed because it is too large
Load diff
2270
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewp
Normal file
2270
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewp
Normal file
File diff suppressed because it is too large
Load diff
2540
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewt
Normal file
2540
FreeRTOS/Demo/CORTEX_M7_M4_AMP_STM32H745I_Discovery_IAR/Project.ewt
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\Project.ewp</path>
|
||||
</project>
|
||||
<batchBuild />
|
||||
</workspace>
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8" />
|
||||
<meta name="generator" content="pandoc" />
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for STM32H745I-DISCO BSP Driver</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="../../../_htmresc/mini-st.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<div class="card fluid">
|
||||
<div class="sectione dark">
|
||||
<center>
|
||||
<h1 id="release-notes-for-stm32h745i-disco-bsp-driver"><strong>Release Notes for STM32H745I-DISCO BSP Driver</strong></h1>
|
||||
<p>Copyright © 2019 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="../../../_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
<h1 id="license"><strong>License</strong></h1>
|
||||
This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
|
||||
<center>
|
||||
<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
|
||||
</center>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history"><strong>Update History</strong></h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 05-April-2019</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,649 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of firmware functions to manage LEDs,
|
||||
* push-buttons, external SDRAM, external QSPI Flash,
|
||||
* available on STM32H745I-Discovery board (MB1381) from
|
||||
* STMicroelectronics.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL STM32H745I_DISCOVERY_LOW_LEVEL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Defines Private Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32H745I Discovery BSP Driver version number V1.0.0
|
||||
*/
|
||||
#define __STM32H745I_DISCOVERY_BSP_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H745I_DISCOVERY_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32H745I_DISCOVERY_BSP_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H745I_DISCOVERY_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H745I_DISCOVERY_BSP_VERSION ((__STM32H745I_DISCOVERY_BSP_VERSION_MAIN << 24)\
|
||||
|(__STM32H745I_DISCOVERY_BSP_VERSION_SUB1 << 16)\
|
||||
|(__STM32H745I_DISCOVERY_BSP_VERSION_SUB2 << 8 )\
|
||||
|(__STM32H745I_DISCOVERY_BSP_VERSION_RC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT,
|
||||
LED2_GPIO_PORT};
|
||||
|
||||
const uint32_t GPIO_PIN[LEDn] = {LED1_PIN,
|
||||
LED2_PIN};
|
||||
|
||||
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT };
|
||||
|
||||
const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN };
|
||||
|
||||
const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn };
|
||||
|
||||
static I2C_HandleTypeDef hdiscovery_I2c = {0};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes Private FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
static void I2Cx_MspInit(void);
|
||||
static void I2Cx_Init(void);
|
||||
static void I2Cx_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
|
||||
static uint8_t I2Cx_Read(uint8_t Addr, uint8_t Reg);
|
||||
static HAL_StatusTypeDef I2Cx_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
|
||||
static HAL_StatusTypeDef I2Cx_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
|
||||
static void I2Cx_Error(uint8_t Addr);
|
||||
|
||||
/* AUDIO IO functions */
|
||||
void AUDIO_IO_Init(void);
|
||||
void AUDIO_IO_DeInit(void);
|
||||
void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
|
||||
uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg);
|
||||
void AUDIO_IO_Delay(uint32_t Delay);
|
||||
|
||||
/* TouchScreen (TS) IO functions */
|
||||
void TS_IO_Init(void);
|
||||
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
|
||||
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg);
|
||||
uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);
|
||||
void TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);
|
||||
void TS_IO_Delay(uint32_t Delay);
|
||||
|
||||
/* LCD Display IO functions */
|
||||
void OTM8009A_IO_Delay(uint32_t Delay);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_BSP_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This method returns the STM32H745I Discovery BSP Driver revision
|
||||
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t BSP_GetVersion(void)
|
||||
{
|
||||
return __STM32H745I_DISCOVERY_BSP_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures LED GPIO.
|
||||
* @param Led: LED to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_LED_Init(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
/* Enable the GPIO_LED clock */
|
||||
LEDx_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Configure the GPIO_LED pin */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN[Led];
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
|
||||
HAL_GPIO_Init(GPIO_PORT[Led], &GPIO_InitStruct);
|
||||
|
||||
/* By default, turn off LED */
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DeInit LEDs.
|
||||
* @param Led: LED to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @note Led DeInit does not disable the GPIO clock
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_LED_DeInit(Led_TypeDef Led)
|
||||
{
|
||||
/* Turn off LED */
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);
|
||||
/* Configure the GPIO_LED pin */
|
||||
HAL_GPIO_DeInit(GPIO_PORT[Led], GPIO_PIN[Led]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED On.
|
||||
* @param Led: LED to be set on
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_LED_On(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED Off.
|
||||
* @param Led: LED to be set off
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_LED_Off(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the selected LED.
|
||||
* @param Led: LED to be toggled
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LED1
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_LED_Toggle(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_TogglePin(GPIO_PORT[Led], GPIO_PIN[Led]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures button GPIO and EXTI Line.
|
||||
* @param Button: Button to be configured
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BUTTON_WAKEUP: Wakeup Push Button
|
||||
* @arg BUTTON_USER: User Push Button
|
||||
* @param Button_Mode: Button mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BUTTON_MODE_GPIO: Button will be used as simple IO
|
||||
* @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line
|
||||
* with interrupt generation capability
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
/* Enable the BUTTON clock */
|
||||
BUTTON_GPIO_CLK_ENABLE();
|
||||
|
||||
if(Button_Mode == BUTTON_MODE_GPIO)
|
||||
{
|
||||
/* Configure Button pin as input */
|
||||
GPIO_InitStruct.Pin = BUTTON_PIN[Button];
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
|
||||
}
|
||||
|
||||
if(Button_Mode == BUTTON_MODE_EXTI)
|
||||
{
|
||||
/* Configure Button pin as input with External interrupt */
|
||||
GPIO_InitStruct.Pin = BUTTON_PIN[Button];
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||
|
||||
HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
|
||||
|
||||
/* Enable and set Button EXTI Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00);
|
||||
HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Push Button DeInit.
|
||||
* @param Button: Button to be configured
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BUTTON_WAKEUP: Wakeup Push Button
|
||||
* @arg BUTTON_USER: User Push Button
|
||||
* @note PB DeInit does not disable the GPIO clock
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_PB_DeInit(Button_TypeDef Button)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
gpio_init_structure.Pin = BUTTON_PIN[Button];
|
||||
HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
|
||||
HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the selected button state.
|
||||
* @param Button: Button to be checked
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BUTTON_WAKEUP: Wakeup Push Button
|
||||
* @arg BUTTON_USER: User Push Button
|
||||
* @retval The Button GPIO pin value
|
||||
*/
|
||||
uint32_t BSP_PB_GetState(Button_TypeDef Button)
|
||||
{
|
||||
return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Private_Functions Private Functions
|
||||
* @{
|
||||
*/
|
||||
/*******************************************************************************
|
||||
BUS OPERATIONS
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* I2C Routines *********************************/
|
||||
/**
|
||||
* @brief Initializes I2C MSP.
|
||||
* @retval None
|
||||
*/
|
||||
static void I2Cx_MspInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
|
||||
|
||||
/* Configure the I2C clock source */
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C123;
|
||||
RCC_PeriphClkInit.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
|
||||
HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
|
||||
|
||||
/* set STOPWUCK in RCC_CFGR */
|
||||
__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_HSI);
|
||||
|
||||
/*** Configure the GPIOs ***/
|
||||
/* Enable GPIO clock */
|
||||
DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Configure I2C Tx as alternate function */
|
||||
gpio_init_structure.Pin = DISCOVERY_I2Cx_SCL_PIN;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
|
||||
gpio_init_structure.Pull = GPIO_NOPULL;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
gpio_init_structure.Alternate = DISCOVERY_I2Cx_SCL_SDA_AF;
|
||||
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* Configure I2C Rx as alternate function */
|
||||
gpio_init_structure.Pin = DISCOVERY_I2Cx_SDA_PIN;
|
||||
HAL_GPIO_Init(DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/*** Configure the I2C peripheral ***/
|
||||
/* Enable I2C clock */
|
||||
DISCOVERY_I2Cx_CLK_ENABLE();
|
||||
|
||||
/* Force the I2C peripheral clock reset */
|
||||
DISCOVERY_I2Cx_FORCE_RESET();
|
||||
|
||||
/* Release the I2C peripheral clock reset */
|
||||
DISCOVERY_I2Cx_RELEASE_RESET();
|
||||
|
||||
/* Enable and set I2Cx Interrupt to a lower priority */
|
||||
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_EV_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_EV_IRQn);
|
||||
|
||||
/* Enable and set I2Cx Interrupt to a lower priority */
|
||||
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_ER_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_ER_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes I2C HAL.
|
||||
* @retval None
|
||||
*/
|
||||
static void I2Cx_Init(void)
|
||||
{
|
||||
if(HAL_I2C_GetState(&hdiscovery_I2c) == HAL_I2C_STATE_RESET)
|
||||
{
|
||||
hdiscovery_I2c.Instance = DISCOVERY_I2Cx;
|
||||
hdiscovery_I2c.Init.Timing = DISCOVERY_I2Cx_TIMING;
|
||||
hdiscovery_I2c.Init.OwnAddress1 = 0x72;
|
||||
hdiscovery_I2c.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
hdiscovery_I2c.Init.DualAddressMode = I2C_DUALADDRESS_ENABLE;
|
||||
hdiscovery_I2c.Init.OwnAddress2 = 0;
|
||||
hdiscovery_I2c.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
||||
hdiscovery_I2c.Init.GeneralCallMode = I2C_GENERALCALL_ENABLE;
|
||||
hdiscovery_I2c.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
||||
|
||||
/* Init the I2C */
|
||||
I2Cx_MspInit();
|
||||
HAL_I2C_Init(&hdiscovery_I2c);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @param Value: Data to be written
|
||||
* @retval None
|
||||
*/
|
||||
static void I2Cx_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
status = HAL_I2C_Mem_Write(&hdiscovery_I2c, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, &Value, 1, 100);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Execute user timeout callback */
|
||||
I2Cx_Error(Addr);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @retval Read data
|
||||
*/
|
||||
static uint8_t I2Cx_Read(uint8_t Addr, uint8_t Reg)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint8_t Value = 0;
|
||||
|
||||
status = HAL_I2C_Mem_Read(&hdiscovery_I2c, Addr, Reg, I2C_MEMADD_SIZE_8BIT, &Value, 1, 1000);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Execute user timeout callback */
|
||||
I2Cx_Error(Addr);
|
||||
}
|
||||
return Value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads multiple data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @param MemAddress: memory address
|
||||
* @param Buffer: Pointer to data buffer
|
||||
* @param Length: Length of the data
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2Cx_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
status = HAL_I2C_Mem_Read(&hdiscovery_I2c, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* I2C error occurred */
|
||||
I2Cx_Error(Addr);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a value in a register of the device through BUS in using DMA mode.
|
||||
* @param Addr: Device address on BUS Bus.
|
||||
* @param Reg: The target register address to write
|
||||
* @param MemAddress: memory address
|
||||
* @param Buffer: The target register value to be written
|
||||
* @param Length: buffer size to be written
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef I2Cx_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddress, uint8_t *Buffer, uint16_t Length)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
status = HAL_I2C_Mem_Write(&hdiscovery_I2c, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Re-Initiaize the I2C Bus */
|
||||
I2Cx_Error(Addr);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Manages error callback by re-initializing I2C.
|
||||
* @param Addr: I2C Address
|
||||
* @retval None
|
||||
*/
|
||||
static void I2Cx_Error(uint8_t Addr)
|
||||
{
|
||||
/* De-initialize the I2C comunication bus */
|
||||
HAL_I2C_DeInit(&hdiscovery_I2c);
|
||||
|
||||
/* Re-Initialize the I2C communication bus */
|
||||
I2Cx_Init();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
LINK OPERATIONS
|
||||
*******************************************************************************/
|
||||
|
||||
/********************************* LINK AUDIO *********************************/
|
||||
|
||||
/**
|
||||
* @brief Initializes Audio low level.
|
||||
* @retval None
|
||||
*/
|
||||
void AUDIO_IO_Init(void)
|
||||
{
|
||||
I2Cx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes Audio low level.
|
||||
* @retval None
|
||||
*/
|
||||
void AUDIO_IO_DeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @param Value: Data to be written
|
||||
* @retval None
|
||||
*/
|
||||
void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
|
||||
{
|
||||
uint16_t tmp = Value;
|
||||
|
||||
Value = ((uint16_t)(tmp >> 8) & 0x00FF);
|
||||
|
||||
Value |= ((uint16_t)(tmp << 8)& 0xFF00);
|
||||
|
||||
I2Cx_WriteMultiple(Addr, Reg, I2C_MEMADD_SIZE_16BIT,(uint8_t*)&Value, 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @retval Data to be read
|
||||
*/
|
||||
uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg)
|
||||
{
|
||||
uint16_t read_value = 0, tmp = 0;
|
||||
|
||||
I2Cx_ReadMultiple(Addr, Reg, I2C_MEMADD_SIZE_16BIT, (uint8_t*)&read_value, 2);
|
||||
|
||||
tmp = ((uint16_t)(read_value >> 8) & 0x00FF);
|
||||
|
||||
tmp |= ((uint16_t)(read_value << 8)& 0xFF00);
|
||||
|
||||
read_value = tmp;
|
||||
|
||||
return read_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AUDIO Codec delay
|
||||
* @param Delay: Delay in ms
|
||||
* @retval None
|
||||
*/
|
||||
void AUDIO_IO_Delay(uint32_t Delay)
|
||||
{
|
||||
HAL_Delay(Delay);
|
||||
}
|
||||
|
||||
/******************************** LINK TS (TouchScreen) *****************************/
|
||||
|
||||
/**
|
||||
* @brief Initialize I2C communication
|
||||
* channel from MCU to TouchScreen (TS).
|
||||
*/
|
||||
void TS_IO_Init(void)
|
||||
{
|
||||
I2Cx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes single data with I2C communication
|
||||
* channel from MCU to TouchScreen.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @param Value: Data to be written
|
||||
*/
|
||||
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
||||
{
|
||||
I2Cx_Write(Addr, Reg, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads single data with I2C communication
|
||||
* channel from TouchScreen.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @retval Read data
|
||||
*/
|
||||
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
|
||||
{
|
||||
return I2Cx_Read(Addr, Reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads multiple data with I2C communication
|
||||
* channel from TouchScreen.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @param Buffer: Pointer to data buffer
|
||||
* @param Length: Length of the data
|
||||
* @retval Number of read data
|
||||
*/
|
||||
uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
|
||||
{
|
||||
return I2Cx_ReadMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes multiple data with I2C communication
|
||||
* channel from MCU to TouchScreen.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Register address
|
||||
* @param Buffer: Pointer to data buffer
|
||||
* @param Length: Length of the data
|
||||
* @retval None
|
||||
*/
|
||||
void TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
|
||||
{
|
||||
I2Cx_WriteMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Delay function used in TouchScreen low level driver.
|
||||
* @param Delay: Delay in ms
|
||||
* @retval None
|
||||
*/
|
||||
void TS_IO_Delay(uint32_t Delay)
|
||||
{
|
||||
HAL_Delay(Delay);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains definitions for STM32H745I-Discovery LEDs,
|
||||
* push-buttons hardware resources.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_H
|
||||
#define __STM32H745I_DISCOVERY_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL STM32H745I_DISCOVERY_LOW_LEVEL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LED1 = 0,
|
||||
LED_GREEN = LED1,
|
||||
LED2 = 1,
|
||||
LED_RED = LED2,
|
||||
} Led_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_WAKEUP = 0,
|
||||
} Button_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_MODE_GPIO = 0,
|
||||
BUTTON_MODE_EXTI = 1
|
||||
} ButtonMode_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PB_SET = 0,
|
||||
PB_RESET = !PB_SET
|
||||
} ButtonValue_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISCO_OK = 0,
|
||||
DISCO_ERROR = 1
|
||||
} DISCO_Status_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Define for STM32H745I_DISCOVERY board
|
||||
*/
|
||||
#if !defined (USE_STM32H745I_DISCO)
|
||||
#define USE_STM32H745I_DISCO
|
||||
#endif
|
||||
|
||||
#define BUTTON_USER BUTTON_WAKEUP
|
||||
|
||||
#define LEDn ((uint32_t)2)
|
||||
|
||||
#define LED1_GPIO_PORT GPIOJ
|
||||
#define LED1_PIN GPIO_PIN_2
|
||||
#define LED2_GPIO_PORT GPIOI
|
||||
#define LED2_PIN GPIO_PIN_13
|
||||
#define LEDx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE();__HAL_RCC_GPIOJ_CLK_ENABLE()
|
||||
#define LEDx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE();__HAL_RCC_GPIOJ_CLK_DISABLE()
|
||||
|
||||
/**
|
||||
* @brief Definition for LCD Timer used to control the Brightnes
|
||||
*/
|
||||
#define LCD_TIMx TIM8
|
||||
#define LCD_TIMx_CLK_ENABLE() __HAL_RCC_TIM8_CLK_ENABLE()
|
||||
#define LCD_TIMx_CLK_DISABLE() __HAL_RCC_TIM8_CLK_DISABLE()
|
||||
#define LCD_TIMx_CHANNEL TIM_CHANNEL_3
|
||||
#define LCD_TIMx_CHANNEL_AF GPIO_AF3_TIM8
|
||||
#define LCD_TIMX_PERIOD_VALUE ((uint32_t)50000) /* Period Value */
|
||||
#define LCD_TIMX_PRESCALER_VALUE ((uint32_t)4) /* Prescaler Value */
|
||||
|
||||
|
||||
/* Only one User/Wakeup button */
|
||||
#define BUTTONn ((uint8_t)1)
|
||||
|
||||
/**
|
||||
* @brief Wakeup push-button
|
||||
*/
|
||||
#define WAKEUP_BUTTON_PIN GPIO_PIN_13
|
||||
#define WAKEUP_BUTTON_GPIO_PORT GPIOC
|
||||
#define WAKEUP_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
#define WAKEUP_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE()
|
||||
#define WAKEUP_BUTTON_EXTI_IRQn EXTI15_10_IRQn
|
||||
|
||||
/* Define the USER button as an alias of the Wakeup button */
|
||||
#define USER_BUTTON_PIN WAKEUP_BUTTON_PIN
|
||||
#define USER_BUTTON_GPIO_PORT WAKEUP_BUTTON_GPIO_PORT
|
||||
#define USER_BUTTON_GPIO_CLK_ENABLE() WAKEUP_BUTTON_GPIO_CLK_ENABLE()
|
||||
#define USER_BUTTON_GPIO_CLK_DISABLE() WAKEUP_BUTTON_GPIO_CLK_DISABLE()
|
||||
#define USER_BUTTON_EXTI_IRQn WAKEUP_BUTTON_EXTI_IRQn
|
||||
|
||||
#define BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
|
||||
/**
|
||||
* @brief TS_INT signal from TouchScreen when it is configured in interrupt mode
|
||||
*/
|
||||
#define TS_INT_PIN ((uint32_t)GPIO_PIN_2)
|
||||
#define TS_INT_GPIO_PORT ((GPIO_TypeDef*)GPIOG)
|
||||
#define TS_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define TS_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOG_CLK_DISABLE()
|
||||
#define TS_INT_EXTI_IRQn EXTI2_IRQn
|
||||
|
||||
/**
|
||||
* @brief TouchScreen FT5336 Slave I2C address
|
||||
*/
|
||||
#define TS_I2C_ADDRESS ((uint16_t)0x70)
|
||||
|
||||
/**
|
||||
* @brief Audio I2C Slave address
|
||||
*/
|
||||
#define AUDIO_I2C_ADDRESS ((uint16_t)0x34)
|
||||
|
||||
/**
|
||||
* @brief User can use this section to tailor I2C4/I2C4 instance used and associated
|
||||
* resources (audio codec).
|
||||
* Definition for I2C4 clock resources
|
||||
*/
|
||||
#define DISCOVERY_I2Cx I2C4
|
||||
#define DISCOVERY_I2Cx_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define DISCOVERY_I2Cx_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
|
||||
#define DISCOVERY_I2Cx_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define DISCOVERY_I2Cx_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
|
||||
/** @brief Definition for I2C4 Pins
|
||||
*/
|
||||
#define DISCOVERY_I2Cx_SCL_PIN GPIO_PIN_12 /*!< PD12 */
|
||||
#define DISCOVERY_I2Cx_SDA_PIN GPIO_PIN_13 /*!< PD13 */
|
||||
#define DISCOVERY_I2Cx_SCL_SDA_AF GPIO_AF4_I2C4
|
||||
#define DISCOVERY_I2Cx_SCL_SDA_GPIO_PORT GPIOD
|
||||
/** @brief Definition of I2C4 interrupt requests
|
||||
*/
|
||||
#define DISCOVERY_I2Cx_EV_IRQn I2C4_EV_IRQn
|
||||
#define DISCOVERY_I2Cx_ER_IRQn I2C4_ER_IRQn
|
||||
|
||||
/* I2C TIMING Register define when I2C clock source is SYSCLK */
|
||||
/* I2C TIMING is calculated from APB1 source clock = 200 MHz */
|
||||
/* 0x40912732 takes in account the big rising and aims a clock of 100khz */
|
||||
#ifndef DISCOVERY_I2Cx_TIMING
|
||||
#define DISCOVERY_I2Cx_TIMING ((uint32_t)0x40912732)
|
||||
#endif /* DISCOVERY_I2Cx_TIMING */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LOW_LEVEL_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t BSP_GetVersion(void);
|
||||
void BSP_LED_Init(Led_TypeDef Led);
|
||||
void BSP_LED_DeInit(Led_TypeDef Led);
|
||||
void BSP_LED_On(Led_TypeDef Led);
|
||||
void BSP_LED_Off(Led_TypeDef Led);
|
||||
void BSP_LED_Toggle(Led_TypeDef Led);
|
||||
void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
|
||||
void BSP_PB_DeInit(Button_TypeDef Button);
|
||||
uint32_t BSP_PB_GetState(Button_TypeDef Button);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,332 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_audio.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32h745i_discovery_audio.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_AUDIO_H
|
||||
#define __STM32H745I_DISCOVERY_AUDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Include audio component Driver */
|
||||
#include "../Components/wm8994/wm8994.h"
|
||||
#include "stm32h745i_discovery.h"
|
||||
#include <stdlib.h>
|
||||
/* Include PDM to PCM lib header file */
|
||||
#include "pdm2pcm_glo.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_AUDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Frequency; /* Record Frequency */
|
||||
uint32_t BitResolution; /* Record bit resolution */
|
||||
uint32_t ChannelNbr; /* Record Channel Number */
|
||||
uint16_t *pRecBuf; /* Pointer to record user buffer */
|
||||
uint32_t RecSize; /* Size to record in mono, double size to record in stereo */
|
||||
uint32_t InputDevice; /* Audio Input Device */
|
||||
uint32_t Interface; /* Audio Input Interface */
|
||||
uint32_t MultiBuffMode; /* Multi buffer mode selection */
|
||||
}AUDIOIN_ContextTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define BSP_AUDIO_FREQUENCY_96K SAI_AUDIO_FREQUENCY_96K
|
||||
#define BSP_AUDIO_FREQUENCY_48K SAI_AUDIO_FREQUENCY_48K
|
||||
#define BSP_AUDIO_FREQUENCY_44K SAI_AUDIO_FREQUENCY_44K
|
||||
#define BSP_AUDIO_FREQUENCY_32K SAI_AUDIO_FREQUENCY_32K
|
||||
#define BSP_AUDIO_FREQUENCY_22K SAI_AUDIO_FREQUENCY_22K
|
||||
#define BSP_AUDIO_FREQUENCY_16K SAI_AUDIO_FREQUENCY_16K
|
||||
#define BSP_AUDIO_FREQUENCY_11K SAI_AUDIO_FREQUENCY_11K
|
||||
#define BSP_AUDIO_FREQUENCY_8K SAI_AUDIO_FREQUENCY_8K
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
USER SAI defines parameters
|
||||
-----------------------------------------------------------------------------*/
|
||||
/** In W8994 codec the Audio frame contains 4 slots : TDM Mode
|
||||
* TDM format :
|
||||
* +------------------|------------------|--------------------|-------------------+
|
||||
* | CODEC_SLOT0 Left | CODEC_SLOT1 Left | CODEC_SLOT0 Right | CODEC_SLOT1 Right |
|
||||
* +------------------------------------------------------------------------------+
|
||||
*/
|
||||
/* To have 2 separate audio stream in Both headphone and speaker the 4 slot must be activated */
|
||||
#define CODEC_AUDIOFRAME_SLOT_0123 SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_2 | SAI_SLOTACTIVE_3
|
||||
|
||||
/* To have an audio stream in headphone only SAI Slot 0 and Slot 2 must be activated */
|
||||
#define CODEC_AUDIOFRAME_SLOT_02 SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_2
|
||||
/* To have an audio stream in speaker only SAI Slot 1 and Slot 3 must be activated */
|
||||
#define CODEC_AUDIOFRAME_SLOT_13 SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_3
|
||||
/* To have an audio stream in SAI PDM input Slot 0 must be activated */
|
||||
#define CODEC_AUDIOFRAME_SLOT_0 SAI_SLOTACTIVE_0
|
||||
/* To have an audio stream in SAI PDM input Slot 1 must be activated */
|
||||
#define CODEC_AUDIOFRAME_SLOT_1 SAI_SLOTACTIVE_1
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
AUDIO OUT CONFIGURATION
|
||||
------------------------------------------------------------------------------*/
|
||||
/* SAI peripheral configuration defines */
|
||||
#define AUDIO_OUT_SAIx SAI2_Block_A
|
||||
#define AUDIO_OUT_SAIx_CLK_ENABLE() __HAL_RCC_SAI2_CLK_ENABLE()
|
||||
#define AUDIO_OUT_SAIx_CLK_DISABLE() __HAL_RCC_SAI2_CLK_DISABLE()
|
||||
#define AUDIO_OUT_SAIx_AF GPIO_AF10_SAI2
|
||||
|
||||
#define AUDIO_OUT_SAIx_MCLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE()
|
||||
#define AUDIO_OUT_SAIx_MCLK_GPIO_PORT GPIOI
|
||||
#define AUDIO_OUT_SAIx_MCLK_PIN GPIO_PIN_4
|
||||
#define AUDIO_OUT_SAIx_SD_FS_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE()
|
||||
#define AUDIO_OUT_SAIx_SD_FS_SCK_GPIO_PORT GPIOI
|
||||
#define AUDIO_OUT_SAIx_FS_PIN GPIO_PIN_7
|
||||
#define AUDIO_OUT_SAIx_SCK_PIN GPIO_PIN_5
|
||||
#define AUDIO_OUT_SAIx_SD_PIN GPIO_PIN_6
|
||||
|
||||
/* SAI DMA Stream definitions */
|
||||
#define AUDIO_OUT_SAIx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
|
||||
#define AUDIO_OUT_SAIx_DMAx_STREAM DMA2_Stream1
|
||||
#define AUDIO_OUT_SAIx_DMAx_REQUEST DMA_REQUEST_SAI2_A
|
||||
#define AUDIO_OUT_SAIx_DMAx_IRQ DMA2_Stream1_IRQn
|
||||
#define AUDIO_OUT_SAIx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
|
||||
#define AUDIO_OUT_SAIx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
|
||||
#define AUDIO_OUT_SAIx_DMAx_IRQHandler DMA2_Stream1_IRQHandler
|
||||
|
||||
/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
|
||||
#define AUDIO_OUT_IRQ_PREPRIO ((uint32_t)0x0E)
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
AUDIO IN CONFIGURATION
|
||||
------------------------------------------------------------------------------*/
|
||||
/* SAI peripheral configuration defines */
|
||||
#define AUDIO_IN_SAIx SAI2_Block_B
|
||||
#define AUDIO_IN_SAIx_CLK_ENABLE() __HAL_RCC_SAI2_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAIx_CLK_DISABLE() __HAL_RCC_SAI2_CLK_DISABLE()
|
||||
#define AUDIO_IN_SAIx_AF GPIO_AF10_SAI2
|
||||
#define AUDIO_IN_SAIx_SD_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAIx_SD_GPIO_PORT GPIOG
|
||||
#define AUDIO_IN_SAIx_SD_PIN GPIO_PIN_10
|
||||
|
||||
/* SAI DMA Stream definitions */
|
||||
#define AUDIO_IN_SAIx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAIx_DMAx_STREAM DMA2_Stream4
|
||||
#define AUDIO_IN_SAIx_DMAx_REQUEST DMA_REQUEST_SAI2_B
|
||||
#define AUDIO_IN_SAIx_DMAx_IRQ DMA2_Stream4_IRQn
|
||||
#define AUDIO_IN_SAIx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
|
||||
#define AUDIO_IN_SAIx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
|
||||
|
||||
#define AUDIO_IN_SAIx_DMAx_IRQHandler DMA2_Stream4_IRQHandler
|
||||
|
||||
/* SAI PDM input definitions */
|
||||
#define AUDIO_IN_SAI_PDMx SAI4_Block_A
|
||||
#define AUDIO_IN_SAI_PDMx_CLK_ENABLE() __HAL_RCC_SAI4_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAI_PDMx_CLK_DISABLE() __HAL_RCC_SAI4_CLK_DISABLE()
|
||||
#define AUDIO_IN_SAI_PDMx_CLK_IN_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAI_PDMx_CLK_IN_PIN GPIO_PIN_5
|
||||
#define AUDIO_IN_SAI_PDMx_CLK_IN_PORT GPIOE
|
||||
#define AUDIO_IN_SAI_PDMx_DATA_IN_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAI_PDMx_DATA_IN_PIN GPIO_PIN_4
|
||||
#define AUDIO_IN_SAI_PDMx_DATA_IN_PORT GPIOE
|
||||
#define AUDIO_IN_SAI_PDMx_DATA_CLK_AF GPIO_AF10_SAI4
|
||||
#define AUDIO_IN_SAI_PDMx_IRQHandler SAI4_IRQHandler
|
||||
#define AUDIO_IN_SAI_PDMx_IRQ SAI4_IRQn
|
||||
|
||||
/* SAI PDM DMA Stream definitions */
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_CLK_ENABLE() __HAL_RCC_BDMA_CLK_ENABLE()
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_STREAM BDMA_Channel1
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_REQUEST BDMA_REQUEST_SAI4_A
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_IRQ BDMA_Channel1_IRQn
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
|
||||
#define AUDIO_IN_SAI_PDMx_DMAx_IRQHandler BDMA_Channel1_IRQHandler
|
||||
|
||||
/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
|
||||
#define AUDIO_IN_IRQ_PREPRIO ((uint32_t)0x0F)
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
CONFIGURATION: Audio Driver Configuration parameters
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
#define AUDIODATA_SIZE ((uint32_t)2) /* 16-bits audio data size */
|
||||
|
||||
/* Audio status definition */
|
||||
#define AUDIO_OK ((uint8_t)0)
|
||||
#define AUDIO_ERROR ((uint8_t)1)
|
||||
#define AUDIO_TIMEOUT ((uint8_t)2)
|
||||
|
||||
/* Audio In default settings */
|
||||
#define DEFAULT_AUDIO_IN_FREQ BSP_AUDIO_FREQUENCY_16K
|
||||
#define DEFAULT_AUDIO_IN_BIT_RESOLUTION ((uint8_t)16)
|
||||
#define DEFAULT_AUDIO_IN_CHANNEL_NBR ((uint8_t)2)
|
||||
#define DEFAULT_AUDIO_IN_VOLUME ((uint16_t)64)
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
OUTPUT DEVICES definition
|
||||
------------------------------------------------------------------------------*/
|
||||
/* Alias on existing output devices to adapt for 2 headphones output */
|
||||
#define OUTPUT_DEVICE_HEADPHONE1 OUTPUT_DEVICE_HEADPHONE
|
||||
#define OUTPUT_DEVICE_HEADPHONE2 OUTPUT_DEVICE_SPEAKER /* Headphone2 is connected to Speaker output of the wm8994 */
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
INPUT DEVICES definition
|
||||
------------------------------------------------------------------------------*/
|
||||
/* Analog microphone input from 3.5 audio jack connector */
|
||||
#define INPUT_DEVICE_ANALOG_MIC ((uint32_t)0x00000001)
|
||||
/* MP34DT01TR digital microphone on PCB top side */
|
||||
#define INPUT_DEVICE_DIGITAL_MIC1 ((uint32_t)0x00000010)
|
||||
#define INPUT_DEVICE_DIGITAL_MIC2 ((uint32_t)0x00000020)
|
||||
#define INPUT_DEVICE_DIGITAL_MIC ((uint32_t)(INPUT_DEVICE_DIGITAL_MIC1 | INPUT_DEVICE_DIGITAL_MIC2))
|
||||
|
||||
/* Audio In interface for Digital mic */
|
||||
#define AUDIO_IN_INTERFACE_SAI ((uint16_t)0)
|
||||
#define AUDIO_IN_INTERFACE_PDM ((uint16_t)1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_AUDIO_Exported_Macros Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MAX_SIZE 0xFFFF
|
||||
#define DMA_MAX(x) (((x) <= DMA_MAX_SIZE)? (x):DMA_MAX_SIZE)
|
||||
#define POS_VAL(VAL) (POSITION_VAL(VAL) - 4)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_AUDIO_OUT_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
|
||||
void BSP_AUDIO_OUT_DeInit(void);
|
||||
uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size);
|
||||
void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size);
|
||||
uint8_t BSP_AUDIO_OUT_Pause(void);
|
||||
uint8_t BSP_AUDIO_OUT_Resume(void);
|
||||
uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option);
|
||||
uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume);
|
||||
void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq);
|
||||
void BSP_AUDIO_OUT_SetAudioFrameSlot(uint32_t AudioFrameSlot);
|
||||
uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd);
|
||||
uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output);
|
||||
|
||||
/* User Callbacks: user has to implement these functions in his code if they are needed. */
|
||||
/* This function is called when the requested data has been completely transferred.*/
|
||||
void BSP_AUDIO_OUT_TransferComplete_CallBack(void);
|
||||
|
||||
/* This function is called when half of the requested buffer has been transferred. */
|
||||
void BSP_AUDIO_OUT_HalfTransfer_CallBack(void);
|
||||
|
||||
/* This function is called when an Interrupt due to transfer error on or peripheral
|
||||
error occurs. */
|
||||
void BSP_AUDIO_OUT_Error_CallBack(void);
|
||||
|
||||
/* These function can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_AUDIO_OUT_ClockConfig(SAI_HandleTypeDef *hsai, uint32_t AudioFreq, void *Params);
|
||||
void BSP_AUDIO_OUT_MspInit(SAI_HandleTypeDef *hsai, void *Params);
|
||||
void BSP_AUDIO_OUT_MspDeInit(SAI_HandleTypeDef *hsai, void *Params);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_AUDIO_IN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);
|
||||
uint8_t BSP_AUDIO_IN_InitEx(uint16_t InputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);
|
||||
uint8_t BSP_AUDIO_IN_AllocScratch (int32_t *pScratch, uint32_t size);
|
||||
uint8_t BSP_AUDIO_IN_Record(uint16_t *pBuf, uint32_t Size);
|
||||
uint8_t BSP_AUDIO_IN_RecordEx(uint32_t *pBuf, uint32_t Size);
|
||||
uint8_t BSP_AUDIO_IN_SetFrequency(uint32_t AudioFreq);
|
||||
uint8_t BSP_AUDIO_IN_Stop(void);
|
||||
uint8_t BSP_AUDIO_IN_StopEx(uint32_t InputDevice);
|
||||
uint8_t BSP_AUDIO_IN_Pause(void);
|
||||
uint8_t BSP_AUDIO_IN_PauseEx(uint32_t InputDevice);
|
||||
uint8_t BSP_AUDIO_IN_Resume(void);
|
||||
uint8_t BSP_AUDIO_IN_ResumeEx(uint32_t *pBuf, uint32_t InputDevice);
|
||||
uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume);
|
||||
void BSP_AUDIO_IN_DeInit(void);
|
||||
uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf);
|
||||
uint8_t BSP_AUDIO_IN_PDMToPCM_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut);
|
||||
void BSP_AUDIO_IN_SelectInterface(uint32_t Interface);
|
||||
uint32_t BSP_AUDIO_IN_GetInterface(void);
|
||||
uint8_t BSP_AUDIO_IN_GetChannelNumber(void);
|
||||
uint8_t BSP_AUDIO_IN_OUT_Init(uint32_t InputDevice, uint32_t OutputDevice, uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);
|
||||
|
||||
/* User Callbacks: user has to implement these functions in his code if they are needed. */
|
||||
/* This function should be implemented by the user application.
|
||||
It is called into this driver when the current buffer is filled to prepare the next
|
||||
buffer pointer and its size. */
|
||||
void BSP_AUDIO_IN_TransferComplete_CallBack(void);
|
||||
void BSP_AUDIO_IN_HalfTransfer_CallBack(void);
|
||||
void BSP_AUDIO_IN_TransferComplete_CallBackEx(uint32_t InputDevice);
|
||||
void BSP_AUDIO_IN_HalfTransfer_CallBackEx(uint32_t InputDevice);
|
||||
|
||||
/* This function is called when an Interrupt due to transfer error on or peripheral
|
||||
error occurs. */
|
||||
void BSP_AUDIO_IN_Error_CallBack(void);
|
||||
|
||||
/* These function can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_AUDIO_IN_ClockConfig(uint32_t AudioFreq, void *Params);
|
||||
void BSP_AUDIO_IN_MspInit(void);
|
||||
void BSP_AUDIO_IN_MspDeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_AUDIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,238 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32h745i_discovery_lcd.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_LCD_H
|
||||
#define __STM32H745I_DISCOVERY_LCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Include LCD component Driver */
|
||||
/* LCD RK043FN48H-CT672B 4,3" 480x272 pixels */
|
||||
#include "../Components/rk043fn48h/rk043fn48h.h"
|
||||
|
||||
/* Include SDRAM Driver */
|
||||
#include "stm32h745i_discovery_sdram.h"
|
||||
|
||||
#include "stm32h745i_discovery.h"
|
||||
#include "../../../Utilities/Fonts/fonts.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LCD_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TextColor;
|
||||
uint32_t BackColor;
|
||||
sFONT *pFont;
|
||||
}LCD_DrawPropTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int16_t X;
|
||||
int16_t Y;
|
||||
}Point, * pPoint;
|
||||
|
||||
/**
|
||||
* @brief Line mode structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CENTER_MODE = 0x01, /* Center mode */
|
||||
RIGHT_MODE = 0x02, /* Right mode */
|
||||
LEFT_MODE = 0x03 /* Left mode */
|
||||
}Text_AlignModeTypdef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_LCD_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define MAX_LAYER_NUMBER ((uint32_t)2)
|
||||
|
||||
#define LCD_LayerCfgTypeDef LTDC_LayerCfgTypeDef
|
||||
|
||||
#define LTDC_ACTIVE_LAYER ((uint32_t)1) /* Layer 1 */
|
||||
/**
|
||||
* @brief LCD status structure definition
|
||||
*/
|
||||
#define LCD_OK ((uint8_t)0x00)
|
||||
#define LCD_ERROR ((uint8_t)0x01)
|
||||
#define LCD_TIMEOUT ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @brief LCD FB_StartAddress
|
||||
*/
|
||||
#define LCD_FB_START_ADDRESS ((uint32_t)0xD0000000)
|
||||
|
||||
/**
|
||||
* @brief LCD color
|
||||
*/
|
||||
#define LCD_COLOR_BLUE ((uint32_t)0xFF0000FF)
|
||||
#define LCD_COLOR_GREEN ((uint32_t)0xFF00FF00)
|
||||
#define LCD_COLOR_RED ((uint32_t)0xFFFF0000)
|
||||
#define LCD_COLOR_CYAN ((uint32_t)0xFF00FFFF)
|
||||
#define LCD_COLOR_MAGENTA ((uint32_t)0xFFFF00FF)
|
||||
#define LCD_COLOR_YELLOW ((uint32_t)0xFFFFFF00)
|
||||
#define LCD_COLOR_LIGHTBLUE ((uint32_t)0xFF8080FF)
|
||||
#define LCD_COLOR_LIGHTGREEN ((uint32_t)0xFF80FF80)
|
||||
#define LCD_COLOR_LIGHTRED ((uint32_t)0xFFFF8080)
|
||||
#define LCD_COLOR_LIGHTCYAN ((uint32_t)0xFF80FFFF)
|
||||
#define LCD_COLOR_LIGHTMAGENTA ((uint32_t)0xFFFF80FF)
|
||||
#define LCD_COLOR_LIGHTYELLOW ((uint32_t)0xFFFFFF80)
|
||||
#define LCD_COLOR_DARKBLUE ((uint32_t)0xFF000080)
|
||||
#define LCD_COLOR_DARKGREEN ((uint32_t)0xFF008000)
|
||||
#define LCD_COLOR_DARKRED ((uint32_t)0xFF800000)
|
||||
#define LCD_COLOR_DARKCYAN ((uint32_t)0xFF008080)
|
||||
#define LCD_COLOR_DARKMAGENTA ((uint32_t)0xFF800080)
|
||||
#define LCD_COLOR_DARKYELLOW ((uint32_t)0xFF808000)
|
||||
#define LCD_COLOR_WHITE ((uint32_t)0xFFFFFFFF)
|
||||
#define LCD_COLOR_LIGHTGRAY ((uint32_t)0xFFD3D3D3)
|
||||
#define LCD_COLOR_GRAY ((uint32_t)0xFF808080)
|
||||
#define LCD_COLOR_DARKGRAY ((uint32_t)0xFF404040)
|
||||
#define LCD_COLOR_BLACK ((uint32_t)0xFF000000)
|
||||
#define LCD_COLOR_BROWN ((uint32_t)0xFFA52A2A)
|
||||
#define LCD_COLOR_ORANGE ((uint32_t)0xFFFFA500)
|
||||
#define LCD_COLOR_TRANSPARENT ((uint32_t)0xFF000000)
|
||||
|
||||
/**
|
||||
* @brief LCD default font
|
||||
*/
|
||||
#define LCD_DEFAULT_FONT Font24
|
||||
|
||||
/**
|
||||
* @brief LCD Reload Types
|
||||
*/
|
||||
#define LCD_RELOAD_IMMEDIATE ((uint32_t)LTDC_SRCR_IMR)
|
||||
#define LCD_RELOAD_VERTICAL_BLANKING ((uint32_t)LTDC_SRCR_VBR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_LCD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_LCD_Init(void);
|
||||
uint8_t BSP_LCD_InitEx(uint32_t PclkConfig);
|
||||
|
||||
uint8_t BSP_LCD_DeInit(void);
|
||||
uint32_t BSP_LCD_GetXSize(void);
|
||||
uint32_t BSP_LCD_GetYSize(void);
|
||||
void BSP_LCD_SetXSize(uint32_t imageWidthPixels);
|
||||
void BSP_LCD_SetYSize(uint32_t imageHeightPixels);
|
||||
|
||||
/* Functions using the LTDC controller */
|
||||
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FrameBuffer);
|
||||
void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency);
|
||||
void BSP_LCD_SetTransparency_NoReload(uint32_t LayerIndex, uint8_t Transparency);
|
||||
void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address);
|
||||
void BSP_LCD_SetLayerAddress_NoReload(uint32_t LayerIndex, uint32_t Address);
|
||||
void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue);
|
||||
void BSP_LCD_SetColorKeying_NoReload(uint32_t LayerIndex, uint32_t RGBValue);
|
||||
void BSP_LCD_ResetColorKeying(uint32_t LayerIndex);
|
||||
void BSP_LCD_ResetColorKeying_NoReload(uint32_t LayerIndex);
|
||||
void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
|
||||
void BSP_LCD_SetLayerWindow_NoReload(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
|
||||
void BSP_LCD_SelectLayer(uint32_t LayerIndex);
|
||||
void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State);
|
||||
void BSP_LCD_SetLayerVisible_NoReload(uint32_t LayerIndex, FunctionalState State);
|
||||
void BSP_LCD_Relaod(uint32_t ReloadType);
|
||||
|
||||
void BSP_LCD_SetTextColor(uint32_t Color);
|
||||
uint32_t BSP_LCD_GetTextColor(void);
|
||||
void BSP_LCD_SetBackColor(uint32_t Color);
|
||||
uint32_t BSP_LCD_GetBackColor(void);
|
||||
void BSP_LCD_SetFont(sFONT *fonts);
|
||||
sFONT *BSP_LCD_GetFont(void);
|
||||
|
||||
uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos);
|
||||
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t pixel);
|
||||
void BSP_LCD_Clear(uint32_t Color);
|
||||
void BSP_LCD_ClearStringLine(uint32_t Line);
|
||||
void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr);
|
||||
void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode);
|
||||
void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii);
|
||||
|
||||
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
|
||||
void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
|
||||
void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
|
||||
void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
|
||||
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
|
||||
void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount);
|
||||
void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
|
||||
void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp);
|
||||
|
||||
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
|
||||
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
|
||||
void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount);
|
||||
void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
|
||||
|
||||
void BSP_LCD_DisplayOff(void);
|
||||
void BSP_LCD_DisplayOn(void);
|
||||
|
||||
void BSP_LCD_SetBrightness(uint8_t BrightnessValue);
|
||||
|
||||
/* These functions can be modified in case the current settings
|
||||
need to be changed for specific application needs */
|
||||
void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params);
|
||||
void BSP_LCD_MspDeInit(LTDC_HandleTypeDef *hltdc, void *Params);
|
||||
void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_LCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_mmc.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file includes the EMMC driver mounted on STM32H745I-DISCOVERY
|
||||
* board.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* File Info : -----------------------------------------------------------------
|
||||
User NOTES
|
||||
1. How To use this driver:
|
||||
--------------------------
|
||||
- This driver is used to drive the EMMC mounted on STM32H745I-DISCOVERY
|
||||
board.
|
||||
- This driver does not need a specific component driver for the EMMC device
|
||||
to be included with.
|
||||
|
||||
2. Driver description:
|
||||
---------------------
|
||||
+ Initialization steps:
|
||||
o Initialize the external EMMC memory using the BSP_MMC_Init() function. This
|
||||
function includes the MSP layer hardware resources initialization and the
|
||||
SDIO interface configuration to interface with the external EMMC. It
|
||||
also includes the EMMC initialization sequence.
|
||||
o The function BSP_MMC_GetCardInfo() is used to get the MMC information
|
||||
which is stored in the structure "HAL_MMC_CardInfoTypedef".
|
||||
|
||||
+ Micro MMC card operations
|
||||
o The micro MMC card can be accessed with read/write block(s) operations once
|
||||
it is ready for access. The access can be performed whether using the polling
|
||||
mode by calling the functions BSP_MMC_ReadBlocks()/BSP_MMC_WriteBlocks(), or by DMA
|
||||
transfer using the functions BSP_MMC_ReadBlocks_DMA()/BSP_MMC_WriteBlocks_DMA()
|
||||
o The DMA transfer complete is used with interrupt mode. Once the MMC transfer
|
||||
is complete, the MMC interrupt is handled using the function BSP_MMC_IRQHandler(),
|
||||
the DMA Tx/Rx transfer complete are handled using the functions
|
||||
MMC_DMA_Tx_IRQHandler()/MMC_DMA_Rx_IRQHandler() that should be defined by user.
|
||||
The corresponding user callbacks are implemented by the user at application level.
|
||||
o The MMC erase block(s) is performed using the function BSP_MMC_Erase() with specifying
|
||||
the number of blocks to erase.
|
||||
o The MMC runtime status is returned when calling the function BSP_MMC_GetStatus().
|
||||
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery_mmc.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_MMC STM32H745I_DISCOVERY_MMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Variables Exported Variables
|
||||
* @{
|
||||
*/
|
||||
MMC_HandleTypeDef uSdHandle;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the MMC card device.
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_Init(void)
|
||||
{
|
||||
uint8_t mmc_state = MMC_OK;
|
||||
|
||||
/* uMMC device interface configuration */
|
||||
uSdHandle.Instance = SDMMC1;
|
||||
|
||||
/* if CLKDIV = 0 then SDMMC Clock frequency = SDMMC Kernel Clock
|
||||
else SDMMC Clock frequency = SDMMC Kernel Clock / [2 * CLKDIV].
|
||||
*/
|
||||
uSdHandle.Init.ClockDiv = 2;
|
||||
uSdHandle.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
|
||||
uSdHandle.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
|
||||
uSdHandle.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
|
||||
uSdHandle.Init.BusWide = SDMMC_BUS_WIDE_8B;
|
||||
|
||||
/* Msp MMC initialization */
|
||||
BSP_MMC_MspInit(&uSdHandle, NULL);
|
||||
|
||||
/* HAL MMC initialization */
|
||||
if(HAL_MMC_Init(&uSdHandle) != HAL_OK)
|
||||
{
|
||||
mmc_state = MMC_ERROR;
|
||||
}
|
||||
|
||||
return mmc_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MMC card device.
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_DeInit(void)
|
||||
{
|
||||
uint8_t mmc_state = MMC_OK;
|
||||
|
||||
uSdHandle.Instance = SDMMC1;
|
||||
|
||||
/* HAL MMC deinitialization */
|
||||
if(HAL_MMC_DeInit(&uSdHandle) != HAL_OK)
|
||||
{
|
||||
mmc_state = MMC_ERROR;
|
||||
}
|
||||
|
||||
/* Msp MMC deinitialization */
|
||||
uSdHandle.Instance = SDMMC1;
|
||||
BSP_MMC_MspDeInit(&uSdHandle, NULL);
|
||||
|
||||
return mmc_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads block(s) from a specified address in an MMC card, in polling mode.
|
||||
* @param pData: Pointer to the buffer that will contain the data to transmit
|
||||
* @param ReadAddr: Address from where data is to be read
|
||||
* @param NumOfBlocks: Number of MMC blocks to read
|
||||
* @param Timeout: Timeout for read operation
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)
|
||||
{
|
||||
|
||||
if( HAL_MMC_ReadBlocks(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) == HAL_OK)
|
||||
{
|
||||
return MMC_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MMC_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes block(s) to a specified address in an MMC card, in polling mode.
|
||||
* @param pData: Pointer to the buffer that will contain the data to transmit
|
||||
* @param WriteAddr: Address from where data is to be written
|
||||
* @param NumOfBlocks: Number of MMC blocks to write
|
||||
* @param Timeout: Timeout for write operation
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)
|
||||
{
|
||||
|
||||
if( HAL_MMC_WriteBlocks(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) == HAL_OK)
|
||||
{
|
||||
return MMC_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MMC_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads block(s) from a specified address in an MMC card, in DMA mode.
|
||||
* @param pData: Pointer to the buffer that will contain the data to transmit
|
||||
* @param ReadAddr: Address from where data is to be read
|
||||
* @param NumOfBlocks: Number of MMC blocks to read
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
|
||||
{
|
||||
|
||||
if( HAL_MMC_ReadBlocks_DMA(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks) == HAL_OK)
|
||||
{
|
||||
return MMC_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MMC_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes block(s) to a specified address in an MMC card, in DMA mode.
|
||||
* @param pData: Pointer to the buffer that will contain the data to transmit
|
||||
* @param WriteAddr: Address from where data is to be written
|
||||
* @param NumOfBlocks: Number of MMC blocks to write
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
|
||||
{
|
||||
|
||||
if( HAL_MMC_WriteBlocks_DMA(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks) == HAL_OK)
|
||||
{
|
||||
return MMC_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MMC_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erases the specified memory area of the given MMC card.
|
||||
* @param StartAddr: Start byte address
|
||||
* @param EndAddr: End byte address
|
||||
* @retval MMC status
|
||||
*/
|
||||
uint8_t BSP_MMC_Erase(uint32_t StartAddr, uint32_t EndAddr)
|
||||
{
|
||||
|
||||
if( HAL_MMC_Erase(&uSdHandle, StartAddr, EndAddr) == HAL_OK)
|
||||
{
|
||||
return MMC_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MMC_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the MMC MSP.
|
||||
* @param hmmc: MMC handle
|
||||
* @param Params User parameters
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_MMC_MspInit(MMC_HandleTypeDef *hmmc, void *Params)
|
||||
{
|
||||
/* __weak function can be modified by the application */
|
||||
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
/* Enable SDIO clock */
|
||||
__HAL_RCC_SDMMC1_CLK_ENABLE();
|
||||
|
||||
/* Enable GPIOs clock */
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
|
||||
|
||||
/* Common GPIO configuration */
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Pull = GPIO_PULLUP;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
gpio_init_structure.Alternate = GPIO_AF12_SDIO1;
|
||||
|
||||
/* SDMMC GPIO CLKIN PB8, D0 PC8, D1 PC9, D2 PC10, D3 PC11, CK PC12, CMD PD2 */
|
||||
/* GPIOC configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
|
||||
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
|
||||
|
||||
/* GPIOD configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_2;
|
||||
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
|
||||
|
||||
gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9;
|
||||
HAL_GPIO_Init(GPIOB, &gpio_init_structure);
|
||||
|
||||
|
||||
/* NVIC configuration for SDIO interrupts */
|
||||
HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MMC MSP.
|
||||
* @param hmmc: MMC handle
|
||||
* @param Params User parameters
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_MMC_MspDeInit(MMC_HandleTypeDef *hmmc, void *Params)
|
||||
{
|
||||
/* Disable NVIC for SDIO interrupts */
|
||||
HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
|
||||
|
||||
/* DeInit GPIO pins can be done in the application
|
||||
(by surcharging this __weak function) */
|
||||
|
||||
/* Disable SDMMC1 clock */
|
||||
__HAL_RCC_SDMMC1_CLK_DISABLE();
|
||||
|
||||
/* GPIO pins clock and DMA clocks can be shut down in the application
|
||||
by surcharging this __weak function */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles MMC card interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_MMC_IRQHandler(void)
|
||||
{
|
||||
HAL_MMC_IRQHandler(&uSdHandle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the current MMC card data status.
|
||||
* @retval Data transfer state.
|
||||
* This value can be one of the following values:
|
||||
* @arg MMC_TRANSFER_OK: No data transfer is acting
|
||||
* @arg MMC_TRANSFER_BUSY: Data transfer is acting
|
||||
* @arg MMC_TRANSFER_ERROR: Data transfer error
|
||||
*/
|
||||
uint8_t BSP_MMC_GetCardState(void)
|
||||
{
|
||||
return((HAL_MMC_GetCardState(&uSdHandle) == HAL_MMC_CARD_TRANSFER ) ? MMC_TRANSFER_OK : MMC_TRANSFER_BUSY);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get MMC information about specific MMC card.
|
||||
* @param CardInfo: Pointer to HAL_MMC_CardInfoTypedef structure
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_MMC_GetCardInfo(BSP_MMC_CardInfo *CardInfo)
|
||||
{
|
||||
HAL_MMC_GetCardInfo(&uSdHandle, CardInfo);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC Abort callbacks
|
||||
* @param hmmc: MMC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
|
||||
{
|
||||
BSP_MMC_AbortCallback();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Tx Transfer completed callbacks
|
||||
* @param hmmc: MMC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
|
||||
{
|
||||
BSP_MMC_WriteCpltCallback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rx Transfer completed callbacks
|
||||
* @param hmmc: MMC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
|
||||
{
|
||||
BSP_MMC_ReadCpltCallback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP MMC Abort callbacks
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_MMC_AbortCallback(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP Tx Transfer completed callbacks
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_MMC_WriteCpltCallback(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP Rx Transfer completed callbacks
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_MMC_ReadCpltCallback(void)
|
||||
{
|
||||
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_mmc.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32h745i_discovery_mmc.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H745I_DISCOVERY_MMC_H
|
||||
#define STM32H745I_DISCOVERY_MMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "stm32h745i_discovery.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_MMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SD Card information structure
|
||||
*/
|
||||
#define BSP_MMC_CardInfo HAL_MMC_CardInfoTypeDef
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_MMC_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief SD status structure definition
|
||||
*/
|
||||
#define MMC_OK ((uint8_t)0x00)
|
||||
#define MMC_ERROR ((uint8_t)0x01)
|
||||
#define MMC_ERROR_MMC_NOT_PRESENT ((uint8_t)0x02)
|
||||
|
||||
/**
|
||||
* @brief MMC transfer state definition
|
||||
*/
|
||||
#define MMC_TRANSFER_OK ((uint8_t)0x00)
|
||||
#define MMC_TRANSFER_BUSY ((uint8_t)0x01)
|
||||
|
||||
|
||||
#define MMC_PRESENT ((uint8_t)0x01)
|
||||
#define MMC_NOT_PRESENT ((uint8_t)0x00)
|
||||
|
||||
#define MMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_MMC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_MMC_Init(void);
|
||||
uint8_t BSP_MMC_DeInit(void);
|
||||
uint8_t BSP_MMC_ITConfig(void);
|
||||
|
||||
uint8_t BSP_MMC_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
|
||||
uint8_t BSP_MMC_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
|
||||
uint8_t BSP_MMC_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);
|
||||
uint8_t BSP_MMC_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);
|
||||
uint8_t BSP_MMC_Erase(uint32_t StartAddr, uint32_t EndAddr);
|
||||
uint8_t BSP_MMC_GetCardState(void);
|
||||
void BSP_MMC_GetCardInfo(BSP_MMC_CardInfo *CardInfo);
|
||||
uint8_t BSP_MMC_IsDetected(void);
|
||||
void BSP_MMC_IRQHandler(void);
|
||||
|
||||
/* These functions can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_MMC_MspInit(MMC_HandleTypeDef *hmmc, void *Params);
|
||||
void BSP_MMC_MspDeInit(MMC_HandleTypeDef *hmmc, void *Params);
|
||||
void BSP_MMC_AbortCallback(void);
|
||||
void BSP_MMC_WriteCpltCallback(void);
|
||||
void BSP_MMC_ReadCpltCallback(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_MMC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,895 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_qspi.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file includes a standard driver for the MT25TL01G QSPI
|
||||
* memory mounted on STM32H745I-DISCOVERY board.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) This driver is used to drive the MT25TL01G QSPI external
|
||||
memory mounted on STM32H745I_DISCOVERY board.
|
||||
|
||||
(#) This driver need a specific component driver (MT25TL01G) to be included with.
|
||||
|
||||
(#) Initialization steps:
|
||||
(++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
|
||||
function includes the MSP layer hardware resources initialization and the
|
||||
QSPI interface with the external memory.
|
||||
|
||||
(#) QSPI memory operations
|
||||
(++) QSPI memory can be accessed with read/write operations once it is
|
||||
initialized.
|
||||
Read/write operation can be performed with AHB access using the functions
|
||||
BSP_QSPI_Read()/BSP_QSPI_Write().
|
||||
(++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
|
||||
(see the QSPI memory data sheet)
|
||||
(++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
|
||||
specifying the block address. You can perform an erase operation of the whole
|
||||
chip by calling the function BSP_QSPI_Erase_Chip().
|
||||
(++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
|
||||
(see the QSPI memory data sheet)
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery_qspi.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI STM32H745I_DISCOVERY_QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
QSPI_HandleTypeDef QSPIHandle;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI_Private_Functions Private Functions
|
||||
* @{
|
||||
*/
|
||||
static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
|
||||
static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi);
|
||||
static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
|
||||
static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
|
||||
static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the QSPI interface.
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_Init(void)
|
||||
{
|
||||
QSPIHandle.Instance = QUADSPI;
|
||||
|
||||
/* Call the DeInit function to reset the driver */
|
||||
if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* System level initialization */
|
||||
BSP_QSPI_MspInit(&QSPIHandle, NULL);
|
||||
|
||||
/* QSPI initialization */
|
||||
/* ClockPrescaler set to 1, so QSPI clock = 200MHz / (1+3) = 50MHz */
|
||||
QSPIHandle.Init.ClockPrescaler = 3;
|
||||
QSPIHandle.Init.FifoThreshold = 1;
|
||||
QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
||||
QSPIHandle.Init.FlashSize = POSITION_VAL(MT25TL01G_FLASH_SIZE) - 1;
|
||||
QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;
|
||||
QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
|
||||
QSPIHandle.Init.FlashID = QSPI_FLASH_ID_2;
|
||||
QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_ENABLE;
|
||||
|
||||
if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* QSPI memory reset */
|
||||
if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
/* Set the QSPI memory in 4-bytes address mode */
|
||||
if (QSPI_EnterFourBytesAddress(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
/* Configuration of the dummy cycles on QSPI memory side */
|
||||
if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-Initializes the QSPI interface.
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_DeInit(void)
|
||||
{
|
||||
QSPIHandle.Instance = QUADSPI;
|
||||
|
||||
/* Call the DeInit function to reset the driver */
|
||||
if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* System level De-initialization */
|
||||
BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data from the QSPI memory.
|
||||
* @param pData: Pointer to data to be read
|
||||
* @param ReadAddr: Read start address
|
||||
* @param Size: Size of data to read
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
/* Initialize the read command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */
|
||||
s_command.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||
s_command.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||
s_command.Address = ReadAddr;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;
|
||||
s_command.NbData = Size;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_ENABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the QSPI memory.
|
||||
* @param pData: Pointer to data to be written
|
||||
* @param WriteAddr: Write start address
|
||||
* @param Size: Size of data to write
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
uint32_t end_addr, current_size, current_addr;
|
||||
|
||||
/* Calculation of the size between the write address and the end of the page */
|
||||
current_size = MT25TL01G_PAGE_SIZE - (WriteAddr % MT25TL01G_PAGE_SIZE);
|
||||
|
||||
/* Check if the size of the data is less than the remaining place in the page */
|
||||
if (current_size > Size)
|
||||
{
|
||||
current_size = Size;
|
||||
}
|
||||
|
||||
/* Initialize the address variables */
|
||||
current_addr = WriteAddr;
|
||||
end_addr = WriteAddr + Size;
|
||||
|
||||
/* Initialize the program command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||
s_command.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Perform the write page by page */
|
||||
do
|
||||
{
|
||||
s_command.Address = current_addr;
|
||||
s_command.NbData = current_size;
|
||||
|
||||
/* Enable write operations */
|
||||
if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait for end of program */
|
||||
if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Update the address and size variables for next page programming */
|
||||
current_addr += current_size;
|
||||
pData += current_size;
|
||||
current_size = ((current_addr + MT25TL01G_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MT25TL01G_PAGE_SIZE;
|
||||
} while (current_addr < end_addr);
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erases the specified block of the QSPI memory.
|
||||
* @param BlockAddress: Block address to erase
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
/* Initialize the erase command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = SUBSECTOR_ERASE_4_BYTE_ADDR_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||
s_command.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||
s_command.Address = BlockAddress;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Enable write operations */
|
||||
if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Send the command */
|
||||
if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait for end of erase */
|
||||
if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Erases the entire QSPI memory.
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_Erase_Chip(void)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
/* Initialize the erase command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = DIE_ERASE_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Enable write operations */
|
||||
if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Send the command */
|
||||
if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait for end of erase */
|
||||
if (QSPI_AutoPollingMemReady(&QSPIHandle, MT25TL01G_DIE_ERASE_MAX_TIME) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads current status of the QSPI memory.
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_GetStatus(void)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
uint16_t reg;
|
||||
|
||||
/* Initialize the read flag status register command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.NbData = 1;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_QSPI_Receive(&QSPIHandle, (uint8_t*)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Check the value of the register */
|
||||
if ((reg & (MT25TL01G_FSR_PRERR | MT25TL01G_FSR_PGERR | MT25TL01G_FSR_ERERR)) != 0)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
else if ((reg & (MT25TL01G_FSR_PGSUS | MT25TL01G_FSR_ERSUS)) != 0)
|
||||
{
|
||||
return QSPI_SUSPENDED;
|
||||
}
|
||||
else if ((reg & MT25TL01G_FSR_READY) != 0)
|
||||
{
|
||||
return QSPI_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return QSPI_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the configuration of the QSPI memory.
|
||||
* @param pInfo: pointer on the configuration structure
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
|
||||
{
|
||||
/* Configure the structure with the memory configuration */
|
||||
pInfo->FlashSize = MT25TL01G_FLASH_SIZE;
|
||||
pInfo->EraseSectorSize = (2 * MT25TL01G_SUBSECTOR_SIZE);
|
||||
pInfo->ProgPageSize = MT25TL01G_PAGE_SIZE;
|
||||
pInfo->EraseSectorsNumber = (MT25TL01G_FLASH_SIZE/pInfo->EraseSectorSize);
|
||||
pInfo->ProgPagesNumber = (MT25TL01G_FLASH_SIZE/pInfo->ProgPageSize);
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the QSPI in memory-mapped mode
|
||||
* @retval QSPI memory status
|
||||
*/
|
||||
uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
|
||||
|
||||
/* Configure the command for the read instruction */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = QUAD_INOUT_FAST_READ_DTR_CMD; /* DTR QUAD INPUT/OUTPUT FAST READ and 4-BYTE DTR FAST READ commands */
|
||||
s_command.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||
s_command.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = MT25TL01G_DUMMY_CYCLES_READ_QUAD_DTR - 1;
|
||||
|
||||
s_command.DdrMode = QSPI_DDR_MODE_ENABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_HALF_CLK_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Configure the memory mapped mode */
|
||||
s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
|
||||
s_mem_mapped_cfg.TimeOutPeriod = 0;
|
||||
|
||||
if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief QSPI MSP Initialization
|
||||
* This function configures the hardware resources used in this example:
|
||||
* - Peripheral's clock enable
|
||||
* - Peripheral's GPIO Configuration
|
||||
* - NVIC configuration for QSPI interrupt
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
/*##-1- Enable peripherals and GPIO Clocks #################################*/
|
||||
/* Enable the QuadSPI memory interface clock */
|
||||
QSPI_CLK_ENABLE();
|
||||
/* Reset the QuadSPI memory interface */
|
||||
QSPI_FORCE_RESET();
|
||||
QSPI_RELEASE_RESET();
|
||||
/* Enable GPIO clocks */
|
||||
QSPI_CLK_GPIO_CLK_ENABLE();
|
||||
QSPI_BK1_CS_GPIO_CLK_ENABLE();
|
||||
QSPI_BK1_D0_GPIO_CLK_ENABLE();
|
||||
QSPI_BK1_D1_GPIO_CLK_ENABLE();
|
||||
QSPI_BK1_D2_GPIO_CLK_ENABLE();
|
||||
QSPI_BK1_D3_GPIO_CLK_ENABLE();
|
||||
|
||||
QSPI_BK2_CS_GPIO_CLK_ENABLE();
|
||||
QSPI_BK2_D0_GPIO_CLK_ENABLE();
|
||||
QSPI_BK2_D1_GPIO_CLK_ENABLE();
|
||||
QSPI_BK2_D2_GPIO_CLK_ENABLE();
|
||||
QSPI_BK2_D3_GPIO_CLK_ENABLE();
|
||||
|
||||
/*##-2- Configure peripheral GPIO ##########################################*/
|
||||
/* QSPI CLK GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_CLK_PIN;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
gpio_init_structure.Pull = GPIO_NOPULL;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* QSPI CS GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_BK1_CS_PIN;
|
||||
gpio_init_structure.Pull = GPIO_PULLUP;
|
||||
gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK1_CS_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* QSPI D0 GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_BK1_D0_PIN;
|
||||
gpio_init_structure.Pull = GPIO_NOPULL;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK1_D0_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
gpio_init_structure.Pin = QSPI_BK2_D0_PIN;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK2_D0_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* QSPI D1 GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_BK1_D1_PIN;
|
||||
gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK1_D1_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
gpio_init_structure.Pin = QSPI_BK2_D1_PIN;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK2_D1_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* QSPI D2 GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_BK1_D2_PIN;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
||||
HAL_GPIO_Init(QSPI_BK1_D2_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
gpio_init_structure.Pin = QSPI_BK2_D2_PIN;
|
||||
HAL_GPIO_Init(QSPI_BK2_D2_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* QSPI D3 GPIO pin configuration */
|
||||
gpio_init_structure.Pin = QSPI_BK1_D3_PIN;
|
||||
HAL_GPIO_Init(QSPI_BK1_D3_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
gpio_init_structure.Pin = QSPI_BK2_D3_PIN;
|
||||
HAL_GPIO_Init(QSPI_BK2_D3_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/*##-3- Configure the NVIC for QSPI #########################################*/
|
||||
/* NVIC configuration for QSPI interrupt */
|
||||
HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief QSPI MSP De-Initialization
|
||||
* This function frees the hardware resources used in this example:
|
||||
* - Disable the Peripheral's clock
|
||||
* - Revert GPIO and NVIC configuration to their default state
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
|
||||
{
|
||||
/*##-1- Disable the NVIC for QSPI ###########################################*/
|
||||
HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
|
||||
|
||||
/*##-2- Disable peripherals and GPIO Clocks ################################*/
|
||||
/* De-Configure QSPI pins */
|
||||
HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK1_CS_GPIO_PORT, QSPI_BK1_CS_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK1_D0_GPIO_PORT, QSPI_BK1_D0_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK1_D1_GPIO_PORT, QSPI_BK1_D1_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK1_D2_GPIO_PORT, QSPI_BK1_D2_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK1_D3_GPIO_PORT, QSPI_BK1_D3_PIN);
|
||||
|
||||
HAL_GPIO_DeInit(QSPI_BK2_CS_GPIO_PORT, QSPI_BK2_CS_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK2_D0_GPIO_PORT, QSPI_BK2_D0_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK2_D1_GPIO_PORT, QSPI_BK2_D1_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK2_D2_GPIO_PORT, QSPI_BK2_D2_PIN);
|
||||
HAL_GPIO_DeInit(QSPI_BK2_D3_GPIO_PORT, QSPI_BK2_D3_PIN);
|
||||
|
||||
/*##-3- Reset peripherals ##################################################*/
|
||||
/* Reset the QuadSPI memory interface */
|
||||
QSPI_FORCE_RESET();
|
||||
QSPI_RELEASE_RESET();
|
||||
|
||||
/* Disable the QuadSPI memory interface clock */
|
||||
QSPI_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_QSPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function reset the QSPI memory.
|
||||
* @param hqspi: QSPI handle
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
/* Initialize the reset enable command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
|
||||
s_command.Instruction = RESET_ENABLE_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Send the command */
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Send the reset memory command */
|
||||
s_command.Instruction = RESET_MEMORY_CMD;
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = RESET_ENABLE_CMD;
|
||||
/* Send the command */
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Send the reset memory command */
|
||||
s_command.Instruction = RESET_MEMORY_CMD;
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Enter QSPI memory in QPI mode */
|
||||
if(QSPI_EnterQPI(&QSPIHandle) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait the memory is ready */
|
||||
if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function set the QSPI memory in 4-byte address mode
|
||||
* @param hqspi: QSPI handle
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
/* Initialize the command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Enable write operations */
|
||||
if (QSPI_WriteEnable(hqspi) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Send the command */
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait the memory is ready */
|
||||
if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configure the dummy cycles on memory side.
|
||||
* @param hqspi: QSPI handle
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
uint16_t reg = 0;
|
||||
|
||||
/* Initialize the read volatile configuration register command */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = READ_VOL_CFG_REG_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.NbData = 2;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_QSPI_Receive(hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Enable write operations */
|
||||
if (QSPI_WriteEnable(hqspi) != QSPI_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Update volatile configuration register (with new dummy cycles) */
|
||||
s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
|
||||
MODIFY_REG(reg, 0xF0F0, ((MT25TL01G_DUMMY_CYCLES_READ_QUAD << 4) |
|
||||
(MT25TL01G_DUMMY_CYCLES_READ_QUAD << 12)));
|
||||
|
||||
/* Configure the write volatile configuration register command */
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_QSPI_Transmit(hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function send a Write Enable and wait it is effective.
|
||||
* @param hqspi: QSPI handle
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
QSPI_AutoPollingTypeDef s_config;
|
||||
|
||||
/* Enable write operations */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = WRITE_ENABLE_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
/* Configure automatic polling mode to wait for write enabling */
|
||||
s_config.Match = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
|
||||
s_config.Mask = MT25TL01G_SR_WREN | (MT25TL01G_SR_WREN << 8);
|
||||
s_config.MatchMode = QSPI_MATCH_MODE_AND;
|
||||
s_config.StatusBytesSize = 2;
|
||||
s_config.Interval = 0x10;
|
||||
s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
|
||||
|
||||
s_command.Instruction = READ_STATUS_REG_CMD;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
|
||||
if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function read the SR of the memory and wait the EOP.
|
||||
* @param hqspi QSPI handle
|
||||
* @param Timeout Autopolling timeout
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
QSPI_AutoPollingTypeDef s_config;
|
||||
|
||||
/* Configure automatic polling mode to wait for memory ready */
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
s_command.Instruction = READ_STATUS_REG_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_4_LINES;
|
||||
s_command.DummyCycles = 2;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
s_config.Match = 0;
|
||||
s_config.MatchMode = QSPI_MATCH_MODE_AND;
|
||||
s_config.Interval = 0x10;
|
||||
s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
|
||||
s_config.Mask = MT25TL01G_SR_WIP | (MT25TL01G_SR_WIP <<8);
|
||||
s_config.StatusBytesSize = 2;
|
||||
|
||||
if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enter the QPSI memory in QPI mode
|
||||
* @param hqspi QSPI handle
|
||||
* @retval QSPI status
|
||||
*/
|
||||
static uint8_t QSPI_EnterQPI(QSPI_HandleTypeDef *hqspi)
|
||||
{
|
||||
QSPI_CommandTypeDef s_command;
|
||||
|
||||
s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
|
||||
s_command.Instruction = ENTER_QUAD_CMD;
|
||||
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
||||
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
s_command.DataMode = QSPI_DATA_NONE;
|
||||
s_command.DummyCycles = 0;
|
||||
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
|
||||
if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return QSPI_ERROR;
|
||||
}
|
||||
|
||||
return QSPI_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32H745i_discovery_qspi.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_QSPI_H
|
||||
#define __STM32H745I_DISCOVERY_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "../Components/mt25tl01g/mt25tl01g.h"
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* QSPI Error codes */
|
||||
#define QSPI_OK ((uint8_t)0x00)
|
||||
#define QSPI_ERROR ((uint8_t)0x01)
|
||||
#define QSPI_BUSY ((uint8_t)0x02)
|
||||
#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
|
||||
#define QSPI_SUSPENDED ((uint8_t)0x08)
|
||||
|
||||
|
||||
/* Definition for QSPI clock resources */
|
||||
#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
|
||||
#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
|
||||
#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
||||
#define QSPI_BK1_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
||||
#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
||||
#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
||||
#define QSPI_BK2_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define QSPI_BK2_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
|
||||
#define QSPI_BK2_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
|
||||
#define QSPI_BK2_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define QSPI_BK2_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
|
||||
|
||||
#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
|
||||
#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
|
||||
|
||||
/* Definition for QSPI Pins */
|
||||
#define QSPI_CLK_PIN GPIO_PIN_10
|
||||
#define QSPI_CLK_GPIO_PORT GPIOF
|
||||
/* Bank 1 */
|
||||
#define QSPI_BK1_CS_PIN GPIO_PIN_6
|
||||
#define QSPI_BK1_CS_GPIO_PORT GPIOG
|
||||
#define QSPI_BK1_D0_PIN GPIO_PIN_11
|
||||
#define QSPI_BK1_D0_GPIO_PORT GPIOD
|
||||
#define QSPI_BK1_D1_PIN GPIO_PIN_9
|
||||
#define QSPI_BK1_D1_GPIO_PORT GPIOF
|
||||
#define QSPI_BK1_D2_PIN GPIO_PIN_7
|
||||
#define QSPI_BK1_D2_GPIO_PORT GPIOF
|
||||
#define QSPI_BK1_D3_PIN GPIO_PIN_6
|
||||
#define QSPI_BK1_D3_GPIO_PORT GPIOF
|
||||
|
||||
/* Bank 2 */
|
||||
#define QSPI_BK2_CS_PIN GPIO_PIN_6
|
||||
#define QSPI_BK2_CS_GPIO_PORT GPIOG
|
||||
#define QSPI_BK2_D0_PIN GPIO_PIN_2
|
||||
#define QSPI_BK2_D0_GPIO_PORT GPIOH
|
||||
#define QSPI_BK2_D1_PIN GPIO_PIN_3
|
||||
#define QSPI_BK2_D1_GPIO_PORT GPIOH
|
||||
#define QSPI_BK2_D2_PIN GPIO_PIN_9
|
||||
#define QSPI_BK2_D2_GPIO_PORT GPIOG
|
||||
#define QSPI_BK2_D3_PIN GPIO_PIN_14
|
||||
#define QSPI_BK2_D3_GPIO_PORT GPIOG
|
||||
|
||||
|
||||
/* MT25TL01G Micron memory */
|
||||
/* Size of the flash */
|
||||
#define QSPI_FLASH_SIZE 26 /* Address bus width to access whole memory space */
|
||||
#define QSPI_PAGE_SIZE 256
|
||||
|
||||
/* QSPI Base Address */
|
||||
#define QSPI_BASE_ADDRESS 0x90000000
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup STM32H745I_DISCOVERY_QSPI_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
/* QSPI Info */
|
||||
typedef struct {
|
||||
uint32_t FlashSize; /*!< Size of the flash */
|
||||
uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
|
||||
uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
|
||||
uint32_t ProgPageSize; /*!< Size of pages for the program operation */
|
||||
uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
|
||||
} QSPI_Info;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup STM32H745I_DISCOVERY_QSPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_QSPI_Init (void);
|
||||
uint8_t BSP_QSPI_DeInit (void);
|
||||
uint8_t BSP_QSPI_Read (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
|
||||
uint8_t BSP_QSPI_Write (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
|
||||
uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
|
||||
uint8_t BSP_QSPI_Erase_Chip (void);
|
||||
uint8_t BSP_QSPI_GetStatus (void);
|
||||
uint8_t BSP_QSPI_GetInfo (QSPI_Info* pInfo);
|
||||
uint8_t BSP_QSPI_EnableMemoryMappedMode(void);
|
||||
|
||||
/* These functions can be modified in case the current settings
|
||||
need to be changed for specific application needs */
|
||||
void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);
|
||||
void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_QSPI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,445 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_sdram.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-6A memory
|
||||
* device mounted on STM32H745I_DISCOVERY boards.
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
How To use this driver:
|
||||
-----------------------
|
||||
- This driver is used to drive the MT48LC4M32B2B5-6A SDRAM external memory mounted
|
||||
on STM32H745I_DISCOVERY board.
|
||||
- This driver does not need a specific component driver for the SDRAM device
|
||||
to be included with.
|
||||
|
||||
Driver description:
|
||||
------------------
|
||||
+ Initialization steps:
|
||||
o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
|
||||
function includes the MSP layer hardware resources initialization and the
|
||||
FMC controller configuration to interface with the external SDRAM memory.
|
||||
o It contains the SDRAM initialization sequence to program the SDRAM external
|
||||
device using the function BSP_SDRAM_Initialization_sequence(). Note that this
|
||||
sequence is standard for all SDRAM devices, but can include some differences
|
||||
from a device to another. If it is the case, the right sequence should be
|
||||
implemented separately.
|
||||
|
||||
+ SDRAM read/write operations
|
||||
o SDRAM external memory can be accessed with read/write operations once it is
|
||||
initialized.
|
||||
Read/write operation can be performed with AHB access using the functions
|
||||
BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by MDMA transfer using the functions
|
||||
BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
|
||||
o The AHB access is performed with 32-bit width transaction, the MDMA transfer
|
||||
configuration is fixed at single (no burst) word transfer (see the
|
||||
SDRAM_MspInit() static function).
|
||||
o User can implement his own functions for read/write access with his desired
|
||||
configurations.
|
||||
o If interrupt mode is used for MDMA transfer, the function BSP_SDRAM_MDMA_IRQHandler()
|
||||
is called in IRQ handler file, to serve the generated interrupt once the MDMA
|
||||
transfer is complete.
|
||||
o You can send a command to the SDRAM device in runtime using the function
|
||||
BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
|
||||
the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery_sdram.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_SDRAM STM32H745I_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_SDRAM_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
SDRAM_HandleTypeDef sdramHandle;
|
||||
static FMC_SDRAM_TimingTypeDef Timing;
|
||||
static FMC_SDRAM_CommandTypeDef Command;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDRAM device.
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void)
|
||||
{
|
||||
static uint8_t sdramstatus = SDRAM_OK;
|
||||
/* SDRAM device configuration */
|
||||
sdramHandle.Instance = FMC_SDRAM_DEVICE;
|
||||
|
||||
/* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */
|
||||
Timing.LoadToActiveDelay = 2;
|
||||
Timing.ExitSelfRefreshDelay = 7;
|
||||
Timing.SelfRefreshTime = 4;
|
||||
Timing.RowCycleDelay = 7;
|
||||
Timing.WriteRecoveryTime = 2;
|
||||
Timing.RPDelay = 2;
|
||||
Timing.RCDDelay = 2;
|
||||
|
||||
sdramHandle.Init.SDBank = FMC_SDRAM_BANK2;
|
||||
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
||||
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
||||
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
|
||||
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
||||
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
|
||||
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
||||
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
|
||||
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
|
||||
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
|
||||
|
||||
/* SDRAM controller initialization */
|
||||
|
||||
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
|
||||
|
||||
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
|
||||
{
|
||||
sdramstatus = SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SDRAM initialization sequence */
|
||||
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
|
||||
}
|
||||
|
||||
return sdramstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the SDRAM device.
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_DeInit(void)
|
||||
{
|
||||
static uint8_t sdramstatus = SDRAM_OK;
|
||||
/* SDRAM device de-initialization */
|
||||
sdramHandle.Instance = FMC_SDRAM_DEVICE;
|
||||
|
||||
if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
|
||||
{
|
||||
sdramstatus = SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SDRAM controller de-initialization */
|
||||
BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
|
||||
}
|
||||
|
||||
return sdramstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs the SDRAM device.
|
||||
* @param RefreshCount: SDRAM refresh counter value
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
|
||||
{
|
||||
__IO uint32_t tmpmrd = 0;
|
||||
|
||||
/* Step 1: Configure a clock configuration enable command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 2: Insert 100 us minimum delay */
|
||||
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Step 3: Configure a PALL (precharge all) command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_PALL;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 4: Configure an Auto Refresh command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
|
||||
Command.AutoRefreshNumber = 8;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 5: Program the external memory mode register */
|
||||
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
|
||||
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
|
||||
SDRAM_MODEREG_CAS_LATENCY_3 |\
|
||||
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
|
||||
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
|
||||
|
||||
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = tmpmrd;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 6: Set the refresh rate counter */
|
||||
/* Set the device refresh rate */
|
||||
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data from the SDRAM memory in polling mode.
|
||||
* @param uwStartAddress: Read start address
|
||||
* @param pData: Pointer to data to be read
|
||||
* @param uwDataSize: Size of read data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data from the SDRAM memory in DMA mode.
|
||||
* @param uwStartAddress: Read start address
|
||||
* @param pData: Pointer to data to be read
|
||||
* @param uwDataSize: Size of read data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the SDRAM memory in polling mode.
|
||||
* @param uwStartAddress: Write start address
|
||||
* @param pData: Pointer to data to be written
|
||||
* @param uwDataSize: Size of written data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the SDRAM memory in DMA mode.
|
||||
* @param uwStartAddress: Write start address
|
||||
* @param pData: Pointer to data to be written
|
||||
* @param uwDataSize: Size of written data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends command to the SDRAM bank.
|
||||
* @param SdramCmd: Pointer to SDRAM command structure
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
|
||||
{
|
||||
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes SDRAM MSP.
|
||||
* @param hsdram SDRAM handle
|
||||
* @param Params User parameters
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
|
||||
{
|
||||
static MDMA_HandleTypeDef mdma_handle;
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
/* Enable FMC clock */
|
||||
__HAL_RCC_FMC_CLK_ENABLE();
|
||||
|
||||
/* Enable chosen MDMAx clock */
|
||||
__MDMAx_CLK_ENABLE();
|
||||
|
||||
/* Enable GPIOs clock */
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
|
||||
/* Common GPIO configuration */
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Pull = GPIO_PULLUP;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
gpio_init_structure.Alternate = GPIO_AF12_FMC;
|
||||
|
||||
/* GPIOD configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
|
||||
GPIO_PIN_14 | GPIO_PIN_15;
|
||||
|
||||
|
||||
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
|
||||
|
||||
/* GPIOE configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
|
||||
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||||
GPIO_PIN_15;
|
||||
|
||||
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
||||
|
||||
/* GPIOF configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
|
||||
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||||
GPIO_PIN_15;
|
||||
|
||||
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
|
||||
|
||||
/* GPIOG configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
|
||||
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
||||
|
||||
/* GPIOH configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 ;
|
||||
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
|
||||
|
||||
|
||||
|
||||
/* Configure common MDMA parameters */
|
||||
mdma_handle.Init.Request = MDMA_REQUEST_SW;
|
||||
mdma_handle.Init.TransferTriggerMode = MDMA_BLOCK_TRANSFER;
|
||||
mdma_handle.Init.Priority = MDMA_PRIORITY_HIGH;
|
||||
mdma_handle.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
|
||||
mdma_handle.Init.SourceInc = MDMA_SRC_INC_WORD;
|
||||
mdma_handle.Init.DestinationInc = MDMA_DEST_INC_WORD;
|
||||
mdma_handle.Init.SourceDataSize = MDMA_SRC_DATASIZE_WORD;
|
||||
mdma_handle.Init.DestDataSize = MDMA_DEST_DATASIZE_WORD;
|
||||
mdma_handle.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
|
||||
mdma_handle.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
|
||||
mdma_handle.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
|
||||
mdma_handle.Init.BufferTransferLength = 128;
|
||||
mdma_handle.Init.SourceBlockAddressOffset = 0;
|
||||
mdma_handle.Init.DestBlockAddressOffset = 0;
|
||||
|
||||
|
||||
mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
|
||||
|
||||
/* Associate the DMA handle */
|
||||
__HAL_LINKDMA(hsdram, hmdma, mdma_handle);
|
||||
|
||||
/* Deinitialize the stream for new transfer */
|
||||
HAL_MDMA_DeInit(&mdma_handle);
|
||||
|
||||
/* Configure the DMA stream */
|
||||
HAL_MDMA_Init(&mdma_handle);
|
||||
|
||||
/* NVIC configuration for DMA transfer complete interrupt */
|
||||
HAL_NVIC_SetPriority(SDRAM_MDMAx_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(SDRAM_MDMAx_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes SDRAM MSP.
|
||||
* @param hsdram SDRAM handle
|
||||
* @param Params User parameters
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
|
||||
{
|
||||
static MDMA_HandleTypeDef mdma_handle;
|
||||
|
||||
/* Disable NVIC configuration for DMA interrupt */
|
||||
HAL_NVIC_DisableIRQ(SDRAM_MDMAx_IRQn);
|
||||
|
||||
/* Deinitialize the stream for new transfer */
|
||||
mdma_handle.Instance = SDRAM_MDMAx_CHANNEL;
|
||||
HAL_MDMA_DeInit(&mdma_handle);
|
||||
|
||||
/* GPIO pins clock, FMC clock and MDMA clock can be shut down in the applications
|
||||
by surcharging this __weak function */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_sdram.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32h745i_discovery_sdram.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_SDRAM_H
|
||||
#define __STM32H745I_DISCOVERY_SDRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SDRAM status structure definition
|
||||
*/
|
||||
#define SDRAM_OK ((uint8_t)0x00)
|
||||
#define SDRAM_ERROR ((uint8_t)0x01)
|
||||
|
||||
#define SDRAM_DEVICE_ADDR ((uint32_t)0xD0000000)
|
||||
#define SDRAM_DEVICE_SIZE ((uint32_t)0x2000000) /* SDRAM device size in MBytes */
|
||||
|
||||
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
|
||||
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
|
||||
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32 */
|
||||
|
||||
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
|
||||
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
|
||||
|
||||
#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
|
||||
|
||||
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
|
||||
|
||||
/* DMA definitions for SDRAM DMA transfer */
|
||||
#define __MDMAx_CLK_ENABLE __HAL_RCC_MDMA_CLK_ENABLE
|
||||
#define __MDMAx_CLK_DISABLE __HAL_RCC_MDMA_CLK_DISABLE
|
||||
#define SDRAM_MDMAx_CHANNEL MDMA_Channel0
|
||||
#define SDRAM_MDMAx_IRQn MDMA_IRQn
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Mode definition register defines
|
||||
*/
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_SDRAM_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void);
|
||||
uint8_t BSP_SDRAM_DeInit(void);
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
|
||||
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
|
||||
|
||||
/* These functions can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_SDRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,417 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_ts.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the Touch
|
||||
* Screen on STM32H745I_DISCOVERY discovery board.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/*
|
||||
@verbatim
|
||||
1. How To use this driver:
|
||||
--------------------------
|
||||
- This driver is used to drive the touch screen module of the STM32H745I_Discovery
|
||||
board on the RK043FN48H-CT672B 480x272 LCD screen with capacitive touch screen.
|
||||
- The FT5336 component driver must be included in project files according to
|
||||
the touch screen driver present on this board.
|
||||
|
||||
2. Driver description:
|
||||
---------------------
|
||||
+ Initialization steps:
|
||||
o Initialize the TS module using the BSP_TS_Init() function. This
|
||||
function includes the MSP layer hardware resources initialization and the
|
||||
communication layer configuration to start the TS use. The LCD size properties
|
||||
(x and y) are passed as parameters.
|
||||
o If TS interrupt mode is desired, you must configure the TS interrupt mode
|
||||
by calling the function BSP_TS_ITConfig(). The TS interrupt mode is generated
|
||||
as an external interrupt whenever a touch is detected.
|
||||
The interrupt mode internally uses the IO functionalities driver driven by
|
||||
the IO expander, to configure the IT line.
|
||||
|
||||
+ Touch screen use
|
||||
o The touch screen state is captured whenever the function BSP_TS_GetState() is
|
||||
used. This function returns information about the last LCD touch occurred
|
||||
in the TS_StateTypeDef structure.
|
||||
o If TS interrupt mode is used, the function BSP_TS_ITGetStatus() is needed to get
|
||||
the interrupt status. To clear the IT pending bits, you should call the
|
||||
function BSP_TS_ITClear().
|
||||
o The IT is handled using the corresponding external interrupt IRQ handler,
|
||||
the user IT callback treatment is implemented on the same external interrupt
|
||||
callback.
|
||||
*/
|
||||
|
||||
/* Dependencies
|
||||
- stm32h745_discovery_lcd.c
|
||||
- ft5336.c
|
||||
EndDependencies */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery.h"
|
||||
#include "stm32h745i_discovery_ts.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS STM32H745I_DISCOVERY_TS
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
static TS_DrvTypeDef *tsDriver;
|
||||
static uint16_t tsXBoundary, tsYBoundary;
|
||||
static uint8_t tsOrientation;
|
||||
static uint8_t I2cAddress;
|
||||
|
||||
/* Table for touchscreen event information display on LCD : table indexed on enum @ref TS_TouchEventTypeDef information */
|
||||
char * ts_event_string_tab[TOUCH_EVENT_NB_MAX] = { "None",
|
||||
"Press down",
|
||||
"Lift up",
|
||||
"Contact"
|
||||
};
|
||||
|
||||
/* Table for touchscreen gesture Id information display on LCD : table indexed on enum @ref TS_GestureIdTypeDef information */
|
||||
char * ts_gesture_id_string_tab[GEST_ID_NB_MAX] = { "None",
|
||||
"Move Up",
|
||||
"Move Right",
|
||||
"Move Down",
|
||||
"Move Left",
|
||||
"Zoom In",
|
||||
"Zoom Out"
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Private_Function_Prototypes Private Function Prototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the touch screen functionalities and
|
||||
* configures all necessary hardware resources (GPIOs, I2C, clocks..).
|
||||
* @param ts_SizeX: Maximum X size of the TS area on LCD
|
||||
* @param ts_SizeY: Maximum Y size of the TS area on LCD
|
||||
* @retval TS_OK if all initializations are OK. Other value if error.
|
||||
*/
|
||||
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
|
||||
{
|
||||
uint8_t status = TS_OK;
|
||||
tsXBoundary = ts_SizeX;
|
||||
tsYBoundary = ts_SizeY;
|
||||
|
||||
/* Read ID and verify if the touch screen driver is ready */
|
||||
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
|
||||
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
|
||||
{
|
||||
/* Initialize the TS driver structure */
|
||||
tsDriver = &ft5336_ts_drv;
|
||||
I2cAddress = TS_I2C_ADDRESS;
|
||||
tsOrientation = TS_SWAP_XY;
|
||||
|
||||
/* Initialize the TS driver */
|
||||
tsDriver->Start(I2cAddress);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = TS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the TouchScreen.
|
||||
* @retval TS state
|
||||
*/
|
||||
uint8_t BSP_TS_DeInit(void)
|
||||
{
|
||||
/* Actually ts_driver does not provide a DeInit function */
|
||||
return TS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and enables the touch screen interrupts.
|
||||
* @retval TS_OK if all initializations are OK. Other value if error.
|
||||
*/
|
||||
uint8_t BSP_TS_ITConfig(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
/* Configure Interrupt mode for SD detection pin */
|
||||
gpio_init_structure.Pin = TS_INT_PIN;
|
||||
gpio_init_structure.Pull = GPIO_NOPULL;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
gpio_init_structure.Mode = GPIO_MODE_IT_RISING;
|
||||
HAL_GPIO_Init(TS_INT_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
/* Enable and set Touch screen EXTI Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority((IRQn_Type)(TS_INT_EXTI_IRQn), 0x0F, 0x00);
|
||||
HAL_NVIC_EnableIRQ((IRQn_Type)(TS_INT_EXTI_IRQn));
|
||||
|
||||
/* Enable the TS ITs */
|
||||
tsDriver->EnableIT(I2cAddress);
|
||||
|
||||
return TS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the touch screen interrupt status.
|
||||
* @retval TS_OK if all initializations are OK. Other value if error.
|
||||
*/
|
||||
uint8_t BSP_TS_ITGetStatus(void)
|
||||
{
|
||||
/* Return the TS IT status */
|
||||
return (tsDriver->GetITStatus(I2cAddress));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns status and positions of the touch screen.
|
||||
* @param TS_State: Pointer to touch screen current state structure
|
||||
* @retval TS_OK if all initializations are OK. Other value if error.
|
||||
*/
|
||||
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
|
||||
{
|
||||
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
|
||||
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
|
||||
uint8_t ts_status = TS_OK;
|
||||
uint16_t x[TS_MAX_NB_TOUCH];
|
||||
uint16_t y[TS_MAX_NB_TOUCH];
|
||||
uint16_t brute_x[TS_MAX_NB_TOUCH];
|
||||
uint16_t brute_y[TS_MAX_NB_TOUCH];
|
||||
uint16_t x_diff;
|
||||
uint16_t y_diff;
|
||||
uint32_t index;
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
uint32_t weight = 0;
|
||||
uint32_t area = 0;
|
||||
uint32_t event = 0;
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
/* Check and update the number of touches active detected */
|
||||
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
|
||||
|
||||
if(TS_State->touchDetected)
|
||||
{
|
||||
for(index=0; index < TS_State->touchDetected; index++)
|
||||
{
|
||||
/* Get each touch coordinates */
|
||||
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
|
||||
|
||||
if(tsOrientation == TS_SWAP_NONE)
|
||||
{
|
||||
x[index] = brute_x[index];
|
||||
y[index] = brute_y[index];
|
||||
}
|
||||
|
||||
if(tsOrientation & TS_SWAP_X)
|
||||
{
|
||||
x[index] = 4096 - brute_x[index];
|
||||
}
|
||||
|
||||
if(tsOrientation & TS_SWAP_Y)
|
||||
{
|
||||
y[index] = 4096 - brute_y[index];
|
||||
}
|
||||
|
||||
if(tsOrientation & TS_SWAP_XY)
|
||||
{
|
||||
y[index] = brute_x[index];
|
||||
x[index] = brute_y[index];
|
||||
}
|
||||
|
||||
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
|
||||
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
|
||||
|
||||
if ((x_diff + y_diff) > 5)
|
||||
{
|
||||
_x[index] = x[index];
|
||||
_y[index] = y[index];
|
||||
}
|
||||
|
||||
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
|
||||
{
|
||||
TS_State->touchX[index] = x[index];
|
||||
TS_State->touchY[index] = y[index];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
|
||||
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
|
||||
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
|
||||
}
|
||||
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
|
||||
/* Get touch info related to the current touch */
|
||||
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
|
||||
|
||||
/* Update TS_State structure */
|
||||
TS_State->touchWeight[index] = weight;
|
||||
TS_State->touchArea[index] = area;
|
||||
|
||||
/* Remap touch event */
|
||||
switch(event)
|
||||
{
|
||||
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
|
||||
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
|
||||
break;
|
||||
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
|
||||
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
|
||||
break;
|
||||
case FT5336_TOUCH_EVT_FLAG_CONTACT :
|
||||
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
|
||||
break;
|
||||
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
|
||||
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
|
||||
break;
|
||||
default :
|
||||
ts_status = TS_ERROR;
|
||||
break;
|
||||
} /* of switch(event) */
|
||||
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
} /* of for(index=0; index < TS_State->touchDetected; index++) */
|
||||
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
/* Get gesture Id */
|
||||
ts_status = BSP_TS_Get_GestureId(TS_State);
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
} /* end of if(TS_State->touchDetected != 0) */
|
||||
|
||||
return (ts_status);
|
||||
}
|
||||
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
/**
|
||||
* @brief Update gesture Id following a touch detected.
|
||||
* @param TS_State: Pointer to touch screen current state structure
|
||||
* @retval TS_OK if all initializations are OK. Other value if error.
|
||||
*/
|
||||
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
|
||||
{
|
||||
uint32_t gestureId = 0;
|
||||
uint8_t ts_status = TS_OK;
|
||||
|
||||
/* Get gesture Id */
|
||||
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
|
||||
|
||||
/* Remap gesture Id to a TS_GestureIdTypeDef value */
|
||||
switch(gestureId)
|
||||
{
|
||||
case FT5336_GEST_ID_NO_GESTURE :
|
||||
TS_State->gestureId = GEST_ID_NO_GESTURE;
|
||||
break;
|
||||
case FT5336_GEST_ID_MOVE_UP :
|
||||
TS_State->gestureId = GEST_ID_MOVE_UP;
|
||||
break;
|
||||
case FT5336_GEST_ID_MOVE_RIGHT :
|
||||
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
|
||||
break;
|
||||
case FT5336_GEST_ID_MOVE_DOWN :
|
||||
TS_State->gestureId = GEST_ID_MOVE_DOWN;
|
||||
break;
|
||||
case FT5336_GEST_ID_MOVE_LEFT :
|
||||
TS_State->gestureId = GEST_ID_MOVE_LEFT;
|
||||
break;
|
||||
case FT5336_GEST_ID_ZOOM_IN :
|
||||
TS_State->gestureId = GEST_ID_ZOOM_IN;
|
||||
break;
|
||||
case FT5336_GEST_ID_ZOOM_OUT :
|
||||
TS_State->gestureId = GEST_ID_ZOOM_OUT;
|
||||
break;
|
||||
default :
|
||||
ts_status = TS_ERROR;
|
||||
break;
|
||||
} /* of switch(gestureId) */
|
||||
|
||||
return(ts_status);
|
||||
}
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
/**
|
||||
* @brief Clears all touch screen interrupts.
|
||||
*/
|
||||
void BSP_TS_ITClear(void)
|
||||
{
|
||||
/* Clear TS IT pending bits */
|
||||
tsDriver->ClearIT(I2cAddress);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function used to reset all touch data before a new acquisition
|
||||
* of touch information.
|
||||
* @param TS_State: Pointer to touch screen current state structure
|
||||
* @retval TS_OK if OK, TE_ERROR if problem found.
|
||||
*/
|
||||
uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State)
|
||||
{
|
||||
uint8_t ts_status = TS_ERROR;
|
||||
uint32_t index;
|
||||
|
||||
if (TS_State != (TS_StateTypeDef *)NULL)
|
||||
{
|
||||
TS_State->gestureId = GEST_ID_NO_GESTURE;
|
||||
TS_State->touchDetected = 0;
|
||||
|
||||
for(index = 0; index < TS_MAX_NB_TOUCH; index++)
|
||||
{
|
||||
TS_State->touchX[index] = 0;
|
||||
TS_State->touchY[index] = 0;
|
||||
TS_State->touchArea[index] = 0;
|
||||
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
|
||||
TS_State->touchWeight[index] = 0;
|
||||
}
|
||||
|
||||
ts_status = TS_OK;
|
||||
|
||||
} /* of if (TS_State != (TS_StateTypeDef *)NULL) */
|
||||
|
||||
return (ts_status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h745i_discovery_ts.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32h745i_discovery_ts.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H745I_DISCOVERY_TS_H
|
||||
#define __STM32H745I_DISCOVERY_TS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h745i_discovery.h"
|
||||
/* Include touch screen FT5336 component Driver */
|
||||
#include "../Components/ft5336/ft5336.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_TS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief With FT5336 : maximum 5 touches detected simultaneously
|
||||
*/
|
||||
#define TS_MAX_NB_TOUCH ((uint32_t) FT5336_MAX_DETECTABLE_TOUCH)
|
||||
|
||||
#define TS_NO_IRQ_PENDING ((uint8_t) 0)
|
||||
#define TS_IRQ_PENDING ((uint8_t) 1)
|
||||
|
||||
#define TS_SWAP_NONE ((uint8_t) 0x01)
|
||||
#define TS_SWAP_X ((uint8_t) 0x02)
|
||||
#define TS_SWAP_Y ((uint8_t) 0x04)
|
||||
#define TS_SWAP_XY ((uint8_t) 0x08)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Types Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief TS_StateTypeDef
|
||||
* Define TS State structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t touchDetected; /*!< Total number of active touches detected at last scan */
|
||||
uint16_t touchX[TS_MAX_NB_TOUCH]; /*!< Touch X[0], X[1] coordinates on 12 bits */
|
||||
uint16_t touchY[TS_MAX_NB_TOUCH]; /*!< Touch Y[0], Y[1] coordinates on 12 bits */
|
||||
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
uint8_t touchWeight[TS_MAX_NB_TOUCH]; /*!< Touch_Weight[0], Touch_Weight[1] : weight property of touches */
|
||||
uint8_t touchEventId[TS_MAX_NB_TOUCH]; /*!< Touch_EventId[0], Touch_EventId[1] : take value of type @ref TS_TouchEventTypeDef */
|
||||
uint8_t touchArea[TS_MAX_NB_TOUCH]; /*!< Touch_Area[0], Touch_Area[1] : touch area of each touch */
|
||||
uint32_t gestureId; /*!< type of gesture detected : take value of type @ref TS_GestureIdTypeDef */
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
} TS_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TS_OK = 0x00, /*!< Touch Ok */
|
||||
TS_ERROR = 0x01, /*!< Touch Error */
|
||||
TS_TIMEOUT = 0x02, /*!< Touch Timeout */
|
||||
TS_DEVICE_NOT_FOUND = 0x03 /*!< Touchscreen device not found */
|
||||
}TS_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TS_GestureIdTypeDef
|
||||
* Define Possible managed gesture identification values returned by touch screen
|
||||
* driver.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GEST_ID_NO_GESTURE = 0x00, /*!< Gesture not defined / recognized */
|
||||
GEST_ID_MOVE_UP = 0x01, /*!< Gesture Move Up */
|
||||
GEST_ID_MOVE_RIGHT = 0x02, /*!< Gesture Move Right */
|
||||
GEST_ID_MOVE_DOWN = 0x03, /*!< Gesture Move Down */
|
||||
GEST_ID_MOVE_LEFT = 0x04, /*!< Gesture Move Left */
|
||||
GEST_ID_ZOOM_IN = 0x05, /*!< Gesture Zoom In */
|
||||
GEST_ID_ZOOM_OUT = 0x06, /*!< Gesture Zoom Out */
|
||||
GEST_ID_NB_MAX = 0x07 /*!< max number of gesture id */
|
||||
|
||||
} TS_GestureIdTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TS_TouchEventTypeDef
|
||||
* Define Possible touch events kind as returned values
|
||||
* by touch screen IC Driver.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TOUCH_EVENT_NO_EVT = 0x00, /*!< Touch Event : undetermined */
|
||||
TOUCH_EVENT_PRESS_DOWN = 0x01, /*!< Touch Event Press Down */
|
||||
TOUCH_EVENT_LIFT_UP = 0x02, /*!< Touch Event Lift Up */
|
||||
TOUCH_EVENT_CONTACT = 0x03, /*!< Touch Event Contact */
|
||||
TOUCH_EVENT_NB_MAX = 0x04 /*!< max number of touch events kind */
|
||||
|
||||
} TS_TouchEventTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32H745I_DISCOVERY_TS_Imported_Variables Imported Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Table for touchscreen event information display on LCD :
|
||||
* table indexed on enum @ref TS_TouchEventTypeDef information
|
||||
*/
|
||||
extern char * ts_event_string_tab[TOUCH_EVENT_NB_MAX];
|
||||
|
||||
/**
|
||||
* @brief Table for touchscreen gesture Id information display on LCD : table indexed
|
||||
* on enum @ref TS_GestureIdTypeDef information
|
||||
*/
|
||||
extern char * ts_gesture_id_string_tab[GEST_ID_NB_MAX];
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H745I_DISCOVERY_TS_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY);
|
||||
uint8_t BSP_TS_DeInit(void);
|
||||
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State);
|
||||
|
||||
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
||||
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State);
|
||||
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
||||
|
||||
uint8_t BSP_TS_ITConfig(void);
|
||||
uint8_t BSP_TS_ITGetStatus(void);
|
||||
void BSP_TS_ITClear(void);
|
||||
uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H745I_DISCOVERY_TS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,206 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32H7xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32H7xx_H
|
||||
#define STM32H7xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32H7)
|
||||
#define STM32H7
|
||||
#endif /* STM32H7 */
|
||||
|
||||
|
||||
/* Uncomment the line below according to the target STM32H7 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
|
||||
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||
/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
|
||||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
||||
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
|
||||
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
|
||||
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
|
||||
#endif
|
||||
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.5.0
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H743xx)
|
||||
#include "stm32h743xx.h"
|
||||
#elif defined(STM32H753xx)
|
||||
#include "stm32h753xx.h"
|
||||
#elif defined(STM32H750xx)
|
||||
#include "stm32h750xx.h"
|
||||
#elif defined(STM32H742xx)
|
||||
#include "stm32h742xx.h"
|
||||
#elif defined(STM32H745xx)
|
||||
#include "stm32h745xx.h"
|
||||
#elif defined(STM32H755xx)
|
||||
#include "stm32h755xx.h"
|
||||
#elif defined(STM32H747xx)
|
||||
#include "stm32h747xx.h"
|
||||
#elif defined(STM32H757xx)
|
||||
#include "stm32h757xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32h7xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32H7xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef SYSTEM_STM32H7XX_H
|
||||
#define SYSTEM_STM32H7XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */
|
||||
extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */
|
||||
extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_STM32H7XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8" />
|
||||
<meta name="generator" content="pandoc" />
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for STM32H7xx CMSIS</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="../../../../../_htmresc/mini-st.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<div class="card fluid">
|
||||
<div class="sectione dark">
|
||||
<center>
|
||||
<h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
|
||||
<p>Copyright © 2017 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="../../../../../_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
<h1 id="license"><strong>License</strong></h1>
|
||||
This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
|
||||
<center>
|
||||
<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
|
||||
</center>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history"><strong>Update History</strong></h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
||||
<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
|
||||
<li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
|
||||
<ul>
|
||||
<li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
|
||||
<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
|
||||
<li>Add part numbers list to stm32h7xx.h header file:
|
||||
<ul>
|
||||
<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
|
||||
<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
|
||||
<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
|
||||
<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
|
||||
<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
|
||||
<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
|
||||
<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
|
||||
<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
|
||||
<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
|
||||
<li>Add system initialization template source file for dual core lines:
|
||||
<ul>
|
||||
<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
|
||||
<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
|
||||
<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
|
||||
</ul></li>
|
||||
<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
|
||||
<li><p>Add EWARM STM32H742xx devices linker files</p></li>
|
||||
</ul></li>
|
||||
</ul></li>
|
||||
<li><strong>Registers and bit field definitions updates</strong>:
|
||||
<ul>
|
||||
<li>Update SYSCFG_TypeDef structure to add
|
||||
<ul>
|
||||
<li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
|
||||
<li>Add definitions of SYSCFG_CFGR register bit fields</li>
|
||||
<li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
|
||||
<li>Add SYSCFG_PWRCR register bit fields</li>
|
||||
</ul></li>
|
||||
<li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
|
||||
<ul>
|
||||
<li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
|
||||
<li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
|
||||
<li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
|
||||
<li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
|
||||
</ul></li>
|
||||
<li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
|
||||
<ul>
|
||||
<li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
|
||||
</ul></li>
|
||||
<li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
|
||||
<li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
|
||||
<li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
|
||||
<li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
|
||||
<li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
|
||||
<li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
|
||||
<li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
|
||||
<li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li><strong>Patch Release on top of V1.3.0</strong></li>
|
||||
<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
|
||||
<ul>
|
||||
<li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<ul>
|
||||
<li>STM32H7xx include files:
|
||||
<ul>
|
||||
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
|
||||
<li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
|
||||
<li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
|
||||
<li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
|
||||
<li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
|
||||
<li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
|
||||
<li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
|
||||
<li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
|
||||
<li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
|
||||
<li>Update <strong>FLASH</strong> user option bytes bit definition</li>
|
||||
<li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
|
||||
<li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
|
||||
<li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
|
||||
<li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
|
||||
<li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
|
||||
<li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
|
||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
|
||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
|
||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
|
||||
<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
|
||||
<li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
|
||||
<li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
|
||||
<li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
|
||||
<li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
|
||||
<li>Add IS_GPIO_AF_INSTANCE macro</li>
|
||||
<li>Update <strong>DAC</strong> bits definition</li>
|
||||
<li>Update <strong>FDCAN</strong> bits definition</li>
|
||||
<li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
|
||||
<li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
|
||||
<li>Update <strong>TIM</strong> registers and bits definition naming</li>
|
||||
<li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
|
||||
<li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
|
||||
<li>Update <strong>BDMA</strong> bits definition</li>
|
||||
<li>Update <strong>FMC</strong> bits definition</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add support for stm32h750xx value line devices:
|
||||
<ul>
|
||||
<li>Add “stm32h750xx.h” file</li>
|
||||
<li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update FDCAN bit definition</li>
|
||||
<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update USB OTG bit definition</li>
|
||||
<li>Adjust PLL fractional computation</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-6">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.1
|
||||
* @date 30. January 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* ARM Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* ARM Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __noreturn
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __root
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32
|
||||
__packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI ARM Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,201 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
|
||||
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|
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
END OF TERMS AND CONDITIONS
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||||
|
||||
APPENDIX: How to apply the Apache License to your work.
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||||
|
||||
To apply the Apache License to your work, attach the following
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
Unless required by applicable law or agreed to in writing, software
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||||
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||||
See the License for the specific language governing permissions and
|
||||
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|
||||
|
|
@ -0,0 +1,66 @@
|
|||
# CMSIS Version 5
|
||||
|
||||
CMSIS Version 5.0.1 release is now available.
|
||||
|
||||
This GitHub repository development branch reflects our current state of development and is constantly updated.
|
||||
|
||||
The [pre-built documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) for the 5.0.1 release
|
||||
is available under http://arm-software.github.io/CMSIS_5/General/html/index.html
|
||||
|
||||
Use *Issues* to provide feedback and report problems for CMSIS Version 5. Note that this repository gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions.
|
||||
|
||||
## Implemented Enhancements
|
||||
- Support for ARMv8-M Architecture (Mainline and Baseline) as well as devices Cortex-M23 and Cortex-M33
|
||||
|
||||
- CMSIS-RTOS Version 2 API and RTX reference implementation with several enhancements:
|
||||
- Dynamic object creation, Flag events, C API, additional thread and timer functions
|
||||
|
||||
- CMSIS-RTOS API Secure and Non-Secure support, multi-processor support
|
||||
|
||||
## Futher Planned Enhancements
|
||||
- Improvements for Cortex-A / M hybrid devices (focus on Cortex-M interaction)
|
||||
|
||||
- CMSIS-Pack
|
||||
- Additions for generic example, project templates, multiple download portals
|
||||
- Adoption of IAR Flash Loader technology
|
||||
|
||||
For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/master/CMSIS_EW2016.pdf).
|
||||
|
||||
## Directory Structure
|
||||
|
||||
| Directory | Content |
|
||||
| --------------- | ---------------------------------------------- |
|
||||
| CMSIS/Core | CMSIS-Core related files (for release) |
|
||||
| CMSIS/DAP | CMSIS-DAP related files and examples |
|
||||
| CMSIS/Driver | CMSIS-Driver API headers and template files |
|
||||
| CMSIS/DSP | CMSIS-DSP related files |
|
||||
| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
|
||||
| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & ARMv8-M) |
|
||||
| CMSIS/Pack | CMSIS-Pack examples and tutorials |
|
||||
| CMSIS/DoxyGen | Source of the documentation |
|
||||
| CMSIS/Utilities | Utility programs |
|
||||
|
||||
## Generate CMSIS Pack for Release
|
||||
|
||||
This GitHub development repository contains already pre-build libraries of various libraries (DSP, RTOS, RTOS2).
|
||||
These libraries are validated for release.
|
||||
|
||||
To build a complete CMSIS pack for installation the following additional tools are required:
|
||||
- **doxygen.exe** Version: 1.8.6 (Documentation Generator)
|
||||
- **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter)
|
||||
- **7z.exe (7-Zip)** Version: 16.02 (File Archiver)
|
||||
|
||||
Using these tools, you can generate on a Windows PC:
|
||||
- **CMSIS Software Pack** using the batch file **gen_pack.bat** (located in ./CMSIS/Utilities). This batch file also generates the documentation.
|
||||
|
||||
- **CMSIS Documentation** using the batch file **genDoc.bat** (located in ./CMSIS/Doxygen).
|
||||
|
||||
The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation.
|
||||
|
||||
## License
|
||||
|
||||
ARM CMSIS is licensed under Apache-2.0.
|
||||
|
||||
## Contributions and Pull Requests
|
||||
|
||||
Contributions are accepted under Apache-2.0. Only submit contributions where you have authored all of the code.
|
||||
|
|
@ -0,0 +1,967 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_H
|
||||
#define STM32H7xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup REV_ID device revision ID
|
||||
* @{
|
||||
*/
|
||||
#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */
|
||||
#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */
|
||||
#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */
|
||||
#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
|
||||
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Ethernet_Config Ethernet Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */
|
||||
#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */
|
||||
|
||||
#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \
|
||||
((CONFIG) == SYSCFG_ETH_RMII))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */
|
||||
#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */
|
||||
#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */
|
||||
#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */
|
||||
|
||||
|
||||
#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
|
||||
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
|
||||
(((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
|
||||
(((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
|
||||
|
||||
|
||||
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */
|
||||
#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
|
||||
#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */
|
||||
#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
|
||||
#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */
|
||||
#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */
|
||||
#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */
|
||||
#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */
|
||||
|
||||
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \
|
||||
(((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Boot_Config Boot Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */
|
||||
#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */
|
||||
|
||||
#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
|
||||
((REGISTER) == SYSCFG_BOOT_ADDR1))
|
||||
|
||||
#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
|
||||
#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */
|
||||
|
||||
#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
|
||||
((SELECT) == SYSCFG_REGISTER_CODE))
|
||||
|
||||
#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup EXTI_Event_Input_Config Event Input Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_MODE_IT ((uint32_t)0x00010000)
|
||||
#define EXTI_MODE_EVT ((uint32_t)0x00020000)
|
||||
#define EXTI_RISING_EDGE ((uint32_t)0x00100000)
|
||||
#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
|
||||
#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
|
||||
|
||||
#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */
|
||||
#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */
|
||||
#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */
|
||||
#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */
|
||||
#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */
|
||||
#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */
|
||||
#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */
|
||||
#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */
|
||||
#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */
|
||||
#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */
|
||||
#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */
|
||||
#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */
|
||||
#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */
|
||||
#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */
|
||||
#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */
|
||||
#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */
|
||||
#define EXTI_LINE16 ((uint32_t)0x10)
|
||||
#define EXTI_LINE17 ((uint32_t)0x11)
|
||||
#define EXTI_LINE18 ((uint32_t)0x12)
|
||||
#define EXTI_LINE19 ((uint32_t)0x13)
|
||||
#define EXTI_LINE20 ((uint32_t)0x14)
|
||||
#define EXTI_LINE21 ((uint32_t)0x15)
|
||||
#define EXTI_LINE22 ((uint32_t)0x16)
|
||||
#define EXTI_LINE23 ((uint32_t)0x17)
|
||||
#define EXTI_LINE24 ((uint32_t)0x18)
|
||||
#define EXTI_LINE25 ((uint32_t)0x19)
|
||||
#define EXTI_LINE26 ((uint32_t)0x1A)
|
||||
#define EXTI_LINE27 ((uint32_t)0x1B)
|
||||
#define EXTI_LINE28 ((uint32_t)0x1C)
|
||||
#define EXTI_LINE29 ((uint32_t)0x1D)
|
||||
#define EXTI_LINE30 ((uint32_t)0x1E)
|
||||
#define EXTI_LINE31 ((uint32_t)0x1F)
|
||||
#define EXTI_LINE32 ((uint32_t)0x20)
|
||||
#define EXTI_LINE33 ((uint32_t)0x21)
|
||||
#define EXTI_LINE34 ((uint32_t)0x22)
|
||||
#define EXTI_LINE35 ((uint32_t)0x23)
|
||||
#define EXTI_LINE36 ((uint32_t)0x24)
|
||||
#define EXTI_LINE37 ((uint32_t)0x25)
|
||||
#define EXTI_LINE38 ((uint32_t)0x26)
|
||||
#define EXTI_LINE39 ((uint32_t)0x27)
|
||||
|
||||
#define EXTI_LINE40 ((uint32_t)0x28)
|
||||
#define EXTI_LINE41 ((uint32_t)0x29)
|
||||
#define EXTI_LINE42 ((uint32_t)0x2A)
|
||||
#define EXTI_LINE43 ((uint32_t)0x2B)
|
||||
#define EXTI_LINE44 ((uint32_t)0x2C)
|
||||
/* EXTI_LINE45 Reserved */
|
||||
#if defined(DUAL_CORE)
|
||||
#define EXTI_LINE46 ((uint32_t)0x2E)
|
||||
#else
|
||||
/* EXTI_LINE46 Reserved */
|
||||
#endif
|
||||
#define EXTI_LINE47 ((uint32_t)0x2F)
|
||||
#define EXTI_LINE48 ((uint32_t)0x30)
|
||||
#define EXTI_LINE49 ((uint32_t)0x31)
|
||||
|
||||
#define EXTI_LINE50 ((uint32_t)0x32)
|
||||
#define EXTI_LINE51 ((uint32_t)0x33)
|
||||
#define EXTI_LINE52 ((uint32_t)0x34)
|
||||
#define EXTI_LINE53 ((uint32_t)0x35)
|
||||
#define EXTI_LINE54 ((uint32_t)0x36)
|
||||
#define EXTI_LINE55 ((uint32_t)0x37)
|
||||
#define EXTI_LINE56 ((uint32_t)0x38)
|
||||
#define EXTI_LINE57 ((uint32_t)0x39)
|
||||
#define EXTI_LINE58 ((uint32_t)0x3A)
|
||||
#define EXTI_LINE59 ((uint32_t)0x3B)
|
||||
|
||||
#define EXTI_LINE60 ((uint32_t)0x3C)
|
||||
#define EXTI_LINE61 ((uint32_t)0x3D)
|
||||
#define EXTI_LINE62 ((uint32_t)0x3E)
|
||||
#define EXTI_LINE63 ((uint32_t)0x3F)
|
||||
#define EXTI_LINE64 ((uint32_t)0x40)
|
||||
#define EXTI_LINE65 ((uint32_t)0x41)
|
||||
#define EXTI_LINE66 ((uint32_t)0x42)
|
||||
#define EXTI_LINE67 ((uint32_t)0x43)
|
||||
#define EXTI_LINE68 ((uint32_t)0x44)
|
||||
#define EXTI_LINE69 ((uint32_t)0x45)
|
||||
|
||||
#define EXTI_LINE70 ((uint32_t)0x46)
|
||||
#define EXTI_LINE71 ((uint32_t)0x47)
|
||||
#define EXTI_LINE72 ((uint32_t)0x48)
|
||||
#define EXTI_LINE73 ((uint32_t)0x49)
|
||||
#define EXTI_LINE74 ((uint32_t)0x4A)
|
||||
#define EXTI_LINE75 ((uint32_t)0x4B)
|
||||
#define EXTI_LINE76 ((uint32_t)0x4C)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define EXTI_LINE77 ((uint32_t)0x4D)
|
||||
#define EXTI_LINE78 ((uint32_t)0x4E)
|
||||
#define EXTI_LINE79 ((uint32_t)0x4F)
|
||||
|
||||
#define EXTI_LINE80 ((uint32_t)0x50)
|
||||
/* EXTI_LINE81 Reserved */
|
||||
#define EXTI_LINE82 ((uint32_t)0x52)
|
||||
/* EXTI_LINE83 Reserved */
|
||||
#define EXTI_LINE84 ((uint32_t)0x54)
|
||||
#define EXTI_LINE85 ((uint32_t)0x55)
|
||||
#define EXTI_LINE86 ((uint32_t)0x56)
|
||||
#define EXTI_LINE87 ((uint32_t)0x57)
|
||||
/* EXTI_LINE88 Reserved */
|
||||
#else
|
||||
/* EXTI_LINE77 Reserved */
|
||||
/* EXTI_LINE78 Reserved */
|
||||
/* EXTI_LINE79 Reserved */
|
||||
/* EXTI_LINE80 Reserved */
|
||||
/* EXTI_LINE81 Reserved */
|
||||
/* EXTI_LINE82 Reserved */
|
||||
/* EXTI_LINE83 Reserved */
|
||||
/* EXTI_LINE84 Reserved */
|
||||
|
||||
#define EXTI_LINE85 ((uint32_t)0x55)
|
||||
#define EXTI_LINE86 ((uint32_t)0x56)
|
||||
#define EXTI_LINE87 ((uint32_t)0x57)
|
||||
|
||||
/* EXTI_LINE88 Reserved */
|
||||
#endif
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
|
||||
((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \
|
||||
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
|
||||
#else
|
||||
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
|
||||
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
|
||||
#endif
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
|
||||
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
|
||||
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
|
||||
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
|
||||
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
|
||||
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
|
||||
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
|
||||
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
|
||||
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
|
||||
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
|
||||
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
|
||||
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
|
||||
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
|
||||
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
|
||||
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
|
||||
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
|
||||
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
|
||||
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
|
||||
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
|
||||
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
|
||||
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
|
||||
((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
|
||||
((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
|
||||
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
|
||||
((LINE) == EXTI_LINE78) || \
|
||||
((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
|
||||
#else
|
||||
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
|
||||
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
|
||||
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
|
||||
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
|
||||
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
|
||||
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
|
||||
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
|
||||
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
|
||||
((LINE) == EXTI_LINE44) || \
|
||||
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
|
||||
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
|
||||
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
|
||||
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
|
||||
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
|
||||
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
|
||||
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
|
||||
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
|
||||
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
|
||||
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
|
||||
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
|
||||
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
|
||||
((LINE) == EXTI_LINE85) || \
|
||||
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
|
||||
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
|
||||
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
|
||||
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
|
||||
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
|
||||
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
|
||||
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
|
||||
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
|
||||
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
|
||||
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
|
||||
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
|
||||
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
|
||||
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
|
||||
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
|
||||
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
|
||||
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
|
||||
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
|
||||
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
|
||||
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
|
||||
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
|
||||
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
|
||||
((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
|
||||
((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
|
||||
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
|
||||
#else
|
||||
#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
|
||||
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
|
||||
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
|
||||
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
|
||||
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
|
||||
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
|
||||
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
|
||||
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
|
||||
((LINE) == EXTI_LINE44) || \
|
||||
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
|
||||
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
|
||||
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
|
||||
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
|
||||
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
|
||||
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
|
||||
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
|
||||
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
|
||||
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
|
||||
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
|
||||
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
|
||||
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
|
||||
((LINE) == EXTI_LINE85) || \
|
||||
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
|
||||
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
|
||||
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
|
||||
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
|
||||
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
|
||||
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
|
||||
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
|
||||
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
|
||||
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
|
||||
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
|
||||
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
|
||||
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
|
||||
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
|
||||
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
|
||||
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
|
||||
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
|
||||
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
|
||||
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
|
||||
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
|
||||
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
|
||||
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
|
||||
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
|
||||
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
|
||||
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
|
||||
((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
|
||||
((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
|
||||
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
|
||||
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53))
|
||||
#else
|
||||
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
|
||||
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
|
||||
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
|
||||
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
|
||||
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
|
||||
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
|
||||
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
|
||||
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
|
||||
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
|
||||
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
|
||||
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
|
||||
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
|
||||
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
|
||||
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
|
||||
((LINE) == EXTI_LINE53))
|
||||
#endif
|
||||
|
||||
|
||||
#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
|
||||
#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/
|
||||
#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/
|
||||
#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/
|
||||
|
||||
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
|
||||
((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config
|
||||
* @{
|
||||
*/
|
||||
#define FMC_SWAPBMAP_DISABLE (0x00000000U)
|
||||
#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
|
||||
#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
|
||||
|
||||
#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \
|
||||
((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
|
||||
((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SYSCFG Break AXIRAM double ECC lock.
|
||||
* Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
|
||||
|
||||
/** @brief SYSCFG Break ITCM double ECC lock.
|
||||
* Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
|
||||
|
||||
/** @brief SYSCFG Break DTCM double ECC lock.
|
||||
* Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
|
||||
|
||||
/** @brief SYSCFG Break SRAM1 double ECC lock.
|
||||
* Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
|
||||
|
||||
/** @brief SYSCFG Break SRAM2 double ECC lock.
|
||||
* Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
|
||||
|
||||
/** @brief SYSCFG Break SRAM3 double ECC lock.
|
||||
* Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
|
||||
|
||||
/** @brief SYSCFG Break SRAM4 double ECC lock.
|
||||
* Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
|
||||
|
||||
/** @brief SYSCFG Break Backup SRAM double ECC lock.
|
||||
* Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
|
||||
|
||||
/** @brief SYSCFG Break Cortex-M7 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
|
||||
|
||||
/** @brief SYSCFG Break FLASH double ECC lock.
|
||||
* Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
|
||||
|
||||
/** @brief SYSCFG Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
This feature is available on STM32H7 rev.B and above.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
|
||||
#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
|
||||
#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
|
||||
#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
|
||||
#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
|
||||
#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
|
||||
#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
|
||||
#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
|
||||
#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
|
||||
#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
|
||||
#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
|
||||
#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
|
||||
#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
|
||||
#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
|
||||
#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
|
||||
#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
|
||||
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2))
|
||||
#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
|
||||
#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
|
||||
#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
|
||||
#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
|
||||
#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
|
||||
#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
|
||||
#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
|
||||
#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
|
||||
#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
|
||||
#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
|
||||
#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
|
||||
#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
|
||||
#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
|
||||
#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
|
||||
#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
|
||||
#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
|
||||
#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
|
||||
#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
|
||||
#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
|
||||
#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
|
||||
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
|
||||
#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
|
||||
#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
|
||||
|
||||
#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
|
||||
#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
|
||||
#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
|
||||
#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
|
||||
#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
|
||||
#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
|
||||
#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
|
||||
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
|
||||
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
|
||||
void HAL_SYSCFG_EnableBOOST(void);
|
||||
void HAL_SYSCFG_DisableBOOST(void);
|
||||
void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
|
||||
void HAL_SYSCFG_EnableCM7BOOT(void);
|
||||
void HAL_SYSCFG_DisableCM7BOOT(void);
|
||||
void HAL_SYSCFG_EnableCM4BOOT(void);
|
||||
void HAL_SYSCFG_DisableCM4BOOT(void);
|
||||
#endif /*DUAL_CORE*/
|
||||
void HAL_EnableCompensationCell(void);
|
||||
void HAL_DisableCompensationCell(void);
|
||||
void HAL_SYSCFG_EnableIOSpeedOptimize(void);
|
||||
void HAL_SYSCFG_DisableIOSpeedOptimize(void);
|
||||
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
|
||||
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
|
||||
void HAL_EnableDBGSleepMode(void);
|
||||
void HAL_DisableDBGSleepMode(void);
|
||||
void HAL_EnableDBGStopMode(void);
|
||||
void HAL_DisableDBGStopMode(void);
|
||||
void HAL_EnableDBGStandbyMode(void);
|
||||
void HAL_DisableDBGStandbyMode(void);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_EnableDomain2DBGSleepMode(void);
|
||||
void HAL_DisableDomain2DBGSleepMode(void);
|
||||
void HAL_EnableDomain2DBGStopMode(void);
|
||||
void HAL_DisableDomain2DBGStopMode(void);
|
||||
void HAL_EnableDomain2DBGStandbyMode(void);
|
||||
void HAL_DisableDomain2DBGStandbyMode(void);
|
||||
#endif /*DUAL_CORE*/
|
||||
void HAL_EnableDomain3DBGStopMode(void);
|
||||
void HAL_DisableDomain3DBGStopMode(void);
|
||||
void HAL_EnableDomain3DBGStandbyMode(void);
|
||||
void HAL_DisableDomain3DBGStandbyMode(void);
|
||||
void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
|
||||
void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
|
||||
#endif /*DUAL_CORE*/
|
||||
void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
|
||||
void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
|
||||
#endif /*DUAL_CORE*/
|
||||
void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
|
||||
void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
|
||||
uint32_t HAL_GetFMCMemorySwappingConfig(void);
|
||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
||||
void HAL_SYSCFG_DisableVREFBUF(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,461 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_CORTEX_H
|
||||
#define STM32H7xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
|
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
|
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
|
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
#if !defined(CORE_CM4)
|
||||
#define MPU_REGION_NUMBER8 ((uint8_t)0x08)
|
||||
#define MPU_REGION_NUMBER9 ((uint8_t)0x09)
|
||||
#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)
|
||||
#define MPU_REGION_NUMBER11 ((uint8_t)0x0B)
|
||||
#define MPU_REGION_NUMBER12 ((uint8_t)0x0C)
|
||||
#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)
|
||||
#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)
|
||||
#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)
|
||||
#endif /* !defined(CORE_CM4) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
|
||||
* @{
|
||||
*/
|
||||
#define CM7_CPUID ((uint32_t)0x00000003)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define CM4_CPUID ((uint32_t)0x00000001)
|
||||
#endif /*DUAL_CORE*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
uint32_t HAL_GetCurrentCPUID(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#if !defined(CORE_CM4)
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER8) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER9) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER10) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER11) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER12) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER13) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER14) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER15))
|
||||
#else
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
#endif /* !defined(CORE_CM4) */
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_DEF
|
||||
#define STM32H7xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx.h"
|
||||
//#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
#include <math.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
|
||||
#elif defined (__CC_ARM) /* ARM Compiler */
|
||||
#define ALIGN_32BYTES(buf) __align(32) buf
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,306 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_DMA_EX_H
|
||||
#define STM32H7xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Memory definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
MEMORY0 = 0x00U, /*!< Memory 0 */
|
||||
MEMORY1 = 0x01U, /*!< Memory 1 */
|
||||
|
||||
}HAL_DMA_MemoryTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX Synchronization configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
||||
This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
|
||||
|
||||
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
||||
This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
|
||||
|
||||
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
||||
This parameter can take the value ENABLE or DISABLE*/
|
||||
|
||||
|
||||
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
||||
This parameter can take the value ENABLE or DISABLE */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
|
||||
This parameters can be in the range 1 to 32 */
|
||||
|
||||
}HAL_DMA_MuxSyncConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX request generator parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||
This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event.
|
||||
This parameters can be in the range 1 to 32 */
|
||||
|
||||
}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
|
||||
* @brief DMAEx Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
|
||||
* @brief DMAEx MUX SyncSignalID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */
|
||||
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
|
||||
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
|
||||
#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */
|
||||
#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */
|
||||
#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */
|
||||
#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */
|
||||
#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */
|
||||
#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */
|
||||
#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */
|
||||
#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */
|
||||
#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
|
||||
* @brief DMAEx MUX SyncPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */
|
||||
#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
|
||||
#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
|
||||
#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
|
||||
* @brief DMAEx MUX SignalGeneratorID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */
|
||||
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
|
||||
#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */
|
||||
#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */
|
||||
#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */
|
||||
#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */
|
||||
#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */
|
||||
#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
|
||||
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
|
||||
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
|
||||
* @brief DMAEx MUX RequestGeneneratorPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
|
||||
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMA Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
|
||||
#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
|
||||
|
||||
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
||||
|
||||
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
||||
((EVENT) == ENABLE))
|
||||
|
||||
#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
|
||||
#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,650 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_FLASH_H
|
||||
#define STM32H7xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_SECTERASE_BANK1,
|
||||
FLASH_PROC_MASSERASE_BANK1,
|
||||
FLASH_PROC_PROGRAM_BANK1,
|
||||
FLASH_PROC_SECTERASE_BANK2,
|
||||
FLASH_PROC_MASSERASE_BANK2,
|
||||
FLASH_PROC_PROGRAM_BANK2,
|
||||
FLASH_PROC_ALLBANK_MASSERASE
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */
|
||||
|
||||
__IO uint32_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */
|
||||
|
||||
__IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */
|
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code */
|
||||
|
||||
}FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Code FLASH Error Code
|
||||
* @brief FLASH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
|
||||
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
|
||||
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
|
||||
#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */
|
||||
#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */
|
||||
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */
|
||||
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */
|
||||
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */
|
||||
#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */
|
||||
|
||||
#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1 */
|
||||
#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 */
|
||||
|
||||
#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 /*!< Write Protection Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 /*!< ECC Double Detection Error on Bank 2 */
|
||||
#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2 /*!< CRC Read Error on Bank2 */
|
||||
|
||||
#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR /*!< Option Byte Change Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_FLASHWORD 0x03U /*!< Program a flash word (256-bit) at a specified address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */
|
||||
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */
|
||||
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */
|
||||
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */
|
||||
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */
|
||||
#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */
|
||||
#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */
|
||||
#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */
|
||||
#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */
|
||||
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */
|
||||
#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */
|
||||
|
||||
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */
|
||||
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */
|
||||
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */
|
||||
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */
|
||||
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */
|
||||
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */
|
||||
#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */
|
||||
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */
|
||||
#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */
|
||||
|
||||
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
|
||||
FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \
|
||||
FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \
|
||||
FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \
|
||||
FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1)
|
||||
|
||||
#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \
|
||||
FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \
|
||||
FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \
|
||||
FLASH_FLAG_ALL_ERRORS_BANK1)
|
||||
|
||||
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */
|
||||
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */
|
||||
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */
|
||||
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */
|
||||
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */
|
||||
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */
|
||||
#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */
|
||||
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */
|
||||
#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */
|
||||
|
||||
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
|
||||
FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \
|
||||
FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \
|
||||
FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \
|
||||
FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2)
|
||||
|
||||
#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \
|
||||
FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \
|
||||
FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \
|
||||
FLASH_FLAG_ALL_ERRORS_BANK2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */
|
||||
#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */
|
||||
#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */
|
||||
|
||||
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
|
||||
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
|
||||
FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \
|
||||
FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \
|
||||
FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \
|
||||
FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1)
|
||||
|
||||
#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */
|
||||
#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */
|
||||
#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */
|
||||
|
||||
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \
|
||||
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \
|
||||
FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \
|
||||
FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \
|
||||
FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \
|
||||
FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE 0x00000000U /*!< Flash program/erase by 8 bits */
|
||||
#define FLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */
|
||||
#define FLASH_PSIZE_WORD FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */
|
||||
#define FLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U
|
||||
#define FLASH_KEY2 0xCDEF89ABU
|
||||
#define FLASH_OPT_KEY1 0x08192A3BU
|
||||
#define FLASH_OPT_KEY2 0x4C5D6E7FU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
|
||||
#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
|
||||
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* In case of Bank 1 This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
|
||||
* @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
|
||||
|
||||
* In case of Bank 2, this parameter can be any combination of the following values: *
|
||||
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
|
||||
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
|
||||
* @retval none
|
||||
*/
|
||||
|
||||
#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
|
||||
|
||||
#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
|
||||
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
|
||||
__HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
|
||||
__HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* In case of Bank 1 This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
|
||||
* @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
|
||||
* @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source
|
||||
|
||||
* In case of Bank 2, this parameter can be any combination of the following values: *
|
||||
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
|
||||
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
|
||||
* @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source
|
||||
* @retval none
|
||||
*/
|
||||
|
||||
#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
|
||||
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
|
||||
__HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
|
||||
__HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* In case of Bank 1 This parameter can be any combination of the following values :
|
||||
* @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
|
||||
* @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
|
||||
* @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
|
||||
* @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
|
||||
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
|
||||
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
|
||||
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
|
||||
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
|
||||
*
|
||||
* In case of Bank 2 This parameter can be any combination of the following values :
|
||||
* @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
|
||||
* @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
|
||||
* @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
|
||||
* @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
|
||||
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
|
||||
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
|
||||
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
|
||||
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
|
||||
|
||||
#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
|
||||
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
|
||||
__HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
|
||||
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
|
||||
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
|
||||
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
|
||||
* @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
|
||||
*
|
||||
* In case of Bank 2 This parameter can be any combination of the following values :
|
||||
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
|
||||
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
|
||||
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
|
||||
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
|
||||
* @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
|
||||
* @retval none
|
||||
*/
|
||||
|
||||
#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
|
||||
|
||||
#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
|
||||
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32h7xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Program operation functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
|
||||
|
||||
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
|
||||
|
||||
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
|
||||
|
||||
/** @defgroup FLASH_Address FLASH Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
|
||||
|
||||
#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
|
||||
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
|
||||
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
|
||||
HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
|
||||
HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,815 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32H7xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_FLASH_EX_H
|
||||
#define STM32H7xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or sector Erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
|
||||
This parameter must be a value of @ref FLASH_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
|
||||
This parameter must be a value of @ref FLASHEx_Voltage_Range */
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Type */
|
||||
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_WRP_State */
|
||||
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
|
||||
The value of this parameter depend on device used within the same series */
|
||||
|
||||
uint32_t RDPLevel; /*!< Set the read protection level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
|
||||
|
||||
uint32_t BORLevel; /*!< Set the BOR Level.
|
||||
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
|
||||
|
||||
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
|
||||
|
||||
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
|
||||
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
|
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not
|
||||
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
|
||||
This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
|
||||
|
||||
uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a value between begin and end of a bank */
|
||||
|
||||
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a value between PCROP Start address and end of a bank */
|
||||
|
||||
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
|
||||
or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
|
||||
|
||||
uint32_t BootAddr0; /*!< Boot Address 0.
|
||||
This parameter must be a value between begin and end of a bank */
|
||||
|
||||
uint32_t BootAddr1; /*!< Boot Address 1.
|
||||
This parameter must be a value between begin and end of a bank */
|
||||
#if defined(DUAL_CORE)
|
||||
uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
|
||||
or both.
|
||||
This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
|
||||
|
||||
uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0.
|
||||
This parameter must be a value between begin and end of a bank */
|
||||
|
||||
uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1.
|
||||
This parameter must be a value between begin and end of a bank */
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
|
||||
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
|
||||
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
|
||||
|
||||
uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
|
||||
This parameter must be a value between begin address and end address of bank1 */
|
||||
|
||||
uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address .
|
||||
This parameter must be a value between Secure Area Start address and end address of a bank1 */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeCRC; /*!< CRC Selection Type.
|
||||
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
|
||||
|
||||
uint32_t BurstSize; /*!< CRC Burst Size.
|
||||
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
|
||||
|
||||
uint32_t Bank; /*!< Select bank where CRC computation is enabled.
|
||||
This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
|
||||
This parameter must be a value of @ref FLASH_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be computed.
|
||||
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t CRCStartAddr; /*!< CRC Start address.
|
||||
This parameter must be a value between begin address and end address of a bank */
|
||||
|
||||
uint32_t CRCEndAddr; /*!< CRC End address.
|
||||
This parameter must be a value between CRC Start address and end address of a bank */
|
||||
|
||||
} FLASH_CRCInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */
|
||||
#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */
|
||||
#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */
|
||||
#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */
|
||||
#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
|
||||
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
|
||||
#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */
|
||||
#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */
|
||||
#if defined(DUAL_CORE)
|
||||
#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */
|
||||
#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */
|
||||
#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */
|
||||
#else /* Single core*/
|
||||
#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */
|
||||
#endif /*DUAL_CORE*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 0xAA00U
|
||||
#define OB_RDP_LEVEL_1 0x5500U
|
||||
#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2
|
||||
it s no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */
|
||||
#define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
|
||||
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
|
||||
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
|
||||
#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
|
||||
#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
|
||||
#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
|
||||
#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
|
||||
#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
|
||||
#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
|
||||
#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
|
||||
#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
|
||||
#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
|
||||
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
|
||||
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
|
||||
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
|
||||
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
|
||||
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
|
||||
#define FLASH_BANK_2 0x02U /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
|
||||
is decreased from Level 1 to Level 0 or during a mass erase */
|
||||
#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
|
||||
decreased from Level 1 to Level 0 (full mass erase) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY
|
||||
* @{
|
||||
*/
|
||||
#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */
|
||||
#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE
|
||||
* @{
|
||||
*/
|
||||
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
|
||||
#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
|
||||
#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
|
||||
#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7
|
||||
* @{
|
||||
*/
|
||||
#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */
|
||||
#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4
|
||||
* @{
|
||||
*/
|
||||
#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */
|
||||
#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
|
||||
#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/
|
||||
#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */
|
||||
#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */
|
||||
#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */
|
||||
#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */
|
||||
#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
|
||||
* @{
|
||||
*/
|
||||
#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */
|
||||
#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
|
||||
* @{
|
||||
*/
|
||||
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
|
||||
#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
|
||||
#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
|
||||
#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */
|
||||
#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/
|
||||
#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/
|
||||
#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */
|
||||
#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */
|
||||
#define OB_USER_SECURITY 0x0040U /*!< security selection */
|
||||
#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
|
||||
#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
|
||||
#if defined(DUAL_CORE)
|
||||
#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
|
||||
#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
|
||||
#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */
|
||||
#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/
|
||||
#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP
|
||||
* @{
|
||||
*/
|
||||
#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level
|
||||
is decreased from Level 1 to Level 0 or during a mass erase */
|
||||
#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
|
||||
decreased from Level 1 to Level 0 (full mass erase) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */
|
||||
#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */
|
||||
#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */
|
||||
#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */
|
||||
#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */
|
||||
#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */
|
||||
#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
|
||||
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
|
||||
* @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
|
||||
* @retval The FLASH Boot Base Adress
|
||||
*/
|
||||
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Program/Erase parallelism.
|
||||
* @param __PSIZE__ FLASH Program/Erase parallelism
|
||||
* This parameter can be a value of @ref FLASH_Program_Parallelism
|
||||
* @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
|
||||
MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
|
||||
MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Program/Erase parallelism.
|
||||
* @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
|
||||
* @retval FLASH Program/Erase parallelism
|
||||
* This return value can be a value of @ref FLASH_Program_Parallelism
|
||||
*/
|
||||
#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
|
||||
READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
|
||||
READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Programming Delay.
|
||||
* @param __DELAY__ FLASH Programming Delay
|
||||
* This parameter can be a value of @ref FLASHEx_Programming_Delay
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Programming Delay.
|
||||
* @retval FLASH Programming Delay
|
||||
* This return value can be a value of @ref FLASHEx_Programming_Delay
|
||||
*/
|
||||
#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension Program operation functions *************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_4))
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
|
||||
#else
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
|
||||
|
||||
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
|
||||
|
||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
|
||||
((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || \
|
||||
((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || \
|
||||
((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || \
|
||||
((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || \
|
||||
((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || \
|
||||
((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || \
|
||||
((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || \
|
||||
((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
|
||||
(((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \
|
||||
(((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))
|
||||
|
||||
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
||||
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
|
||||
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
|
||||
((CONFIG) == OB_PCROP_RDP_ERASE))
|
||||
|
||||
#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
|
||||
((CONFIG) == OB_SECURE_RDP_ERASE))
|
||||
|
||||
#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
|
||||
|
||||
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
|
||||
|
||||
#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
|
||||
#endif /*DUAL_CORE*/
|
||||
#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
|
||||
|
||||
#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
|
||||
|
||||
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
|
||||
|
||||
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
|
||||
|
||||
#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
|
||||
((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
|
||||
|
||||
#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
|
||||
|
||||
#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
|
||||
|
||||
#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
|
||||
|
||||
#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
|
||||
#endif /*DUAL_CORE*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
|
||||
#else
|
||||
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
|
||||
#endif
|
||||
|
||||
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
|
||||
((VALUE) == OB_BOOT_ADD1) || \
|
||||
((VALUE) == OB_BOOT_ADD_BOTH))
|
||||
|
||||
#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
|
||||
((VALUE) == FLASH_CRC_SECTORS) || \
|
||||
((VALUE) == FLASH_CRC_BANK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_GPIO_H
|
||||
#define STM32H7xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_Alternate_function_selection */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (0x11120000U) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x11220000U) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32h7xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_GPIO_EX_H
|
||||
#define STM32H7xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#if defined(DUAL_CORE)
|
||||
#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
|
||||
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
|
||||
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
|
||||
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
|
||||
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
|
||||
#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
|
||||
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
|
||||
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
|
||||
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO pin available on the platform
|
||||
*/
|
||||
/* Defines the available pins per GPIOs */
|
||||
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
|
||||
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
|
||||
((__GPIOx__) == (GPIOB))? 1UL :\
|
||||
((__GPIOx__) == (GPIOC))? 2UL :\
|
||||
((__GPIOx__) == (GPIOD))? 3UL :\
|
||||
((__GPIOx__) == (GPIOE))? 4UL :\
|
||||
((__GPIOx__) == (GPIOF))? 5UL :\
|
||||
((__GPIOx__) == (GPIOG))? 6UL :\
|
||||
((__GPIOx__) == (GPIOH))? 7UL :\
|
||||
((__GPIOx__) == (GPIOI))? 8UL :\
|
||||
((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,621 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_HASH_H
|
||||
#define STM32H7xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (HASH)
|
||||
/** @addtogroup HASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HASH Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
|
||||
This parameter can be a value of @ref HASH_Data_Type. */
|
||||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
} HASH_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
|
||||
HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
|
||||
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
|
||||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
|
||||
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
|
||||
(step 1 consists in entering the inner hash function key) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
|
||||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key) */
|
||||
}HAL_HASH_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
}HAL_HASH_SuspendTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL HASH common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
|
||||
HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
|
||||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
}HAL_HASH_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @brief HASH Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __HASH_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
{
|
||||
HASH_InitTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
|
||||
|
||||
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
|
||||
|
||||
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
|
||||
|
||||
__IO uint32_t HashInCount; /*!< Counter of inputted data */
|
||||
|
||||
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
|
||||
|
||||
__IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
|
||||
|
||||
HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
|
||||
|
||||
FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
|
||||
|
||||
__IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< HASH Error code */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
|
||||
|
||||
void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
} HASH_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Algo_Selection HASH algorithm selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
|
||||
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
|
||||
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
|
||||
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
|
||||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type HASH input data type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
|
||||
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */
|
||||
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_flags_definition HASH flags definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
|
||||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
|
||||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Error_Definition HASH Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */
|
||||
#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether or not the specified HASH flag is set.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
|
||||
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
|
||||
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
|
||||
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified HASH interrupt.
|
||||
* @param __INTERRUPT__: specifies the HASH interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified HASH interrupt.
|
||||
* @param __INTERRUPT__: specifies the HASH interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Reset HASH handle state.
|
||||
* @param __HANDLE__: HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_HASH_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/** @brief Reset HASH handle status.
|
||||
* @param __HANDLE__: HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
|
||||
|
||||
/**
|
||||
* @brief Enable the multi-buffer DMA transfer mode.
|
||||
* @note This bit is set when hashing large files when multiple DMA transfers are needed.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief Disable the multi-buffer DMA transfer mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start the digest computation.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
|
||||
|
||||
/**
|
||||
* @brief Set the number of valid bits in the last word written in data register DIN.
|
||||
* @param __SIZE__: size in bytes of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
|
||||
|
||||
/**
|
||||
* @brief Reset the HASH core.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Return digest length in bytes.
|
||||
* @retval Digest length
|
||||
*/
|
||||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
/**
|
||||
* @brief Return number of words already pushed in the FIFO.
|
||||
* @retval Number of words already pushed in the FIFO
|
||||
*/
|
||||
#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that HASH input data type is valid.
|
||||
* @param __DATATYPE__: HASH input data type.
|
||||
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_16B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_8B) || \
|
||||
((__DATATYPE__) == HASH_DATATYPE_1B))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
|
||||
* processing in polling mode.
|
||||
* @note This check is valid only for multi-buffer HASH processing in polling mode.
|
||||
* @param __SIZE__: input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
|
||||
/**
|
||||
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
|
||||
* processing in DMA mode.
|
||||
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
|
||||
* @param __SIZE__: input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
|
||||
* processing in DMA mode.
|
||||
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
|
||||
* @param __HANDLE__: HASH handle.
|
||||
* @param __SIZE__: input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
|
||||
/**
|
||||
* @brief Ensure that handle phase is set to HASH processing.
|
||||
* @param __HANDLE__: HASH handle.
|
||||
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
|
||||
*/
|
||||
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
|
||||
|
||||
/**
|
||||
* @brief Ensure that handle phase is set to HMAC processing.
|
||||
* @param __HANDLE__: HASH handle.
|
||||
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
|
||||
*/
|
||||
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
|
||||
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
|
||||
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include HASH HAL Extended module */
|
||||
#include "stm32h7xx_hal_hash_ex.h"
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization methods **********************************/
|
||||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* HASH processing using polling *********************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HASH processing using IT **************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HASH processing using DMA *************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HASH-MAC processing using polling *****************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HASH-HMAC processing using DMA ********************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Peripheral State methods **************************************************/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Private_Functions HASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private functions */
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HASH*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_HASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_hash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_HASH_EX_H
|
||||
#define STM32H7xx_HAL_HASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (HASH)
|
||||
/** @addtogroup HASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HASH*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_HASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_hsem.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HSEM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_HSEM_H
|
||||
#define STM32H7xx_HAL_HSEM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SemID to mask helper Macro.
|
||||
* @param __SEMID__: semaphore ID from 0 to 31
|
||||
* @retval Semaphore Mask.
|
||||
*/
|
||||
#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
|
||||
|
||||
/**
|
||||
* @brief Enables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2IER |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
/**
|
||||
* @brief Disables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER &= ~(__SEM_MASK__)) : \
|
||||
(HSEM->C2IER &= ~(__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where an interrupt occurred.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
((__SEM_MASK__) & HSEM->C1MISR) : \
|
||||
((__SEM_MASK__) & HSEM->C2MISR1))
|
||||
#else
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Get the semaphores release status flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where Release flags rise.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(__SEM_MASK__) & HSEM->C1ISR : \
|
||||
(__SEM_MASK__) & HSEM->C2ISR)
|
||||
#else
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Clears the HSEM Interrupt flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1ICR |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2ICR |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
|
||||
* @brief HSEM Take and Release functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HSEM semaphore take (lock) using 2-Step method ****************************/
|
||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
|
||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
|
||||
/* HSEM Check semaphore state Taken or not **********************************/
|
||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
|
||||
/* HSEM Release **************************************************************/
|
||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM Release All************************************************************/
|
||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
||||
* @brief HSEM Set and Get Key functions.
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Set Clear Key *********************************************************/
|
||||
void HAL_HSEM_SetClearKey(uint32_t Key);
|
||||
/* HSEM Get Clear Key *********************************************************/
|
||||
uint32_t HAL_HSEM_GetClearKey(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group3
|
||||
* @brief HSEM Notification functions
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
|
||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask);
|
||||
/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
|
||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
|
||||
/* HSEM Free Callback (When a semaphore is released) *******************************/
|
||||
void HAL_HSEM_FreeCallback(uint32_t SemMask);
|
||||
/* HSEM IRQ Handler **********************************************************/
|
||||
void HAL_HSEM_IRQHandler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Private_Macros HSEM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
|
||||
|
||||
#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
|
||||
|
||||
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
|
||||
((__COREID__) == HSEM_CPU2_COREID))
|
||||
#else
|
||||
#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_HSEM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,782 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_I2C_H
|
||||
#define STM32H7xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32h7xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_I2C_EX_H
|
||||
#define STM32H7xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
|
||||
#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
|
||||
#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
|
||||
#elif defined(SYSCFG_PMCR_I2C1_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
|
||||
#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_I2C_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,597 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_PWR_H
|
||||
#define STM32H7xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */
|
||||
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */
|
||||
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */
|
||||
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */
|
||||
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */
|
||||
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */
|
||||
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */
|
||||
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_STOP ((uint8_t)0x01U)
|
||||
#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
|
||||
#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
|
||||
#define PWR_FLAG_SB ((uint8_t)0x04U)
|
||||
#if defined(DUAL_CORE)
|
||||
#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U)
|
||||
#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U)
|
||||
#define PWR_FLAG2_STOP ((uint8_t)0x07U)
|
||||
#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U)
|
||||
#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U)
|
||||
#define PWR_FLAG2_SB ((uint8_t)0x0AU)
|
||||
#endif /*DUAL_CORE*/
|
||||
#define PWR_FLAG_PVDO ((uint8_t)0x0BU)
|
||||
#define PWR_FLAG_AVDO ((uint8_t)0x0CU)
|
||||
#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU)
|
||||
#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU)
|
||||
#define PWR_FLAG_BRR ((uint8_t)0x0FU)
|
||||
#define PWR_FLAG_VOSRDY ((uint8_t)0x10U)
|
||||
#if defined(SMPS)
|
||||
#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)
|
||||
#else
|
||||
#define PWR_FLAG_SCUEN ((uint8_t)0x11U)
|
||||
#endif /* SMPS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief macros configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__: specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption when the device does
|
||||
* not operate at the maximum frequency (refer to the datasheets for more details).
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
|
||||
* @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.
|
||||
* the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0
|
||||
* using macro __HAL_RCC_SYSCFG_CLK_ENABLE().
|
||||
* Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in
|
||||
* PWR_REGULATOR_VOLTAGE_SCALE1.
|
||||
* transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1
|
||||
* then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.
|
||||
* After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG
|
||||
* To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first
|
||||
* switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
|
||||
do { \
|
||||
__IO uint32_t tmpreg = 0x00; \
|
||||
if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
|
||||
{ \
|
||||
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
|
||||
/* Delay after setting the voltage scaling */ \
|
||||
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
|
||||
MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
|
||||
/* Delay after setting the syscfg boost setting */ \
|
||||
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
|
||||
/* Delay after setting the syscfg boost setting */ \
|
||||
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
|
||||
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
|
||||
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
|
||||
} \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
|
||||
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the AVDE bit is set.
|
||||
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.
|
||||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
||||
* when the device wakes up from Standby mode or by a system reset
|
||||
* or power reset.
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @arg PWR_FLAG_STOP: STOP flag
|
||||
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
|
||||
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
|
||||
* @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold
|
||||
* @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
|
||||
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
|
||||
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
|
||||
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \
|
||||
((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \
|
||||
((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
|
||||
((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \
|
||||
((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
|
||||
((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \
|
||||
((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
|
||||
((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \
|
||||
((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \
|
||||
(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))
|
||||
#else
|
||||
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
|
||||
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the AVDE bit is set.
|
||||
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
||||
* when the device wakes up from Standby mode or by a system reset
|
||||
* or power reset.
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @arg PWR_FLAG_STOP: STOP flag
|
||||
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
|
||||
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
|
||||
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
|
||||
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
|
||||
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
|
||||
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
|
||||
((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
|
||||
((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
|
||||
((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
|
||||
((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @brief Clear PWR flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_SB: Standby flag.
|
||||
* @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
|
||||
do { \
|
||||
SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
|
||||
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
|
||||
} while(0)
|
||||
#else
|
||||
/** @brief Clear PWR flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_SB: Standby flag.
|
||||
* @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Enable the PVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Disable the PVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Enable event on PVD EXTI D2 Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Disable event on PVD EXTI D2 Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
|
||||
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
|
||||
* @retval EXTI D2 PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Clear the PVD EXTI D2 flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on PVD EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32h7xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* PVD configuration */
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration */
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes entry */
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Power PVD IRQ Handler */
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
/* Cortex System Control functions *******************************************/
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
|
||||
* @{
|
||||
*/
|
||||
/*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,638 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_PWR_EX_H
|
||||
#define STM32H7xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Types PWREx Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief PWREx AVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.
|
||||
This parameter can be a value of @ref PWREx_AVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_AVD_Mode */
|
||||
}PWREx_AVDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PWREx Wakeup pin configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
|
||||
This parameter can be a value of @ref PWREx_WakeUp_Pins */
|
||||
|
||||
uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
|
||||
This parameter can be a value of @ref PWREx_PIN_Polarity */
|
||||
|
||||
uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull.
|
||||
This parameter can be a value of @ref PWREx_PIN_Pull */
|
||||
}PWREx_WakeupPinTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6
|
||||
#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5
|
||||
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4
|
||||
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3
|
||||
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2
|
||||
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1
|
||||
/* High level and No pull */
|
||||
#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
|
||||
/* Low level and No pull */
|
||||
#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
|
||||
#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
|
||||
#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
|
||||
#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
|
||||
#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
|
||||
#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
|
||||
#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
|
||||
#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
|
||||
#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
|
||||
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
|
||||
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
|
||||
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
|
||||
#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
|
||||
#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/** @defgroup PWREx_Core_Select PWREx Core definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_CORE_CPU1 ((uint32_t)0x00000000U)
|
||||
#define PWR_CORE_CPU2 ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/** @defgroup PWREx_Domains PWREx Domains definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)
|
||||
#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)
|
||||
#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define PWR_D1_DOMAIN_FLAGS ((uint32_t)0x00000000U)
|
||||
#define PWR_D2_DOMAIN_FLAGS ((uint32_t)0x00000001U)
|
||||
#else
|
||||
#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)
|
||||
#endif /*DUAL_CORE*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_D3_State PWREx D3 Domain State
|
||||
* @{
|
||||
*/
|
||||
#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
|
||||
#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
|
||||
#if defined(SMPS)
|
||||
#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */
|
||||
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
|
||||
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
|
||||
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
|
||||
#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
|
||||
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
|
||||
#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
|
||||
#endif /* SMPS */
|
||||
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
|
||||
|
||||
#if defined(SMPS)
|
||||
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
|
||||
PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
|
||||
#else
|
||||
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
|
||||
#endif /* SMPS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
|
||||
#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
|
||||
#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
|
||||
#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
|
||||
#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
|
||||
#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
|
||||
#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
|
||||
* @{
|
||||
*/
|
||||
#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
|
||||
#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
|
||||
#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
|
||||
* @{
|
||||
*/
|
||||
#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
|
||||
#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
|
||||
#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the AVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Enable the AVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Disable the AVD EXTI Line 16
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Disable the AVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Enable event on AVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Enable event on AVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Disable event on AVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Disable event on AVD EXTI D2 Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Enable the AVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the AVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the AVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the AVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief AVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified AVD EXTI interrupt flag is set or not.
|
||||
* @retval EXTI AVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
|
||||
* @retval EXTI D2 AVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @brief Clear the AVD EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/**
|
||||
* @brief Clear the AVD EXTI D2 flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
|
||||
* @{
|
||||
*/
|
||||
/* Power supply control functions */
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
|
||||
uint32_t HAL_PWREx_GetSupplyConfig(void);
|
||||
/* Power volatge scaling functions */
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
|
||||
uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
|
||||
* @{
|
||||
*/
|
||||
/* System low power control functions */
|
||||
void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
|
||||
void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
|
||||
void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
|
||||
|
||||
/* Power core holding functions */
|
||||
HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
|
||||
void HAL_PWREx_ReleaseCore(uint32_t CPU);
|
||||
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/* Clear pending event function */
|
||||
void HAL_PWREx_ClearPendingEvent(void);
|
||||
|
||||
/* Flash low power control functions */
|
||||
void HAL_PWREx_EnableFlashPowerDown(void);
|
||||
void HAL_PWREx_DisableFlashPowerDown(void);
|
||||
/* Wakeup Pins control functions */
|
||||
void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
|
||||
void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
|
||||
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
|
||||
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
|
||||
|
||||
/* Power Wakeup PIN IRQ Handler */
|
||||
void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
|
||||
void HAL_PWREx_WKUP1_Callback(void);
|
||||
void HAL_PWREx_WKUP2_Callback(void);
|
||||
void HAL_PWREx_WKUP3_Callback(void);
|
||||
void HAL_PWREx_WKUP4_Callback(void);
|
||||
void HAL_PWREx_WKUP5_Callback(void);
|
||||
void HAL_PWREx_WKUP6_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
|
||||
* @{
|
||||
*/
|
||||
/* Backup regulator control functions */
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
|
||||
|
||||
/* USB regulator control functions */
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
|
||||
void HAL_PWREx_EnableUSBVoltageDetector(void);
|
||||
void HAL_PWREx_DisableUSBVoltageDetector(void);
|
||||
|
||||
/* Battery control functions */
|
||||
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
|
||||
void HAL_PWREx_DisableBatteryCharging(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
|
||||
* @{
|
||||
*/
|
||||
/* Power VBAT/Temperature monitoring functions */
|
||||
void HAL_PWREx_EnableMonitoring(void);
|
||||
void HAL_PWREx_DisableMonitoring(void);
|
||||
uint32_t HAL_PWREx_GetTemperatureLevel(void);
|
||||
uint32_t HAL_PWREx_GetVBATLevel(void);
|
||||
|
||||
/* Power AVD configuration functions */
|
||||
void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
|
||||
void HAL_PWREx_EnableAVD(void);
|
||||
void HAL_PWREx_DisableAVD(void);
|
||||
|
||||
/* Power PVD/AVD IRQ Handler */
|
||||
void HAL_PWREx_PVD_AVD_IRQHandler(void);
|
||||
void HAL_PWREx_AVDCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Macros PWREx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#if defined(SMPS)
|
||||
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
|
||||
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \
|
||||
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \
|
||||
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
|
||||
|
||||
#else
|
||||
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
|
||||
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
|
||||
#endif /*SMPS*/
|
||||
|
||||
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
|
||||
|
||||
#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \
|
||||
((DOMAIN) == PWR_D2_DOMAIN) || \
|
||||
((DOMAIN) == PWR_D3_DOMAIN))
|
||||
|
||||
#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6_LOW))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
|
||||
((POLARITY) == PWR_PIN_POLARITY_LOW))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \
|
||||
((PULL) == PWR_PIN_PULL_UP) || \
|
||||
((PULL) == PWR_PIN_PULL_DOWN))
|
||||
|
||||
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \
|
||||
((FLAG) == PWR_WAKEUP_FLAG2) || \
|
||||
((FLAG) == PWR_WAKEUP_FLAG3) || \
|
||||
((FLAG) == PWR_WAKEUP_FLAG4) || \
|
||||
((FLAG) == PWR_WAKEUP_FLAG5) || \
|
||||
((FLAG) == PWR_WAKEUP_FLAG6))
|
||||
|
||||
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
|
||||
((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
|
||||
|
||||
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_AVD_MODE_NORMAL))
|
||||
|
||||
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
||||
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
||||
|
||||
#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
|
||||
|
||||
#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
|
||||
|
||||
#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
|
||||
((FLAG) == PWR_D2_DOMAIN_FLAGS))
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,487 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_TIM_EX_H
|
||||
#define STM32H7xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
|
||||
/**
|
||||
* @brief TIM Break/Break2 input configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Specifies the source of the timer break input.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source */
|
||||
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
uint32_t Polarity; /*!< Specifies the break input source polarity.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
|
||||
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
|
||||
}
|
||||
TIMEx_BreakInputConfigTypeDef;
|
||||
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
|
||||
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
|
||||
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
|
||||
|
||||
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
|
||||
#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
|
||||
#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
|
||||
#define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
|
||||
|
||||
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
|
||||
#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
|
||||
#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
|
||||
#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
|
||||
#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
|
||||
#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
|
||||
|
||||
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
|
||||
#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
|
||||
|
||||
#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
|
||||
#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
|
||||
#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
|
||||
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
|
||||
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
||||
/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
|
||||
#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */
|
||||
|
||||
#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */
|
||||
#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */
|
||||
|
||||
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */
|
||||
#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
|
||||
#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */
|
||||
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
|
||||
|
||||
#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */
|
||||
#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */
|
||||
#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */
|
||||
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
|
||||
|
||||
#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
|
||||
#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */
|
||||
#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */
|
||||
|
||||
#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
|
||||
#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
|
||||
#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
|
||||
#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
|
||||
#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_3) /* !< TIM15_TI1 is connected to RCC LSE */
|
||||
#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
|
||||
#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
|
||||
|
||||
#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
|
||||
#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
|
||||
#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */
|
||||
#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
|
||||
|
||||
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
|
||||
#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */
|
||||
#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */
|
||||
#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
|
||||
|
||||
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
|
||||
#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to RCC LSI */
|
||||
#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC LSE */
|
||||
#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||||
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||||
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
|
||||
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
|
||||
|
||||
#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\
|
||||
((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\
|
||||
((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\
|
||||
((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\
|
||||
((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\
|
||||
((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\
|
||||
((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\
|
||||
((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\
|
||||
((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
|
||||
((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\
|
||||
((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\
|
||||
((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\
|
||||
((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\
|
||||
((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\
|
||||
((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
|
||||
((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
|
||||
((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
|
||||
((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1))
|
||||
|
||||
#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
|
||||
((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\
|
||||
((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\
|
||||
((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\
|
||||
((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\
|
||||
((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
|
||||
((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
|
||||
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
|
||||
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
|
||||
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7xx_HAL_TIM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,554 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_UART_EX_H
|
||||
#define STM32H7xx_HAL_UART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief UART wake up from stop mode parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
|
||||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
|
||||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
|
||||
be filled up. */
|
||||
|
||||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
||||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
|
||||
|
||||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
|
||||
} UART_WakeUpTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
|
||||
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
|
||||
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
|
||||
* @brief UART FIFO mode
|
||||
* @{
|
||||
*/
|
||||
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
|
||||
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
|
||||
* @brief UART TXFIFO threshold level
|
||||
* @{
|
||||
*/
|
||||
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
|
||||
* @brief UART RXFIFO threshold level
|
||||
* @{
|
||||
*/
|
||||
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
|
||||
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
|
||||
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_D2PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_D2PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART7) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART7_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART7CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART8) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART8_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART8CLKSOURCE_D2PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == LPUART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_LPUART1CLKSOURCE_D3PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_PLL2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_PLL3: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART frame length is valid.
|
||||
* @param __LENGTH__ UART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART wake-up address length is valid.
|
||||
* @param __ADDRESS__ UART wake-up address length.
|
||||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
|
||||
*/
|
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
|
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART TXFIFO threshold level is valid.
|
||||
* @param __THRESHOLD__ UART TXFIFO threshold level.
|
||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
|
||||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
|
||||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
|
||||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
|
||||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
|
||||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART RXFIFO threshold level is valid.
|
||||
* @param __THRESHOLD__ UART RXFIFO threshold level.
|
||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
|
||||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
|
||||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
|
||||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
|
||||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
|
||||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_UART_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,285 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_usart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_USART_EX_H
|
||||
#define STM32H7xx_HAL_USART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Word_Length USARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
|
||||
* @{
|
||||
*/
|
||||
#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */
|
||||
#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
|
||||
* @brief USART SLAVE mode
|
||||
* @{
|
||||
*/
|
||||
#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
|
||||
#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
|
||||
* @brief USART FIFO mode
|
||||
* @{
|
||||
*/
|
||||
#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
|
||||
#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
|
||||
* @brief USART TXFIFO level
|
||||
* @{
|
||||
*/
|
||||
#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
|
||||
#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
|
||||
#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
|
||||
#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
|
||||
#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
|
||||
#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
|
||||
* @brief USART RXFIFO level
|
||||
* @{
|
||||
*/
|
||||
#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
|
||||
#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
|
||||
#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
|
||||
#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
|
||||
#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
|
||||
#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Compute the USART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define USART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame length is valid.
|
||||
* @param __LENGTH__ USART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_9B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
|
||||
* @param __NSS__ USART Negative Slave Select pin management.
|
||||
* @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
|
||||
*/
|
||||
#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
|
||||
((__NSS__) == USART_NSS_SOFT))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART Slave Mode is valid.
|
||||
* @param __STATE__ USART Slave Mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
|
||||
((__STATE__) == USART_SLAVEMODE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART FIFO mode is valid.
|
||||
* @param __STATE__ USART FIFO mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
|
||||
((__STATE__) == USART_FIFOMODE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART TXFIFO threshold level is valid.
|
||||
* @param __THRESHOLD__ USART TXFIFO threshold level.
|
||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
|
||||
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
|
||||
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
|
||||
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
|
||||
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
|
||||
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART RXFIFO threshold level is valid.
|
||||
* @param __THRESHOLD__ USART RXFIFO threshold level.
|
||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
|
||||
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
|
||||
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
|
||||
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
|
||||
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
|
||||
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
|
||||
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
|
||||
HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_USART_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,533 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
|
||||
(#) please refer to programming manual for details in how to configure priority.
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest preemption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
|
||||
inside the stm32h7xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (preemption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @param PreemptPriority The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Disables the MPU
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
|
||||
/* Disable fault exceptions */
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Disable the MPU and clear the control register*/
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU
|
||||
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Enable fault exceptions */
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Ensure MPU setting take effects */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != 0UL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @param PriorityGroup the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval status - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
|
||||
* @retval status - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
|
||||
/**
|
||||
* @brief Returns the current CPU ID.
|
||||
* @retval CPU identifier
|
||||
*/
|
||||
uint32_t HAL_GetCurrentCPUID(void)
|
||||
{
|
||||
if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
|
||||
{
|
||||
return CM7_CPUID;
|
||||
}
|
||||
else
|
||||
{
|
||||
return CM4_CPUID;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/**
|
||||
* @brief Returns the current CPU ID.
|
||||
* @retval CPU identifier
|
||||
*/
|
||||
uint32_t HAL_GetCurrentCPUID(void)
|
||||
{
|
||||
return CM7_CPUID;
|
||||
}
|
||||
|
||||
#endif /*DUAL_CORE*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,705 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_dma_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA Extension HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the DMA Extension peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The DMA Extension HAL driver can be used as follows:
|
||||
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
|
||||
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
|
||||
|
||||
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
|
||||
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
|
||||
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
|
||||
to respectively enable/disable the request generator.
|
||||
|
||||
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
|
||||
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
|
||||
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
|
||||
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
|
||||
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
|
||||
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
|
||||
-@- In Multi (Double) buffer mode, it is possible to update the base address for
|
||||
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
|
||||
-@- Multi (Double) buffer mode is possible with DMA and BDMA instances.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private Constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer with interrupt
|
||||
(+) Change on the fly the memory0 or memory1 address.
|
||||
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
|
||||
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
|
||||
(+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
|
||||
to respectively enable/disable the request generator.
|
||||
(+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
|
||||
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer.
|
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Initialize the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
/* Enable the Double buffer mode */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
|
||||
|
||||
/* Calculate the interrupt clear flag register (IFCR) base address */
|
||||
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
|
||||
|
||||
/* Clear all flags */
|
||||
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
|
||||
}
|
||||
else /* BDMA instance(s) */
|
||||
{
|
||||
/* Enable the Double buffer mode */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
|
||||
|
||||
/* Calculate the interrupt clear flag register (IFCR) base address */
|
||||
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
|
||||
|
||||
/* Clear all flags */
|
||||
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
|
||||
}
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* Clear the DMAMUX request generator overrun flag */
|
||||
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||||
}
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Initialize the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
/* Enable the Double buffer mode */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
|
||||
|
||||
/* Calculate the interrupt clear flag register (IFCR) base address */
|
||||
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
|
||||
|
||||
/* Clear all flags */
|
||||
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
|
||||
}
|
||||
else /* BDMA instance(s) */
|
||||
{
|
||||
/* Enable the Double buffer mode */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
|
||||
|
||||
/* Calculate the interrupt clear flag register (IFCR) base address */
|
||||
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
|
||||
|
||||
/* Clear all flags */
|
||||
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
|
||||
}
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* Clear the DMAMUX request generator overrun flag */
|
||||
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||||
}
|
||||
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
/* Enable Common interrupts*/
|
||||
MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
|
||||
|
||||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
||||
{
|
||||
/*Enable Half Transfer IT if corresponding Callback is set*/
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
|
||||
}
|
||||
}
|
||||
else /* BDMA instance(s) */
|
||||
{
|
||||
/* Enable Common interrupts*/
|
||||
MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
|
||||
|
||||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
||||
{
|
||||
/*Enable Half Transfer IT if corresponding Callback is set*/
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if DMAMUX Synchronization is enabled*/
|
||||
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
||||
{
|
||||
/* Enable DMAMUX sync overrun IT*/
|
||||
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
||||
}
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
|
||||
/* enable the request gen overrun IT*/
|
||||
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
||||
}
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change the memory0 or memory1 address on the fly.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param Address: The new address
|
||||
* @param memory: the memory to be changed, This parameter can be one of
|
||||
* the following values:
|
||||
* MEMORY0 /
|
||||
* MEMORY1
|
||||
* @note The MEMORY0 address can be changed only when the current transfer use
|
||||
* MEMORY1 and the MEMORY1 address can be changed only when the current
|
||||
* transfer use MEMORY0.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
|
||||
{
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
if(memory == MEMORY0)
|
||||
{
|
||||
/* change the memory0 address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* change the memory1 address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
|
||||
}
|
||||
}
|
||||
else /* BDMA instance(s) */
|
||||
{
|
||||
if(memory == MEMORY0)
|
||||
{
|
||||
/* change the memory0 address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* change the memory1 address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
|
||||
{
|
||||
uint32_t syncSignalID = 0;
|
||||
uint32_t syncPolarity = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
|
||||
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
|
||||
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
|
||||
|
||||
if(pSyncConfig->SyncEnable == ENABLE)
|
||||
{
|
||||
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
|
||||
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
|
||||
}
|
||||
syncSignalID = pSyncConfig->SyncSignalID;
|
||||
syncPolarity = pSyncConfig->SyncPolarity;
|
||||
}
|
||||
|
||||
/*Check if the DMA state is ready */
|
||||
if(hdma->State == HAL_DMA_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Disable the synchronization and event generation before applying a new config */
|
||||
CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
|
||||
|
||||
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
|
||||
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
|
||||
(~DMAMUX_CxCR_DMAREQ_ID) , \
|
||||
(syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \
|
||||
((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
|
||||
syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
|
||||
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
|
||||
* contains the request generator parameters.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
HAL_DMA_StateTypeDef temp_state = hdma->State;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
|
||||
}
|
||||
|
||||
|
||||
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
|
||||
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if(hdma->DMAmuxRequestGen == 0U)
|
||||
{
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
||||
|
||||
/* error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
|
||||
{
|
||||
/* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Set the request generator new parameters */
|
||||
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
|
||||
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
|
||||
pRequestGeneratorConfig->Polarity;
|
||||
/* Process Locked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block */
|
||||
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
|
||||
{
|
||||
/* Enable the request generator*/
|
||||
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block */
|
||||
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
|
||||
{
|
||||
/* Disable the request generator*/
|
||||
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DMAMUX interrupt request.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check for DMAMUX Synchronization overrun */
|
||||
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the synchro overrun interrupt */
|
||||
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
if(hdma->DMAmuxRequestGen != 0)
|
||||
{
|
||||
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
|
||||
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the request gen overrun interrupt */
|
||||
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
||||
|
||||
/* Clear the DMAMUX request generator overrun flag */
|
||||
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameter.
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress: The source memory Buffer address
|
||||
* @param DstAddress: The destination memory Buffer address
|
||||
* @param DataLength: The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
||||
{
|
||||
/* Configure DMA Stream data length */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Stream destination address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
|
||||
|
||||
/* Configure DMA Stream source address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Stream source address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
|
||||
}
|
||||
}
|
||||
else /* BDMA instance(s) */
|
||||
{
|
||||
/* Configure DMA Stream data length */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Stream destination address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Stream source address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Stream source address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,559 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
The external interrupt/event controller consists of up to 23 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE (0x00000003U)
|
||||
#define ANALOG_MODE (0x00000008U)
|
||||
#define EXTI_MODE (0x10000000U)
|
||||
#define GPIO_MODE_IT (0x00010000U)
|
||||
#define GPIO_MODE_EVT (0x00020000U)
|
||||
#define RISING_EDGE (0x00100000U)
|
||||
#define FALLING_EDGE (0x00200000U)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010U)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define EXTI_CPU1 (0x01000000U)
|
||||
#define EXTI_CPU2 (0x02000000U)
|
||||
#endif /*DUAL_CORE*/
|
||||
#define GPIO_NUMBER (16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize and de-initialize the GPIOs
|
||||
to be ready for use.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00U;
|
||||
uint32_t iocurrent;
|
||||
uint32_t temp;
|
||||
EXTI_Core_TypeDef *EXTI_CurrentCPU;
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
|
||||
#else
|
||||
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
|
||||
#endif
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00U)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1UL << position);
|
||||
|
||||
if (iocurrent != 0x00U)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3U];
|
||||
temp &= ~(0xFU << ((position & 0x07U) * 4U));
|
||||
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
|
||||
GPIOx->AFR[position >> 3U] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
||||
temp |= (GPIO_Init->Speed << (position * 2U));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2U];
|
||||
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
|
||||
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
|
||||
SYSCFG->EXTICR[position >> 2U] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI_CurrentCPU->IMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->IMR1 = temp;
|
||||
|
||||
temp = EXTI_CurrentCPU->EMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->EMR1 = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR1 = temp;
|
||||
|
||||
temp = EXTI->FTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR1 = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00U;
|
||||
uint32_t iocurrent;
|
||||
uint32_t tmp;
|
||||
EXTI_Core_TypeDef *EXTI_CurrentCPU;
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
|
||||
#else
|
||||
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
|
||||
#endif
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0x00U)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = GPIO_Pin & (1UL << position) ;
|
||||
|
||||
if (iocurrent != 0x00U)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
tmp = SYSCFG->EXTICR[position >> 2U];
|
||||
tmp &= (0x0FUL << (8U * (position & 0x03U)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
|
||||
{
|
||||
tmp = 0x0FUL << (8U * (position & 0x03U));
|
||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
||||
|
||||
/* Clear EXTI line configuration for Current CPU */
|
||||
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
|
||||
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR1 &= ~(iocurrent);
|
||||
EXTI->FTSR1 &= ~(iocurrent);
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO in Analog Mode */
|
||||
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins.
|
||||
* @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
|
||||
{
|
||||
__HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
#else
|
||||
/* EXTI line interrupt detected */
|
||||
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callback.
|
||||
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_hsem.c
|
||||
* @author MCD Application Team
|
||||
* @brief HSEM HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the semaphore peripheral:
|
||||
* + Semaphore Take function (2-Step Procedure) , non blocking
|
||||
* + Semaphore FastTake function (1-Step Procedure) , non blocking
|
||||
* + Semaphore Status check
|
||||
* + Semaphore Clear Key Set and Get
|
||||
* + Release and release all functions
|
||||
* + Semaphore notification enabling and disabling and callnack functions
|
||||
* + IRQ handler management
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
|
||||
(++) the semaphore ID from 0 to 31
|
||||
(++) the process ID from 0 to 255
|
||||
(#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
|
||||
(++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
|
||||
(#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
|
||||
(++) the semaphore ID from 0_ID to 31
|
||||
(++) It returns 1 if the given semaphore is taken otherwise (Free) zero
|
||||
(#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
|
||||
(++) the semaphore ID from 0 to 31
|
||||
(++) the process ID from 0 to 255:
|
||||
(++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
|
||||
may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
|
||||
semaphore remains taken (locked)
|
||||
|
||||
(#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
|
||||
This function takes as parameters :
|
||||
(++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
|
||||
HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
|
||||
(++) the Master ID:
|
||||
(++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
|
||||
to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
|
||||
Key or the MasterID doesn't match, semaphores remains taken (locked)
|
||||
|
||||
(#)Semaphores Release all key functions:
|
||||
(++) HAL_HSEM_SetClearKey() to set semaphore release all Key
|
||||
(++) HAL_HSEM_GetClearKey() to get release all Key
|
||||
(#)Semaphores notification functions :
|
||||
(++) HAL_HSEM_ActivateNotification to activate a notification callback on
|
||||
a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
|
||||
the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
|
||||
semaphores (bitfield).
|
||||
|
||||
(++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
|
||||
(++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
|
||||
Used by the notification functions
|
||||
*** HSEM HAL driver macros list ***
|
||||
=============================================
|
||||
[..] Below the list of most used macros in HSEM HAL driver.
|
||||
|
||||
(+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
|
||||
[..] Example of use :
|
||||
[..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
|
||||
[..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
|
||||
(+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
|
||||
(+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
|
||||
(+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
|
||||
(+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
|
||||
(+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM HSEM
|
||||
* @brief HSEM HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#if defined(DUAL_CORE)
|
||||
#ifndef HSEM_R_MASTERID
|
||||
#define HSEM_R_MASTERID HSEM_R_COREID
|
||||
#endif
|
||||
|
||||
#ifndef HSEM_RLR_MASTERID
|
||||
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
|
||||
#endif
|
||||
|
||||
#ifndef HSEM_CR_MASTERID
|
||||
#define HSEM_CR_MASTERID HSEM_CR_COREID
|
||||
#endif
|
||||
#endif /* DUAL_CORE */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
|
||||
* @brief HSEM Take and Release functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM Take and Release functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Take a semaphore with 2 Step method
|
||||
(+) Fast Take a semaphore with 1 Step method
|
||||
(+) Check semaphore state Taken or not
|
||||
(+) Release a semaphore
|
||||
(+) Release all semaphore at once
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Take a semaphore in 2 Step mode.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @param ProcessID: Process ID from 0 to 255
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
assert_param(IS_HSEM_PROCESSID(ProcessID));
|
||||
|
||||
#if USE_MULTI_CORE_SHARED_CODE != 0U
|
||||
/* First step write R register with MasterID, processID and take bit=1*/
|
||||
HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
|
||||
|
||||
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
|
||||
if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
|
||||
{
|
||||
/*take success when MasterID and ProcessID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
#else
|
||||
/* First step write R register with MasterID, processID and take bit=1*/
|
||||
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
|
||||
|
||||
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
|
||||
if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
|
||||
{
|
||||
/*take success when MasterID and ProcessID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Semaphore take fails*/
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fast Take a semaphore with 1 Step mode.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
|
||||
#if USE_MULTI_CORE_SHARED_CODE != 0U
|
||||
/* Read the RLR register to take the semaphore */
|
||||
if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
|
||||
{
|
||||
/*take success when MasterID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
#else
|
||||
/* Read the RLR register to take the semaphore */
|
||||
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
|
||||
{
|
||||
/*take success when MasterID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Semaphore take fails */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/**
|
||||
* @brief Check semaphore state Taken or not.
|
||||
* @param SemID: semaphore ID
|
||||
* @retval HAL HSEM state
|
||||
*/
|
||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
|
||||
{
|
||||
return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Release a semaphore.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @param ProcessID: Process ID from 0 to 255
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
assert_param(IS_HSEM_PROCESSID(ProcessID));
|
||||
|
||||
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
|
||||
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release All semaphore used by a given Master .
|
||||
* @param Key: Semaphore Key , value from 0 to 0xFFFF
|
||||
* @param CoreID: CoreID of the CPU that is using semaphores to be released
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
|
||||
{
|
||||
assert_param(IS_HSEM_KEY(Key));
|
||||
assert_param(IS_HSEM_COREID(CoreID));
|
||||
|
||||
HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
||||
* @brief HSEM Set and Get Key functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM Set and Get Key functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set semaphore Key
|
||||
(+) Get semaphore Key
|
||||
@endverbatim
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set semaphore Key .
|
||||
* @param Key: Semaphore Key , value from 0 to 0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_SetClearKey(uint32_t Key)
|
||||
{
|
||||
assert_param(IS_HSEM_KEY(Key));
|
||||
|
||||
MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get semaphore Key .
|
||||
* @retval Semaphore Key , value from 0 to 0xFFFF
|
||||
*/
|
||||
uint32_t HAL_HSEM_GetClearKey(void)
|
||||
{
|
||||
return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
|
||||
* @brief HSEM Notification functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM IRQ handler management and Notification functions #####
|
||||
==============================================================================
|
||||
[..] This section provides HSEM IRQ handler and Notification function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Activate Semaphore release Notification for a given Semaphores Mask .
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval Semaphore Key
|
||||
*/
|
||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
|
||||
{
|
||||
#if USE_MULTI_CORE_SHARED_CODE != 0U
|
||||
/*enable the semaphore mask interrupts */
|
||||
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
|
||||
{
|
||||
/*Use interrupt line 0 for CPU1 Master */
|
||||
HSEM->C1IER |= SemMask;
|
||||
}
|
||||
else /* HSEM_CPU2_COREID */
|
||||
{
|
||||
/*Use interrupt line 1 for CPU2 Master*/
|
||||
HSEM->C2IER |= SemMask;
|
||||
}
|
||||
#else
|
||||
HSEM_COMMON->IER |= SemMask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval Semaphore Key
|
||||
*/
|
||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
|
||||
{
|
||||
#if USE_MULTI_CORE_SHARED_CODE != 0U
|
||||
/*enable the semaphore mask interrupts */
|
||||
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
|
||||
{
|
||||
/*Use interrupt line 0 for CPU1 Master */
|
||||
HSEM->C1IER &= ~SemMask;
|
||||
}
|
||||
else /* HSEM_CPU2_COREID */
|
||||
{
|
||||
/*Use interrupt line 1 for CPU2 Master*/
|
||||
HSEM->C2IER &= ~SemMask;
|
||||
}
|
||||
#else
|
||||
HSEM_COMMON->IER &= ~SemMask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles HSEM interrupt request
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_IRQHandler(void)
|
||||
{
|
||||
uint32_t statusreg;
|
||||
#if USE_MULTI_CORE_SHARED_CODE != 0U
|
||||
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
|
||||
{
|
||||
/* Get the list of masked freed semaphores*/
|
||||
statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
|
||||
|
||||
/*Disable Interrupts*/
|
||||
HSEM->C1IER &= ~((uint32_t)statusreg);
|
||||
|
||||
/*Clear Flags*/
|
||||
HSEM->C1ICR = ((uint32_t)statusreg);
|
||||
}
|
||||
else /* HSEM_CPU2_COREID */
|
||||
{
|
||||
/* Get the list of masked freed semaphores*/
|
||||
statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
|
||||
|
||||
/*Disable Interrupts*/
|
||||
HSEM->C2IER &= ~((uint32_t)statusreg);
|
||||
|
||||
/*Clear Flags*/
|
||||
HSEM->C2ICR = ((uint32_t)statusreg);
|
||||
}
|
||||
#else
|
||||
/* Get the list of masked freed semaphores*/
|
||||
statusreg = HSEM_COMMON->MISR;
|
||||
|
||||
/*Disable Interrupts*/
|
||||
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
|
||||
|
||||
/*Clear Flags*/
|
||||
HSEM_COMMON->ICR = ((uint32_t)statusreg);
|
||||
|
||||
#endif
|
||||
/* Call FreeCallback */
|
||||
HAL_HSEM_FreeCallback(statusreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Semaphore Released Callback.
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(SemMask);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_HSEM_FreeCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,635 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
#if !defined (DUAL_CORE)
|
||||
#define PVD_MODE_IT ((uint32_t)0x00010000U)
|
||||
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
|
||||
#endif /* DUAL_CORE */
|
||||
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
|
||||
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
|
||||
#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
|
||||
* @brief Initialization and De-Initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and De-Initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers and backup SRAM) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
|
||||
* @note This functionality is not available in this product.
|
||||
* The prototype is kept just to maintain compatibility with other products.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
/* Enable access to RTC and backup registers */
|
||||
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
/* Disable access to RTC and backup registers */
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).
|
||||
(+) A PVDO flag is available to indicate if VDD is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line 16 to generate an interrupt if enabled.
|
||||
It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
*** Wake-up pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) Wake-up pin is used to wake up the system from Standby mode.
|
||||
The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.
|
||||
The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.
|
||||
(+) There are up to six Wake-up pin in the STM32H7 devices family.
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The device present 3 principles low-power modes features:
|
||||
(+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.
|
||||
(+) STOP mode: all clocks are stopped and the regulator is running in main or low power mode.
|
||||
(+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply
|
||||
regulator is powered off.
|
||||
|
||||
*** SLEEP mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
|
||||
function.
|
||||
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
-@@- The Regulator parameter is not used for the STM32H7 family
|
||||
and is kept as parameter just to maintain compatibility with the
|
||||
lower power families (STM32L).
|
||||
(+) Exit:
|
||||
Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** STOP mode ***
|
||||
=================
|
||||
[..]
|
||||
In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption In Stop mode, FLASH can be powered off before
|
||||
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
|
||||
It can be switched on again by software after exiting the Stop mode using
|
||||
the HAL_PWREx_DisableFlashPowerDown() function.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
|
||||
function with:
|
||||
(++) Regulator:
|
||||
(+++) PWR_MAINREGULATOR_ON: Main regulator ON.
|
||||
(+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
|
||||
(++) STOPEntry:
|
||||
(+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
(+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
(+) Exit:
|
||||
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
|
||||
*** STANDBY mode ***
|
||||
====================
|
||||
[..]
|
||||
(+)
|
||||
The system Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
|
||||
The system is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||||
circuitry.
|
||||
[..]
|
||||
The voltage regulator is OFF.
|
||||
(++) Entry:
|
||||
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(++) Exit:
|
||||
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
|
||||
wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event or a time-stamp event, without depending on
|
||||
an external interrupt (Auto-wakeup mode).
|
||||
(+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config */
|
||||
#if !defined (DUAL_CORE)
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
#endif /* DUAL_CORE */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
#if !defined (DUAL_CORE)
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
/* Enable the power voltage detector */
|
||||
SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
/* Disable the power voltage detector */
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality.
|
||||
* @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
|
||||
* This parameter can be one of the following legacy values, which sets the default:
|
||||
* polarity detection on high level (rising edge):
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4,
|
||||
* PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where
|
||||
* the user can explicitly states the enabled pin and the chosen polarity.
|
||||
* @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
|
||||
* @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
|
||||
* @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
|
||||
* @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
|
||||
* @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
|
||||
* @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
|
||||
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
|
||||
|
||||
/* Enable and Specify the Wake-Up pin polarity and the pull configuration
|
||||
for the event detection (rising or falling edge) */
|
||||
MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3
|
||||
* @arg PWR_WAKEUP_PIN4
|
||||
* @arg PWR_WAKEUP_PIN5
|
||||
* @arg PWR_WAKEUP_PIN6
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
|
||||
CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter the current core to Sleep mode.
|
||||
* @param Regulator: Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @note This parameter is not used for the STM32H7 family and is kept as parameter
|
||||
* just to maintain compatibility with the lower power families.
|
||||
* @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select SLEEP mode entry */
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter the system to STOP mode.
|
||||
* @note This API must be used only for single core devices.
|
||||
* @note In System Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting System Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as default system wakeup clock.
|
||||
* @note In System STOP mode, when the voltage regulator operates in low power mode,
|
||||
* an additional startup delay is incurred when the system is waking up.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator: Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in Stop mode */
|
||||
tmpreg = PWR->CR1;
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR1_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR1 = tmpreg;
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/* Keep DSTOP mode when D1 domain enters Deepsleep */
|
||||
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
|
||||
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);
|
||||
#else
|
||||
/* Keep DSTOP mode when D1 domain enters Deepsleep */
|
||||
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
|
||||
|
||||
/* Keep DSTOP mode when D2 domain enters Deepsleep */
|
||||
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
|
||||
|
||||
/* Keep DSTOP mode when D3 domain enters Deepsleep */
|
||||
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Ensure that all instructions done before entering STOP mode */
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* Select Stop mode entry */
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter the system to STANDBY mode.
|
||||
* @note The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
|
||||
* @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
#if defined(DUAL_CORE)
|
||||
/* Keep DSTANDBY mode when D1 domain enters Deepsleep */
|
||||
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
|
||||
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);
|
||||
#else
|
||||
/* Keep DSTANDBY mode when D1 domain enters Deepsleep */
|
||||
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
|
||||
|
||||
/* Keep DSTANDBY mode when D2 domain enters Deepsleep */
|
||||
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
|
||||
|
||||
/* Keep DSTANDBY mode when D3 domain enters Deepsleep */
|
||||
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable CORTEX SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable CORTEX SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
#if defined(DUAL_CORE)
|
||||
/* PVD EXTI line interrupt detected */
|
||||
if (HAL_GetCurrentCPUID() == CM7_CPUID)
|
||||
{
|
||||
/* Check PWR EXTI flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR EXTI pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check PWR EXTI D2 flag */
|
||||
if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR EXTI D2 pending bit */
|
||||
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* PVD EXTI line interrupt detected */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR EXTI pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
#endif /*DUAL_CORE*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,731 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_uart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended UART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### UART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure.
|
||||
|
||||
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
|
||||
by calling the HAL_RS485Ex_Init() API.
|
||||
|
||||
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
|
||||
|
||||
-@- When UART operates in FIFO mode, FIFO mode must be enabled prior
|
||||
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
|
||||
configured prior starting RX/TX transfers.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx UARTEx
|
||||
* @brief UART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* UART RX FIFO depth */
|
||||
#define RX_FIFO_DEPTH 8U
|
||||
|
||||
/* UART TX FIFO depth */
|
||||
#define TX_FIFO_DEPTH 8U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
|
||||
in asynchronous mode.
|
||||
(+) For the asynchronous mode the parameters below can be configured:
|
||||
(++) Baud Rate
|
||||
(++) Word Length
|
||||
(++) Stop Bit
|
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written
|
||||
in the data register is transmitted but is changed by the parity bit.
|
||||
(++) Hardware flow control
|
||||
(++) Receiver/transmitter modes
|
||||
(++) Over Sampling Method
|
||||
(++) One-Bit Sampling Method
|
||||
(+) For the asynchronous mode, the following advanced features can be configured as well:
|
||||
(++) TX and/or RX pin level inversion
|
||||
(++) data logical level inversion
|
||||
(++) RX and TX pins swap
|
||||
(++) RX overrun detection disabling
|
||||
(++) DMA disabling on RX error
|
||||
(++) MSB first on communication line
|
||||
(++) auto Baud rate detection
|
||||
[..]
|
||||
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
|
||||
procedures (details for the procedures are available in reference manual).
|
||||
|
||||
@endverbatim
|
||||
|
||||
Depending on the frame length defined by the M1 and M0 bits (7-bit,
|
||||
8-bit or 9-bit), the possible UART formats are listed in the
|
||||
following table.
|
||||
|
||||
Table 1. UART frame format.
|
||||
+-----------------------------------------------------------------------+
|
||||
| M1 bit | M0 bit | PCE bit | UART frame |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
|
||||
+-----------------------------------------------------------------------+
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the RS485 Driver enable feature according to the specified
|
||||
* parameters in the UART_InitTypeDef and creates the associated handle.
|
||||
* @param huart UART handle.
|
||||
* @param Polarity Select the driver enable polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
|
||||
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
|
||||
* @param AssertionTime Driver Enable assertion time:
|
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable)
|
||||
* signal and the beginning of the start bit. It is expressed in sample time
|
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
|
||||
* @param DeassertionTime Driver Enable deassertion time:
|
||||
* 5-bit value defining the time between the end of the last stop bit, in a
|
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
|
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
|
||||
* oversampling rate).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the Driver Enable UART instance */
|
||||
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
|
||||
|
||||
/* Check the Driver Enable polarity */
|
||||
assert_param(IS_UART_DE_POLARITY(Polarity));
|
||||
|
||||
/* Check the Driver Enable assertion time */
|
||||
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
|
||||
|
||||
/* Check the Driver Enable deassertion time */
|
||||
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
huart->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
UART_InitCallbacksToDefault(huart);
|
||||
|
||||
if (huart->MspInitCallback == NULL)
|
||||
{
|
||||
huart->MspInitCallback = HAL_UART_MspInit;
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
huart->MspInitCallback(huart);
|
||||
#else
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
|
||||
HAL_UART_MspInit(huart);
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
/* Set the Driver Enable polarity */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */
|
||||
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
||||
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
|
||||
* @brief Extended functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of Wakeup and FIFO mode related callback functions.
|
||||
|
||||
(#) Wakeup from Stop mode Callback:
|
||||
(+) HAL_UARTEx_WakeupCallback()
|
||||
|
||||
(#) TX/RX Fifos Callbacks:
|
||||
(+) HAL_UARTEx_RxFifoFullCallback()
|
||||
(+) HAL_UARTEx_TxFifoEmptyCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief UART wakeup from Stop mode callback.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(huart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART RX Fifo full callback.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(huart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART TX Fifo empty callback.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(huart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
|
||||
detection length to more than 4 bits for multiprocessor address mark wake up.
|
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
|
||||
trigger: address match, Start Bit detection or RXNE bit status.
|
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
|
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
|
||||
(+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
|
||||
(+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
|
||||
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
|
||||
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set
|
||||
* to address mark, the UART handles only 4-bit long addresses detection;
|
||||
* this API allows to enable longer addresses detection (6-, 7- or 8-bit
|
||||
* long).
|
||||
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
|
||||
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
|
||||
* @param huart UART handle.
|
||||
* @param AddressLength This parameter can be one of the following values:
|
||||
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
|
||||
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
|
||||
{
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the address length parameter */
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection.
|
||||
* @note It is the application responsibility to enable the interrupt used as
|
||||
* usart_wkup interrupt source before entering low-power mode.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_WAKEUP_ON_ADDRESS
|
||||
* @arg @ref UART_WAKEUP_ON_STARTBIT
|
||||
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* check the wake-up from stop mode UART instance */
|
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
||||
/* check the wake-up selection parameter */
|
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the wake-up selection scheme */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
||||
{
|
||||
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* Init tickstart for timeout managment*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until REACK flag is set */
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
status = HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the UART State */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode.
|
||||
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UESM bit */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UESM bit */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the FIFO mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Save actual UART configuration */
|
||||
tmpcr1 = READ_REG(huart->Instance->CR1);
|
||||
|
||||
/* Disable UART */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Enable FIFO mode */
|
||||
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
|
||||
huart->FifoMode = UART_FIFOMODE_ENABLE;
|
||||
|
||||
/* Restore UART configuration */
|
||||
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
UARTEx_SetNbDataToProcess(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the FIFO mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Save actual UART configuration */
|
||||
tmpcr1 = READ_REG(huart->Instance->CR1);
|
||||
|
||||
/* Disable UART */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Enable FIFO mode */
|
||||
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
|
||||
huart->FifoMode = UART_FIFOMODE_DISABLE;
|
||||
|
||||
/* Restore UART configuration */
|
||||
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the TXFIFO threshold.
|
||||
* @param huart UART handle.
|
||||
* @param Threshold TX FIFO threshold value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_1_8
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_1_4
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_1_2
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_3_4
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
|
||||
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
||||
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Save actual UART configuration */
|
||||
tmpcr1 = READ_REG(huart->Instance->CR1);
|
||||
|
||||
/* Disable UART */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Update TX threshold configuration */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
UARTEx_SetNbDataToProcess(huart);
|
||||
|
||||
/* Restore UART configuration */
|
||||
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RXFIFO threshold.
|
||||
* @param huart UART handle.
|
||||
* @param Threshold RX FIFO threshold value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_1_8
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_1_4
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_1_2
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_3_4
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
|
||||
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
||||
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Save actual UART configuration */
|
||||
tmpcr1 = READ_REG(huart->Instance->CR1);
|
||||
|
||||
/* Disable UART */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Update RX threshold configuration */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
UARTEx_SetNbDataToProcess(huart);
|
||||
|
||||
/* Restore UART configuration */
|
||||
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection UART wake up from stop mode parameters.
|
||||
* @retval None
|
||||
*/
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
|
||||
|
||||
/* Set the USART address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
|
||||
|
||||
/* Set the USART address node */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calculate the number of data to process in RX/TX ISR.
|
||||
* @note The RX FIFO depth and the TX FIFO depth is extracted from
|
||||
* the UART configuration registers.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
||||
{
|
||||
uint8_t rx_fifo_depth;
|
||||
uint8_t tx_fifo_depth;
|
||||
uint8_t rx_fifo_threshold;
|
||||
uint8_t tx_fifo_threshold;
|
||||
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
|
||||
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
||||
{
|
||||
huart->NbTxDataToProcess = 1U;
|
||||
huart->NbRxDataToProcess = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_fifo_depth = RX_FIFO_DEPTH;
|
||||
tx_fifo_depth = TX_FIFO_DEPTH;
|
||||
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
||||
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
||||
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
|
||||
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,532 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_usart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended USART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### USART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
|
||||
|
||||
-@- When USART operates in FIFO mode, FIFO mode must be enabled prior
|
||||
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
|
||||
configured prior starting RX/TX transfers.
|
||||
|
||||
(#) Slave mode enabling/disabling and NSS pin configuration.
|
||||
|
||||
-@- When USART operates in Slave mode, Slave mode must be enabled prior
|
||||
starting RX/TX transfers.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx USARTEx
|
||||
* @brief USART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* UART RX FIFO depth */
|
||||
#define RX_FIFO_DEPTH 8U
|
||||
|
||||
/* UART TX FIFO depth */
|
||||
#define TX_FIFO_DEPTH 8U
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
|
||||
* @brief Extended USART Transmit/Receive functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of FIFO mode related callback functions.
|
||||
|
||||
(#) TX/RX Fifos Callbacks:
|
||||
(+) HAL_USARTEx_RxFifoFullCallback()
|
||||
(+) HAL_USARTEx_TxFifoEmptyCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART RX Fifo full callback.
|
||||
* @param husart USART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(husart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USART TX Fifo empty callback.
|
||||
* @param husart USART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(husart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
|
||||
(+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
|
||||
(+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
|
||||
(+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
|
||||
(+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
|
||||
(+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
|
||||
(+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the SPI slave mode.
|
||||
* @note When the USART operates in SPI slave mode, it handles data flow using
|
||||
* the serial interface clock derived from the external SCLK signal
|
||||
* provided by the external master SPI device.
|
||||
* @note In SPI slave mode, the USART must be enabled before starting the master
|
||||
* communications (or between frames while the clock is stable). Otherwise,
|
||||
* if the USART slave is enabled while the master is in the middle of a
|
||||
* frame, it will become desynchronized with the master.
|
||||
* @note The data register of the slave needs to be ready before the first edge
|
||||
* of the communication clock or before the end of the ongoing communication,
|
||||
* otherwise the SPI slave will transmit zeros.
|
||||
* @param husart USART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* In SPI slave mode mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bit in the USART_CR2 register
|
||||
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
|
||||
CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
||||
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
||||
|
||||
/* Enable SPI slave mode */
|
||||
SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->SlaveMode = USART_SLAVEMODE_ENABLE;
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Enable USART */
|
||||
__HAL_USART_ENABLE(husart);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SPI slave mode.
|
||||
* @param husart USART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Disable SPI slave mode */
|
||||
CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->SlaveMode = USART_SLAVEMODE_ENABLE;
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the Slave Select input pin (NSS).
|
||||
* @note Software NSS management: SPI slave will always be selected and NSS
|
||||
* input pin will be ignored.
|
||||
* @note Hardware NSS management: the SPI slave selection depends on NSS
|
||||
* input pin. The slave is selected when NSS is low and deselected when
|
||||
* NSS is high.
|
||||
* @param husart USART handle.
|
||||
* @param NSSConfig NSS configuration.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_NSS_HARD
|
||||
* @arg @ref USART_NSS_SOFT
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
|
||||
assert_param(IS_USART_NSS(NSSConfig));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Program DIS_NSS bit in the USART_CR2 register */
|
||||
MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the FIFO mode.
|
||||
* @param husart USART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Enable FIFO mode */
|
||||
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
|
||||
husart->FifoMode = USART_FIFOMODE_ENABLE;
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
USARTEx_SetNbDataToProcess(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the FIFO mode.
|
||||
* @param husart USART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Enable FIFO mode */
|
||||
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
|
||||
husart->FifoMode = USART_FIFOMODE_DISABLE;
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the TXFIFO threshold.
|
||||
* @param husart USART handle.
|
||||
* @param Threshold TX FIFO threshold value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_1_8
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_1_4
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_1_2
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_3_4
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_7_8
|
||||
* @arg @ref USART_TXFIFO_THRESHOLD_8_8
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
|
||||
assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Update TX threshold configuration */
|
||||
MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
USARTEx_SetNbDataToProcess(husart);
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RXFIFO threshold.
|
||||
* @param husart USART handle.
|
||||
* @param Threshold RX FIFO threshold value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_1_8
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_1_4
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_1_2
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_3_4
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_7_8
|
||||
* @arg @ref USART_RXFIFO_THRESHOLD_8_8
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
|
||||
assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(husart);
|
||||
|
||||
husart->State = HAL_USART_STATE_BUSY;
|
||||
|
||||
/* Save actual USART configuration */
|
||||
tmpcr1 = READ_REG(husart->Instance->CR1);
|
||||
|
||||
/* Disable USART */
|
||||
__HAL_USART_DISABLE(husart);
|
||||
|
||||
/* Update RX threshold configuration */
|
||||
MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
||||
|
||||
/* Determine the number of data to process during RX/TX ISR execution */
|
||||
USARTEx_SetNbDataToProcess(husart);
|
||||
|
||||
/* Restore USART configuration */
|
||||
WRITE_REG(husart->Instance->CR1, tmpcr1);
|
||||
|
||||
husart->State = HAL_USART_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(husart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Calculate the number of data to process in RX/TX ISR.
|
||||
* @note The RX FIFO depth and the TX FIFO depth is extracted from
|
||||
* the USART configuration registers.
|
||||
* @param husart USART handle.
|
||||
* @retval None
|
||||
*/
|
||||
static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
|
||||
{
|
||||
uint8_t rx_fifo_depth;
|
||||
uint8_t tx_fifo_depth;
|
||||
uint8_t rx_fifo_threshold;
|
||||
uint8_t tx_fifo_threshold;
|
||||
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
|
||||
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
|
||||
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
|
||||
{
|
||||
husart->NbTxDataToProcess = 1U;
|
||||
husart->NbRxDataToProcess = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
rx_fifo_depth = RX_FIFO_DEPTH;
|
||||
tx_fifo_depth = TX_FIFO_DEPTH;
|
||||
rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
|
||||
tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
|
||||
husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
|
||||
husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM
|
||||
@REM Read about available command line parameters in the C-SPY Debugging
|
||||
@REM Guide. Hints about additional command line parameters that may be
|
||||
@REM useful in specific cases:
|
||||
@REM --download_only Downloads a code image without starting a debug
|
||||
@REM session afterwards.
|
||||
@REM --silent Omits the sign-on message.
|
||||
@REM --timeout Limits the maximum allowed execution time.
|
||||
@REM
|
||||
|
||||
|
||||
@echo off
|
||||
|
||||
if not "%~1" == "" goto debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl"
|
||||
|
||||
@echo off
|
||||
goto end
|
||||
|
||||
:debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl"
|
||||
|
||||
@echo off
|
||||
:end
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
param([String]$debugfile = "");
|
||||
|
||||
# This powershell file has been generated by the IAR Embedded Workbench
|
||||
# C - SPY Debugger, as an aid to preparing a command line for running
|
||||
# the cspybat command line utility using the appropriate settings.
|
||||
#
|
||||
# Note that this file is generated every time a new debug session
|
||||
# is initialized, so you may want to move or rename the file before
|
||||
# making changes.
|
||||
#
|
||||
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
|
||||
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
|
||||
#
|
||||
# Read about available command line parameters in the C - SPY Debugging
|
||||
# Guide. Hints about additional command line parameters that may be
|
||||
# useful in specific cases :
|
||||
# --download_only Downloads a code image without starting a debug
|
||||
# session afterwards.
|
||||
# --silent Omits the sign - on message.
|
||||
# --timeout Limits the maximum allowed execution time.
|
||||
#
|
||||
|
||||
|
||||
if ($debugfile -eq "")
|
||||
{
|
||||
& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl"
|
||||
}
|
||||
else
|
||||
{
|
||||
& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM4.driver.xcl"
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
"--endian=little"
|
||||
|
||||
"--cpu=Cortex-M4"
|
||||
|
||||
"--fpu=VFPv4_SP"
|
||||
|
||||
"-p"
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\ST\STM32H7x5_CM4.ddf"
|
||||
|
||||
"--semihosting"
|
||||
|
||||
"--device=STM32H745XI_CM4"
|
||||
|
||||
"--multicore_nr_of_cores=1"
|
||||
|
||||
"--jet_script_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32.ProbeScript"
|
||||
|
||||
"--jet_standard_reset=9,0,0"
|
||||
|
||||
"--reset_style=\"0,-,0,Disabled__no_reset_\""
|
||||
|
||||
"--reset_style=\"1,-,0,Software\""
|
||||
|
||||
"--reset_style=\"2,-,0,Hardware\""
|
||||
|
||||
"--reset_style=\"3,-,0,Core\""
|
||||
|
||||
"--reset_style=\"4,-,0,System\""
|
||||
|
||||
"--reset_style=\"9,ConnectUnderReset,1,Connect_during_reset\""
|
||||
|
||||
"--jet_power_from_probe=leave_on"
|
||||
|
||||
"--drv_interface=SWD"
|
||||
|
||||
"--drv_catch_exceptions=0xff0"
|
||||
|
||||
"--board_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM4.board"
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll"
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armJET.dll"
|
||||
|
||||
"C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\STM32H745I_Discovery_CM4\Exe\STM32H745I_Discovery_CM4.out"
|
||||
|
||||
--plugin="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armbat.dll"
|
||||
|
||||
--flash_loader="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM4.board"
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
@REM This batch file has been generated by the IAR Embedded Workbench
|
||||
@REM C-SPY Debugger, as an aid to preparing a command line for running
|
||||
@REM the cspybat command line utility using the appropriate settings.
|
||||
@REM
|
||||
@REM Note that this file is generated every time a new debug session
|
||||
@REM is initialized, so you may want to move or rename the file before
|
||||
@REM making changes.
|
||||
@REM
|
||||
@REM You can launch cspybat by typing the name of this batch file followed
|
||||
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
|
||||
@REM
|
||||
@REM Read about available command line parameters in the C-SPY Debugging
|
||||
@REM Guide. Hints about additional command line parameters that may be
|
||||
@REM useful in specific cases:
|
||||
@REM --download_only Downloads a code image without starting a debug
|
||||
@REM session afterwards.
|
||||
@REM --silent Omits the sign-on message.
|
||||
@REM --timeout Limits the maximum allowed execution time.
|
||||
@REM
|
||||
|
||||
|
||||
@echo off
|
||||
|
||||
if not "%~1" == "" goto debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl"
|
||||
|
||||
@echo off
|
||||
goto end
|
||||
|
||||
:debugFile
|
||||
|
||||
@echo on
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl"
|
||||
|
||||
@echo off
|
||||
:end
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
param([String]$debugfile = "");
|
||||
|
||||
# This powershell file has been generated by the IAR Embedded Workbench
|
||||
# C - SPY Debugger, as an aid to preparing a command line for running
|
||||
# the cspybat command line utility using the appropriate settings.
|
||||
#
|
||||
# Note that this file is generated every time a new debug session
|
||||
# is initialized, so you may want to move or rename the file before
|
||||
# making changes.
|
||||
#
|
||||
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
|
||||
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
|
||||
#
|
||||
# Read about available command line parameters in the C - SPY Debugging
|
||||
# Guide. Hints about additional command line parameters that may be
|
||||
# useful in specific cases :
|
||||
# --download_only Downloads a code image without starting a debug
|
||||
# session afterwards.
|
||||
# --silent Omits the sign - on message.
|
||||
# --timeout Limits the maximum allowed execution time.
|
||||
#
|
||||
|
||||
|
||||
if ($debugfile -eq "")
|
||||
{
|
||||
& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl"
|
||||
}
|
||||
else
|
||||
{
|
||||
& "C:\devtools\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\settings\Project.STM32H745I_Discovery_CM7.driver.xcl"
|
||||
}
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
"--endian=little"
|
||||
|
||||
"--cpu=Cortex-M7"
|
||||
|
||||
"--fpu=VFPv5_D16"
|
||||
|
||||
"-p"
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\ST\STM32H7x5_CM7.ddf"
|
||||
|
||||
"--drv_verify_download"
|
||||
|
||||
"--semihosting"
|
||||
|
||||
"--device=STM32H745XI_CM7"
|
||||
|
||||
"--multicore_nr_of_cores=1"
|
||||
|
||||
"--jet_script_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32.ProbeScript"
|
||||
|
||||
"--jet_standard_reset=9,0,0"
|
||||
|
||||
"--reset_style=\"0,-,0,Disabled__no_reset_\""
|
||||
|
||||
"--reset_style=\"1,-,0,Software\""
|
||||
|
||||
"--reset_style=\"2,-,0,Hardware\""
|
||||
|
||||
"--reset_style=\"3,-,0,Core\""
|
||||
|
||||
"--reset_style=\"4,-,0,System\""
|
||||
|
||||
"--reset_style=\"9,ConnectUnderReset,1,Connect_during_reset\""
|
||||
|
||||
"--jet_power_from_probe=leave_on"
|
||||
|
||||
"--drv_interface=SWD"
|
||||
|
||||
"--drv_catch_exceptions=0xff0"
|
||||
|
||||
"--board_file=C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM7.board"
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll"
|
||||
|
||||
"C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armJET.dll"
|
||||
|
||||
"C:\Users\ribarry\Dev\FreeRTOS\Trial\Active\STM32H7_dual_core\WorkingCopy\Demo\CORTEX_M7_M4_STM32H745I_Discovery_IAR\STM32H745I_Discovery_CM7\Exe\STM32H745I_Discovery_CM7.out"
|
||||
|
||||
--plugin="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\bin\armbat.dll"
|
||||
|
||||
--flash_loader="C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_CM7.board"
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<crun>
|
||||
<version>1</version>
|
||||
<filter_entries>
|
||||
<filter index="0" type="default">
|
||||
<type>*</type>
|
||||
<start_file>*</start_file>
|
||||
<end_file>*</end_file>
|
||||
<action_debugger>0</action_debugger>
|
||||
<action_log>1</action_log>
|
||||
</filter>
|
||||
</filter_entries>
|
||||
</crun>
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,131 @@
|
|||
<?xml version="1.0"?>
|
||||
<settings>
|
||||
<ArmDriver>
|
||||
<EnableCache>0</EnableCache>
|
||||
</ArmDriver>
|
||||
<StLinkDriver>
|
||||
<stlinkResetStyle>0</stlinkResetStyle>
|
||||
<stlinkResetStrategy>2</stlinkResetStrategy>
|
||||
<CStepIntDis>_ 0</CStepIntDis>
|
||||
<LeaveTargetRunning>_ 1</LeaveTargetRunning>
|
||||
</StLinkDriver>
|
||||
<Stack>
|
||||
<FillEnabled>0</FillEnabled>
|
||||
<OverflowWarningsEnabled>1</OverflowWarningsEnabled>
|
||||
<WarningThreshold>90</WarningThreshold>
|
||||
<SpWarningsEnabled>1</SpWarningsEnabled>
|
||||
<WarnLogOnly>1</WarnLogOnly>
|
||||
<UseTrigger>1</UseTrigger>
|
||||
<TriggerName>main</TriggerName>
|
||||
<LimitSize>0</LimitSize>
|
||||
<ByteLimit>50</ByteLimit>
|
||||
</Stack>
|
||||
<PlDriver>
|
||||
<FirstRun>0</FirstRun>
|
||||
<MemConfigValue>C:\devtools\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\ST\STM32H7x5_CM4.ddf</MemConfigValue>
|
||||
</PlDriver>
|
||||
<Jet>
|
||||
<JetConnSerialNo>73866</JetConnSerialNo>
|
||||
<JetConnFoundProbes />
|
||||
<PrevWtdReset>Connect during reset</PrevWtdReset>
|
||||
<OnlineReset>Software</OnlineReset>
|
||||
<DisableInterrupts>0</DisableInterrupts>
|
||||
<LeaveRunning>0</LeaveRunning>
|
||||
<MultiCoreRunAll>0</MultiCoreRunAll>
|
||||
</Jet>
|
||||
<DebugChecksum>
|
||||
<Checksum>1765034686</Checksum>
|
||||
</DebugChecksum>
|
||||
<Exceptions>
|
||||
<StopOnUncaught>_ 0</StopOnUncaught>
|
||||
<StopOnThrow>_ 0</StopOnThrow>
|
||||
</Exceptions>
|
||||
<SWOManager>
|
||||
<SamplingDivider>8192</SamplingDivider>
|
||||
<OverrideClock>0</OverrideClock>
|
||||
<CpuClock>7929970</CpuClock>
|
||||
<SwoClock>4456540</SwoClock>
|
||||
<DataLogMode>0</DataLogMode>
|
||||
<ItmPortsEnabled>63</ItmPortsEnabled>
|
||||
<ItmTermIOPorts>1</ItmTermIOPorts>
|
||||
<ItmLogPorts>0</ItmLogPorts>
|
||||
<ItmLogFile>$PROJ_DIR$\ITM.log</ItmLogFile>
|
||||
<PowerForcePC>1</PowerForcePC>
|
||||
<PowerConnectPC>1</PowerConnectPC>
|
||||
</SWOManager>
|
||||
<CallStack>
|
||||
<ShowArgs>0</ShowArgs>
|
||||
</CallStack>
|
||||
<Disassembly>
|
||||
<MixedMode>1</MixedMode>
|
||||
</Disassembly>
|
||||
<struct_types>
|
||||
<Fmt0>struct StreamBufferDef_t-xTail 4 0</Fmt0>
|
||||
<Fmt1>struct StreamBufferDef_t-xTriggerLevelBytes 4 0</Fmt1>
|
||||
</struct_types>
|
||||
<Trace1>
|
||||
<Enabled>0</Enabled>
|
||||
<ShowSource>1</ShowSource>
|
||||
</Trace1>
|
||||
<ETMTraceWindow>
|
||||
<PortWidth>4</PortWidth>
|
||||
<PortMode>0</PortMode>
|
||||
<CaptureDataValues>0</CaptureDataValues>
|
||||
<CaptureDataAddresses>0</CaptureDataAddresses>
|
||||
<CaptureDataRange>0</CaptureDataRange>
|
||||
<DataFirst>0</DataFirst>
|
||||
<DataLast>4294967295</DataLast>
|
||||
<StopWhen>0</StopWhen>
|
||||
<StallCPU>0</StallCPU>
|
||||
<NoPCCapture>0</NoPCCapture>
|
||||
</ETMTraceWindow>
|
||||
<Trace2>
|
||||
<Enabled>0</Enabled>
|
||||
<ShowSource>0</ShowSource>
|
||||
</Trace2>
|
||||
<SWOTraceWindow>
|
||||
<ForcedPcSampling>0</ForcedPcSampling>
|
||||
<ForcedInterruptLogs>0</ForcedInterruptLogs>
|
||||
<ForcedItmLogs>0</ForcedItmLogs>
|
||||
<EventCPI>0</EventCPI>
|
||||
<EventEXC>0</EventEXC>
|
||||
<EventFOLD>0</EventFOLD>
|
||||
<EventLSU>0</EventLSU>
|
||||
<EventSLEEP>0</EventSLEEP>
|
||||
</SWOTraceWindow>
|
||||
<PowerLog>
|
||||
<Title_0>ITrgPwr</Title_0>
|
||||
<Symbol_0>0 4 0</Symbol_0>
|
||||
<LogEnabled>0</LogEnabled>
|
||||
<GraphEnabled>0</GraphEnabled>
|
||||
<ShowTimeLog>1</ShowTimeLog>
|
||||
<LiveEnabled>0</LiveEnabled>
|
||||
<LiveFile>PowerLogLive.log</LiveFile>
|
||||
</PowerLog>
|
||||
<PowerProbe>
|
||||
<Frequency>10000</Frequency>
|
||||
<Probe0>ITrgPwr</Probe0>
|
||||
<ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
|
||||
</PowerProbe>
|
||||
<TermIOLog>
|
||||
<LoggingEnabled>_ 0</LoggingEnabled>
|
||||
<LogFile>_ ""</LogFile>
|
||||
</TermIOLog>
|
||||
<LogFile>
|
||||
<LoggingEnabled>_ 0</LoggingEnabled>
|
||||
<LogFile>_ ""</LogFile>
|
||||
<Category>_ 0</Category>
|
||||
</LogFile>
|
||||
<DisassembleMode>
|
||||
<mode>0</mode>
|
||||
</DisassembleMode>
|
||||
<Breakpoints2>
|
||||
<Bp0>_ 0 "EMUL_CODE" "{$PROJ_DIR$\CM7\Src\main.c}.404.2" 0 0 1 "" 0 "" 0</Bp0>
|
||||
<Bp1>_ 0 "EMUL_CODE" "{$PROJ_DIR$\CM7\Src\main.c}.91.7" 0 0 1 "" 0 "" 0</Bp1>
|
||||
<Count>2</Count>
|
||||
</Breakpoints2>
|
||||
<Aliases>
|
||||
<Count>0</Count>
|
||||
<SuppressDialog>0</SuppressDialog>
|
||||
</Aliases>
|
||||
</settings>
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,31 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1003FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2401FFFF;
|
||||
define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue