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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Replace the CLZ function with a CLZ intrinsic in the Cortex-R4 port layer.
Add EDS support in the PIC24 port layer. Remove unnecessary EHB instructions from PIC32 port. In the PIC32 port assembly code, replace the &= code with a single ins instruction.
This commit is contained in:
Richard Barry
parent
b5cf299df1
commit
4e7b460eaf
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@ -233,15 +233,6 @@ vPortPreemptiveTick:
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; Restore the context of the task selected to execute.
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; Restore the context of the task selected to execute.
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portRESTORE_CONTEXT
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portRESTORE_CONTEXT
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;-------------------------------------------------------------------------------
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.def ulPortCountLeadingZeros
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ulPortCountLeadingZeros:
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CLZ R0, R0
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BX LR
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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.if (__TI_VFP_SUPPORT__)
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.if (__TI_VFP_SUPPORT__)
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@ -122,9 +122,6 @@ extern void vPortYield( void );
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/* Architecture specific optimisations. */
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/* Architecture specific optimisations. */
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Generic helper function. */
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unsigned long ulPortCountLeadingZeros( unsigned long ulBitmap );
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/* Check the configuration. */
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/* Check the configuration. */
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#if( configMAX_PRIORITIES > 32 )
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#if( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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@ -136,7 +133,7 @@ extern void vPortYield( void );
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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@ -103,25 +103,46 @@ unsigned portBASE_TYPE uxCriticalNesting = 0xef;
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#ifdef MPLAB_PIC24_PORT
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#ifdef MPLAB_PIC24_PORT
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#define portRESTORE_CONTEXT() \
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#ifdef __HAS_EDS__
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asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
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#define portRESTORE_CONTEXT() \
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"MOV [W0], W15 \n" \
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asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
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"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
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"MOV [W0], W15 \n" \
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"MOV W0, _uxCriticalNesting \n" \
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"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
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"POP PSVPAG \n" \
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"MOV W0, _uxCriticalNesting \n" \
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"POP CORCON \n" \
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"POP DSWPAG \n" \
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"POP TBLPAG \n" \
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"POP DSRPAG \n" \
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"POP RCOUNT \n" /* Restore the registers from the stack. */ \
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"POP CORCON \n" \
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"POP W14 \n" \
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"POP TBLPAG \n" \
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"POP.D W12 \n" \
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"POP RCOUNT \n" /* Restore the registers from the stack. */ \
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"POP.D W10 \n" \
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"POP W14 \n" \
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"POP.D W8 \n" \
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"POP.D W12 \n" \
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"POP.D W6 \n" \
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"POP.D W10 \n" \
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"POP.D W4 \n" \
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"POP.D W8 \n" \
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"POP.D W2 \n" \
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"POP.D W6 \n" \
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"POP.D W0 \n" \
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"POP.D W4 \n" \
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"POP SR " );
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"POP.D W2 \n" \
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"POP.D W0 \n" \
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"POP SR " );
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#else /* __HAS_EDS__ */
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#define portRESTORE_CONTEXT() \
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asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \
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"MOV [W0], W15 \n" \
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"POP W0 \n" /* Restore the critical nesting counter for the task. */ \
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"MOV W0, _uxCriticalNesting \n" \
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"POP PSVPAG \n" \
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"POP CORCON \n" \
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"POP TBLPAG \n" \
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"POP RCOUNT \n" /* Restore the registers from the stack. */ \
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"POP W14 \n" \
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"POP.D W12 \n" \
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"POP.D W10 \n" \
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"POP.D W8 \n" \
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"POP.D W6 \n" \
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"POP.D W4 \n" \
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"POP.D W2 \n" \
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"POP.D W0 \n" \
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"POP SR " );
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#endif /* __HAS_EDS__ */
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#endif /* MPLAB_PIC24_PORT */
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#endif /* MPLAB_PIC24_PORT */
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#ifdef MPLAB_DSPIC_PORT
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#ifdef MPLAB_DSPIC_PORT
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@ -235,8 +256,16 @@ const portSTACK_TYPE xInitialStack[] =
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*pxTopOfStack = CORCON;
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*pxTopOfStack = CORCON;
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pxTopOfStack++;
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pxTopOfStack++;
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*pxTopOfStack = PSVPAG;
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pxTopOfStack++;
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#if defined(__HAS_EDS__)
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*pxTopOfStack = DSRPAG;
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pxTopOfStack++;
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*pxTopOfStack = DSWPAG;
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pxTopOfStack++;
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#else /* __HAS_EDS__ */
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*pxTopOfStack = PSVPAG;
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pxTopOfStack++;
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#endif /* __HAS_EDS__ */
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/* Finally the critical nesting depth. */
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/* Finally the critical nesting depth. */
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*pxTopOfStack = 0x00;
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*pxTopOfStack = 0x00;
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@ -88,7 +88,12 @@ _vPortYield:
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PUSH TBLPAG
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PUSH TBLPAG
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PUSH CORCON
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PUSH CORCON
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PUSH PSVPAG
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#ifdef __HAS_EDS__
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PUSH DSRPAG
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PUSH DSWPAG
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#else
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PUSH PSVPAG
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#endif /* __HAS_EDS__ */
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MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
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MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
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PUSH W0
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PUSH W0
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MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
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MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
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@ -100,7 +105,12 @@ _vPortYield:
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MOV [W0], W15
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MOV [W0], W15
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POP W0 /* Restore the critical nesting counter for the task. */
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POP W0 /* Restore the critical nesting counter for the task. */
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MOV W0, _uxCriticalNesting
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MOV W0, _uxCriticalNesting
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#ifdef __HAS_EDS__
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POP DSWPAG
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POP DSRPAG
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#else
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POP PSVPAG
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POP PSVPAG
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#endif /* __HAS_EDS__ */
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POP CORCON
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POP CORCON
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POP TBLPAG
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POP TBLPAG
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POP RCOUNT /* Restore the registers from the stack. */
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POP RCOUNT /* Restore the registers from the stack. */
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@ -224,7 +224,6 @@
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mtc0 k0, _CP0_STATUS
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mtc0 k0, _CP0_STATUS
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mtc0 k1, _CP0_EPC
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mtc0 k1, _CP0_EPC
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ehb
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eret
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eret
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nop
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nop
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@ -222,8 +222,7 @@ vPortYieldISR:
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/* Clear the software interrupt in the core. */
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/* Clear the software interrupt in the core. */
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mfc0 s6, _CP0_CAUSE
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mfc0 s6, _CP0_CAUSE
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addiu s4,zero,-257
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ins s6, zero, 8, 1
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and s6, s6, s4
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mtc0 s6, _CP0_CAUSE
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mtc0 s6, _CP0_CAUSE
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/* Clear the interrupt in the interrupt controller. */
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/* Clear the interrupt in the interrupt controller. */
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@ -298,7 +297,6 @@ vPortYieldISR:
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mtc0 k1, _CP0_STATUS
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mtc0 k1, _CP0_STATUS
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mtc0 k0, _CP0_EPC
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mtc0 k0, _CP0_EPC
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ehb
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eret
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eret
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nop
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nop
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