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RISCV Add FPU context save (#1250)

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* port: riscv: Split the number of registers and the size of the context

* port: riscv: Create some macros for the FPU context

* port: riscv: Add a couple of macros that store fpu context

* port: riscv: Update the stack init function to include the fpu context size

* port: riscv: Add a chip_specific_extensions file that includes the F extension

* Update dictionary to include some risc-v instructions

* port: riscv: Fix a few typos

* port: riscv: Apply @aggarg's sugestions
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Jonathan Cubides 2025-03-06 19:34:48 +01:00 • committed by GitHub
parent 742729ed29
commit 4d9cd906d3
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4 changed files with 287 additions and 123 deletions
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24
portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
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@ -80,22 +80,22 @@ csrr t2, lpcount0
csrr t3, lpstart1
csrr t4, lpend1
csrr t5, lpcount1
sw t0, 1 * portWORD_SIZE( sp )
sw t1, 2 * portWORD_SIZE( sp )
sw t2, 3 * portWORD_SIZE( sp )
sw t3, 4 * portWORD_SIZE( sp )
sw t4, 5 * portWORD_SIZE( sp )
sw t5, 6 * portWORD_SIZE( sp )
sw t0, 2 * portWORD_SIZE( sp )
sw t1, 3 * portWORD_SIZE( sp )
sw t2, 4 * portWORD_SIZE( sp )
sw t3, 5 * portWORD_SIZE( sp )
sw t4, 6 * portWORD_SIZE( sp )
sw t5, 7 * portWORD_SIZE( sp )
.endm
/* Restore the additional registers found on the Pulpino. */
.macro portasmRESTORE_ADDITIONAL_REGISTERS
lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
lw t1, 2 * portWORD_SIZE( sp )
lw t2, 3 * portWORD_SIZE( sp )
lw t3, 4 * portWORD_SIZE( sp )
lw t4, 5 * portWORD_SIZE( sp )
lw t5, 6 * portWORD_SIZE( sp )
lw t0, 2 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
lw t1, 3 * portWORD_SIZE( sp )
lw t2, 4 * portWORD_SIZE( sp )
lw t3, 5 * portWORD_SIZE( sp )
lw t4, 6 * portWORD_SIZE( sp )
lw t5, 7 * portWORD_SIZE( sp )
csrw lpstart0, t0
csrw lpend0, t1
csrw lpcount0, t2