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RISCV Add FPU context save (#1250)

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* port: riscv: Split the number of registers and the size of the context

* port: riscv: Create some macros for the FPU context

* port: riscv: Add a couple of macros that store fpu context

* port: riscv: Update the stack init function to include the fpu context size

* port: riscv: Add a chip_specific_extensions file that includes the F extension

* Update dictionary to include some risc-v instructions

* port: riscv: Fix a few typos

* port: riscv: Apply @aggarg's sugestions
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Jonathan Cubides 2025-03-06 19:34:48 +01:00 • committed by GitHub
parent 742729ed29
commit 4d9cd906d3
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4 changed files with 287 additions and 123 deletions
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3
.github/.cSpellWords.txt vendored
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@ -23,6 +23,7 @@ AIRCR
ALMIEN
ALMV
ANDC
andi
ANDCCR
APIC
APROCFREQ
@ -47,6 +48,7 @@ bcpc
BCPC
beevt
BEEVT
beqz
BERR
bfextu
Biagioni
@ -298,6 +300,7 @@ FADD
FCMD
fcolor
FCSE
fcsr
fdiagnostics
fdiv
FDIV