len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-04-20 05:21:59 -04:00
Code Issues Packages Projects Releases Wiki Activity

Small tidy up of the new MicroBlaze port layer.

Browse source
This commit is contained in:
Richard Barry 2011-06-15 08:39:45 +00:00
parent 00bfe2f025
commit 4d287dd1bf
1 changed files with 8 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
Demo/MicroBlaze_Spartan-6_EthernetLite/SDKProjects/RTOSDemoSource/FreeRTOS_Source/portable/GCC/MicroBlaze/port.c
View file

@ -68,16 +68,16 @@
#include <xintc_i.h> #include <xintc_i.h>
#include <xtmrctr.h> #include <xtmrctr.h>
#include <xil_exception.h> #include <xil_exception.h>
#include <mb_interface.h>
/* Tasks are started with interrupts disabled as they will have their interrupts
enabled as the task starts (when its context is restored for the first time). */
#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x00 )
/* Tasks are started with a critical section nesting of 0 - however prior /* Tasks are started with a critical section nesting of 0 - however prior
to the scheduler being commenced we don't want the critical nesting level to the scheduler being commenced we don't want the critical nesting level
to reach zero, so it is initialised to a high value. */ to reach zero, so it is initialised to a high value. */
#define portINITIAL_NESTING_VALUE ( 0xff ) #define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts. */
#define portMSR_IE ( 0x02U )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* /*
@ -119,19 +119,6 @@ extern void *_SDA2_BASE_, *_SDA_BASE_;
const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_; const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;
const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_; const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;
#if 0
//_RB_
#ifdef XPAR_MICROBLAZE_USE_ICACHE
microblaze_invalidate_icache();
microblaze_enable_icache();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
microblaze_invalidate_dcache();
microblaze_enable_dcache();
#endif
#endif
/* Place a few bytes of known values on the bottom of the stack. /* Place a few bytes of known values on the bottom of the stack.
This is essential for the Microblaze port and these lines must This is essential for the Microblaze port and these lines must
not be omitted. The parameter value will overwrite the not be omitted. The parameter value will overwrite the
@ -219,8 +206,10 @@ const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;
*pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
pxTopOfStack--; pxTopOfStack--;
/* The MSR is stacked between R30 and R31. */ /* The MSR is stacked between R30 and R31. This should have interrupts
*pxTopOfStack = portINITIAL_MSR_STATE; disabled. Each task will enable interrupts automatically when it enters
the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */