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Update to V5.0.0.
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Richard Barry
parent
e939542f32
commit
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184 changed files with 9510 additions and 1662 deletions
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@ -2,7 +2,7 @@
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//
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// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
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//
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// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
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// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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@ -10,10 +10,11 @@
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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@ -21,7 +22,7 @@
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
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// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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@ -30,7 +31,7 @@
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//*****************************************************************************
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//
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// The following define the offsets of the Watchdog Timer registers.
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// The following are defines for the Watchdog Timer register offsets.
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//
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//*****************************************************************************
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#define WDT_O_LOAD 0x00000000 // Load register
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@ -41,22 +42,10 @@
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#define WDT_O_MIS 0x00000014 // Masked interrupt status register
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#define WDT_O_TEST 0x00000418 // Test register
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#define WDT_O_LOCK 0x00000C00 // Lock register
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#define WDT_O_PeriphID4 0x00000FD0 //
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#define WDT_O_PeriphID5 0x00000FD4 //
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#define WDT_O_PeriphID6 0x00000FD8 //
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#define WDT_O_PeriphID7 0x00000FDC //
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#define WDT_O_PeriphID0 0x00000FE0 //
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#define WDT_O_PeriphID1 0x00000FE4 //
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#define WDT_O_PeriphID2 0x00000FE8 //
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#define WDT_O_PeriphID3 0x00000FEC //
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#define WDT_O_PCellID0 0x00000FF0 //
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#define WDT_O_PCellID1 0x00000FF4 //
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#define WDT_O_PCellID2 0x00000FF8 //
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#define WDT_O_PCellID3 0x00000FFC //
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//*****************************************************************************
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//
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// The following define the bit fields in the WDT_CTL register.
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// The following are defines for the bit fields in the WDT_CTL register.
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//
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//*****************************************************************************
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#define WDT_CTL_RESEN 0x00000002 // Enable reset output
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//*****************************************************************************
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//
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// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
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// registers.
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// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
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// WDT_MIS registers.
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//
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//*****************************************************************************
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#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
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//*****************************************************************************
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//
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// The following define the bit fields in the WDT_TEST register.
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// The following are defines for the bit fields in the WDT_TEST register.
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//
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//*****************************************************************************
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#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
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#ifndef DEPRECATED
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#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
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#endif
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//*****************************************************************************
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//
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// The following define the bit fields in the WDT_LOCK register.
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// The following are defines for the bit fields in the WDT_LOCK register.
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//
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//*****************************************************************************
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#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.
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#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
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#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
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#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
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#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
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//*****************************************************************************
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//
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// The following define the reset values for the WDT registers.
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// The following are defines for the bit fields in the WDT_O_LOAD register.
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//
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//*****************************************************************************
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#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
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#define WDT_LOAD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_VALUE register.
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//
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//*****************************************************************************
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#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
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#define WDT_VALUE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_ICR register.
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//
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//*****************************************************************************
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#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.
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#define WDT_ICR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_RIS register.
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//
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//*****************************************************************************
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#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_MIS register.
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//
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//*****************************************************************************
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#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt
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// Status.
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the Watchdog Timer register
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// offsets.
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//
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//*****************************************************************************
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#define WDT_O_PeriphID4 0x00000FD0
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#define WDT_O_PeriphID5 0x00000FD4
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#define WDT_O_PeriphID6 0x00000FD8
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#define WDT_O_PeriphID7 0x00000FDC
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#define WDT_O_PeriphID0 0x00000FE0
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#define WDT_O_PeriphID1 0x00000FE4
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#define WDT_O_PeriphID2 0x00000FE8
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#define WDT_O_PeriphID3 0x00000FEC
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#define WDT_O_PCellID0 0x00000FF0
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#define WDT_O_PCellID1 0x00000FF4
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#define WDT_O_PCellID2 0x00000FF8
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#define WDT_O_PCellID3 0x00000FFC
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the WDT_TEST
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// register.
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//
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//*****************************************************************************
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#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
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//*****************************************************************************
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//
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// The following are deprecated defines for the reset values for the WDT
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// registers.
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//
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//*****************************************************************************
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#define WDT_RV_LOAD 0xFFFFFFFF // Load register
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#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
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#define WDT_RV_CTL 0x00000000 // Control register
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#define WDT_RV_LOAD 0xFFFFFFFF // Load register
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#define WDT_RV_PCellID1 0x000000F0
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#define WDT_RV_PCellID3 0x000000B1
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#define WDT_RV_PeriphID1 0x00000018
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#define WDT_RV_PeriphID2 0x00000018
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#define WDT_RV_PCellID0 0x0000000D
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#define WDT_RV_PCellID2 0x00000005
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#define WDT_RV_PeriphID0 0x00000005
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#define WDT_RV_PeriphID3 0x00000001
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#define WDT_RV_PeriphID5 0x00000000
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#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
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#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
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#define WDT_RV_CTL 0x00000000 // Control register
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#define WDT_RV_PeriphID4 0x00000000
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#define WDT_RV_PeriphID6 0x00000000
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#define WDT_RV_PeriphID7 0x00000000
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#define WDT_RV_LOCK 0x00000000 // Lock register
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#define WDT_RV_PeriphID4 0x00000000 //
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#define WDT_RV_PeriphID5 0x00000000 //
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#define WDT_RV_PeriphID6 0x00000000 //
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#define WDT_RV_PeriphID7 0x00000000 //
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#define WDT_RV_PeriphID0 0x00000005 //
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#define WDT_RV_PeriphID1 0x00000018 //
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#define WDT_RV_PeriphID2 0x00000018 //
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#define WDT_RV_PeriphID3 0x00000001 //
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#define WDT_RV_PCellID0 0x0000000D //
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#define WDT_RV_PCellID1 0x000000F0 //
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#define WDT_RV_PCellID2 0x00000005 //
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#define WDT_RV_PCellID3 0x000000B1 //
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#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
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#endif
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#endif // __HW_WATCHDOG_H__
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