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Update to V5.0.0.
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Richard Barry
parent
e939542f32
commit
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184 changed files with 9510 additions and 1662 deletions
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@ -2,7 +2,7 @@
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//
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// hw_hibernate.h - Defines and Macros for the Hibernation module.
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//
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// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
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// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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@ -10,10 +10,11 @@
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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@ -21,7 +22,7 @@
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
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// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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@ -30,55 +31,64 @@
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//*****************************************************************************
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//
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// The following define the addresses of the hibernation module registers.
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// The following are defines for the Hibernation module register addresses.
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//
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//*****************************************************************************
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#define HIB_RTCC 0x400fc000 // Hibernate RTC counter
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#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0
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#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1
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#define HIB_RTCLD 0x400fc00C // Hibernate RTC load
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#define HIB_CTL 0x400fc010 // Hibernate RTC control
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#define HIB_IM 0x400fc014 // Hibernate interrupt mask
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#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status
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#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat
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#define HIB_IC 0x400fc020 // Hibernate interrupt clear
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#define HIB_RTCT 0x400fc024 // Hibernate RTC trim
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#define HIB_DATA 0x400fc030 // Hibernate data area
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#define HIB_DATA_END 0x400fc130 // end of data area, exclusive
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#define HIB_RTCC 0x400FC000 // Hibernate RTC counter
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#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0
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#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1
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#define HIB_RTCLD 0x400FC00C // Hibernate RTC load
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#define HIB_CTL 0x400FC010 // Hibernate RTC control
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#define HIB_IM 0x400FC014 // Hibernate interrupt mask
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#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status
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#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat
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#define HIB_IC 0x400FC020 // Hibernate interrupt clear
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#define HIB_RTCT 0x400FC024 // Hibernate RTC trim
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#define HIB_DATA 0x400FC030 // Hibernate data area
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate RTC counter register.
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// The following are defines for the bit fields in the Hibernate RTC counter
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCC_MASK 0xffffffff // RTC counter mask
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#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.
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#define HIB_RTCC_S 0
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate RTC match 0 register.
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// The following are defines for the bit fields in the Hibernate RTC match 0
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask
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#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.
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#define HIB_RTCM0_S 0
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate RTC match 1 register.
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// The following are defines for the bit fields in the Hibernate RTC match 1
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask
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#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.
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#define HIB_RTCM1_S 0
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate RTC load register.
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// The following are defines for the bit fields in the Hibernate RTC load
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_MASK 0xffffffff // RTC load mask
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#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.
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#define HIB_RTCLD_S 0
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate control register
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// The following are defines for the bit fields in the Hibernate control
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// register
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//
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//*****************************************************************************
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#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.
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#define HIB_CTL_VABORT 0x00000080 // low bat abort
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#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
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#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate interrupt mask reg.
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// The following are defines for the bit fields in the Hibernate interrupt mask
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// reg.
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//
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//*****************************************************************************
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#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
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@ -100,27 +111,31 @@
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate raw interrupt status.
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// The following are defines for the bit fields in the Hibernate raw interrupt
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// status.
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//
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//*****************************************************************************
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#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
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#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
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#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
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#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
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#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate masked int status.
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// The following are defines for the bit fields in the Hibernate masked int
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// status.
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//
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//*****************************************************************************
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#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
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#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
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#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
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#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
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#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
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// Status.
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate interrupt clear reg.
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// The following are defines for the bit fields in the Hibernate interrupt
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// clear reg.
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//
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//*****************************************************************************
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#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate RTC trim register.
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// The following are defines for the bit fields in the Hibernate RTC trim
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask
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#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.
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#define HIB_RTCT_TRIM_S 0
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//*****************************************************************************
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//
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// The following define the bit fields in the Hibernate data register.
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// The following are defines for the bit fields in the Hibernate data register.
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//
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//*****************************************************************************
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#define HIB_DATA_MASK 0xffffffff // NV memory data mask
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#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV
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// Registers[63:0].
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#define HIB_DATA_RTD_S 0
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the Hibernation module register
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// addresses.
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//
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//*****************************************************************************
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#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate RTC
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// counter register.
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//
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//*****************************************************************************
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#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate RTC
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// match 0 register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate RTC
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// match 1 register.
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//
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//*****************************************************************************
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#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate RTC
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// load register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate raw
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// interrupt status.
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//
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//*****************************************************************************
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#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate
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// masked int status.
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//
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//*****************************************************************************
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#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate RTC
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// trim register.
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//
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//*****************************************************************************
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#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the Hibernate
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// data register.
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//
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//*****************************************************************************
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#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
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#endif
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#endif // __HW_HIBERNATE_H__
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