mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Update to V5.0.0.
This commit is contained in:
Richard Barry
parent
e939542f32
commit
4c8425da01
184 changed files with 9510 additions and 1662 deletions
|
|
@ -2,7 +2,7 @@
|
|||
//
|
||||
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
|
||||
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
|
|
@ -10,10 +10,11 @@
|
|||
// exclusively on LMI's microcontroller products.
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. Any use in violation
|
||||
// of the foregoing restrictions may subject the user to criminal sanctions
|
||||
// under applicable laws, as well as to civil liability for the breach of the
|
||||
// terms and conditions of this license.
|
||||
// applicable copyright laws. All rights are reserved. You may not combine
|
||||
// this software with "viral" open-source software in order to form a larger
|
||||
// program. Any use in violation of the foregoing restrictions may subject
|
||||
// the user to criminal sanctions under applicable laws, as well as to civil
|
||||
// liability for the breach of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
|
|
@ -21,7 +22,7 @@
|
|||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
|
||||
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
|
|
@ -30,7 +31,7 @@
|
|||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO Register Offsets.
|
||||
// The following are defines for the GPIO Register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_DATA 0x00000000 // Data register.
|
||||
|
|
@ -53,63 +54,83 @@
|
|||
#define GPIO_O_DEN 0x0000051C // Digital input enable register.
|
||||
#define GPIO_O_LOCK 0x00000520 // Lock register.
|
||||
#define GPIO_O_CR 0x00000524 // Commit register.
|
||||
#define GPIO_O_PeriphID4 0x00000FD0 //
|
||||
#define GPIO_O_PeriphID5 0x00000FD4 //
|
||||
#define GPIO_O_PeriphID6 0x00000FD8 //
|
||||
#define GPIO_O_PeriphID7 0x00000FDC //
|
||||
#define GPIO_O_PeriphID0 0x00000FE0 //
|
||||
#define GPIO_O_PeriphID1 0x00000FE4 //
|
||||
#define GPIO_O_PeriphID2 0x00000FE8 //
|
||||
#define GPIO_O_PeriphID3 0x00000FEC //
|
||||
#define GPIO_O_PCellID0 0x00000FF0 //
|
||||
#define GPIO_O_PCellID1 0x00000FF4 //
|
||||
#define GPIO_O_PCellID2 0x00000FF8 //
|
||||
#define GPIO_O_PCellID3 0x00000FFC //
|
||||
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following define the bit fields in the GPIO_LOCK register.
|
||||
// The following are defines for the bit fields in the GPIO_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
|
||||
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.
|
||||
#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked
|
||||
#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked
|
||||
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
|
||||
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
|
||||
// DustDevil-class devices and
|
||||
// later.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// GPIO Register reset values.
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO Register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_PeriphID4 0x00000FD0
|
||||
#define GPIO_O_PeriphID5 0x00000FD4
|
||||
#define GPIO_O_PeriphID6 0x00000FD8
|
||||
#define GPIO_O_PeriphID7 0x00000FDC
|
||||
#define GPIO_O_PeriphID0 0x00000FE0
|
||||
#define GPIO_O_PeriphID1 0x00000FE4
|
||||
#define GPIO_O_PeriphID2 0x00000FE8
|
||||
#define GPIO_O_PeriphID3 0x00000FEC
|
||||
#define GPIO_O_PCellID0 0x00000FF0
|
||||
#define GPIO_O_PCellID1 0x00000FF4
|
||||
#define GPIO_O_PCellID2 0x00000FF8
|
||||
#define GPIO_O_PCellID3 0x00000FFC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
|
||||
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
|
||||
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
|
||||
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
|
||||
#define GPIO_RV_IEV 0x00000000 // Interrupt event reg RV.
|
||||
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
|
||||
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
|
||||
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
|
||||
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
|
||||
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
|
||||
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
|
||||
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
|
||||
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
|
||||
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
|
||||
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
|
||||
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
|
||||
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
|
||||
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.
|
||||
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.
|
||||
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.
|
||||
#define GPIO_RV_PCellID1 0x000000F0
|
||||
#define GPIO_RV_PCellID3 0x000000B1
|
||||
#define GPIO_RV_PeriphID0 0x00000061
|
||||
#define GPIO_RV_PeriphID1 0x00000010
|
||||
#define GPIO_RV_PCellID0 0x0000000D
|
||||
#define GPIO_RV_PCellID2 0x00000005
|
||||
#define GPIO_RV_PeriphID2 0x00000004
|
||||
#define GPIO_RV_LOCK 0x00000001 // Lock register RV.
|
||||
#define GPIO_RV_PeriphID4 0x00000000 //
|
||||
#define GPIO_RV_PeriphID5 0x00000000 //
|
||||
#define GPIO_RV_PeriphID6 0x00000000 //
|
||||
#define GPIO_RV_PeriphID7 0x00000000 //
|
||||
#define GPIO_RV_PeriphID0 0x00000061 //
|
||||
#define GPIO_RV_PeriphID1 0x00000010 //
|
||||
#define GPIO_RV_PeriphID2 0x00000004 //
|
||||
#define GPIO_RV_PeriphID3 0x00000000 //
|
||||
#define GPIO_RV_PCellID0 0x0000000D //
|
||||
#define GPIO_RV_PCellID1 0x000000F0 //
|
||||
#define GPIO_RV_PCellID2 0x00000005 //
|
||||
#define GPIO_RV_PCellID3 0x000000B1 //
|
||||
#define GPIO_RV_PeriphID7 0x00000000
|
||||
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.
|
||||
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.
|
||||
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.
|
||||
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.
|
||||
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.
|
||||
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.
|
||||
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.
|
||||
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.
|
||||
#define GPIO_RV_PeriphID4 0x00000000
|
||||
#define GPIO_RV_PeriphID5 0x00000000
|
||||
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.
|
||||
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.
|
||||
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.
|
||||
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.
|
||||
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.
|
||||
#define GPIO_RV_PeriphID6 0x00000000
|
||||
#define GPIO_RV_PeriphID3 0x00000000
|
||||
#define GPIO_RV_DATA 0x00000000 // Data register reset value.
|
||||
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
#endif
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue