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Update to V5.0.0.
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Richard Barry
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commit
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184 changed files with 9510 additions and 1662 deletions
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@ -2,7 +2,7 @@
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//
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// ethernet.h - Defines and Macros for the ethernet module.
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//
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// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
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// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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@ -10,10 +10,11 @@
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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@ -21,13 +22,19 @@
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
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// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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#ifndef __ETHERNET_H__
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#define __ETHERNET_H__
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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@ -62,116 +69,6 @@ extern "C"
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#define ETH_INT_TXER 0x002 // TX Error
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#define ETH_INT_RX 0x001 // RX Complete
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//*****************************************************************************
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//
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// The following define values that can be passed as register addresses to
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// EthernetPHYRead and EthernetPHYWrite.
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//
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//*****************************************************************************
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#define PHY_MR0 0 // Control
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#define PHY_MR1 1 // Status
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#define PHY_MR2 2 // PHY Identifier 1
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#define PHY_MR3 3 // PHY Identifier 2
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#define PHY_MR4 4 // Auto-Neg. Advertisement
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#define PHY_MR5 5 // Auto-Neg. Link Partner Ability
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#define PHY_MR6 6 // Auto-Neg. Expansion
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// 7-15 Reserved/Not Implemented
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#define PHY_MR16 16 // Vendor Specific
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#define PHY_MR17 17 // Interrupt Control/Status
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#define PHY_MR18 18 // Diagnostic Register
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#define PHY_MR19 19 // Transceiver Control
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// 20-22 Reserved
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#define PHY_MR23 23 // LED Configuration Register
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#define PHY_MR24 24 // MDI/MDIX Control Register
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// 25-31 Reserved/Not Implemented
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR0 register
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//
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//*****************************************************************************
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#define PHY_MR0_RESET 0x8000 // Reset the PHY
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#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback
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#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection
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#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T
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#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T
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#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable
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#define PHY_MR0_PWRDN 0x0800 // Power Down
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#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation
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#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex
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#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode
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#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR1 register
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//
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//*****************************************************************************
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#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete
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#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected
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#define PHY_MR1_LINK 0x0004 // Link Established
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#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR17 register
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//
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//*****************************************************************************
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#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt
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#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.
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#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.
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#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt
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#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt
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#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR18 register
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//
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//*****************************************************************************
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#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed
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#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated
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#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated
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#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated
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#define PHY_MR18_RATE 0x0400 // Rate Negotiated
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#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T
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#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR23 register
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//
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//*****************************************************************************
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#define PHY_MR23_LED1 0x00f0 // LED1 Configuration
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#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status
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#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity
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#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity
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#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity
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#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity
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#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity
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#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity
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#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity
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#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity
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#define PHY_MR23_LED0 0x000f // LED0 Configuration
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#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status
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#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity
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#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity
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#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity
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#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity
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#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity
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#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity
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#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity
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#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity
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//*****************************************************************************
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//
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// The following define bit fields in the ETH_MR24 register
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//
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//*****************************************************************************
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#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration
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#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough
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#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover
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//*****************************************************************************
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//
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// Helper Macros for Ethernet Processing
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@ -264,6 +161,11 @@ extern unsigned long EthernetPHYRead(unsigned long ulBase,
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EthernetPacketPutNonBlocking(a, b, c)
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#endif
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//*****************************************************************************
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//
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// Mark the end of the C bindings section for C++ compilers.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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}
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#endif
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