len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-09-05 22:03:49 -04:00
Code Issues Projects Releases Packages Wiki Activity

Update RISCC-V-RV32-SiFive_HiFive1_FreedomStudio project to latest tools and metal library versions.

Browse source
This commit is contained in:
Richard Barry 2020-01-01 22:02:06 +00:00
parent cfa83672ef
commit 4b943b35e0
85 changed files with 3835 additions and 595 deletions
Download patch file Download diff file Expand all files Collapse all files

28
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_FreedomStudio/freedom-metal/gloss/crt0.S
View file

@ -80,11 +80,19 @@ _start:
bge t1, t2, 2f
1:
#if __riscv_xlen == 32
lw a0, 0(t0)
addi t0, t0, 4
sw a0, 0(t1)
addi t1, t1, 4
blt t1, t2, 1b
#else
ld a0, 0(t0)
addi t0, t0, 8
sd a0, 0(t1)
addi t1, t1, 8
blt t1, t2, 1b
#endif
2:
/* Copy the ITIM section */
@ -96,13 +104,25 @@ _start:
bge t1, t2, 2f
1:
#if __riscv_xlen == 32
lw a0, 0(t0)
addi t0, t0, 4
sw a0, 0(t1)
addi t1, t1, 4
blt t1, t2, 1b
#else
ld a0, 0(t0)
addi t0, t0, 8
sd a0, 0(t1)
addi t1, t1, 8
blt t1, t2, 1b
#endif
2:
/* Fence all subsequent instruction fetches until after the ITIM writes
complete */
fence.i
/* Zero the BSS segment. */
la t1, metal_segment_bss_target_start
la t2, metal_segment_bss_target_end
@ -110,9 +130,15 @@ _start:
bge t1, t2, 2f
1:
#if __riscv_xlen == 32
sw x0, 0(t1)
addi t1, t1, 4
blt t1, t2, 1b
#else
sd x0, 0(t1)
addi t1, t1, 8
blt t1, t2, 1b
#endif
2:
/* At this point we're in an environment that can execute C code. The first
@ -131,7 +157,7 @@ _skip_init:
/* Synchronize harts so that secondary harts wait until hart 0 finishes
initializing */
call _synchronize_harts
call __metal_synchronize_harts
/* Check RISC-V isa and enable FS bits if Floating Point architecture. */
csrr a5, misa

6
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_FreedomStudio/freedom-metal/gloss/sys_gettimeofday.c
View file

@ -7,10 +7,12 @@ _gettimeofday(struct timeval *tp, void *tzp)
{
int rv;
unsigned long long mcc, timebase;
if (rv = metal_timer_get_cyclecount(0, &mcc)) {
rv = metal_timer_get_cyclecount(0, &mcc);
if (rv != 0) {
return -1;
}
if (rv = metal_timer_get_timebase_frequency(0, &timebase)) {
rv = metal_timer_get_timebase_frequency(0, &timebase);
if (rv != 0) {
return -1;
}
tp->tv_sec = mcc / timebase;

3
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_FreedomStudio/freedom-metal/gloss/sys_sbrk.c
View file

@ -24,7 +24,7 @@ _sbrk(ptrdiff_t incr)
/* If __heap_size == 0, we can't allocate memory on the heap */
if(&metal_segment_heap_target_start == &metal_segment_heap_target_end) {
return NULL;
return (void *)-1;
}
/* Don't move the break past the end of the heap */
@ -32,6 +32,7 @@ _sbrk(ptrdiff_t incr)
brk += incr;
} else {
brk = &metal_segment_heap_target_end;
return (void *)-1;
}
return old;

3
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_FreedomStudio/freedom-metal/gloss/sys_times.c
View file

@ -30,7 +30,8 @@ _times(struct tms *buf)
_gettimeofday (&t, 0);
unsigned long long timebase;
if (rv = metal_timer_get_timebase_frequency(0, &timebase)) {
rv = metal_timer_get_timebase_frequency(0, &timebase);
if (rv != 0) {
return -1;
}