From 4a35c97fec56891dd747a07641ae2eab7ed78803 Mon Sep 17 00:00:00 2001 From: chinglee-iot <61685396+chinglee-iot@users.noreply.github.com> Date: Thu, 8 Jun 2023 10:52:08 +0800 Subject: [PATCH] Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683) * Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8. * Add hardware not implemented bits check. These bits should be zero. --------- Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> --- portable/ARMv8M/non_secure/port.c | 33 +++----------------- portable/CCS/ARM_CM3/port.c | 26 +++------------ portable/CCS/ARM_CM4F/port.c | 26 +++------------ portable/GCC/ARM_CM23/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM3/port.c | 26 +++------------ portable/GCC/ARM_CM33/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM35P/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM3_MPU/port.c | 26 +++------------ portable/GCC/ARM_CM4F/port.c | 26 +++------------ portable/GCC/ARM_CM4_MPU/port.c | 26 +++------------ portable/GCC/ARM_CM55/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM55_NTZ/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM7/r0p1/port.c | 26 +++------------ portable/GCC/ARM_CM85/non_secure/port.c | 33 +++----------------- portable/GCC/ARM_CM85_NTZ/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM23/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM3/port.c | 26 +++------------ portable/IAR/ARM_CM33/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM35P/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM4F/port.c | 26 +++------------ portable/IAR/ARM_CM4F_MPU/port.c | 26 +++------------ portable/IAR/ARM_CM55/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM55_NTZ/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM7/r0p1/port.c | 26 +++------------ portable/IAR/ARM_CM85/non_secure/port.c | 33 +++----------------- portable/IAR/ARM_CM85_NTZ/non_secure/port.c | 33 +++----------------- portable/MikroC/ARM_CM4F/port.c | 26 +++------------ portable/RVDS/ARM_CM3/port.c | 26 +++------------ portable/RVDS/ARM_CM4F/port.c | 26 +++------------ portable/RVDS/ARM_CM4_MPU/port.c | 26 +++------------ portable/RVDS/ARM_CM7/r0p1/port.c | 26 +++------------ 37 files changed, 148 insertions(+), 961 deletions(-) diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c index f3c4e5add..a04efc911 100755 --- a/portable/CCS/ARM_CM3/port.c +++ b/portable/CCS/ARM_CM3/port.c @@ -249,6 +249,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -285,28 +289,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c index c675afe67..1aff18b58 100755 --- a/portable/CCS/ARM_CM4F/port.c +++ b/portable/CCS/ARM_CM4F/port.c @@ -268,6 +268,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -304,28 +308,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index 9b42eac5a..198793bd5 100755 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -292,6 +292,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -328,28 +332,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index 619f2b0c8..e9e4b5772 100755 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -415,6 +415,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -451,28 +455,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index 88fc76db8..c59995f1a 100755 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -335,6 +335,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -371,28 +375,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index ab76ee842..17b3aa934 100755 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -458,6 +458,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -494,28 +498,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried - * from hardware is at least as many as specified in the - * CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried - * from hardware is at least as many as specified in the - * FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM55/non_secure/port.c +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 2be4f2770..0fcbf5048 100755 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -323,6 +323,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -359,28 +363,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM85/non_secure/port.c +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c index d54c3aceb..21b69bdd0 100755 --- a/portable/IAR/ARM_CM3/port.c +++ b/portable/IAR/ARM_CM3/port.c @@ -241,6 +241,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -277,28 +281,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c index e0deaf128..0352fc3bd 100755 --- a/portable/IAR/ARM_CM4F/port.c +++ b/portable/IAR/ARM_CM4F/port.c @@ -279,6 +279,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -315,28 +319,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 1b7cca65c..742518be5 100755 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -393,6 +393,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -429,28 +433,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM55/non_secure/port.c +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c index 63f83993d..3baf38aaa 100755 --- a/portable/IAR/ARM_CM7/r0p1/port.c +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -267,6 +267,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -303,28 +307,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM85/non_secure/port.c +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 7bbe1b7bc..dbbb99507 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index 8ef593f55..2fef250a1 100755 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -329,6 +329,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -365,28 +369,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index ae7ce37f3..054ab02ee 100755 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -294,6 +294,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -330,28 +334,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index cb003aa38..de48443bb 100755 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -360,6 +360,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -396,28 +400,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 13e2f8a8e..fdf1ff95b 100755 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -453,6 +453,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -489,28 +493,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index 1df54ab28..ad9971c8d 100755 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -344,6 +344,10 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -380,28 +384,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;