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UpdUpdate IAR projects to use Embedded Workbench V5.11.

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This commit is contained in:
Richard Barry 2008-01-23 08:35:47 +00:00
parent dfb8e7003b
commit 474cb76864
104 changed files with 10988 additions and 22710 deletions
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2
Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
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@ -37,7 +37,7 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <intrinsic.h>
#include <intrinsics.h>
#include "Board.h"
/*-----------------------------------------------------------

302
Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s Normal file
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@ -0,0 +1,302 @@
;* ----------------------------------------------------------------------------
;* ATMEL Microcontroller Software Support - ROUSSET -
;* ----------------------------------------------------------------------------
;* Copyright (c) 2006, Atmel Corporation
;
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* - Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the disclaimer below.
;*
;* - Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the disclaimer below in the documentation and/or
;* other materials provided with the distribution.
;*
;* Atmel's name may not be used to endorse or promote products derived from
;* this software without specific prior written permission.
;*
;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;* ----------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Include your AT91 Library files
;------------------------------------------------------------------------------
#include "AT91SAM7X256_inc.h"
;------------------------------------------------------------------------------
#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE)
#define IRQ_STACK_SIZE 200
; 3 words to be saved per interrupt priority level
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
USR_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode
I_BIT DEFINE 0x80
F_BIT DEFINE 0x40
;------------------------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;------------------------------------------------------------------------------
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __iar_program_start
EXTERN vPortYieldProcessor
ARM
__vector:
ldr pc,[pc,#+24] ;; Reset
__und_handler:
ldr pc,[pc,#+24] ;; Undefined instructions
__swi_handler:
ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
__prefetch_handler:
ldr pc,[pc,#+24] ;; Prefetch abort
__data_handler:
ldr pc,[pc,#+24] ;; Data abort
DC32 0xFFFFFFFF ;; RESERVED
__irq_handler:
LDR PC, [PC, #-0xF20]
__fiq_handler:
ldr pc,[pc,#+24] ;; FIQ
DC32 __iar_program_start
DC32 __und_handler
DC32 vPortYieldProcessor
DC32 __prefetch_handler
DC32 __data_handler
B .
DC32 IRQ_Handler_Entry
DC32 FIQ_Handler_Entry
;------------------------------------------------------------------------------
;- Manage exception: The exception must be ensure in ARM mode
;------------------------------------------------------------------------------
SECTION text:CODE:NOROOT(2)
ARM
;------------------------------------------------------------------------------
;- Function : FIQ_Handler_Entry
;- Treatments : FIQ Controller Interrupt Handler.
;- R8 is initialize in Cstartup
;- Called Functions : None only by FIQ
;------------------------------------------------------------------------------
FIQ_Handler_Entry:
;- Switch in SVC/User Mode to allow User Stack access for C code
; because the FIQ is not yet acknowledged
;- Save and r0 in FIQ_Register
mov r9,r0
ldr r0 , [r8, #AIC_FVR]
msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, lr}
;- Branch to the routine pointed by the AIC_FVR
mov r14, pc
bx r0
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, lr}
;- Leave Interrupts disabled and switch back in FIQ mode
msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE
;- Restore the R0 ARM_MODE_SVC register
mov r0,r9
;- Restore the Program Counter using the LR_fiq directly in the PC
subs pc,lr,#4
;------------------------------------------------------------------------------
;- Function : IRQ_Handler_Entry
;- Treatments : IRQ Controller Interrupt Handler.
;- Called Functions : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
IRQ_Handler_Entry:
;-------------------------
;- Manage Exception Entry
;-------------------------
;- Adjust and save LR_irq in IRQ stack
sub lr, lr, #4
stmfd sp!, {lr}
;- Save r0 and SPSR (need to be saved for nested interrupt)
mrs r14, SPSR
stmfd sp!, {r0,r14}
;- Write in the IVR to support Protect Mode
;- No effect in Normal Mode
;- De-assert the NIRQ and clear the source in Protect Mode
ldr r14, =AT91C_BASE_AIC
ldr r0 , [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
;- Enable Interrupt and Switch in Supervisor Mode
msr CPSR_c, #SVC_MODE
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, r14}
;----------------------------------------------
;- Branch to the routine pointed by the AIC_IVR
;----------------------------------------------
mov r14, pc
bx r0
;----------------------------------------------
;- Manage Exception Exit
;----------------------------------------------
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, r14}
;- Disable Interrupt and switch back in IRQ mode
msr CPSR_c, #I_BIT | IRQ_MODE
;- Mark the End of Interrupt on the AIC
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
;- Restore SPSR_irq and r0 from IRQ stack
ldmia sp!, {r0,r14}
msr SPSR_cxsf, r14
;- Restore adjusted LR_irq from IRQ stack directly in the PC
ldmia sp!, {pc}^
;------------------------------------------------------------------------------
;- Exception Vectors
;------------------------------------------------------------------------------
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
ARM ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
;------------------------------------------------------------------------------
; ?INIT
; Program entry.
;------------------------------------------------------------------------------
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
SECTION text:CODE:NOROOT(2)
REQUIRE __vector
EXTERN ?main
PUBLIC __iar_program_start
EXTERN AT91F_LowLevelInit
__iar_program_start:
;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;------------------------------------------------------------------------------
;- Retrieve end of RAM address
ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution
ldr r0,=AT91F_LowLevelInit
mov lr, pc
bx r0 ;- Branch on C function (with interworking)
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
mrs r0,cpsr ; Original PSR value
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SVC_MODE ; Set SVC mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#UND_MODE ; Set UND mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(UND_STACK) ; End of UND_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#ABT_MODE ; Set ABT mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#FIQ_MODE ; Set FIQ mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
;- Init the FIQ register
ldr r8, =AT91C_BASE_AIC
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#IRQ_MODE ; Set IRQ mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SYS_MODE ; Set System mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(CSTACK) ; End of CSTACK
#ifdef __ARMVFP__
; Enable the VFP coprocessor.
mov r0, #0x40000000 ; Set EN bit in VFP
fmxr fpexc, r0 ; FPEXC, clear others.
; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
mov r0, #0x01000000 ; Set FZ bit in VFP
fmxr fpscr, r0 ; FPSCR, clear others.
#endif
; Add more initialization here
msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
; Continue to ?main for more IAR specific system startup
ldr r0,=?main
bx r0
END ;- Terminates the assembly of the last module in a file

151
Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
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@ -1,94 +1,97 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : Cstartup_SAM7.c
//* Object : Low level initializations written in C for IAR
//* tools
//* 1.0 08/Sep/04 JPP : Creation
//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
//*----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
//-----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//-----------------------------------------------------------------------------
// File Name : Cstartup_SAM7.c
// Object : Low level initialisations written in C for Tools
// For AT91SAM7X256 with 2 flash plane
// Creation : JPP 14-Sep-2006
//-----------------------------------------------------------------------------
// Include the board file description
#include "Board.h"
//#include "init.h"
#include <string.h>
// The following functions must be write in ARM mode this function called directly
// by exception vector
// The following functions must be write in ARM mode this function called
// directly by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* this function can use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void);
void AT91F_LowLevelInit( void ) @ "ICODE"
void AT91F_LowLevelInit(void) @ "ICODE"
{
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
unsigned char i;
///////////////////////////////////////////////////////////////////////////
// EFC Init
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
//* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
///////////////////////////////////////////////////////////////////////////
// Init PMC Step 1. Enable Main Oscillator
// Main Oscillator startup time is board specific:
// Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
// (0x40 for AT91C_CKGR_OSCOUNT field)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
// Wait Main Oscillator stabilization
while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
///////////////////////////////////////////////////////////////////////////
// Init PMC Step 2.
// Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
// PLL Startup time depends on PLL RC filter: worst case is choosen
// UDP Clock (48,058MHz) is compliant with the Universal Serial Bus
// Specification (+/- 0.25% for full speed)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 |
(16 << 8) |
(AT91C_CKGR_MUL & (72 << 16)) |
(AT91C_CKGR_DIV & 14);
// Wait for PLL stabilization
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
// Wait until the master clock is established for the case we already
// turn on the PLL
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
// If we are running off a j-link then the PLL will have already been setup.
if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) )
{
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSeconde
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
//eld out NOT USED = 0 Fi
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
(AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (25<<16)));
///////////////////////////////////////////////////////////////////////////
// Init PMC Step 3.
// Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
// The PMC_MCKR register must not be programmed in a single write operation
// (see. Product Errata Sheet)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
///////////////////////////////////////////////////////////////////////////
// Disable Watchdog (write once register)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
}
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i=1;i < 31; i++)
{
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
///////////////////////////////////////////////////////////////////////////
// Init AIC: assign corresponding handler for each interrupt source
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
}

1590
Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep
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File diff suppressed because it is too large Load diff

586
Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd
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@ -12,7 +12,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>12</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -37,7 +37,7 @@
</option>
<option>
<name>MacFile</name>
<state>$PROJ_DIR$\resource\SAM7.mac</state>
<state>$PROJ_DIR$\resource\SAM7_FLASH.mac</state>
</option>
<option>
<name>MemOverride</name>
@ -45,7 +45,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\ioat91sam7x256.ddf</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ioAT91SAM7X256.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@ -77,24 +77,8 @@
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashDownload</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashLoader</name>
<state>$TOOLKIT_DIR$\config\flashloader\Atmel\FlashAT91SAM7X256.d79</state>
</option>
<option>
<name>OCDownloadFlashLoaderSlave</name>
<state></state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.10B</state>
@ -105,37 +89,53 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>4.20A</state>
</option>
<option>
<name>OCDownloadFlashLoaderArgs</name>
<state></state>
</option>
<option>
<name>OCDownloadFlashBaseAddrOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashBaseAddr</name>
<state></state>
<state>5.11.0.50615</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
<state>1</state>
</option>
<option>
<name>OCBE8Slave</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCSimEnablePSP</name>
<state>0</state>
</option>
<option>
<name>OCSimPspOverrideConfig</name>
<state>0</state>
</option>
<option>
<name>OCSimPspConfigFile</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -181,6 +181,43 @@
</option>
</data>
</settings>
<settings>
<name>GDBSERVER_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
@ -220,29 +257,13 @@
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>9</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>JLinkSpeed</name>
<state>30</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
@ -255,10 +276,6 @@
<name>CCJLinkHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
@ -267,13 +284,124 @@
<name>JLinkInitialSpeed</name>
<state>32</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>CCJLinkSpeedRadioV2</name>
<state>0</state>
</option>
<option>
<name>CCUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCJLinkBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJLinkUpdateBreakpoints</name>
<state>main</state>
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>OCJLinkAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>0</version>
<state>5</state>
</option>
</data>
</settings>
<settings>
<name>LMIFTDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>LmiftdiSpeed</name>
<state>500</state>
</option>
<option>
<name>CCLmiftdiDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCLmiftdiLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -336,6 +464,18 @@
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
@ -426,23 +566,23 @@
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
@ -450,7 +590,23 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
</debuggerPlugins>
@ -465,7 +621,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>12</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -532,22 +688,6 @@
<name>OCDownloadVerifyAll</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashDownload</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashLoader</name>
<state>$TOOLKIT_DIR$\config\flashloader\Atmel\FlashAT91SAM7X256.d79</state>
</option>
<option>
<name>OCDownloadFlashLoaderSlave</name>
<state></state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.10B</state>
@ -560,35 +700,51 @@
<name>OCLastSavedByProductVersion</name>
<state>4.20A</state>
</option>
<option>
<name>OCDownloadFlashLoaderArgs</name>
<state></state>
</option>
<option>
<name>OCDownloadFlashBaseAddrOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashBaseAddr</name>
<state></state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
<state>1</state>
</option>
<option>
<name>OCBE8Slave</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCSimEnablePSP</name>
<state>0</state>
</option>
<option>
<name>OCSimPspOverrideConfig</name>
<state>0</state>
</option>
<option>
<name>OCSimPspConfigFile</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -634,6 +790,43 @@
</option>
</data>
</settings>
<settings>
<name>GDBSERVER_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
@ -673,29 +866,13 @@
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>9</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>JLinkSpeed</name>
<state>30</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
@ -708,10 +885,6 @@
<name>CCJLinkHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
@ -720,13 +893,124 @@
<name>JLinkInitialSpeed</name>
<state>32</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>CCJLinkSpeedRadioV2</name>
<state>0</state>
</option>
<option>
<name>CCUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCJLinkBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJLinkUpdateBreakpoints</name>
<state>main</state>
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>OCJLinkAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>0</version>
<state>5</state>
</option>
</data>
</settings>
<settings>
<name>LMIFTDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>LmiftdiSpeed</name>
<state>500</state>
</option>
<option>
<name>CCLmiftdiDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCLmiftdiLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -789,6 +1073,18 @@
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
@ -879,23 +1175,23 @@
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
@ -903,9 +1199,25 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
</debuggerPlugins>
</configuration>
</project>

1080
Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp
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