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UpdUpdate IAR projects to use Embedded Workbench V5.11.

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Richard Barry 2008-01-23 08:35:47 +00:00
parent dfb8e7003b
commit 474cb76864
104 changed files with 10988 additions and 22710 deletions
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297
Demo/ARM7_STR71x_IAR/71x_init.s Normal file
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;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
;* File Name : 71x_init.s
;* Author : MCD Application Team
;* Date First Issued : 06/23/2004
;* Description : This is the first code executed after RESET.
;* This code used to initialize system stacks
;* and critical peripherals before entering the C code.
;*******************************************************************************
;* History:
;* 13/01/2006 : V3.1
;* 24/05/2005 : V3.0
;* 30/11/2004 : V2.0
;* 14/07/2004 : V1.3
;* 01/01/2004 : V1.2
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************/
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UNDEF EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
EIC_Base_addr EQU 0xFFFFF800; EIC base address
ICR_off_addr EQU 0x00 ; Interrupt Control register offset
CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset
IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset
FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset
IER_off_addr EQU 0x20 ; Interrupt Enable Register offset
IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset
SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0
EMI_Base_addr EQU 0x6C000000; EMI base address
BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset
BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset
BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset
BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset
EMI_ENABLE EQU 0x8000
EMI_SIZE_16 EQU 0x0001
GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address
PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset
PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset
PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset
PD_off_addr EQU 0x0C ; Port Data Register offset
CPM_Base_addr EQU 0xA0000040; CPM Base Address
BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register
FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0
RAM_mask EQU 0x0002 ; to remap RAM at 0x0
;|----------------------------------------------------------------------------------|
;| - APB Bridge (System Peripheral) |
;|----------------------------------------------------------------------------------|
APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address
APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address
CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register
SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register
CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals
SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals
CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals
SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals
;---------------------------------------------------------------
; ?program_start
;---------------------------------------------------------------
MODULE ?program_start
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
SECTION .text:CODE(2)
PUBLIC __iar_program_start
EXTERN ?main
EXTERN ?main
CODE32
;*******************************************************************************
;******* -- MACROS -- *******
;*******************************************************************************
;*******************************************************************************
;* Macro Name : EMI_INIT
;* Description : This macro Initialize EMI bank 1: 16-bit 7 wait state
;* Input : None.
;* Output : None.
;*******************************************************************************
EMI_INIT MACRO
LDR r0, =GPIO2_Base_addr ; Configure P2.0 -> 3 in AF_PP mode
LDR r2, [r0, #PC0_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC0_off_addr]
LDR r2, [r0, #PC1_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC1_off_addr]
LDR r2, [r0, #PC2_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC2_off_addr]
LDR r0, =EMI_Base_addr
LDR r1, =0x18|EMI_ENABLE|EMI_SIZE_16
STR r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state
ENDM
;*******************************************************************************
;* Macro Name : EIC_INIT
;* Description : This macro Initialize the EIC as following :
; - IRQ disabled
; - FIQ disabled
; - IVR contain the load PC opcode (0xE59FFXXX)
; - Current priority level equal to 0
; - All channels are disabled
; - All channels priority equal to 0
; - All SIR registers contain offset to the related IRQ
; table entry
;* Input : None.
;* Output : None.
;*******************************************************************************
EIC_INIT MACRO
LDR r3, =EIC_Base_addr
LDR r4, =0xE59F0000
STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]
; instruction code in IVR[31:16]
LDR r2, =32 ; 32 Channel to initialize
LDR r0, =T0TIMI_Addr ; Read the address of the IRQs
; address table
LDR r1, =0x00000FFF
AND r0,r0,r1
LDR r5, =SIR0_off_addr ; Read SIR0 address
SUB r4,r0,#8 ; subtract 8 for prefetch
LDR r1, =0xF7E8 ; Add the offset from IVR to 0x00000000
; address(IVR address + 7E8 = 0x00000000)
; 0xF7E8 used to complete the
; LDR pc,[pc,#offset] opcode (0xE59FFXXX)
ADD r1,r4,r1 ; Compute the jump offset from IVR to the
; IRQ table entry.
EIC_INI MOV r4, r1, LSL #16 ; Left shift the result
STR r4, [r3, r5] ; Store the result in SIRx register
ADD r1, r1, #4 ; Next IRQ address
ADD r5, r5, #4 ; Next SIR
SUBS r2, r2, #1 ; Decrement the number of SIR registers
; to initialize
BNE EIC_INI ; If more then continue
ENDM
;*******************************************************************************
;* Macro Name : PERIPHERAL_INIT
;* Description : This macro reset all device peripherals.
;* Input : None.
;* Output : None.
;*******************************************************************************
PERIPHERAL_INIT MACRO
LDR r1, =APB1_base_addr ; r0= APB1 base address
LDR r2, =APB2_base_addr ; r0= APB2 base address
LDR r0, =CKDIS1_config_all
STRH r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals
LDR r0, =CKDIS2_config_all
STRH r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals
LDR r0, =SWRES1_config_all
STRH r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset
LDR r0, =SWRES2_config_all
STRH r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset
MOV r7, #10 ; Wait that the selected macrocells exit from reset
loop1 SUBS r7, r7, #1
BNE loop1
MOV r0, #0
STRH r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals
STRH r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals
STRH r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals
STRH r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals
MOV r7, #10 ; Wait that the selected macrocells exit from reset
loop2 SUBS r7, r7, #1
BNE loop2
ENDM
;********************************************************************************************
; define remapping
; If you need to remap memory before entring the main program
; uncomment next ligne
; #define remapping
; Then define which memory to remap to address 0x00000000
; Uncomment next line if you want to remap RAM
; #define remap_ram
; Uncomment next line if you want to remap FLASH
; #define remap_flash
IMPORT T0TIMI_Addr
__iar_program_start
LDR pc, =NextInst
NextInst
NOP ; Wait for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
ldr sp,=SFE(UND_STACK) ; End of UNDEF_STACK
MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
; Uncomment next ligne if you need to reset all device pripherals
; PERIPHERAL_INIT ; Reset all device peripherals
; Uncomment next ligne if you need to enable the EMI Bank 1
; EMI_INIT ; Initialize EIM Bank 1
;Uncomment next ligne if you need to initialize the EIC
EIC_INIT ; Initialize EIC
;******************************************************************************
;REMAPPING
;Description : Remapping memory whether RAM,FLASH
; at Address 0x0 after the application has started executing.
; Remapping is generally done to allow RAM to replace FLASH
; at 0x0.
; the remapping of RAM allow copying of vector table into RAM
; To enable the memory remapping uncomment: (see above)
; #define remapping to enable memory remapping
; AND
; #define remap_ram to remap RAM
; OR
; #define remap_flash to remap FLASH
;******************************************************************************
#ifdef remapping
#ifdef remap_flash
MOV r0, #FLASH_mask
#endif
#ifdef remap_ram
MOV r0, #RAM_mask
#endif
LDR r1, =CPM_Base_addr
LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register
BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR
ORR r2, r2, r0 ; change the two LSB bits of BOOTCR
STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register
#endif
MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode
ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode
ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
MSR CPSR_c, #Mode_SYS ; Change to system mode, Enable IRQ and FIQ
ldr sp,=SFE(CSTACK) ; End of CSTACK(user)
; --- Now branches to a C lib function that copies RO data from their
; load region to their execute region, create the RW and ZI regions
; then jumps to user C main program.
; main() must be called from Supervisor mode
MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
b ?main ; Note : use B not BL, because an application will
; never return this way
LTORG
END
;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****

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Demo/ARM7_STR71x_IAR/71x_vect.s Normal file
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#include "FreeRTOSConfig.h"
;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
;* File Name : 71x_vect.s
;* Author : MCD Application Team
;* Date First Issued : 16/05/2003
;* Description : This file used to initialize the exception and IRQ
;* vectors, and to enter/return to/from exceptions handlers.
;*******************************************************************************
;* History:
;* 13/01/2006 : V3.1
;* 24/05/2005 : V3.0
;* 30/11/2004 : V2.0
;* 14/07/2004 : V1.3
;* 01/01/2004 : V1.2
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************/
MODULE ?RESET
SECTION .intvec:CODE(2)
CODE32
EIC_base_addr EQU 0xFFFFF800; EIC base address.
CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register.
IVR_off_addr EQU 0x18 ; Interrupt Vector Register.
IPR_off_addr EQU 0x40 ; Interrupt Pending Register.
;*******************************************************************************
; Import the __iar_program_start address from 71x_init.s
;*******************************************************************************
IMPORT __iar_program_start
;*******************************************************************************
; Import exception handlers
;*******************************************************************************
IMPORT Undefined_Handler
IMPORT Prefetch_Handler
IMPORT Abort_Handler
IMPORT FIQ_Handler
;*******************************************************************************
; Import IRQ handlers from 71x_it.c
;*******************************************************************************
IMPORT Default_Handler
IMPORT vPortYieldProcessor
IMPORT vSerialISREntry
IMPORT vPortPreemptiveTickISR
IMPORT vPortNonPreemptiveTick
;*******************************************************************************
; Export Peripherals IRQ handlers table address
;*******************************************************************************
EXPORT T0TIMI_Addr
;*******************************************************************************
; Exception vectors
;*******************************************************************************
IVR_ADDR DEFINE 0xFFFFF818
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP ; Reserved vector
LDR PC, =IVR_ADDR
LDR PC, FIQ_Addr
;*******************************************************************************
; Exception handlers address table
;*******************************************************************************
Reset_Addr DCD __iar_program_start
Undefined_Addr DCD UndefinedHandler
SWI_Addr DCD vPortYieldProcessor
Prefetch_Addr DCD PrefetchAbortHandler
Abort_Addr DCD DataAbortHandler
DCD 0 ; Reserved vector
IRQ_Addr DCD 0 ; Direct vectors are used. See the STR75x demo for an alternative implementation
FIQ_Addr DCD FIQHandler
;*******************************************************************************
; Peripherals IRQ handlers address table
;*******************************************************************************
T0TIMI_Addr DCD Default_Handler
FLASH_Addr DCD Default_Handler
RCCU_Addr DCD Default_Handler
RTC_Addr DCD Default_Handler
#if configUSE_PREEMPTION == 0
WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used.
#else
WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used.
#endif
XTI_Addr DCD Default_Handler
USBHP_Addr DCD Default_Handler
I2C0ITERR_Addr DCD Default_Handler
I2C1ITERR_ADDR DCD Default_Handler
UART0_Addr DCD vSerialISREntry
UART1_Addr DCD Default_Handler
UART2_ADDR DCD Default_Handler
UART3_ADDR DCD Default_Handler
BSPI0_ADDR DCD Default_Handler
BSPI1_Addr DCD Default_Handler
I2C0_Addr DCD Default_Handler
I2C1_Addr DCD Default_Handler
CAN_Addr DCD Default_Handler
ADC12_Addr DCD Default_Handler
T1TIMI_Addr DCD Default_Handler
T2TIMI_Addr DCD Default_Handler
T3TIMI_Addr DCD Default_Handler
DCD 0 ; reserved
DCD 0 ; reserved
DCD 0 ; reserved
HDLC_Addr DCD Default_Handler
USBLP_Addr DCD Default_Handler
DCD 0 ; reserved
DCD 0 ; reserved
T0TOI_Addr DCD Default_Handler
T0OC1_Addr DCD Default_Handler
T0OC2_Addr DCD Default_Handler
;*******************************************************************************
; Exception Handlers
;*******************************************************************************
;*******************************************************************************
;* Macro Name : SaveContext
;* Description : This macro used to save the context before entering
; an exception handler.
;* Input : The range of registers to store.
;* Output : none
;*******************************************************************************
SaveContext MACRO reg1,reg2
STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return
; address lr_ mode into the stack.
MRS r1,spsr ; Save the spsr_mode into r1.
STMFD sp!,{r1} ; Save spsr.
ENDM
;*******************************************************************************
;* Macro Name : RestoreContext
;* Description : This macro used to restore the context to return from
; an exception handler and continue the program execution.
;* Input : The range of registers to restore.
;* Output : none
;*******************************************************************************
RestoreContext MACRO reg1,reg2
LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1.
MSR spsr_cxsf,r1 ; Restore spsr_mode.
LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following...
; ...the exception interrupt.
ENDM
;*******************************************************************************
;* Function Name : UndefinedHandler
;* Description : This function called when undefined instruction
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************
UndefinedHandler
SaveContext r0,r12 ; Save the workspace plus the current
; return address lr_ und and spsr_und.
ldr r0,=Undefined_Handler
ldr lr,=Undefined_Handler_end
bx r0 ; Branch to Undefined_Handler
Undefined_Handler_end:
RestoreContext r0,r12 ; Return to the instruction following...
; ...the undefined instruction.
;*******************************************************************************
;* Function Name : PrefetchAbortHandler
;* Description : This function called when Prefetch Abort
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************
PrefetchAbortHandler
SUB lr,lr,#4 ; Update the link register.
SaveContext r0,r12 ; Save the workspace plus the current
; return address lr_abt and spsr_abt.
ldr r0,=Prefetch_Handler
ldr lr,=Prefetch_Handler_end
bx r0 ; Branch to Prefetch_Handler.
Prefetch_Handler_end:
RestoreContext r0,r12 ; Return to the instruction following that...
; ...has generated the prefetch abort exception.
;*******************************************************************************
;* Function Name : DataAbortHandler
;* Description : This function is called when Data Abort
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************
DataAbortHandler
SUB lr,lr,#8 ; Update the link register.
SaveContext r0,r12 ; Save the workspace plus the current
; return address lr_ abt and spsr_abt.
ldr r0,=Abort_Handler
ldr lr,=Abort_Handler_end
bx r0 ; Branch to Abort_Handler.
Abort_Handler_end:
RestoreContext r0,r12 ; Return to the instruction following that...
; ...has generated the data abort exception.
;*******************************************************************************
;* Function Name : FIQHandler
;* Description : This function is called when FIQ
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************
FIQHandler
SUB lr,lr,#4 ; Update the link register.
SaveContext r0,r7 ; Save the workspace plus the current
; return address lr_ fiq and spsr_fiq.
ldr r0,=FIQ_Handler
ldr lr,=FIQ_Handler_end
bx r0 ; Branch to FIQ_Handler.
FIQ_Handler_end:
RestoreContext r0,r7 ; Restore the context and return to the...
; ...program execution.
LTORG
END
;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****

78
Demo/ARM7_STR71x_IAR/Library/71x_it.c Normal file
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@ -0,0 +1,78 @@
/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_it.c
* Author : MCD Application Team
* Date First Issued : 16/05/2003
* Description : Main Interrupt Service Routines
*******************************************************************************
* History:
* 24/05/05 : V3.0
* 30/11/04 : V2.0
* 16/05/03 : Created
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#include "71x_it.h"
u32 counter=1;
/*******************************************************************************
* Function Name : Undefined_Handler
* Description : This function handles Undefined instruction exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Undefined_Handler(void)
{
for( ;; );
}
/*******************************************************************************
* Function Name : FIQ_Handler
* Description : This function handles FIQ exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FIQ_Handler(void)
{
for( ;; );
}
/*******************************************************************************
* Function Name : Prefetch_Handler
* Description : This function handles Prefetch Abort exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Prefetch_Handler(void)
{
for( ;; );
}
/*******************************************************************************
* Function Name : Abort_Handler
* Description : This function handles Data Abort exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Abort_Handler(void)
{
for( ;; );
}
void Default_Handler( void );
void Default_Handler( void )
{
for( ;; );
}
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

584
Demo/ARM7_STR71x_IAR/RTOSDemo.ewd
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@ -12,7 +12,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>12</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -77,24 +77,8 @@
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashDownload</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashOverride</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashLoader</name>
<state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTR71xF.d79</state>
</option>
<option>
<name>OCDownloadFlashLoaderSlave</name>
<state></state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.20A</state>
@ -105,37 +89,53 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>4.20A</state>
</option>
<option>
<name>OCDownloadFlashLoaderArgs</name>
<state></state>
</option>
<option>
<name>OCDownloadFlashBaseAddrOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashBaseAddr</name>
<state></state>
<state>5.11.0.50615</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,0x40000000,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
<state>1</state>
</option>
<option>
<name>OCBE8Slave</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCSimEnablePSP</name>
<state>0</state>
</option>
<option>
<name>OCSimPspOverrideConfig</name>
<state>0</state>
</option>
<option>
<name>OCSimPspConfigFile</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -181,6 +181,43 @@
</option>
</data>
</settings>
<settings>
<name>GDBSERVER_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
@ -220,29 +257,13 @@
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>9</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>JLinkSpeed</name>
<state>32</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>1</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
@ -255,10 +276,6 @@
<name>CCJLinkHWResetDelay</name>
<state>0</state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
@ -267,13 +284,124 @@
<name>JLinkInitialSpeed</name>
<state>4000</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>CCJLinkSpeedRadioV2</name>
<state>0</state>
</option>
<option>
<name>CCUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCJLinkBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJLinkUpdateBreakpoints</name>
<state>main</state>
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>OCJLinkAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>LMIFTDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>LmiftdiSpeed</name>
<state>500</state>
</option>
<option>
<name>CCLmiftdiDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCLmiftdiLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -336,6 +464,18 @@
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
@ -426,23 +566,23 @@
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
@ -450,9 +590,25 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
</debuggerPlugins>
</configuration>
<configuration>
@ -465,7 +621,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>12</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -532,22 +688,6 @@
<name>OCDownloadVerifyAll</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashDownload</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashOverride</name>
<state>1</state>
</option>
<option>
<name>OCDownloadFlashLoader</name>
<state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTR71xF.d79</state>
</option>
<option>
<name>OCDownloadFlashLoaderSlave</name>
<state></state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.20A</state>
@ -558,37 +698,53 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>4.20A</state>
</option>
<option>
<name>OCDownloadFlashLoaderArgs</name>
<state></state>
</option>
<option>
<name>OCDownloadFlashBaseAddrOverride</name>
<state>0</state>
</option>
<option>
<name>OCDownloadFlashBaseAddr</name>
<state></state>
<state>5.11.0.50615</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,0x40000000,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
<state>1</state>
</option>
<option>
<name>OCBE8Slave</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
<option>
<name>OCSimEnablePSP</name>
<state>0</state>
</option>
<option>
<name>OCSimPspOverrideConfig</name>
<state>0</state>
</option>
<option>
<name>OCSimPspConfigFile</name>
<state></state>
</option>
</data>
</settings>
<settings>
@ -634,6 +790,43 @@
</option>
</data>
</settings>
<settings>
<name>GDBSERVER_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
@ -673,29 +866,13 @@
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>9</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>JLinkSpeed</name>
<state>32</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>1</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
@ -708,10 +885,6 @@
<name>CCJLinkHWResetDelay</name>
<state>0</state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
@ -720,13 +893,124 @@
<name>JLinkInitialSpeed</name>
<state>4000</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>CCJLinkSpeedRadioV2</name>
<state>0</state>
</option>
<option>
<name>CCUSBDevice</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCJLinkBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJLinkUpdateBreakpoints</name>
<state>main</state>
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
</option>
<option>
<name>OCJLinkAttachSlave</name>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>LMIFTDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>LmiftdiSpeed</name>
<state>500</state>
</option>
<option>
<name>CCLmiftdiDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCLmiftdiLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -789,6 +1073,18 @@
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJTagBreakpointRadio</name>
<state>0</state>
</option>
<option>
<name>CCJTagDoUpdateBreakpoints</name>
<state>0</state>
</option>
<option>
<name>CCJTagUpdateBreakpoints</name>
<state>main</state>
</option>
</data>
</settings>
<settings>
@ -879,23 +1175,23 @@
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
@ -903,7 +1199,23 @@
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
</debuggerPlugins>

1214
Demo/ARM7_STR71x_IAR/RTOSDemo.ewp
View file

File diff suppressed because it is too large Load diff

42
Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf Normal file
View file

@ -0,0 +1,42 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x40000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x4000062C;
define symbol __ICFEDIT_region_ROM_end__ = 0x4003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_svcstack__ = 0x100;
define symbol __ICFEDIT_size_irqstack__ = 0x200;
define symbol __ICFEDIT_size_fiqstack__ = 0x10;
define symbol __ICFEDIT_size_undstack__ = 0x10;
define symbol __ICFEDIT_size_abtstack__ = 0x10;
define symbol __ICFEDIT_size_heap__ = 0x4;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };

14
Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt
View file

@ -9,7 +9,7 @@
<Column0>129</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
<Column0>273</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows>
@ -21,7 +21,7 @@
<MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
<CodeCovEnabled>0</CodeCovEnabled><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow></Disassembly>
<Debug-Log/>
<Build>
@ -33,7 +33,7 @@
<Windows>
<Wnd2>
<Wnd3>
<Tabs>
<Tab>
<Identity>TabID-24393-22702</Identity>
@ -45,7 +45,7 @@
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
<SelectedTab>0</SelectedTab></Wnd3><Wnd4>
<Tabs>
<Tab>
<Identity>TabID-13122-22708</Identity>
@ -61,20 +61,20 @@
</Tab>
<Tab><Identity>TabID-19116-28152</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs>
<SelectedTab>0</SelectedTab></Wnd3><Wnd0><Tabs><Tab><Identity>TabID-10243-6871</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd0></Windows>
<SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-10802-25870</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5></Windows>
<Editor>
<Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
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30
Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni
View file

@ -4,16 +4,25 @@ State 1=_ 1
[JLinkDriver]
WatchVectorCatch=_ 0
WatchCond=_ 0
Watch0=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0
Watch1=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[Low Level]
Pipeline mode=0
Initialized=0
[Disassemble mode]
mode=0
[Breakpoints]
Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\STR71x\port.c}.240.4@1" 1 0 0 0 "" 0 ""
Count=1
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OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnHow=0
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ByteLimit=50
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LogFile=_ ""
@ -21,3 +30,10 @@ Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Disassemble mode]
mode=0
[Breakpoints]
Count=0
[TraceHelper]
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ShowSource=1

16
Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt
View file

@ -3,7 +3,7 @@
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>
<CurrentConfigs><Project>RTOSDemo/Release</Project></CurrentConfigs></ConfigDictionary>
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@ -12,7 +12,7 @@
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<Column0>189</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
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<Build>
@ -23,11 +23,11 @@
<TerminalIO/>
<Profiling/>
<Debug-Log/>
<CodeCoveragePlugin/><Breakpoints/></Static>
<CodeCoveragePlugin/><Breakpoints/><Disassembly><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow></Disassembly></Static>
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<Tab>
<Identity>TabID-14962-21036</Identity>
@ -39,7 +39,7 @@
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<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
<SelectedTab>0</SelectedTab></Wnd3><Wnd4>
<Tabs>
<Tab>
<Identity>TabID-24623-22493</Identity>
@ -55,20 +55,20 @@
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<Tab><Identity>TabID-25855-25419</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs>
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