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Merge branch 'main' into MISRA-13.2

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bradleysmith23 2024-02-05 10:50:39 -08:00 • committed by GitHub
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12 changed files with 32 additions and 32 deletions
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8
portable/CMakeLists.txt
View file

@ -68,12 +68,12 @@ add_library(freertos_kernel_port OBJECT
# ARMv8-A ports for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:
GCC/Arm_AARCH64/port.c
GCC/Arm_AARCH64/portASM.S>
GCC/ARM_AARCH64/port.c
GCC/ARM_AARCH64/portASM.S>
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:
GCC/Arm_AARCH64_SRE/port.c
GCC/Arm_AARCH64_SRE/portASM.S>
GCC/ARM_AARCH64_SRE/port.c
GCC/ARM_AARCH64_SRE/portASM.S>
# ARMv6-M port for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:

38
portable/Common/mpu_wrappers_v2.c
View file

@ -92,16 +92,16 @@
/**
* @brief Checks whether an external index is valid or not.
*/
#define IS_EXTERNAL_INDEX_VALID( lIndex ) \
( ( ( lIndex ) >= INDEX_OFFSET ) && \
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) )
#define IS_EXTERNAL_INDEX_VALID( lIndex ) \
( ( ( ( lIndex ) >= INDEX_OFFSET ) && \
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) ) ? pdTRUE : pdFALSE )
/**
* @brief Checks whether an internal index is valid or not.
*/
#define IS_INTERNAL_INDEX_VALID( lIndex ) \
( ( ( lIndex ) >= 0 ) && \
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) )
#define IS_INTERNAL_INDEX_VALID( lIndex ) \
( ( ( ( lIndex ) >= 0 ) && \
( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) ) ? pdTRUE : pdFALSE )
/**
* @brief Converts an internal index into external.
@ -2197,7 +2197,7 @@
if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) &&
( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
@ -2312,7 +2312,7 @@
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
@ -2364,7 +2364,7 @@
if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
@ -2411,9 +2411,9 @@
{
uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle );
if( ( uxQueueItemSize == 0 )
if( ( uxQueueItemSize == 0U )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{
@ -3906,10 +3906,10 @@
if( xAreParamsReadable == pdTRUE )
{
if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
( pxParams->uxBitsToWaitFor != 0 )
if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
( pxParams->uxBitsToWaitFor != 0U )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) )
#endif
)
{
@ -3951,7 +3951,7 @@
int32_t lIndex;
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
{
lIndex = ( int32_t ) xEventGroup;
@ -3986,7 +3986,7 @@
int32_t lIndex;
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 )
if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U )
{
lIndex = ( int32_t ) xEventGroup;
@ -4025,10 +4025,10 @@
int32_t lIndex;
BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE;
if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ) &&
( uxBitsToWaitFor != 0 )
if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) &&
( uxBitsToWaitFor != 0U )
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) )
&& ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) )
#endif
)
{

4
portable/GCC/Arm_AARCH64/README.md → portable/GCC/ARM_AARCH64/README.md
View file

@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
for more information.
## Arm_AARCH64 port
## ARM_AARCH64 port
This port adds support for Armv8-A architecture AArch64 execution state.
This port is generic and can be used as a starting point for Armv8-A
application processors.
* Arm_AARCH64
* ARM_AARCH64
* Memory mapped interace to access Arm GIC registers

0
portable/GCC/Arm_AARCH64/port.c → portable/GCC/ARM_AARCH64/port.c
View file

0
portable/GCC/Arm_AARCH64/portASM.S → portable/GCC/ARM_AARCH64/portASM.S
View file

0
portable/GCC/Arm_AARCH64/portmacro.h → portable/GCC/ARM_AARCH64/portmacro.h
View file

4
portable/GCC/Arm_AARCH64_SRE/README.md → portable/GCC/ARM_AARCH64_SRE/README.md
View file

@ -13,11 +13,11 @@ the T32 and A32 instruction sets. Follow the
[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
for more information.
## Arm_AARCH64_SRE port
## ARM_AARCH64_SRE port
This port adds support for Armv8-A architecture AArch64 execution state.
This port is generic and can be used as a starting point for Armv8-A
application processors.
* Arm_AARCH64_SRE
* ARM_AARCH64_SRE
* System Register interace to access Arm GIC registers

0
portable/GCC/Arm_AARCH64_SRE/port.c → portable/GCC/ARM_AARCH64_SRE/port.c
View file

0
portable/GCC/Arm_AARCH64_SRE/portASM.S → portable/GCC/ARM_AARCH64_SRE/portASM.S
View file

0
portable/GCC/Arm_AARCH64_SRE/portmacro.h → portable/GCC/ARM_AARCH64_SRE/portmacro.h
View file

4
portable/GCC/ARM_CA53_64_BIT/README.md
View file

@ -8,8 +8,8 @@ Arm Cortex-A53 processor.
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
should migrate to renamed port `Arm_AARCH64`.
`ARM_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
should migrate to renamed port `ARM_AARCH64`.
**NOTE**

6
portable/GCC/ARM_CA53_64_BIT_SRE/README.md
View file

@ -7,9 +7,9 @@ Arm Cortex-A53 processor.
* System Register interace to access Arm GIC registers
This port is generic and can be used as a starting point for other Armv8-A
application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
should migrate to renamed port `Arm_AARCH64_SRE`.
application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as
`ARM_AARCH64_SRE`. The existing projects that use old port `ARM_AARCH64_SRE`,
should migrate to renamed port `ARM_AARCH64_SRE`.
**NOTE**