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Run the peripheral clock at 48MHz. It was set to 96MHz which was too fast.

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This commit is contained in:
Richard Barry 2006-08-10 20:15:54 +00:00
parent df9b2abe91
commit 430893f5f8
2 changed files with 3 additions and 2 deletions
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2
Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h
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@ -47,7 +47,7 @@
#define configUSE_IDLE_HOOK 0 #define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0 #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 ) #define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 )
#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 96000000 ) #define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 48000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 ) #define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 )

3
Demo/ARM9_STR91X_IAR/main.c
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@ -228,7 +228,8 @@ static void prvSetupHardware( void )
/* FMI Waite States */ /* FMI Waite States */
FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH ); FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH );
/* Configure the FPLL = 96MHz */ /* Configure the FPLL = 96MHz, and APB to 48MHz. */
SCU_PCLKDivisorConfig( SCU_PCLK_Div2 );
SCU_PLLFactorsConfig( 192, 25, 2 ); SCU_PLLFactorsConfig( 192, 25, 2 );
SCU_PLLCmd( ENABLE ); SCU_PLLCmd( ENABLE );
SCU_MCLKSourceConfig( SCU_MCLK_PLL ); SCU_MCLKSourceConfig( SCU_MCLK_PLL );