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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2026-05-12 19:52:55 -04:00
Update SiFive FreedomStudio project (#785)
SiFive FreedomStudio project changes needed for refactored code Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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673d3d7eea
commit
4255ac5c28
5 changed files with 144 additions and 7 deletions
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@ -57,7 +57,7 @@
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<tool id="cdt.managedbuild.tool.gnu.cross.cpp.linker.2105463183" name="Cross G++ Linker" superClass="cdt.managedbuild.tool.gnu.cross.cpp.linker"/>
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<tool id="cdt.managedbuild.tool.gnu.cross.archiver.424513814" name="Cross GCC Archiver" superClass="cdt.managedbuild.tool.gnu.cross.archiver"/>
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<tool command="riscv64-unknown-elf-gcc" id="cdt.managedbuild.tool.gnu.cross.assembler.825438707" name="Cross GCC Assembler" superClass="cdt.managedbuild.tool.gnu.cross.assembler">
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<option id="gnu.both.asm.option.flags.1946908814" name="Assembler flags" superClass="gnu.both.asm.option.flags" useByScannerDiscovery="false" value="-march=rv32imac -mabi=ilp32 -mcmodel=medlow -c -DportasmHANDLE_INTERRUPT=handle_trap -g3" valueType="string"/>
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<option id="gnu.both.asm.option.flags.1946908814" name="Assembler flags" superClass="gnu.both.asm.option.flags" useByScannerDiscovery="false" value="-march=rv32imac -mabi=ilp32 -mcmodel=medlow -c -g3" valueType="string"/>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.both.asm.option.include.paths.1448234506" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions}""/>
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</option>
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@ -5,7 +5,7 @@
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<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
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<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
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<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="644150116465149599" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
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<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1654240179677726431" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
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<language-scope id="org.eclipse.cdt.core.gcc"/>
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<language-scope id="org.eclipse.cdt.core.g++"/>
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</provider>
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@ -20,7 +20,7 @@
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://aws.amazon.com/freertos
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* https://github.com/FreeRTOS
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*
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*/
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@ -47,8 +47,8 @@
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#define configCPU_CLOCK_HZ ( 32768 )
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#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
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#define configMAX_PRIORITIES ( 7 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */
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#define configTOTAL_HEAP_SIZE ( ( size_t ) 10900 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) 10 * 1024 )
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 0
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#define configUSE_16_BIT_TICKS 0
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@ -20,7 +20,7 @@
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://aws.amazon.com/freertos
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* https://github.com/FreeRTOS
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*
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*/
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@ -59,6 +59,17 @@
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or 0 to run the more comprehensive test and demo application. */
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#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
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/* Set to 1 to use direct mode and set to 0 to use vectored mode.
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VECTOR MODE=Direct --> all traps into machine mode cause the pc to be set to the
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vector base address (BASE) in the mtvec register.
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VECTOR MODE=Vectored --> all synchronous exceptions into machine mode cause the
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pc to be set to the BASE, whereas interrupts cause the pc to be set to the
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address BASE plus four times the interrupt cause number.
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*/
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#define mainVECTOR_MODE_DIRECT 0
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/* Index to first HART (there is only one). */
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#define mainHART_0 0
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@ -70,6 +81,9 @@ or 0 to run the more comprehensive test and demo application. */
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/*-----------------------------------------------------------*/
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extern void freertos_risc_v_trap_handler( void );
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extern void freertos_vector_table( void );
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/*
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* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
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* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
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@ -118,7 +132,6 @@ int main( void )
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#endif
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}
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/*-----------------------------------------------------------*/
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static void prvSetupHardware( void )
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{
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struct metal_cpu *pxCPU;
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@ -137,6 +150,16 @@ struct metal_interrupt *pxInterruptController;
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configASSERT( pxInterruptController );
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metal_interrupt_init( pxInterruptController );
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#if( mainVECTOR_MODE_DIRECT == 1 )
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{
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__asm__ volatile( "csrw mtvec, %0" :: "r"( freertos_risc_v_trap_handler ) );
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}
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#else
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{
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__asm__ volatile( "csrw mtvec, %0" :: "r"( ( uintptr_t )freertos_vector_table | 0x1 ) );
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}
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#endif
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/* Set all interrupt enable bits to 0. */
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mainPLIC_ENABLE_0 = 0UL;
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mainPLIC_ENABLE_1 = 0UL;
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@ -248,6 +271,22 @@ volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL, ulPLICPending0Register = 0UL, ul
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}
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/*-----------------------------------------------------------*/
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void freertos_risc_v_application_interrupt_handler( uint32_t ulMcause )
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{
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( void )ulMcause;
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handle_trap();
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}
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/*-----------------------------------------------------------*/
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void freertos_risc_v_application_exception_handler( uint32_t ulMcause )
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{
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( void )ulMcause;
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handle_trap();
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}
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/*-----------------------------------------------------------*/
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void vToggleLED( void )
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{
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metal_led_toggle( pxBlueLED );
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@ -0,0 +1,98 @@
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/*
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* FreeRTOS V202112.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.extern freertos_risc_v_exception_handler
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.extern freertos_risc_v_interrupt_handler
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.extern freertos_risc_v_mtimer_interrupt_handler
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.balign 128, 0
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.option norvc
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.global freertos_vector_table
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freertos_vector_table:
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IRQ_0:
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j freertos_risc_v_exception_handler
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IRQ_1:
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j freertos_risc_v_interrupt_handler
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IRQ_2:
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j freertos_risc_v_interrupt_handler
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IRQ_3:
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j freertos_risc_v_interrupt_handler
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IRQ_4:
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j freertos_risc_v_interrupt_handler
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IRQ_5:
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j freertos_risc_v_interrupt_handler
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IRQ_6:
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j freertos_risc_v_interrupt_handler
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IRQ_7:
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j freertos_risc_v_mtimer_interrupt_handler
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IRQ_8:
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j freertos_risc_v_interrupt_handler
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IRQ_9:
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j freertos_risc_v_interrupt_handler
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IRQ_10:
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j freertos_risc_v_interrupt_handler
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IRQ_11:
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j freertos_risc_v_interrupt_handler
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IRQ_12:
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j freertos_risc_v_interrupt_handler
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IRQ_13:
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j freertos_risc_v_interrupt_handler
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IRQ_14:
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j freertos_risc_v_interrupt_handler
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IRQ_15:
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j freertos_risc_v_interrupt_handler
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IRQ_LC0:
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j freertos_risc_v_interrupt_handler
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IRQ_LC1:
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j freertos_risc_v_interrupt_handler
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IRQ_LC2:
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j freertos_risc_v_interrupt_handler
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IRQ_LC3:
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j freertos_risc_v_interrupt_handler
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IRQ_LC4:
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j freertos_risc_v_interrupt_handler
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IRQ_LC5:
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j freertos_risc_v_interrupt_handler
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IRQ_LC6:
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j freertos_risc_v_interrupt_handler
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IRQ_LC7:
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j freertos_risc_v_interrupt_handler
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IRQ_LC8:
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j freertos_risc_v_interrupt_handler
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IRQ_LC9:
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j freertos_risc_v_interrupt_handler
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IRQ_LC10:
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j freertos_risc_v_interrupt_handler
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IRQ_LC11:
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j freertos_risc_v_interrupt_handler
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IRQ_LC12:
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j freertos_risc_v_interrupt_handler
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IRQ_LC13:
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j freertos_risc_v_interrupt_handler
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IRQ_LC14:
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j freertos_risc_v_interrupt_handler
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IRQ_LC15:
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j freertos_risc_v_interrupt_handler
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