mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-05-09 06:39:03 -04:00
Carry on working on the Cortex-A/GCC port layer - still a work in progress.
This commit is contained in:
Richard Barry
parent
33351b02c9
commit
3e430b3801
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@ -110,6 +110,10 @@
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#endif
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#ifndef configINSTALL_FREERTOS_VECTOR_TABLE
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#warning configINSTALL_FREERTOS_VECTOR_TABLE was undefined. Defaulting configINSTALL_FREERTOS_VECTOR_TABLE to 0.
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#endif
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/* A critical section is exited when the critical section nesting count reaches
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this value. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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@ -126,7 +130,8 @@ context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#warning FIQ is disabled
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#define portINITIAL_SPSR ( ( StackType_t ) 0x5f ) /* System mode, ARM mode, IRQ enabled FIQ disabled. 1f is required to enable FIQ. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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#define portTHUMB_MODE_ADDRESS ( 0x01UL )
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@ -146,12 +151,20 @@ mode. */
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#define portCLEAR_INTERRUPT_MASK() \
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{ \
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__asm volatile ( "cpsid i" ); \
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__asm volatile ( "dsb" ); \
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__asm volatile ( "isb" ); \
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portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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__asm( "DSB \n" \
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"ISB \n" ); \
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__asm volatile( "cpsie i" ); \
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__asm volatile ( "dsb" ); \
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__asm volatile ( "isb" ); \
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}
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#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portBIT_0_SET ( ( uint8_t ) 0x01 )
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/*-----------------------------------------------------------*/
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/*
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@ -182,6 +195,8 @@ uint32_t ulPortInterruptNesting = 0UL;
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__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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@ -264,12 +279,54 @@ BaseType_t xPortStartScheduler( void )
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{
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uint32_t ulAPSR;
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#if( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine how many priority bits are implemented in the GIC.
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Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to
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all possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Shift to the least significant bits. */
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while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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{
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ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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}
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/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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value. */
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configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
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/* Restore the clobbered interrupt priority register to its original
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value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* conifgASSERT_DEFINED */
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/* Only continue if the CPU is not in User mode. The CPU must be in a
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Privileged mode for the scheduler to start. */
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__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
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ulAPSR &= portAPSR_MODE_BITS_MASK;
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configASSERT( ulAPSR != portAPSR_USER_MODE );
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#if configINSTALL_FREERTOS_VECTOR_TABLE == 1
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{
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vPortInstallFreeRTOSVectorTable();
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}
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#endif
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if( ulAPSR != portAPSR_USER_MODE )
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{
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/* Only continue if the binary point value is set to its lowest possible
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@ -282,7 +339,7 @@ uint32_t ulAPSR;
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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__asm volatile( "cpsie i" );
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// __asm volatile( "cpsie i" );
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vPortRestoreTaskContext();
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}
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}
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@ -340,10 +397,14 @@ void FreeRTOS_Tick_Handler( void )
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handler runs at the lowest priority, so interrupts cannot already be masked,
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so there is no need to save and restore the current mask value. */
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__asm volatile( "cpsid i" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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__asm( "dsb \n"
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"isb \n"
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"cpsie i ");
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"cpsie i \n"
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"dsb \n"
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"isb" );
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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@ -383,6 +444,8 @@ uint32_t ulPortSetInterruptMask( void )
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uint32_t ulReturn;
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__asm volatile ( "cpsid i" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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if( portICCPMR_PRIORITY_MASK_REGISTER == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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{
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/* Interrupts were already masked. */
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@ -396,6 +459,8 @@ uint32_t ulReturn;
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"isb \n" );
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}
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__asm volatile ( "cpsie i" );
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__asm volatile ( "dsb" );
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__asm volatile ( "isb" );
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return ulReturn;
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}
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@ -441,13 +506,3 @@ uint32_t ulReturn;
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#endif /* configASSERT_DEFINED */
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/*-----------------------------------------------------------*/
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void vPortRestoreTaskContext( void )
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{
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}
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void vPortRestoreContext( void )
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{
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}
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/*-----------------------------------------------------------*/
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@ -53,40 +53,124 @@
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*/
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.org 0
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.text
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.set SYS_MODE, 0x1f
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.set SVC_MODE, 0x13
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.set IRQ_MODE, 0x12
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.extern _boot
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.extern vTaskSwitchContext
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.extern ulICCIAR
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.extern ulICCEOIR
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.extern ulMaxAPIPriorityMask
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.extern ulICCPMR
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.extern _freertos_vector_table
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.global _vector_table
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.global FreeRTOS_vector_table
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.global FIQInterrupt
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.global Undefined
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.global PrefetchAbortHandler
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.global DataAbortInterrupt
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.extern pxCurrentTCB
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.extern XIntc_DeviceInterruptHandler
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.extern vTaskSwitchContext
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.extern uxCriticalNesting
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.extern pulISRStack
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.extern ulTaskSwitchRequested
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.extern vPortExceptionHandler
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.extern pulStackPointerOnFunctionEntry
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.global vPortInstallFreeRTOSVectorTable
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.macro portSAVE_CONTEXT
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/* Save the LR and SPSR onto the system mode stack before switching to
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system mode to save the remaining system mode registers. */
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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/* Push the critical nesting count. */
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LDR R2, =ulCriticalNesting
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LDR R1, [R2]
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PUSH {R1}
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/* Does the task have a floating point context that needs saving? If
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ulPortTaskHasFPUContext is 0 then no. */
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LDR R2, =ulPortTaskHasFPUContext
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LDR R3, [R2]
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CMP R3, #0
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/* Save the floating point context, if any. */
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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VPUSHNE {D16-D31}
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PUSHNE {R1}
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/* Save ulPortTaskHasFPUContext itself. */
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PUSH {R3}
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/* Save the stack pointer in the TCB. */
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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STR SP, [R1]
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.endm
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; /**********************************************************************/
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.macro portRESTORE_CONTEXT
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/* Switch to system mode. */
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CPS #SYS_MODE
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/* Set the SP to point to the stack of the task being restored. */
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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LDR SP, [R1]
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/* Is there a floating point context to restore? If the restored
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ulPortTaskHasFPUContext is zero then no. */
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LDR R0, =ulPortTaskHasFPUContext
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POP {R1}
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STR R1, [R0]
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CMP R1, #0
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/* Restore the floating point context, if any. */
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POPNE {R0}
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VPOPNE {D16-D31}
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VPOPNE {D0-D15}
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VMSRNE FPSCR, R0
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/* Restore the critical section nesting depth. */
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LDR R0, =ulCriticalNesting
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POP {R1}
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STR R1, [R0]
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/* Ensure the priority mask is correct for the critical nesting depth. */
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LDR R2, =ulICCPMR
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CMP R1, #0
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MOVEQ R4, #255
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LDRNE R4, =ulMaxAPIPriorityMask
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STR R4, [r2]
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/* Restore all system mode registers other than the SP (which is already
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being used). */
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POP {R0-R12, R14}
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/* Return to the task code, loading CPSR on the way. */
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RFEIA sp!
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.endm
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.section .vectors
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_vector_table:
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B _boot
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B Undefined
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ldr pc, _swi
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B PrefetchAbortHandler
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B DataAbortHandler
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NOP /* Placeholder for address exception vector*/
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LDR PC, _irq
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B FIQHandler
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_irq: .word FreeRTOS_IRQ_Handler
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_swi: .word FreeRTOS_SWI_Handler
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/******************************************************************************
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* SVC handler is used to start the scheduler and yield a task.
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@ -94,12 +178,42 @@ _swi: .word FreeRTOS_SWI_Handler
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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// portSAVE_CONTEXT
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/* Save the LR and SPSR onto the system mode stack before switching to
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system mode to save the remaining system mode registers. */
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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/* Push the critical nesting count. */
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LDR R2, =ulCriticalNesting
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LDR R1, [R2]
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PUSH {R1}
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/* Does the task have a floating point context that needs saving? If
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ulPortTaskHasFPUContext is 0 then no. */
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LDR R2, =ulPortTaskHasFPUContext
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LDR R3, [R2]
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CMP R3, #0
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/* Save the floating point context, if any. */
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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VPUSHNE {D16-D31}
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PUSHNE {R1}
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/* Save ulPortTaskHasFPUContext itself. */
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PUSH {R3}
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/* Save the stack pointer in the TCB. */
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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STR SP, [R1]
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LDR R0, =vTaskSwitchContext
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BLX R0
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vPortRestoreTaskContext:
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// portRESTORE_CONTEXT
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portRESTORE_CONTEXT
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FreeRTOS_IRQ_Handler:
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/* Return to the interrupted instruction. */
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@ -185,7 +299,7 @@ switch_before_exit:
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POP {LR}
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MSR SPSR_cxsf, LR
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POP {LR}
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// portSAVE_CONTEXT
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portSAVE_CONTEXT
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/* Call the function that selects the new task to execute.
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vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
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@ -195,23 +309,19 @@ switch_before_exit:
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/* Restore the context of, and branch to, the task selected to execute
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next. */
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// portRESTORE_CONTEXT
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portRESTORE_CONTEXT
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ulICCIARConst: .word ulICCIAR
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ulICCEOIRConst: .word ulICCEOIR
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vPortInstallFreeRTOSVectorTable:
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/* Set VBAR to the vector table that contains the FreeRTOS handlers. */
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ldr r0, =_freertos_vector_table
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mcr p15, 0, r0, c12, c0, 0
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dsb
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isb
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bx lr
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Undefined:
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B .
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PrefetchAbortHandler:
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B .
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FIQHandler:
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B .
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DataAbortHandler:
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B .
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.end
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|
|
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@ -1,145 +0,0 @@
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;/*
|
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; FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
|
||||
; All rights reserved
|
||||
;
|
||||
;
|
||||
; ***************************************************************************
|
||||
; * *
|
||||
; * FreeRTOS tutorial books are available in pdf and paperback. *
|
||||
; * Complete, revised, and edited pdf reference manuals are also *
|
||||
; * available. *
|
||||
; * *
|
||||
; * Purchasing FreeRTOS documentation will not only help you, by *
|
||||
; * ensuring you get running as quickly as possible and with an *
|
||||
; * in-depth knowledge of how to use FreeRTOS, it will also help *
|
||||
; * the FreeRTOS project to continue with its mission of providing *
|
||||
; * professional grade, cross platform, de facto standard solutions *
|
||||
; * for microcontrollers - completely free of charge! *
|
||||
; * *
|
||||
; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
|
||||
; * *
|
||||
; * Thank you for using FreeRTOS, and thank you for your support! *
|
||||
; * *
|
||||
; ***************************************************************************
|
||||
;
|
||||
;
|
||||
; This file is part of the FreeRTOS distribution.
|
||||
;
|
||||
; FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License (version 2) as published by the
|
||||
; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
||||
; >>>NOTE<<< The modification to the GPL is included to allow you to
|
||||
; distribute a combined work that includes FreeRTOS without being obliged to
|
||||
; provide the source code for proprietary components outside of the FreeRTOS
|
||||
; kernel. FreeRTOS is distributed in the hope that it will be useful, but
|
||||
; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
; more details. You should have received a copy of the GNU General Public
|
||||
; License and the FreeRTOS license exception along with FreeRTOS; if not it
|
||||
; can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
||||
; by writing to Richard Barry, contact details for whom are available on the
|
||||
; FreeRTOS WEB site.
|
||||
;
|
||||
; 1 tab == 4 spaces!
|
||||
;
|
||||
; http://www.FreeRTOS.org - Documentation, latest information, license and
|
||||
; contact details.
|
||||
;
|
||||
; http://www.SafeRTOS.com - A version that is certified for use in safety
|
||||
; critical systems.
|
||||
;
|
||||
; http://www.OpenRTOS.com - Commercial support, development, porting,
|
||||
; licensing and training services.
|
||||
;*/
|
||||
|
||||
EXTERN vTaskSwitchContext
|
||||
EXTERN ulCriticalNesting
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||||
EXTERN pxCurrentTCB
|
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EXTERN ulPortTaskHasFPUContext
|
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EXTERN ulAsmAPIPriorityMask
|
||||
|
||||
portSAVE_CONTEXT macro
|
||||
|
||||
; Save the LR and SPSR onto the system mode stack before switching to
|
||||
; system mode to save the remaining system mode registers
|
||||
SRSDB sp!, #SYS_MODE
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||||
CPS #SYS_MODE
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||||
PUSH {R0-R12, R14}
|
||||
|
||||
; Push the critical nesting count
|
||||
LDR R2, =ulCriticalNesting
|
||||
LDR R1, [R2]
|
||||
PUSH {R1}
|
||||
|
||||
; Does the task have a floating point context that needs saving? If
|
||||
; ulPortTaskHasFPUContext is 0 then no.
|
||||
LDR R2, =ulPortTaskHasFPUContext
|
||||
LDR R3, [R2]
|
||||
CMP R3, #0
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||||
|
||||
; Save the floating point context, if any
|
||||
FMRXNE R1, FPSCR
|
||||
VPUSHNE {D0-D15}
|
||||
VPUSHNE {D16-D31}
|
||||
PUSHNE {R1}
|
||||
|
||||
; Save ulPortTaskHasFPUContext itself
|
||||
PUSH {R3}
|
||||
|
||||
; Save the stack pointer in the TCB
|
||||
LDR R0, =pxCurrentTCB
|
||||
LDR R1, [R0]
|
||||
STR SP, [R1]
|
||||
|
||||
endm
|
||||
|
||||
; /**********************************************************************/
|
||||
|
||||
portRESTORE_CONTEXT macro
|
||||
|
||||
; Switch to system mode
|
||||
CPS #SYS_MODE
|
||||
|
||||
; Set the SP to point to the stack of the task being restored.
|
||||
LDR R0, =pxCurrentTCB
|
||||
LDR R1, [R0]
|
||||
LDR SP, [R1]
|
||||
|
||||
; Is there a floating point context to restore? If the restored
|
||||
; ulPortTaskHasFPUContext is zero then no.
|
||||
LDR R0, =ulPortTaskHasFPUContext
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
CMP R1, #0
|
||||
|
||||
; Restore the floating point context, if any
|
||||
LDMFDNE SP!, {R0}
|
||||
VPOPNE {D16-D31}
|
||||
VPOPNE {D0-D15}
|
||||
VMSRNE FPSCR, R0
|
||||
|
||||
; Restore the critical section nesting depth
|
||||
LDR R0, =ulCriticalNesting
|
||||
POP {R1}
|
||||
STR R1, [R0]
|
||||
|
||||
; Ensure the priority mask is correct for the critical nesting depth
|
||||
LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
|
||||
CMP R1, #0
|
||||
MOVEQ R4, #255
|
||||
LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
|
||||
STR R4, [r2]
|
||||
|
||||
; Restore all system mode registers other than the SP (which is already
|
||||
; being used)
|
||||
POP {R0-R12, R14}
|
||||
|
||||
; Return to the task code, loading CPSR on the way.
|
||||
RFEIA sp!
|
||||
|
||||
endm
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in a new issue