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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-12 00:57:44 -04:00
merge #1 :: enable MMU and supervisor mode switch support
* Supervisor mode related code. * Update to fix type mismatch in debugging code. * Smode switch worked with command loop. * Wip, turn off debugging and not used code. * Delte debugging code and add compile flag for priviledge related functions. * delete debugging code * use smode scratch register for ecall index * delete unused code. * The first code worked with mmu and smode. * The code updates such that mmu and s-mode switching working. * Use compile flag to enable/disable MMU. Code clean up.
This commit is contained in:
Enya Cheng
GitHub
parent
021e86659d
commit
37f2fa5db7
4 changed files with 184 additions and 9 deletions
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@ -166,7 +166,11 @@ void vPortSetupTimerInterrupt(void)
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BaseType_t xPortStartScheduler(void)
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{
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extern void xPortStartFirstTask(void);
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#if( USE_PRIVILEDGE_MODE == 1 )
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{
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vRaisePriviledge();
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}
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#endif
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#if (configASSERT_DEFINED == 1)
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{
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volatile uint32_t mtvec = 0;
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@ -100,9 +100,16 @@ specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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at the top of this file. */
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#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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#ifdef DISABLE_PRIVILEDGE_MODE
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#define USE_PRIVILEDGE_MODE 0
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#else
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#define USE_PRIVILEDGE_MODE 1
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#endif
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.global xPortStartFirstTask
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.global freertos_risc_v_trap_handler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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@ -114,11 +121,103 @@ at the top of this file. */
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.extern xISRStackTop
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.extern portasmHANDLE_INTERRUPT
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#if 0
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.extern int_record //the variable used for debugging utility
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#endif
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#if( USE_PRIVILEDGE_MODE != 0 )
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.extern priviledge_status
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#endif
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/*-----------------------------------------------------------*/
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.align 8
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.func
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freertos_risc_v_trap_handler:
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#if( USE_PRIVILEDGE_MODE != 0 )
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//csrw mscratch, t0
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csrr t0, mcause
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blt t0, x0, handle_other_traps
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addi t0, t0, -8
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blt t0, x0, is_exception /* mcause < 8, not ecall */
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addi t0, t0, -3
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bgt t0, x0, is_exception
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environment_switch:
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csrr t5, sscratch
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csrw mscratch, t5
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csrwi sscratch, 1
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beq t5, x0, handle_other_traps
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la t0, 1f
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slli t5, t5, 2
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add t0, t0, t5
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jr t0
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1:
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jal x0, ecall_yield
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jal x0, ecall_disable_interrupt
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jal x0, ecall_enable_interrupt
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jal x0, ecall_switch_to_machine
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jal x0, ecall_switch_to_supervisor
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ecall_disable_interrupt:
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/* Clear mpie */
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li t6, 0x880
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csrc mie, t6
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j ecall_mret
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ecall_enable_interrupt:
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/* Set mpie */
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li t6, 0x880
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csrs mie, t6
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j ecall_mret
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ecall_switch_to_machine:
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/* Set mpp */
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li t6, 0x1800
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csrs mstatus, t6
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j ecall_mret
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ecall_switch_to_supervisor:
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/* Clear mpp */
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li t6, 0x1800
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csrc mstatus, t6
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li t6, 0x800
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csrs mstatus, t6
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j ecall_mret
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ecall_mret:
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csrr t0, mstatus
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li t6, 0x1800
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and t0, t0, t6
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srli t0, t0, 11
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//for debug
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#if 0
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csrr t1, mie
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la t6, int_record
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sw t1, 0(t6)
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add t0, t0, t1
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slli t0, t0, 4
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csrr t1, mscratch
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add t0, t0, t1
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#endif
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la t6, priviledge_status
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sw t0, 0(t6)
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csrr t0, mepc
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addi t0, t0, 4
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csrw mepc, t0
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/* restore t0 */
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//csrr t0, mscratch
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mret
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ecall_yield:
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handle_other_traps:
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#endif
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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@ -149,8 +248,10 @@ freertos_risc_v_trap_handler:
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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#if ( USE_PRIVILEDGE_MODE == 0 )
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, 29 * portWORD_SIZE( sp )
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#endif
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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@ -172,11 +273,9 @@ handle_asynchronous:
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test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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addi t0, x0, 1
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slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
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addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
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bne a0, t1, test_if_external_interrupt
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load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
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@ -230,8 +329,16 @@ handle_synchronous:
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store_x a1, 0( sp ) /* Save updated exception return address. */
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test_if_environment_call:
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#if( USE_PRIVILEDGE_MODE == 0 )
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li t0, 11 /* 11 == environment call. */
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#else
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li t0, 9 /* 9 == environment call. */
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#endif
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beq a0, t0, next
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li t0, 11
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bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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next:
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load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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@ -257,8 +364,38 @@ processed_source:
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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#if ( USE_PRIVILEDGE_MODE == 0 )
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load_x t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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#endif
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#if( USE_PRIVILEDGE_MODE != 0 )
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li a0, 0x1000
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csrc mstatus, a0
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li a0, 0x800
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csrs mstatus, a0
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csrr t0, mstatus
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li a0, 0x1800
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and t0, t0, a0
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srli t0, t0, 11
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#if 0 //for debug
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csrr t1, mie
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la t6, int_record
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sw t1, 0(t6)
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add t0, t0, t1
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slli t0, t0, 4
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csrr t1, mscratch
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add t0, t0, t1
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#endif
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la t6, priviledge_status
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sw t0, 0(t6)
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li t0, 0x880
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csrw mie, t0
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#endif
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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@ -312,10 +449,15 @@ xPortStartFirstTask:
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load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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#if ( USE_PRIVILEDGE_MODE == 0 )
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load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */
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addi t0, t0, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
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#endif
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#if( USE_PRIVILEDGE_MODE != 0 )
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csrwi sscratch, 4
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#endif
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load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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@ -345,6 +487,11 @@ xPortStartFirstTask:
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load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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#if( USE_PRIVILEDGE_MODE != 0 )
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ecall
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#endif
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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@ -416,7 +563,11 @@ xPortStartFirstTask:
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pxPortInitialiseStack:
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csrr t0, mstatus /* Obtain current mstatus value. */
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#if ( USE_PRIVILEDGE_MODE == 0 )
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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#else
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addi t1, x0, 0x180
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#endif
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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@ -436,6 +587,7 @@ chip_specific_stack_frame: /* First add any chip specific registers to the st
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1:
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addi a0, a0, -portWORD_SIZE
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store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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@ -29,6 +29,8 @@
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#include "../../../../../src/scpu/hal/drivers/recogni_priviledge.h"
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#ifdef __cplusplus
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extern "C"
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{
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@ -90,7 +92,12 @@ not need to be guarded with a critical section. */
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/* Scheduler utilities. */
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extern void vTaskSwitchContext(void);
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#if( USE_PRIVILEDGE_MODE != 1 )
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#define portYIELD() __asm volatile( "ecall" );
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#else
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#define portYIELD() vPortSyscall()
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#endif
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#define portEND_SWITCHING_ISR(xSwitchRequired) \
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if (xSwitchRequired) vTaskSwitchContext()
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#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
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@ -104,8 +111,14 @@ not need to be guarded with a critical section. */
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) \
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(void)uxSavedStatusValue
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#if( USE_PRIVILEDGE_MODE != 1 )
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#define portDISABLE_INTERRUPTS() __asm volatile("csrc mstatus, 8")
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#define portENABLE_INTERRUPTS() __asm volatile("csrs mstatus, 8")
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#else
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#define portDISABLE_INTERRUPTS() vDisableInterrupt()
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#define portENABLE_INTERRUPTS() vEnableInterrupt()
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#endif
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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14
tasks.c
14
tasks.c
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@ -1013,6 +1013,11 @@ UBaseType_t x;
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but had been interrupted by the scheduler. The return address is set
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to the start of the task function. Once the stack has been initialised
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the top of stack variable is updated. */
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#if( USE_PRIVILEDGE_MODE == 1 )
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{
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vRaisePriviledge();
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}
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#endif
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#if( portUSING_MPU_WRAPPERS == 1 )
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{
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/* If the port has capability to detect stack overflow,
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@ -1061,6 +1066,11 @@ UBaseType_t x;
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}
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#endif /* portUSING_MPU_WRAPPERS */
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#if( USE_PRIVILEDGE_MODE == 1 )
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{
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vResetPriviledge();
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}
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#endif
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if( pxCreatedTask != NULL )
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{
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/* Pass the handle out in an anonymous way. The handle can be used to
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@ -1156,7 +1166,6 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
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}
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}
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/*-----------------------------------------------------------*/
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#if ( INCLUDE_vTaskDelete == 1 )
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void vTaskDelete( TaskHandle_t xTaskToDelete )
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@ -1251,7 +1260,6 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
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#endif /* INCLUDE_vTaskDelete */
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/*-----------------------------------------------------------*/
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#if ( INCLUDE_vTaskDelayUntil == 1 )
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void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
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@ -1947,7 +1955,6 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
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{
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mtCOVERAGE_TEST_MARKER();
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}
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( void ) uxListRemove( &( pxTCB->xStateListItem ) );
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prvAddTaskToReadyList( pxTCB );
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}
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@ -3134,7 +3141,6 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xIte
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#endif /* configUSE_TIMERS */
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/*-----------------------------------------------------------*/
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BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
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{
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TCB_t *pxUnblockedTCB;
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