len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-09-12 09:07:46 -04:00
Code Issues Projects Releases Packages Wiki Activity

Support RV32E - RISC-V architecture (GCC)

Browse source 
Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>
This commit is contained in:
Emmanuel Puerto 2020-08-26 09:26:35 +02:00
parent d0d2442f14
commit 37aaa0abbc
2 changed files with 442 additions and 263 deletions
Download patch file Download diff file Expand all files Collapse all files

23
portable/GCC/RISC-V/port.c
View file

@ -25,9 +25,11 @@
* 1 tab == 4 spaces! * 1 tab == 4 spaces!
*/ */
/*----------------------------------------------------------- /* ------------------------------------------------------------------
* Implementation of functions defined in portable.h for the RISC-V RV32 port. * This file is part of the FreeRTOS distribution and was contributed
*----------------------------------------------------------*/ * to the project by SiFive
* ------------------------------------------------------------------
*/
/* Scheduler includes. */ /* Scheduler includes. */
#include "FreeRTOS.h" #include "FreeRTOS.h"
@ -215,20 +217,7 @@ extern void xPortStartFirstTask( void );
configure whichever clock is to be used to generate the tick interrupt. */ configure whichever clock is to be used to generate the tick interrupt. */
vPortSetupTimerInterrupt(); vPortSetupTimerInterrupt();
#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) /* Enabling mtime and external interrupts will be made into xPortStartFirstTask function */
{
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
for external interrupt. _RB_ What happens here when mtime is not present as
with pulpino? */
__asm volatile( "csrs mie, %0" :: "r"(0x880) );
}
#else
{
/* Enable external interrupts. */
__asm volatile( "csrs mie, %0" :: "r"(0x800) );
}
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
xPortStartFirstTask(); xPortStartFirstTask();
/* Should not get here as after calling xPortStartFirstTask() only tasks /* Should not get here as after calling xPortStartFirstTask() only tasks

636
portable/GCC/RISC-V/portASM.S
View file

@ -55,17 +55,35 @@
* registers. * registers.
* *
*/ */
#if __riscv_xlen == 64
#define portWORD_SIZE 8 /* ------------------------------------------------------------------
* This file is part of the FreeRTOS distribution and was contributed
* to the project by SiFive
* ------------------------------------------------------------------
*/
#if( __riscv_xlen == 64 )
#define store_x sd #define store_x sd
#define load_x ld #define load_x ld
#elif __riscv_xlen == 32 #elif( __riscv_xlen == 32 )
#define store_x sw #define store_x sw
#define load_x lw #define load_x lw
#define portWORD_SIZE 4
#else #else
#error Assembler did not define __riscv_xlen #error Assembler did not define __riscv_xlen
#endif #endif /* ( __riscv_xlen == xx ) */
/* Nb registers to save */
#ifdef __riscv_32e
#define portasmNB_REGS_SAVED (16)
#else
#define portasmNB_REGS_SAVED (32)
#endif /* __riscv_32e */
#define portWORD_SIZE (__riscv_xlen / 8)
/* Number of FPU register */
/* FPU is not yet supported so PORT_FPU_REGISTER = 0 */
#define portasmFPU_CONTEXT_SIZE 0
#include "freertos_risc_v_chip_specific_extensions.h" #include "freertos_risc_v_chip_specific_extensions.h"
@ -85,20 +103,45 @@ definitions. */
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif #endif
#ifndef portasmHANDLE_INTERRUPT #ifndef portHANDLE_INTERRUPT
#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html #error portHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.
#endif
#ifndef portHANDLE_EXCEPTION
#error portHANDLE_EXCEPTION must be defined to the function to be called to handle execptions.
#endif #endif
#ifndef portasmHAS_SIFIVE_CLINT #ifndef portasmHAS_SIFIVE_CLINT
#define portasmHAS_SIFIVE_CLINT 0 #define portasmHAS_SIFIVE_CLINT 0
#endif #endif
/* Only the standard core registers are stored by default. Any additional /*
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and * To maintain RISCV ABI stack alignment requirements (16bytes)
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip * this data structure must be a MULTIPLE of 16 bytes in size.
specific version of freertos_risc_v_chip_specific_extensions.h. See the notes * 32 Registers (for standard core) is 16byte aligned :)
at the top of this file. */ * We add space to save additional information so it must be multiple of 4.
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE ) * mepc 33th register
* mstatus 34th register
* ruf 35th register
* ruf 36th register
*/
#define PORT_CONTEXT_mepcIDX (portasmNB_REGS_SAVED)
#define PORT_CONTEXT_mstatusIDX (portasmNB_REGS_SAVED + 1)
#define portasmLAST_BASE_REGS (portasmNB_REGS_SAVED + 4)
#define PORT_CONTEXT_lastIDX ((portasmNB_REGS_SAVED) + portasmADDITIONAL_CONTEXT_SIZE)
/* used in assembler, as byte offsets from the start of the context */
#define PORT_CONTEXT_xIDX(X) (X) /* index into "raw" for register x? */
#define PORT_CONTEXT_xOFFSET(X) (PORT_CONTEXT_xIDX(X) * portWORD_SIZE)
#define PORT_CONTEXT_mepcOFFSET (PORT_CONTEXT_mepcIDX * portWORD_SIZE)
#define PORT_CONTEXT_mstatusOFFSET (PORT_CONTEXT_mstatusIDX * portWORD_SIZE)
#define PORT_CONTEXT_rufOFFSET (PORT_CONTEXT_rufIDX * portWORD_SIZE)
/* total size of the structure usable in ASM. */
#define portasmREGISTER_CONTEXT_WORDSIZE ((portasmLAST_BASE_REGS) * (portWORD_SIZE))
#define portasmADDITIONAL_CONTEXT_WORDSIZE ((portasmADDITIONAL_CONTEXT_SIZE) * (portWORD_SIZE))
.global xPortStartFirstTask .global xPortStartFirstTask
.global freertos_risc_v_trap_handler .global freertos_risc_v_trap_handler
@ -112,184 +155,289 @@ at the top of this file. */
.extern pullNextTime .extern pullNextTime
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */ .extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
.extern xISRStackTop .extern xISRStackTop
.extern portasmHANDLE_INTERRUPT .extern portHANDLE_INTERRUPT
.extern portHANDLE_EXCEPTION
/*-----------------------------------------------------------*/
.macro portSAVE_BaseReg
/* Make room for the registers. */
addi sp, sp, -portasmREGISTER_CONTEXT_WORDSIZE
store_x x1, PORT_CONTEXT_xOFFSET(1)(sp) /* x1(ra) Return address */
/* x2(sp) ***** Should be save ouside this macro */
store_x x3, PORT_CONTEXT_xOFFSET(3)(sp) /* x3(gp) Global pointer */
store_x x4, PORT_CONTEXT_xOFFSET(4)(sp) /* x4(tp) Thread pointer */
store_x x5, PORT_CONTEXT_xOFFSET(5)(sp) /* x5(t0) Temporary register */
store_x x6, PORT_CONTEXT_xOFFSET(6)(sp) /* x6(t1) Temporary register*/
store_x x7, PORT_CONTEXT_xOFFSET(7)(sp) /* x7(t2) Temporary register */
store_x x8, PORT_CONTEXT_xOFFSET(8)(sp) /* x8(s0/fp) Saved register/Frame pointer */
store_x x9, PORT_CONTEXT_xOFFSET(9)(sp) /* x9(s1) Saved register */
store_x x10, PORT_CONTEXT_xOFFSET(10)(sp) /* x10(a0) Function argument */
store_x x11, PORT_CONTEXT_xOFFSET(11)(sp) /* x11(a1) Function argument */
store_x x12, PORT_CONTEXT_xOFFSET(12)(sp) /* x12(a2) Function argument */
store_x x13, PORT_CONTEXT_xOFFSET(13)(sp) /* x13(a3) Function argument */
store_x x14, PORT_CONTEXT_xOFFSET(14)(sp) /* x14(a4) Function argument */
store_x x15, PORT_CONTEXT_xOFFSET(15)(sp) /* x15(a5) Function argument */
#ifndef __riscv_32e
store_x x16, PORT_CONTEXT_xOFFSET(16)(sp) /* x16(a6) Function arguments */
store_x x17, PORT_CONTEXT_xOFFSET(17)(sp) /* x17(a7) Function arguments */
store_x x18, PORT_CONTEXT_xOFFSET(18)(sp) /* x18(s2) Saved register */
store_x x19, PORT_CONTEXT_xOFFSET(19)(sp) /* x19(s3) Saved register */
store_x x20, PORT_CONTEXT_xOFFSET(20)(sp) /* x20(s4) Saved register */
store_x x21, PORT_CONTEXT_xOFFSET(21)(sp) /* x21(s5) Saved register */
store_x x22, PORT_CONTEXT_xOFFSET(22)(sp) /* x22(s6) Saved register */
store_x x23, PORT_CONTEXT_xOFFSET(23)(sp) /* x23(s7) Saved register */
store_x x24, PORT_CONTEXT_xOFFSET(24)(sp) /* x24(s8) Saved register */
store_x x25, PORT_CONTEXT_xOFFSET(25)(sp) /* x25(s9) Saved register */
store_x x26, PORT_CONTEXT_xOFFSET(26)(sp) /* x26(s10) Saved register */
store_x x27, PORT_CONTEXT_xOFFSET(27)(sp) /* x27(s11) Saved register */
store_x x28, PORT_CONTEXT_xOFFSET(28)(sp) /* x28(t3) Temporary register */
store_x x29, PORT_CONTEXT_xOFFSET(29)(sp) /* x29(t4) Temporary register */
store_x x30, PORT_CONTEXT_xOFFSET(30)(sp) /* x30(t5) Temporary register */
store_x x31, PORT_CONTEXT_xOFFSET(31)(sp) /* x31(t6) Temporary register */
#endif /* __riscv_32e */
/* Save mcause, mepc & mstatus state */
csrr a4, mepc
csrr a5, mstatus /* Required for MPIE bit. */
store_x a4, PORT_CONTEXT_mepcOFFSET(sp)
store_x a5, PORT_CONTEXT_mstatusOFFSET(sp)
.endm
/*-----------------------------------------------------------*/
.macro portRESTORE_BaseReg
/* Restore mepc & mstatus state */
load_x t0, PORT_CONTEXT_mepcOFFSET(sp)
load_x t1, PORT_CONTEXT_mstatusOFFSET(sp)
csrw mepc, t0
csrw mstatus, t1
load_x x1, PORT_CONTEXT_xOFFSET(1)(sp) /* x1(ra) Return address */
/* x2(sp) ***** Should be save ouside this macro */
load_x x3, PORT_CONTEXT_xOFFSET(3)(sp) /* x3(gp) Global pointer */
load_x x4, PORT_CONTEXT_xOFFSET(4)(sp) /* x4(tp) Thread pointer */
load_x x5, PORT_CONTEXT_xOFFSET(5)(sp) /* x5(t0) Temporary register */
load_x x6, PORT_CONTEXT_xOFFSET(6)(sp) /* x6(t1) Temporary register*/
load_x x7, PORT_CONTEXT_xOFFSET(7)(sp) /* x7(t2) Temporary register */
load_x x8, PORT_CONTEXT_xOFFSET(8)(sp) /* x8(s0/fp) Saved register/Frame pointer */
load_x x9, PORT_CONTEXT_xOFFSET(9)(sp) /* x9(s1) Saved register */
load_x x10, PORT_CONTEXT_xOFFSET(10)(sp) /* x10(a0) Function argument */
load_x x11, PORT_CONTEXT_xOFFSET(11)(sp) /* x11(a1) Function argument */
load_x x12, PORT_CONTEXT_xOFFSET(12)(sp) /* x12(a2) Function argument */
load_x x13, PORT_CONTEXT_xOFFSET(13)(sp) /* x13(a3) Function argument */
load_x x14, PORT_CONTEXT_xOFFSET(14)(sp) /* x14(a4) Function argument */
load_x x15, PORT_CONTEXT_xOFFSET(15)(sp) /* x15(a5) Function argument */
#ifndef __riscv_32e
load_x x16, PORT_CONTEXT_xOFFSET(16)(sp) /* x16(a6) Function arguments */
load_x x17, PORT_CONTEXT_xOFFSET(17)(sp) /* x17(a7) Function arguments */
load_x x18, PORT_CONTEXT_xOFFSET(18)(sp) /* x18(s2) Saved register */
load_x x19, PORT_CONTEXT_xOFFSET(19)(sp) /* x19(s3) Saved register */
load_x x20, PORT_CONTEXT_xOFFSET(20)(sp) /* x20(s4) Saved register */
load_x x21, PORT_CONTEXT_xOFFSET(21)(sp) /* x21(s5) Saved register */
load_x x22, PORT_CONTEXT_xOFFSET(22)(sp) /* x22(s6) Saved register */
load_x x23, PORT_CONTEXT_xOFFSET(23)(sp) /* x23(s7) Saved register */
load_x x24, PORT_CONTEXT_xOFFSET(24)(sp) /* x24(s8) Saved register */
load_x x25, PORT_CONTEXT_xOFFSET(25)(sp) /* x25(s9) Saved register */
load_x x26, PORT_CONTEXT_xOFFSET(26)(sp) /* x26(s10) Saved register */
load_x x27, PORT_CONTEXT_xOFFSET(27)(sp) /* x27(s11) Saved register */
load_x x28, PORT_CONTEXT_xOFFSET(28)(sp) /* x28(t3) Temporary register */
load_x x29, PORT_CONTEXT_xOFFSET(29)(sp) /* x29(t4) Temporary register */
load_x x30, PORT_CONTEXT_xOFFSET(30)(sp) /* x30(t5) Temporary register */
load_x x31, PORT_CONTEXT_xOFFSET(31)(sp) /* x31(t6) Temporary register */
#endif /* __riscv_32e */
.endm
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
.align 8 .align 8
.func .func
freertos_risc_v_trap_handler: freertos_risc_v_trap_handler:
addi sp, sp, -portCONTEXT_SIZE /* We do not know if this is an ASYNC or SYNC
store_x x1, 1 * portWORD_SIZE( sp ) * If ASYNC, it is a normal interrupt
store_x x5, 2 * portWORD_SIZE( sp ) * and the stack pointer is assumed good.
store_x x6, 3 * portWORD_SIZE( sp ) * else (SYNC)
store_x x7, 4 * portWORD_SIZE( sp ) * We could be here due to a bus fault.
store_x x8, 5 * portWORD_SIZE( sp ) */
store_x x9, 6 * portWORD_SIZE( sp ) csrw mscratch, t0
store_x x10, 7 * portWORD_SIZE( sp ) csrr t0, mcause
store_x x11, 8 * portWORD_SIZE( sp ) blt t0, x0, handle_interrupt
store_x x12, 9 * portWORD_SIZE( sp )
store_x x13, 10 * portWORD_SIZE( sp )
store_x x14, 11 * portWORD_SIZE( sp )
store_x x15, 12 * portWORD_SIZE( sp )
store_x x16, 13 * portWORD_SIZE( sp )
store_x x17, 14 * portWORD_SIZE( sp )
store_x x18, 15 * portWORD_SIZE( sp )
store_x x19, 16 * portWORD_SIZE( sp )
store_x x20, 17 * portWORD_SIZE( sp )
store_x x21, 18 * portWORD_SIZE( sp )
store_x x22, 19 * portWORD_SIZE( sp )
store_x x23, 20 * portWORD_SIZE( sp )
store_x x24, 21 * portWORD_SIZE( sp )
store_x x25, 22 * portWORD_SIZE( sp )
store_x x26, 23 * portWORD_SIZE( sp )
store_x x27, 24 * portWORD_SIZE( sp )
store_x x28, 25 * portWORD_SIZE( sp )
store_x x29, 26 * portWORD_SIZE( sp )
store_x x30, 27 * portWORD_SIZE( sp )
store_x x31, 28 * portWORD_SIZE( sp )
csrr t0, mstatus /* Required for MPIE bit. */ handle_exception:
store_x t0, 29 * portWORD_SIZE( sp ) /* mscratch = old t0
* t0 = mcause
* mcause = small number 0..16
* 0 Instruction address misaligned
* 1 Instruction access fault
* 2 Illegal instruction
* 3 Breakpoint
* 4 Load address misaligned
* 5 Load access fault
* 6 Store/AMO address misaligned
* 7 Store/AMO access fault
* 8 Environment call from U-mode
* 9 Environment call from S-mode
* 10 Reserved
* 11 Environment call from M-mode
* 12 Instruction page fault
* 13 Load page fault
* 14 Reserved
* 15 Store/AMO page fault
* ≥16 Reserved
*
* if( mcause between 8 and 11 ) we are good - ecall
* else: problem
*/
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ addi t0, t0, -8
blt t0, x0, is_exception /* mcause < 8, must be fault */
addi t0, t0, -4
blt t0, x0, ecall_yield
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ is_exception:
store_x sp, 0( t0 ) /* Write sp to first TCB member. */ /* restore t0 and save sp in mscratch. */
csrr t0, mscratch
csrw mscratch, sp
/* Switch to ISR stack before function call. */
load_x sp, xISRStackTop
portSAVE_BaseReg
csrrw t0, mscratch, t0
/* SP = X2, so save it */
store_x t0, PORT_CONTEXT_xOFFSET(2)(sp)
/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
portasmSAVE_ADDITIONAL_REGISTERS
/* Execption is treated by external function */
jal portHANDLE_EXCEPTION
/* in case that the go back from exception, restore registers */
portasmRESTORE_ADDITIONAL_REGISTERS
portRESTORE_BaseReg
load_x x2, PORT_CONTEXT_xOFFSET(2)(sp)
mret
csrr a0, mcause ecall_yield:
csrr a1, mepc portSAVE_BaseReg
/* a4 = mepc
* a5 = mstatus
* s0 will be use for pxCurrentTCB
* s1 will be use to save sp
*/
/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
addi t0, a4, 4
store_x t0, PORT_CONTEXT_mepcOFFSET(sp)
/* Store the value of sp when the interrupt occur */
addi t0, sp, portasmREGISTER_CONTEXT_WORDSIZE
store_x t0, PORT_CONTEXT_xOFFSET(2)(sp)
test_if_asynchronous: /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */ portasmSAVE_ADDITIONAL_REGISTERS
beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
handle_asynchronous: /* Load pxCurrentTCB and update first TCB member(pxTopOfStack) with sp. */
load_x s0, pxCurrentTCB
store_x sp, 0( s0 )
/* Save sp into s1 */
mv s1, sp
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
j switch_context
handle_interrupt:
portSAVE_BaseReg
/* a4 = mepc
* a5 = mstatus
* s0 will be use for pxCurrentTCB
* s1 will be use to save sp
*/
/* Store the value of sp when the interrupt occur */
addi t0, sp, portasmREGISTER_CONTEXT_WORDSIZE
store_x t0, PORT_CONTEXT_xOFFSET(2)(sp)
/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
portasmSAVE_ADDITIONAL_REGISTERS
/* Load pxCurrentTCB and update first TCB member(pxTopOfStack) with sp. */
load_x s0, pxCurrentTCB
store_x sp, 0( s0 )
/* Save sp into s1 */
mv s1, sp
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
#if( portasmHAS_MTIME != 0 ) #if( portasmHAS_MTIME != 0 )
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
addi t0, x0, 1 addi t0, x0, 1
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */ slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */ addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
bne a0, t1, test_if_external_interrupt csrr t2, mcause
bne t2, t1, test_if_external_interrupt
load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */ load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */ load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
#if( __riscv_xlen == 32 ) #if( __riscv_xlen == 32 )
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */ /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
li t4, -1 lw a0, 0(t1) /* Load the low word of ullNextTime into a0. */
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */ lw a1, 4(t1) /* Load the high word of ullNextTime into a1. */
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */ li t2, -1
sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */ sw t2, 4(t0) /* Store low word of ullNextTime into compare register. */
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ sw a0, 0(t0) /* Store low word of ullNextTime into compare register. */
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */ sw a1, 4(t0) /* Store high word of ullNextTime into compare register. */
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */ add a2, t0, a0 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */ sltu t2, a2, a0 /* See if the sum of low words overflowed (what about the zero case?). */
add t6, t3, t5 /* Add overflow to high word of ullNextTime. */ add a3, a1, t2 /* Add overflow to high word of ullNextTime. */
sw t4, 0(t1) /* Store new low word of ullNextTime. */ sw a2, 0(t1) /* Store new low word of ullNextTime. */
sw t6, 4(t1) /* Store new high word of ullNextTime. */ sw a3, 4(t1) /* Store new high word of ullNextTime. */
#endif /* ( __riscv_xlen == 32 ) */
#endif /* __riscv_xlen == 32 */
#if( __riscv_xlen == 64 ) #if( __riscv_xlen == 64 )
/* Update the 64-bit mtimer compare match value. */ /* Update the 64-bit mtimer compare match value. */
ld t2, 0(t1) /* Load ullNextTime into t2. */ ld a0, 0(t1) /* Load ullNextTime into a0. */
sd t2, 0(t0) /* Store ullNextTime into compare register. */ sd a0, 0(t0) /* Store ullNextTime into compare register. */
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */ add a2, t0, a0 /* Add ullNextTime to the timer increments for one tick. */
sd t4, 0(t1) /* Store ullNextTime. */ sd a2, 0(t1) /* Store ullNextTime. */
#endif /* ( __riscv_xlen == 64 ) */
#endif /* __riscv_xlen == 64 */
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
jal xTaskIncrementTick jal xTaskIncrementTick
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */ beqz a0, restore_before_exit /* Don't switch context if incrementing tick didn't unblock a task. */
jal vTaskSwitchContext j switch_context
j processed_source
restore_before_exit:
mv sp, s1
j end_trap_handler
test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */ test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */ addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */ csrr t2, mcause
bne t2, t1, unrecoverable_error /* Something as yet unhandled. */
j unrecoverable_error
#endif /* ( portasmHAS_MTIME != 0 ) */
#endif /* portasmHAS_MTIME */ external_interrupt:
/* Switch to ISR stack before function call. */
load_x sp, xISRStackTop
jal portHANDLE_INTERRUPT
mv sp, s1
j end_trap_handler
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */ unrecoverable_error:
jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
j processed_source
handle_synchronous:
addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
store_x a1, 0( sp ) /* Save updated exception return address. */
test_if_environment_call:
li t0, 11 /* 11 == environment call. */
bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
jal vTaskSwitchContext
j processed_source
is_exception:
csrr t0, mcause /* For viewing in the debugger only. */ csrr t0, mcause /* For viewing in the debugger only. */
csrr t1, mepc /* For viewing in the debugger only */ csrr t1, mepc /* For viewing in the debugger only. */
csrr t2, mstatus csrr t2, mstatus
j is_exception /* No other exceptions handled yet. */ wfi
j unrecoverable_error
as_yet_unhandled: switch_context:
csrr t0, mcause /* For viewing in the debugger only. */ jal vTaskSwitchContext
j as_yet_unhandled load_x s0, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( s0 ) /* Read sp from first TCB member. */
processed_source: end_trap_handler:
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ load_x s0, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( t1 ) /* Read sp from first TCB member. */ load_x t1, PORT_CONTEXT_xOFFSET(2)(sp)
store_x t1, 0( s0 ) /* Write sp saved value to first TCB member. */
/* Load mret with the address of the next instruction in the task to run next. */
load_x t0, 0( sp )
csrw mepc, t0
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
/* Load mstatus with the interrupt enable bits used by the task. */
load_x t0, 29 * portWORD_SIZE( sp )
csrw mstatus, t0 /* Required for MPIE bit. */
load_x x1, 1 * portWORD_SIZE( sp )
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
addi sp, sp, portCONTEXT_SIZE
/* restore registers */
portasmRESTORE_ADDITIONAL_REGISTERS
portRESTORE_BaseReg
load_x x2, PORT_CONTEXT_xOFFSET(2)(sp)
mret mret
.endfunc .endfunc
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -304,49 +452,31 @@ xPortStartFirstTask:
outside of this file. */ outside of this file. */
la t0, freertos_risc_v_trap_handler la t0, freertos_risc_v_trap_handler
csrw mtvec, t0 csrw mtvec, t0
#endif /* portasmHAS_CLILNT */ #endif /* ( portasmHAS_SIFIVE_CLINT != 0 ) */
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */ /** Set all register to the FirstTask context */
load_x sp, 0( sp ) /* Read sp from first TCB member. */ load_x t2, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( t2 ) /* Read sp from first TCB member. */
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ /* Restore first TCB member */
load_x t1, PORT_CONTEXT_xOFFSET(2)(sp)
store_x t1, 0( t2 ) /* Write sp saved value to first TCB member. */
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ /* enable interrupt */
#if( portasmHAS_MTIME != 0 )
li t0, 0x880
csrs mie, t0
#else
li t0, 0x800
csrs mie, t0
#endif /* ( portasmHAS_MTIME != 0 ) */
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */ portasmRESTORE_ADDITIONAL_REGISTERS
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ portRESTORE_BaseReg
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */ load_x ra, PORT_CONTEXT_mepcOFFSET(sp) /* Note for starting the scheduler the exception return address is used as the function return address. */
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ load_x x2, PORT_CONTEXT_xOFFSET(2)(sp)
csrrw x0, mstatus, x5 /* Interrupts enabled from here! */ mret
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
addi sp, sp, portCONTEXT_SIZE
ret
.endfunc .endfunc
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -360,7 +490,7 @@ xPortStartFirstTask:
* a1, and pvParameters in a2. The new top of stack is passed out in a0. * a1, and pvParameters in a2. The new top of stack is passed out in a0.
* *
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). * for the 'I' profile, X1 to X15 for the 'E' profile).
* *
* Register ABI Name Description Saver * Register ABI Name Description Saver
* x0 zero Hard-wired zero - * x0 zero Hard-wired zero -
@ -379,36 +509,44 @@ xPortStartFirstTask:
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame, * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
* where the global and thread pointers are currently assumed to be constant so * where the global and thread pointers are currently assumed to be constant so
* are not saved: * are not saved:
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame:
* *
* ruf (in order to be 16 bytes aligned)
* ruf (in order to be 16 bytes aligned)
* pxCode - mepc
* mstatus * mstatus
* x31 * x31 (Only for 'I' profile)
* x30 * x30 (Only for 'I' profile)
* x29 * x29 (Only for 'I' profile)
* x28 * x28 (Only for 'I' profile)
* x27 * x27 (Only for 'I' profile)
* x26 * x26 (Only for 'I' profile)
* x25 * x25 (Only for 'I' profile)
* x24 * x24 (Only for 'I' profile)
* x23 * x23 (Only for 'I' profile)
* x22 * x22 (Only for 'I' profile)
* x21 * x21 (Only for 'I' profile)
* x20 * x20 (Only for 'I' profile)
* x19 * x19 (Only for 'I' profile)
* x18 * x18 (Only for 'I' profile)
* x17 * x17 (Only for 'I' profile)
* x16 * x16 (Only for 'I' profile)
* x15 * x15
* x14 * x14
* x13 * x13
* x12 * x12
* x11 * x11
* pvParameters * pvParameters - x10 (a0)
* x9 * x9
* x8 * x8
* x7 * x7
* x6 * x6
* x5 * x5
* portTASK_RETURN_ADDRESS * x4 (tp)
* x3 (gp)
* x2 (sp)
* portTASK_RETURN_ADDRESS - x1 (ra)
* x0
* [chip specific registers go here] * [chip specific registers go here]
* pxCode * pxCode
*/ */
@ -416,28 +554,80 @@ xPortStartFirstTask:
.func .func
pxPortInitialiseStack: pxPortInitialiseStack:
csrr t0, mstatus /* Obtain current mstatus value. */ /* Obtain current mstatus value. */
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ csrr t0, mstatus
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
addi t1, x0, 0x188
slli t1, t1, 4 slli t1, t1, 4
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ /* reset previous value */
not t2, t1
and t0, t0, t2
/* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
addi t1, x0, 0x188
slli t1, t1, 4
/* Set MPIE and MPP bits in mstatus value. */
or t0, t0, t1
addi a0, a0, -portWORD_SIZE /* Make room for the registers. */
store_x t0, 0(a0) /* mstatus onto the stack. */ addi t2, a0, -portasmREGISTER_CONTEXT_WORDSIZE
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */ /* x1(ra) Return address */
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ store_x x0, PORT_CONTEXT_xOFFSET(1)(t2)
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */ /* x2(sp) ***** Should be save ouside this macro */
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */ store_x a0, PORT_CONTEXT_xOFFSET(2)(t2)
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ /* x3(gp) Global pointer */
store_x x3, PORT_CONTEXT_xOFFSET(3)(t2)
/* x4(tp) Thread pointer */
store_x x4, PORT_CONTEXT_xOFFSET(4)(t2)
/* x5-7(t0-2) Temporaries */
store_x x0, PORT_CONTEXT_xOFFSET(5)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(6)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(7)(t2)
/* x8(s0/fp) Saved register/Frame pointer */
store_x x0, PORT_CONTEXT_xOFFSET(8)(t2)
/* x9(s1) Saved register */
store_x x0, PORT_CONTEXT_xOFFSET(9)(t2)
/* x10-17(a0-7) Function arguments */
store_x a2, PORT_CONTEXT_xOFFSET(10)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(11)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(12)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(13)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(14)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(15)(t2)
#ifndef __riscv_32e
store_x x0, PORT_CONTEXT_xOFFSET(16)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(17)(t2)
/* x18-27(s2-11) Saved registers */
store_x x0, PORT_CONTEXT_xOFFSET(18)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(19)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(20)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(21)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(22)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(23)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(24)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(25)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(26)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(27)(t2)
/* x28-31(t3-6) Temporaries */
store_x x0, PORT_CONTEXT_xOFFSET(28)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(29)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(30)(t2)
store_x x0, PORT_CONTEXT_xOFFSET(31)(t2)
#endif /* __riscv_32e */
store_x a1, PORT_CONTEXT_mepcOFFSET(t2)
store_x t0, PORT_CONTEXT_mstatusOFFSET(t2)
/* The number of additional registers. */
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
beq t0, x0, 1f /* No more chip specific registers to save. */ beq t0, x0, 1f /* No more chip specific registers to save. */
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ addi t2, t2, -portWORD_SIZE /* Make space for chip specific register. */
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */ store_x x0, 0(t2) /* Give the chip specific register an initial value of zero. */
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
j chip_specific_stack_frame /* Until no more chip specific registers. */ j chip_specific_stack_frame /* Until no more chip specific registers. */
1: 1:
addi a0, a0, -portWORD_SIZE
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ mv a0, t2
ret ret
.endfunc .endfunc
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/