mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Added PPC440 demo that does not use any floating point hardware.
This commit is contained in:
Richard Barry
parent
b49cf69600
commit
3634ebb497
113 changed files with 26580 additions and 0 deletions
236
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs
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236
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/map.xmsgs
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@ -0,0 +1,236 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="Map" num="220" delta="new" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
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</msg>
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<msg type="warning" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N194</arg> has no load.
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</msg>
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<msg type="warning" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">1200</arg> more times for the following (max. 5 shown):
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<arg fmt="%s" index="4">N195,
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N196,
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N197,
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N198,
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N199</arg>
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To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
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</msg>
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<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
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</msg>
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<msg type="info" file="MapLib" num="159" delta="new" >Net Timing constraints on signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_CLK_pin</arg> are pushed forward through input buffer.
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</msg>
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<msg type="info" file="MapLib" num="856" delta="new" >PLL_ADV <arg fmt="%s" index="1">clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst</arg> CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin.
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</msg>
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<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin</arg> has been removed.
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</msg>
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<msg type="warning" file="MapLib" num="701" delta="new" >Signal <arg fmt="%s" index="1">fpga_0_Ethernet_MAC_PHY_col_pin</arg> connected to top level port <arg fmt="%s" index="2">fpga_0_Ethernet_MAC_PHY_col_pin</arg> has been removed.
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</msg>
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<msg type="warning" file="MapLib" num="41" delta="new" >All members of TNM group "<arg fmt="%s" index="1">ppc440_0_PPCS0PLBMBUSY</arg>" have been optimized out of the design.
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst</arg> of frag <arg fmt="%s" index="2">REGCLKAL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKU</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig</arg>
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</msg>
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<msg type="warning" file="Pack" num="231" delta="new" >trimming timing constraints from pin <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</arg> of frag <arg fmt="%s" index="2">RDRCLKL</arg> connected to power/ground net <arg fmt="%s" index="3">PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig</arg>
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</msg>
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<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
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</msg>
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<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts)
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</msg>
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<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4</arg> ignored during timing analysis.</msg>
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<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
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<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
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</msg>
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<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
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<arg fmt="%s" index="1">Components associated with this bus are as follows:
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18
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</arg>
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</msg>
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<msg type="warning" file="Place" num="838" delta="new" >An IO Bus with more than one IO standard is found.
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<arg fmt="%s" index="1">Components associated with this bus are as follows:
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Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33
|
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Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33
|
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Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33
|
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Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33
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Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33
|
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Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33
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Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33
|
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</arg>
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</msg>
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<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
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</msg>
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||||
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<msg type="warning" file="PhysDesignRules" num="0">One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance.
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</msg>
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|
||||
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0></arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="372" delta="new" >Gated clock. Clock net <arg fmt="%s" index="1">Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0></arg>> is incomplete. The signal does not drive any load pins in the design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0></arg>> is incomplete. The signal does not drive any load pins in the design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal <<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<31></arg>> is incomplete. The signal does not drive any load pins in the design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal <<arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<30></arg>> is incomplete. The signal does not drive any load pins in the design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal <<arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg>> is incomplete. The signal does not drive any load pins in the design.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1269" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The Q1 output pin of IFF is not used.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="PhysDesignRules" num="1273" delta="new" >Dangling pins on block:<<arg fmt="%s" index="1">DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce</arg>>:<<arg fmt="%s" index="2">ILOGIC_IFF</arg>>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
1067
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs
Normal file
1067
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/ngdbuild.xmsgs
Normal file
File diff suppressed because it is too large
Load diff
52
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs
Normal file
52
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/par.xmsgs
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(66100)]</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0></arg> has no load. PAR will not attempt to route this signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0></arg> has no load. PAR will not attempt to route this signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<31></arg> has no load. PAR will not attempt to route this signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">xps_bram_if_cntlr_1_port_BRAM_Addr<30></arg> has no load. PAR will not attempt to route this signal.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull</arg> has no load. PAR will not attempt to route this signal.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Route" num="501" delta="new" >One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.</msg>
|
||||
|
||||
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
|
||||
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">5</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
|
||||
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ParHelpers" num="197" delta="new" >Number of "Exact" mode Directed Routing Constraints: <arg fmt="%d" index="1">128</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ParHelpers" num="199" delta="new" >All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints found: <arg fmt="%d" index="1">128</arg>, number successful: <arg fmt="%d" index="2">128</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
20
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs
Normal file
20
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/trce.xmsgs
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="ConstraintSystem" num="65" delta="new" >Constraint <arg fmt="%s" index="1"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(66101)]</arg> overrides constraint <arg fmt="%s" index="2"><NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(66100)]</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;</arg> ignored during timing analysis.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
1029
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs
Normal file
1029
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/_xmsgs/xst.xmsgs
Normal file
File diff suppressed because it is too large
Load diff
26
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.gise
Normal file
26
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.gise
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise
Normal file
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ise
Normal file
Binary file not shown.
4
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log
Normal file
4
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.ntrc_log
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
--------------------
|
||||
Xst NTRC: "/" : OUT_OF_DATE
|
||||
--------------------
|
||||
Map NTRC: "/" : OUT_OF_DATE
|
||||
42
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise
Normal file
42
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
|
||||
|
||||
<files/>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Device" xil_pn:value="xa2c*"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Automotive CoolRunner2"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="system"/>
|
||||
<property xil_pn:name="PROP_Enable_Incremental_Messaging" xil_pn:value="true"/>
|
||||
<property xil_pn:name="PROP_Enable_Message_Filtering" xil_pn:value="true"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="*"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-*"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
|
||||
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<partitions>
|
||||
<partition xil_pn:name="/"/>
|
||||
</partitions>
|
||||
|
||||
</project>
|
||||
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd
Normal file
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/cst.xbcd
Normal file
Binary file not shown.
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock
Normal file
BIN
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system_xdb/tmp/ise.lock
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,24 @@
|
|||
CommandLine-Map
|
||||
|
||||
s
|
||||
CommandLine-Ngdbuild
|
||||
ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm system.bmm E:/my_projects/Wittenstein/release/svn/main/FreeRTOS/Demo/PCC440_Xilinx_Virtex5_GCC/implementation/system.ngc -uc system.ucf system.ngd
|
||||
s
|
||||
CommandLine-Par
|
||||
|
||||
s
|
||||
CommandLine-Xst
|
||||
|
||||
s
|
||||
Previous-NGD
|
||||
|
||||
s
|
||||
Previous-NGM
|
||||
|
||||
s
|
||||
Previous-Packed-NCD
|
||||
|
||||
s
|
||||
Previous-Routed-NCD
|
||||
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ISE_VERSION_LAST_SAVED_WITH
|
||||
11.1
|
||||
s
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
ISE_VERSION_LAST_SAVED_WITH
|
||||
11.1
|
||||
s
|
||||
XISE_FILE
|
||||
system.xise
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/XSLTProcess.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
ISE_VERSION_CREATED_WITH
|
||||
11.1
|
||||
s
|
||||
ISE_VERSION_LAST_SAVED_WITH
|
||||
11.1
|
||||
s
|
||||
LastRepoDir
|
||||
E:\my_projects\Wittenstein\release\svn\main\FreeRTOS\Demo\PCC440_Xilinx_Virtex5_GCC\__xps\ise\
|
||||
s
|
||||
OBJSTORE_VERSION
|
||||
1.3
|
||||
s
|
||||
PROJECT_CREATION_TIMESTAMP
|
||||
2009-06-11T19:26:19
|
||||
s
|
||||
REGISTRY_VERSION
|
||||
1.1
|
||||
s
|
||||
REPOSITORY_VERSION
|
||||
1.1
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/bitgen.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/bitinit.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
IncrementalMessagingEnabled
|
||||
true
|
||||
s
|
||||
MessageCaptureEnabled
|
||||
true
|
||||
s
|
||||
MessageFilterFile
|
||||
filter.filter
|
||||
s
|
||||
MessageFilteringEnabled
|
||||
true
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/cpldfit.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/dumpngdio.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/fuse.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/hprep6.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/idem.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/libgen.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/map.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/netgen.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/ngc2edif.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/ngcbuild.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/ngdbuild.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/par.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/platgen.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/runner.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/simgen.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/taengine.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/trce.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/tsim.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/vhpcomp.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/vlogcomp.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/xpwr.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
ClientMessageOutputFile
|
||||
_xmsgs/xst.xmsgs
|
||||
s
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
REPOSITORY_VERSION
|
||||
1.1
|
||||
REGISTRY_VERSION
|
||||
1.1
|
||||
OBJSTORE_VERSION
|
||||
1.3
|
||||
ISE_VERSION_CREATED_WITH
|
||||
11.1
|
||||
ISE_VERSION_LAST_SAVED_WITH
|
||||
11.1
|
||||
0
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst
Normal file
0
Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/xmsgprops.lst
Normal file
Loading…
Add table
Add a link
Reference in a new issue