is the name of an
-# input file. Doxygen will then use the output that the filter program writes
-# to standard output. If FILTER_PATTERNS is specified, this tag will be
-# ignored.
-
-INPUT_FILTER =
-
-# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
-# basis. Doxygen will compare the file name with each pattern and apply the
-# filter if there is a match. The filters are a list of the form:
-# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
-# info on how filters are used. If FILTER_PATTERNS is empty or if
-# non of the patterns match the file name, INPUT_FILTER is applied.
-
-FILTER_PATTERNS =
-
-# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
-# INPUT_FILTER) will be used to filter the input files when producing source
-# files to browse (i.e. when SOURCE_BROWSER is set to YES).
-
-FILTER_SOURCE_FILES = NO
-
-# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
-# pattern. A pattern will override the setting for FILTER_PATTERN (if any)
-# and it is also possible to disable source filtering for a specific pattern
-# using *.ext= (so without naming a filter). This option only has effect when
-# FILTER_SOURCE_FILES is enabled.
-
-FILTER_SOURCE_PATTERNS =
-
-#---------------------------------------------------------------------------
-# configuration options related to source browsing
-#---------------------------------------------------------------------------
-
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will
-# be generated. Documented entities will be cross-referenced with these sources.
-# Note: To get rid of all source code in the generated output, make sure also
-# VERBATIM_HEADERS is set to NO.
-
-SOURCE_BROWSER = NO
-
-# Setting the INLINE_SOURCES tag to YES will include the body
-# of functions and classes directly in the documentation.
-
-INLINE_SOURCES = NO
-
-# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
-# doxygen to hide any special comment blocks from generated source code
-# fragments. Normal C and C++ comments will always remain visible.
-
-STRIP_CODE_COMMENTS = YES
-
-# If the REFERENCED_BY_RELATION tag is set to YES
-# then for each documented function all documented
-# functions referencing it will be listed.
-
-REFERENCED_BY_RELATION = NO
-
-# If the REFERENCES_RELATION tag is set to YES
-# then for each documented function all documented entities
-# called/used by that function will be listed.
-
-REFERENCES_RELATION = NO
-
-# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
-# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
-# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
-# link to the source code. Otherwise they will link to the documentation.
-
-REFERENCES_LINK_SOURCE = NO
-
-# If the USE_HTAGS tag is set to YES then the references to source code
-# will point to the HTML generated by the htags(1) tool instead of doxygen
-# built-in source browser. The htags tool is part of GNU's global source
-# tagging system (see http://www.gnu.org/software/global/global.html). You
-# will need version 4.8.6 or higher.
-
-USE_HTAGS = NO
-
-# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
-# will generate a verbatim copy of the header file for each class for
-# which an include is specified. Set to NO to disable this.
-
-VERBATIM_HEADERS = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
-# of all compounds will be generated. Enable this if the project
-# contains a lot of classes, structs, unions or interfaces.
-
-ALPHABETICAL_INDEX = YES
-
-# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
-# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
-# in which this list will be split (can be a number in the range [1..20])
-
-COLS_IN_ALPHA_INDEX = 5
-
-# In case all classes in a project start with a common prefix, all
-# classes will be put under the same header in the alphabetical index.
-# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
-# should be ignored while generating the index headers.
-
-IGNORE_PREFIX =
-
-#---------------------------------------------------------------------------
-# configuration options related to the HTML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
-# generate HTML output.
-
-GENERATE_HTML = YES
-
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `html' will be used as the default path.
-
-HTML_OUTPUT = html
-
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
-# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
-# doxygen will generate files with .html extension.
-
-HTML_FILE_EXTENSION = .html
-
-# The HTML_HEADER tag can be used to specify a personal HTML header for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard header. Note that when using a custom header you are responsible
-# for the proper inclusion of any scripts and style sheets that doxygen
-# needs, which is dependent on the configuration options used.
-# It is advised to generate a default header using "doxygen -w html
-# header.html footer.html stylesheet.css YourConfigFile" and then modify
-# that header. Note that the header is subject to change so you typically
-# have to redo this when upgrading to a newer version of doxygen or when
-# changing the value of configuration settings such as GENERATE_TREEVIEW!
-
-HTML_HEADER =
-
-# The HTML_FOOTER tag can be used to specify a personal HTML footer for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard footer.
-
-HTML_FOOTER = ./footer.htm
-
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
-# style sheet that is used by each HTML page. It can be used to
-# fine-tune the look of the HTML output. If the tag is left blank doxygen
-# will generate a default style sheet. Note that doxygen will try to copy
-# the style sheet file to the HTML output directory, so don't put your own
-# style sheet in the HTML output directory as well, or it will be erased!
-
-HTML_STYLESHEET =
-
-# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
-# other source files which should be copied to the HTML output directory. Note
-# that these files will be copied to the base HTML output directory. Use the
-# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
-# files. In the HTML_STYLESHEET file, use the file name only. Also note that
-# the files will be copied as-is; there are no commands or markers available.
-
-HTML_EXTRA_FILES =
-
-# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
-# Doxygen will adjust the colors in the style sheet and background images
-# according to this color. Hue is specified as an angle on a colorwheel,
-# see http://en.wikipedia.org/wiki/Hue for more information.
-# For instance the value 0 represents red, 60 is yellow, 120 is green,
-# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
-# The allowed range is 0 to 359.
-
-HTML_COLORSTYLE_HUE = 221
-
-# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
-# the colors in the HTML output. For a value of 0 the output will use
-# grayscales only. A value of 255 will produce the most vivid colors.
-
-HTML_COLORSTYLE_SAT = 120
-
-# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
-# the luminance component of the colors in the HTML output. Values below
-# 100 gradually make the output lighter, whereas values above 100 make
-# the output darker. The value divided by 100 is the actual gamma applied,
-# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
-# and 100 does not change the gamma.
-
-HTML_COLORSTYLE_GAMMA = 80
-
-# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
-# page will contain the date and time when the page was generated. Setting
-# this to NO can help when comparing the output of multiple runs.
-
-HTML_TIMESTAMP = NO
-
-# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
-# files or namespaces will be aligned in HTML using tables. If set to
-# NO a bullet list will be used.
-
-HTML_ALIGN_MEMBERS = YES
-
-# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
-# documentation will contain sections that can be hidden and shown after the
-# page has loaded. For this to work a browser that supports
-# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
-# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
-
-HTML_DYNAMIC_SECTIONS = YES
-
-# If the GENERATE_DOCSET tag is set to YES, additional index files
-# will be generated that can be used as input for Apple's Xcode 3
-# integrated development environment, introduced with OSX 10.5 (Leopard).
-# To create a documentation set, doxygen will generate a Makefile in the
-# HTML output directory. Running make will produce the docset in that
-# directory and running "make install" will install the docset in
-# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
-# it at startup.
-# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
-# for more information.
-
-GENERATE_DOCSET = NO
-
-# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
-# feed. A documentation feed provides an umbrella under which multiple
-# documentation sets from a single provider (such as a company or product suite)
-# can be grouped.
-
-DOCSET_FEEDNAME = "Doxygen generated docs"
-
-# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
-# should uniquely identify the documentation set bundle. This should be a
-# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
-# will append .docset to the name.
-
-DOCSET_BUNDLE_ID = org.doxygen.Project
-
-# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
-# the documentation publisher. This should be a reverse domain-name style
-# string, e.g. com.mycompany.MyDocSet.documentation.
-
-DOCSET_PUBLISHER_ID = com.lufa-lib.library.documentation
-
-# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
-
-DOCSET_PUBLISHER_NAME = DeanCamera
-
-# If the GENERATE_HTMLHELP tag is set to YES, additional index files
-# will be generated that can be used as input for tools like the
-# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
-# of the generated HTML documentation.
-
-GENERATE_HTMLHELP = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
-# be used to specify the file name of the resulting .chm file. You
-# can add a path in front of the file if the result should not be
-# written to the html output directory.
-
-CHM_FILE = ../LUFA.chm
-
-# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
-# be used to specify the location (absolute path including file name) of
-# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
-# the HTML help compiler on the generated index.hhp.
-
-HHC_LOCATION =
-
-# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
-# controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
-
-GENERATE_CHI = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
-# is used to encode HtmlHelp index (hhk), content (hhc) and project file
-# content.
-
-CHM_INDEX_ENCODING =
-
-# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
-# controls whether a binary table of contents is generated (YES) or a
-# normal table of contents (NO) in the .chm file.
-
-BINARY_TOC = NO
-
-# The TOC_EXPAND flag can be set to YES to add extra items for group members
-# to the contents of the HTML help documentation and to the tree view.
-
-TOC_EXPAND = YES
-
-# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
-# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
-# that can be used as input for Qt's qhelpgenerator to generate a
-# Qt Compressed Help (.qch) of the generated HTML documentation.
-
-GENERATE_QHP = NO
-
-# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
-# be used to specify the file name of the resulting .qch file.
-# The path specified is relative to the HTML output folder.
-
-QCH_FILE =
-
-# The QHP_NAMESPACE tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#namespace
-
-QHP_NAMESPACE = org.doxygen.Project
-
-# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#virtual-folders
-
-QHP_VIRTUAL_FOLDER = doc
-
-# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
-# add. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#custom-filters
-
-QHP_CUST_FILTER_NAME =
-
-# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
-# custom filter to add. For more information please see
-#
-# Qt Help Project / Custom Filters.
-
-QHP_CUST_FILTER_ATTRS =
-
-# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
-# project's
-# filter section matches.
-#
-# Qt Help Project / Filter Attributes.
-
-QHP_SECT_FILTER_ATTRS =
-
-# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
-# be used to specify the location of Qt's qhelpgenerator.
-# If non-empty doxygen will try to run qhelpgenerator on the generated
-# .qhp file.
-
-QHG_LOCATION =
-
-# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
-# will be generated, which together with the HTML files, form an Eclipse help
-# plugin. To install this plugin and make it available under the help contents
-# menu in Eclipse, the contents of the directory containing the HTML and XML
-# files needs to be copied into the plugins directory of eclipse. The name of
-# the directory within the plugins directory should be the same as
-# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
-# the help appears.
-
-GENERATE_ECLIPSEHELP = NO
-
-# A unique identifier for the eclipse help plugin. When installing the plugin
-# the directory name containing the HTML and XML files should also have
-# this name.
-
-ECLIPSE_DOC_ID = org.doxygen.Project
-
-# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs)
-# at top of each HTML page. The value NO (the default) enables the index and
-# the value YES disables it. Since the tabs have the same information as the
-# navigation tree you can set this option to NO if you already set
-# GENERATE_TREEVIEW to YES.
-
-DISABLE_INDEX = NO
-
-# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
-# structure should be generated to display hierarchical information.
-# If the tag value is set to YES, a side panel will be generated
-# containing a tree-like index structure (just like the one that
-# is generated for HTML Help). For this to work a browser that supports
-# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
-# Windows users are probably better off using the HTML help feature.
-# Since the tree basically has the same information as the tab index you
-# could consider to set DISABLE_INDEX to NO when enabling this option.
-
-GENERATE_TREEVIEW = YES
-
-# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
-# (range [0,1..20]) that doxygen will group on one line in the generated HTML
-# documentation. Note that a value of 0 will completely suppress the enum
-# values from appearing in the overview section.
-
-ENUM_VALUES_PER_LINE = 1
-
-# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
-# and Class Hierarchy pages using a tree view instead of an ordered list.
-
-USE_INLINE_TREES = YES
-
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
-# used to set the initial width (in pixels) of the frame in which the tree
-# is shown.
-
-TREEVIEW_WIDTH = 300
-
-# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
-# links to external symbols imported via tag files in a separate window.
-
-EXT_LINKS_IN_WINDOW = NO
-
-# Use this tag to change the font size of Latex formulas included
-# as images in the HTML documentation. The default is 10. Note that
-# when you change the font size after a successful doxygen run you need
-# to manually remove any form_*.png images from the HTML output directory
-# to force them to be regenerated.
-
-FORMULA_FONTSIZE = 10
-
-# Use the FORMULA_TRANPARENT tag to determine whether or not the images
-# generated for formulas are transparent PNGs. Transparent PNGs are
-# not supported properly for IE 6.0, but are supported on all modern browsers.
-# Note that when changing this option you need to delete any form_*.png files
-# in the HTML output before the changes have effect.
-
-FORMULA_TRANSPARENT = YES
-
-# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
-# (see http://www.mathjax.org) which uses client side Javascript for the
-# rendering instead of using prerendered bitmaps. Use this if you do not
-# have LaTeX installed or if you want to formulas look prettier in the HTML
-# output. When enabled you may also need to install MathJax separately and
-# configure the path to it using the MATHJAX_RELPATH option.
-
-USE_MATHJAX = NO
-
-# When MathJax is enabled you need to specify the location relative to the
-# HTML output directory using the MATHJAX_RELPATH option. The destination
-# directory should contain the MathJax.js script. For instance, if the mathjax
-# directory is located at the same level as the HTML output directory, then
-# MATHJAX_RELPATH should be ../mathjax. The default value points to
-# the MathJax Content Delivery Network so you can quickly see the result without
-# installing MathJax. However, it is strongly recommended to install a local
-# copy of MathJax from http://www.mathjax.org before deployment.
-
-MATHJAX_RELPATH = http://www.mathjax.org/mathjax
-
-# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension
-# names that should be enabled during MathJax rendering.
-
-MATHJAX_EXTENSIONS =
-
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box
-# for the HTML output. The underlying search engine uses javascript
-# and DHTML and should work on any modern browser. Note that when using
-# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
-# (GENERATE_DOCSET) there is already a search function so this one should
-# typically be disabled. For large projects the javascript based search engine
-# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
-
-SEARCHENGINE = YES
-
-# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
-# implemented using a PHP enabled web server instead of at the web client
-# using Javascript. Doxygen will generate the search PHP script and index
-# file to put on the web server. The advantage of the server
-# based approach is that it scales better to large projects and allows
-# full text search. The disadvantages are that it is more difficult to setup
-# and does not have live searching capabilities.
-
-SERVER_BASED_SEARCH = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
-# generate Latex output.
-
-GENERATE_LATEX = NO
-
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `latex' will be used as the default path.
-
-LATEX_OUTPUT = latex
-
-# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
-# invoked. If left blank `latex' will be used as the default command name.
-# Note that when enabling USE_PDFLATEX this option is only used for
-# generating bitmaps for formulas in the HTML output, but not in the
-# Makefile that is written to the output directory.
-
-LATEX_CMD_NAME = latex
-
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
-# generate index for LaTeX. If left blank `makeindex' will be used as the
-# default command name.
-
-MAKEINDEX_CMD_NAME = makeindex
-
-# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
-# LaTeX documents. This may be useful for small projects and may help to
-# save some trees in general.
-
-COMPACT_LATEX = NO
-
-# The PAPER_TYPE tag can be used to set the paper type that is used
-# by the printer. Possible values are: a4, letter, legal and
-# executive. If left blank a4wide will be used.
-
-PAPER_TYPE = a4wide
-
-# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
-# packages that should be included in the LaTeX output.
-
-EXTRA_PACKAGES =
-
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
-# the generated latex document. The header should contain everything until
-# the first chapter. If it is left blank doxygen will generate a
-# standard header. Notice: only use this tag if you know what you are doing!
-
-LATEX_HEADER =
-
-# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
-# the generated latex document. The footer should contain everything after
-# the last chapter. If it is left blank doxygen will generate a
-# standard footer. Notice: only use this tag if you know what you are doing!
-
-LATEX_FOOTER =
-
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
-# is prepared for conversion to pdf (using ps2pdf). The pdf file will
-# contain links (just like the HTML output) instead of page references
-# This makes the output suitable for online browsing using a pdf viewer.
-
-PDF_HYPERLINKS = YES
-
-# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
-# plain latex in the generated Makefile. Set this option to YES to get a
-# higher quality PDF documentation.
-
-USE_PDFLATEX = YES
-
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
-# command to the generated LaTeX files. This will instruct LaTeX to keep
-# running if errors occur, instead of asking the user for help.
-# This option is also used when generating formulas in HTML.
-
-LATEX_BATCHMODE = NO
-
-# If LATEX_HIDE_INDICES is set to YES then doxygen will not
-# include the index chapters (such as File Index, Compound Index, etc.)
-# in the output.
-
-LATEX_HIDE_INDICES = NO
-
-# If LATEX_SOURCE_CODE is set to YES then doxygen will include
-# source code with syntax highlighting in the LaTeX output.
-# Note that which sources are shown also depends on other settings
-# such as SOURCE_BROWSER.
-
-LATEX_SOURCE_CODE = NO
-
-# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
-# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See
-# http://en.wikipedia.org/wiki/BibTeX for more info.
-
-LATEX_BIB_STYLE = plain
-
-#---------------------------------------------------------------------------
-# configuration options related to the RTF output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
-# The RTF output is optimized for Word 97 and may not look very pretty with
-# other RTF readers or editors.
-
-GENERATE_RTF = NO
-
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `rtf' will be used as the default path.
-
-RTF_OUTPUT = rtf
-
-# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
-# RTF documents. This may be useful for small projects and may help to
-# save some trees in general.
-
-COMPACT_RTF = NO
-
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
-# will contain hyperlink fields. The RTF file will
-# contain links (just like the HTML output) instead of page references.
-# This makes the output suitable for online browsing using WORD or other
-# programs which support those fields.
-# Note: wordpad (write) and others do not support links.
-
-RTF_HYPERLINKS = NO
-
-# Load style sheet definitions from file. Syntax is similar to doxygen's
-# config file, i.e. a series of assignments. You only have to provide
-# replacements, missing definitions are set to their default value.
-
-RTF_STYLESHEET_FILE =
-
-# Set optional variables used in the generation of an rtf document.
-# Syntax is similar to doxygen's config file.
-
-RTF_EXTENSIONS_FILE =
-
-#---------------------------------------------------------------------------
-# configuration options related to the man page output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
-# generate man pages
-
-GENERATE_MAN = NO
-
-# The MAN_OUTPUT tag is used to specify where the man pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `man' will be used as the default path.
-
-MAN_OUTPUT = man
-
-# The MAN_EXTENSION tag determines the extension that is added to
-# the generated man pages (default is the subroutine's section .3)
-
-MAN_EXTENSION = .3
-
-# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
-# then it will generate one additional man file for each entity
-# documented in the real man page(s). These additional files
-# only source the real man page, but without them the man command
-# would be unable to find the correct page. The default is NO.
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-MAN_LINKS = NO
-
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-# configuration options related to the XML output
-#---------------------------------------------------------------------------
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-# If the GENERATE_XML tag is set to YES Doxygen will
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-GENERATE_XML = NO
-
-# The XML_OUTPUT tag is used to specify where the XML pages will be put.
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-XML_DTD =
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-# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
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-
-XML_PROGRAMLISTING = YES
-
-#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
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-GENERATE_AUTOGEN_DEF = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
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-
-# If the GENERATE_PERLMOD tag is set to YES Doxygen will
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-
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-PERLMOD_PRETTY = YES
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-MACRO_EXPANSION = YES
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-PREDEFINED = __DOXYGEN__ \
- PROGMEM \
- EEMEM \
- ATTR_PACKED
-
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
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-# Use the PREDEFINED tag if you want to use a different macro definition that
-# overrules the definition found in the source code.
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-EXPAND_AS_DEFINED =
-
-# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
-# doxygen's preprocessor will remove all references to function-like macros
-# that are alone on a line, have an all uppercase name, and do not end with a
-# semicolon, because these will confuse the parser if not removed.
-
-SKIP_FUNCTION_MACROS = YES
-
-#---------------------------------------------------------------------------
-# Configuration::additions related to external references
-#---------------------------------------------------------------------------
-
-# The TAGFILES option can be used to specify one or more tagfiles. For each
-# tag file the location of the external documentation should be added. The
-# format of a tag file without this location is as follows:
-# TAGFILES = file1 file2 ...
-# Adding location for the tag files is done as follows:
-# TAGFILES = file1=loc1 "file2 = loc2" ...
-# where "loc1" and "loc2" can be relative or absolute paths
-# or URLs. Note that each tag file must have a unique name (where the name does
-# NOT include the path). If a tag file is not located in the directory in which
-# doxygen is run, you must also specify the path to the tagfile here.
-
-TAGFILES =
-
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create
-# a tag file that is based on the input files it reads.
-
-GENERATE_TAGFILE = Documentation/LPCUSBlib.tag
-
-# If the ALLEXTERNALS tag is set to YES all external classes will be listed
-# in the class index. If set to NO only the inherited external classes
-# will be listed.
-
-ALLEXTERNALS = NO
-
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
-# in the modules index. If set to NO, only the current project's groups will
-# be listed.
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-EXTERNAL_GROUPS = NO
-
-# The PERL_PATH should be the absolute path and name of the perl script
-# interpreter (i.e. the result of `which perl').
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-PERL_PATH = /usr/bin/perl
-
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
-#---------------------------------------------------------------------------
-
-# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
-# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
-# or super classes. Setting the tag to NO turns the diagrams off. Note that
-# this option also works with HAVE_DOT disabled, but it is recommended to
-# install and use dot, since it yields more powerful graphs.
-
-CLASS_DIAGRAMS = NO
-
-# You can define message sequence charts within doxygen comments using the \msc
-# command. Doxygen will then run the mscgen tool (see
-# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
-# documentation. The MSCGEN_PATH tag allows you to specify the directory where
-# the mscgen tool resides. If left empty the tool is assumed to be found in the
-# default search path.
-
-MSCGEN_PATH =
-
-# If set to YES, the inheritance and collaboration graphs will hide
-# inheritance and usage relations if the target is undocumented
-# or is not a class.
-
-HIDE_UNDOC_RELATIONS = YES
-
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
-# available from the path. This tool is part of Graphviz, a graph visualization
-# toolkit from AT&T and Lucent Bell Labs. The other options in this section
-# have no effect if this option is set to NO (the default)
-
-HAVE_DOT = NO
-
-# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
-# allowed to run in parallel. When set to 0 (the default) doxygen will
-# base this on the number of processors available in the system. You can set it
-# explicitly to a value larger than 0 to get control over the balance
-# between CPU load and processing speed.
-
-DOT_NUM_THREADS = 0
-
-# By default doxygen will use the Helvetica font for all dot files that
-# doxygen generates. When you want a differently looking font you can specify
-# the font name using DOT_FONTNAME. You need to make sure dot is able to find
-# the font, which can be done by putting it in a standard location or by setting
-# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
-# directory containing the font.
-
-DOT_FONTNAME = FreeSans
-
-# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
-# The default size is 10pt.
-
-DOT_FONTSIZE = 10
-
-# By default doxygen will tell dot to use the Helvetica font.
-# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to
-# set the path where dot can find it.
-
-DOT_FONTPATH =
-
-# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect inheritance relations. Setting this tag to YES will force the
-# CLASS_DIAGRAMS tag to NO.
-
-CLASS_GRAPH = NO
-
-# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect implementation dependencies (inheritance, containment, and
-# class references variables) of the class with other documented classes.
-
-COLLABORATION_GRAPH = NO
-
-# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for groups, showing the direct groups dependencies
-
-GROUP_GRAPHS = YES
-
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
-# collaboration diagrams in a style similar to the OMG's Unified Modeling
-# Language.
-
-UML_LOOK = NO
-
-# If the UML_LOOK tag is enabled, the fields and methods are shown inside
-# the class node. If there are many fields or methods and many nodes the
-# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS
-# threshold limits the number of items for each type to make the size more
-# managable. Set this to 0 for no limit. Note that the threshold may be
-# exceeded by 50% before the limit is enforced.
-
-UML_LIMIT_NUM_FIELDS = 10
-
-# If set to YES, the inheritance and collaboration graphs will show the
-# relations between templates and their instances.
-
-TEMPLATE_RELATIONS = NO
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
-# tags are set to YES then doxygen will generate a graph for each documented
-# file showing the direct and indirect include dependencies of the file with
-# other documented files.
-
-INCLUDE_GRAPH = YES
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
-# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
-# documented header file showing the documented files that directly or
-# indirectly include this file.
-
-INCLUDED_BY_GRAPH = YES
-
-# If the CALL_GRAPH and HAVE_DOT options are set to YES then
-# doxygen will generate a call dependency graph for every global function
-# or class method. Note that enabling this option will significantly increase
-# the time of a run. So in most cases it will be better to enable call graphs
-# for selected functions only using the \callgraph command.
-
-CALL_GRAPH = NO
-
-# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
-# doxygen will generate a caller dependency graph for every global function
-# or class method. Note that enabling this option will significantly increase
-# the time of a run. So in most cases it will be better to enable caller
-# graphs for selected functions only using the \callergraph command.
-
-CALLER_GRAPH = NO
-
-# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
-# will generate a graphical hierarchy of all classes instead of a textual one.
-
-GRAPHICAL_HIERARCHY = NO
-
-# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
-# then doxygen will show the dependencies a directory has on other directories
-# in a graphical way. The dependency relations are determined by the #include
-# relations between the files in the directories.
-
-DIRECTORY_GRAPH = YES
-
-# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
-# generated by dot. Possible values are svg, png, jpg, or gif.
-# If left blank png will be used. If you choose svg you need to set
-# HTML_FILE_EXTENSION to xhtml in order to make the SVG files
-# visible in IE 9+ (other browsers do not have this requirement).
-
-DOT_IMAGE_FORMAT = png
-
-# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
-# enable generation of interactive SVG images that allow zooming and panning.
-# Note that this requires a modern browser other than Internet Explorer.
-# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you
-# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files
-# visible. Older versions of IE do not have SVG support.
-
-INTERACTIVE_SVG = NO
-
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-# found. If left blank, it is assumed the dot tool can be found in the path.
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-DOT_PATH =
-
-# The DOTFILE_DIRS tag can be used to specify one or more directories that
-# contain dot files that are included in the documentation (see the
-# \dotfile command).
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-DOTFILE_DIRS =
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-# The MSCFILE_DIRS tag can be used to specify one or more directories that
-# contain msc files that are included in the documentation (see the
-# \mscfile command).
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-MSCFILE_DIRS =
-
-# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
-# nodes that will be shown in the graph. If the number of nodes in a graph
-# becomes larger than this value, doxygen will truncate the graph, which is
-# visualized by representing a node as a red box. Note that doxygen if the
-# number of direct children of the root node in a graph is already larger than
-# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
-# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
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-
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-# graphs generated by dot. A depth value of 3 means that only nodes reachable
-# from the root by following a path via at most 3 edges will be shown. Nodes
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-# code bases. Also note that the size of a graph can be further restricted by
-# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
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-# background. This is disabled by default, because dot on Windows does not
-# seem to support this out of the box. Warning: Depending on the platform used,
-# enabling this option may lead to badly anti-aliased labels on the edges of
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-
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-
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-# generate a legend page explaining the meaning of the various boxes and
-# arrows in the dot generated graphs.
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-GENERATE_LEGEND = YES
-
-# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
-# remove the intermediate dot files that are used to generate
-# the various graphs.
-
-DOT_CLEANUP = YES
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/LPCUSBLib_thumb.png b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/LPCUSBLib_thumb.png
deleted file mode 100644
index c4be9d154..000000000
Binary files a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/LPCUSBLib_thumb.png and /dev/null differ
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/MainPage.txt b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/MainPage.txt
deleted file mode 100644
index 05dc30f1e..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/MainPage.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-/** \file
-*
-* This file contains special DoxyGen information for the generation of the main page and other special
-* documentation pages. It is not a project source file.
-*/
-
-/**
-* \mainpage
-*
-*
-
-LPCUSBlib is a full featured, open-source USB library designed
-to run on all USB capable LPC microcontrollers from NXP.
-
-The library includes support for
-
-- USB 2.0
-- Host and device modes
-- Low, full and high speed transfer rates
-- Control, bulk, interrupt, and isochronous transfer types
-
-
-
-
- *
- */
-
-
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/footer.htm b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/footer.htm
deleted file mode 100644
index f0f091348..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/UsersManual/footer.htm
+++ /dev/null
@@ -1,12 +0,0 @@
-
-
-
-
-
-
-
- LPCUSBlib
- – USB software for your LPC world
-
-
-
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Version.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Version.h
deleted file mode 100644
index 9e678b35a..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/LPCUSBLib/Version.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * @brief LPCUSB library version constants
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-/** @defgroup USB_Version Version of LPC USB library
- * @ingroup LPCUSBlib
- * @{
- */
-#ifndef __LPCUSBlib_VERSION_H__
-#define __LPCUSBlib_VERSION_H__
-
- #define LPCUSBlib_VERSION_INTEGER 0x000000
-
- #define LPCUSBlib_VERSION_STRING "XXXXXX"
-
-#endif
-/**
-* @}
-*/
-
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/board_api.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/board_api.h
deleted file mode 100644
index 1657b9aac..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/board_api.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * @brief Common board API functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_API_H_
-#define __BOARD_API_H_
-
-#include "lpc_types.h"
-#include
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_COMMON_API BOARD: Common board functions
- * @ingroup BOARD_Common
- * This file contains common board definitions that are shared across
- * boards and devices. All of these functions do not need to be
- * impemented for a specific board, but if they are implemented, they
- * should use this API standard.
- * @{
- */
-
-/**
- * @brief Set up and initialize all required blocks and functions related to the board hardware.
- * @return None
- */
-void Board_Init(void);
-
-/**
- * @brief Initializes board UART for output, required for printf redirection
- * @return None
- */
-void Board_Debug_Init(void);
-
-/**
- * @brief Sends a single character on the UART, required for printf redirection
- * @param ch : character to send
- * @return None
- */
-void Board_UARTPutChar(char ch);
-
-/**
- * @brief Get a single character from the UART, required for scanf input
- * @return EOF if not character was received, or character value
- */
-int Board_UARTGetChar(void);
-
-/**
- * @brief Prints a string to the UART
- * @param str : Terminated string to output
- * @return None
- */
-void Board_UARTPutSTR(char *str);
-
-/**
- * @brief Sets the state of a board LED to on or off
- * @param LEDNumber : LED number to set state for
- * @param State : true for on, false for off
- * @return None
- */
-void Board_LED_Set(uint8_t LEDNumber, bool State);
-
-/**
- * @brief Returns the current state of a board LED
- * @param LEDNumber : LED number to set state for
- * @return true if the LED is on, otherwise false
- */
-bool Board_LED_Test(uint8_t LEDNumber);
-
-/**
- * @brief Toggles the current state of a board LED
- * @param LEDNumber : LED number to change state for
- * @return None
- */
-STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)
-{
- Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));
-}
-
-/**
- * @brief Current system clock rate, mainly used for sysTick
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Update system core clock rate, should be called if the
- * system has a clock rate change
- * @return None
- */
-void SystemCoreClockUpdate(void);
-
-/**
- * @brief Turn on Board LCD Backlight
- * @param Intensity : Backlight intensity (0 = off, >=1 = on)
- * @return None
- * @note On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
- * value will turn off or on the backlight. On some boards, a non-0 value will
- * control backlight intensity via a PWN. For PWM systems, the intensity value
- * is a percentage value between 0 and 100%.
- */
-void Board_SetLCDBacklight(uint8_t Intensity);
-
-/**
- * @brief Function prototype for a MS delay function. Board layers or example code may
- * define this function as needed.
- */
-typedef void (*p_msDelay_func_t)(uint32_t);
-
-/* The DEBUG* functions are selected based on system configuration.
- Code that uses the DEBUG* functions will have their I/O routed to
- the UART, semihosting, or nowhere. */
-#if defined(DEBUG_ENABLE)
-#if defined(DEBUG_SEMIHOSTING)
-#define DEBUGINIT()
-#define DEBUGOUT(...) printf(__VA_ARGS__)
-#define DEBUGSTR(str) printf(str)
-#define DEBUGIN() (int) EOF
-
-#else
-#define DEBUGINIT() Board_Debug_Init()
-#define DEBUGOUT(...) printf(__VA_ARGS__)
-#define DEBUGSTR(str) Board_UARTPutSTR(str)
-#define DEBUGIN() Board_UARTGetChar()
-#endif /* defined(DEBUG_SEMIHOSTING) */
-
-#else
-#define DEBUGINIT()
-#define DEBUGOUT(...)
-#define DEBUGSTR(str)
-#define DEBUGIN() (int) EOF
-#endif /* defined(DEBUG_ENABLE) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_API_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/lpc_phy.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/lpc_phy.h
deleted file mode 100644
index 80b771304..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/lpc_phy.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * @brief Common PHY functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LPC_PHY_H_
-#define __LPC_PHY_H_
-
-#include "board.h"
-#include "chip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers
- * @ingroup BOARD_Common
- * The simple PHY function API provides simple non-blocking PHY status
- * monitoring and initialization support for various Ethernet PHYs.
- * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires
- * several standard functions from the MAC driver for interfacing to the
- * PHY via a MII link (Chip_ENET_StartMIIWrite(), Chip_ENET_IsMIIBusy(),
- * Chip_ENET_StartMIIRead(), and Chip_ENET_ReadMIIData()).
- *
- * Once initialized, just preiodically call the lpcPHYStsPoll() function
- * from the background loop or a thread and monitor the returned status
- * to determine if the PHY state has changed and the current PHY state.
- * @{
- */
-#define PHY_LINK_ERROR (1 << 0) /*!< PHY status bit for link error */
-#define PHY_LINK_BUSY (1 << 1) /*!< PHY status bit for MII link busy */
-#define PHY_LINK_CHANGED (1 << 2) /*!< PHY status bit for changed state (not persistent) */
-#define PHY_LINK_CONNECTED (1 << 3) /*!< PHY status bit for connected state */
-#define PHY_LINK_SPEED100 (1 << 4) /*!< PHY status bit for 100Mbps mode */
-#define PHY_LINK_FULLDUPLX (1 << 5) /*!< PHY status bit for full duplex mode */
-
-/**
- * @brief Phy status update state machine
- * @return An Or'ed value of PHY_LINK_* statuses
- * @note This function can be called at any rate and will poll the the PHY status. Multiple
- * calls may be needed to determine PHY status.
- */
-uint32_t lpcPHYStsPoll(void);
-
-/**
- * @brief Initialize the PHY
- * @param rmii : Initializes PHY for RMII mode if true, MII if false
- * @param pDelayMsFunc : Delay function (in mS) used for this driver
- * @return PHY_LINK_ERROR or 0 on success
- * @note This function initializes the PHY. It will block until complete. It will not
- * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to
- * detect cable insertion.
- */
-uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_PHY_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/uda1380.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/uda1380.h
deleted file mode 100644
index ffb5bb417..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common/uda1380.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * @brief UDA1380 Audio Codec header
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __UDA1380_H_
-#define __UDA1380_H_
-
-/** @defgroup BOARD_COMMON_UDA1380 BOARD: UDA1380 Audio codec interface module
- * UDA1380 Audio codec interface module, the module registers are accessed
- * using I2C. The board which uses this module must define #UDA1380_I2C_BUS to #I2C0
- * , #I2C1, etc, based on which I2C bus is connected to UDA1380. All the
- * functions in this modules assumes that the I2C interrupt for #UDA1380_I2C_BUS
- * is enabled and ::Chip_I2C_MasterStateHandler(#UDA1380_I2C_BUS) is called from the
- * ISR. If the functions are to be used in polling mode the caller must replace
- * the event handler to Chip_I2C_EventHandlerPolling(), by using API
- * Chip_I2C_SetMasterEventHandler(). A macro #I2CDEV_UDA1380_ADDR must be defined
- * to the appropriate slave address of UDA1380 audio codec.
- * @ingroup BOARD_Common
- * @{
- */
-
-/* UDA1380 Registers */
-#define UDA_EVALM_CLK 0x00
-#define UDA_BUS_CTRL 0x01
-#define UDA_POWER_CTRL 0x02
-#define UDA_ANALOG_CTRL 0x03
-#define UDA_HPAMP_CTRL 0x04
-#define UDA_MASTER_VOL_CTRL 0x10
-#define UDA_MIXER_VOL_CTRL 0x11
-#define UDA_MODE_CTRL 0x12
-#define UDA_MUTE_CTRL 0x13
-#define UDA_MIXER_FILTER_CTRL 0x14
-#define UDA_DEC_VOL_CTRL 0x20
-#define UDA_PGA_CTRL 0x21
-#define UDA_ADC_CTRL 0x22
-#define UDA_AGC_CTRL 0x23
-#define UDA_TOTAL_REG 0x24
-
-/** Evalutation mode and clock setting register bits */
-#define EVCLK_EV2 (1 << 15)
-#define EVCLK_EV1 (1 << 14)
-#define EVCLK_EV0 (1 << 13)
-#define EVCLK_EN_ADC (1 << 11)
-#define EVCLK_EN_DEC (1 << 10)
-#define EVCLK_EN_DAC (1 << 9)
-#define EVCLK_EN_INT (1 << 8)
-#define EVCLK_ADC_CLK (1 << 5)
-#define EVCLK_DAC_CLK (1 << 4)
-#define EVCLK_SYS_DIV1 (1 << 3)
-#define EVCLK_SYS_DIV0 (1 << 2)
-#define EVCLK_PLL1 (1 << 1)
-#define EVCLK_PLL0 (1 << 0)
-
-/** UDA1380 register default values */
-#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1)
-#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)
-#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2)
-
-#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2)
-#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */
-#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000
-#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */
-#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000
-
-#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000
-
-/* UDA1380 Audio input selection */
-#define UDA1380_LINE_IN 0 /**< LINE_IN_L in left stream, LINE_IN_R in Right stream */
-#define UDA1380_MIC_IN_L (1 << 2) /**< MIC audio in Left stream, Line_IN_R in Right stream */
-#define UDA1380_MIC_IN_LR (3 << 2) /**< MIC audio in Left & Right stream */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @def UDA1380_U8(val)
- * Convert a 16 bit register value to 2 x 8 bit values that could be written
- * to the I2C bus in an efficient way.
- */
-#define UDA1380_U8(val) (((val) >> 8) & 0xFF), ((val) & 0xFF)
-
-/**
- * @brief Write a 16-bit value to UDA Register
- * @param reg : Register to which @a val be written
- * @param val : 16-Bit value to be written
- * @return Nothing
- */
-void UDA1380_REG_Write(uint8_t reg, uint16_t val);
-
-/**
- * @brief Read a 16-bit value from UDA1380 codec register
- * @param reg : Register from which the value to be read
- * @return Returns the value read from the register
- */
-uint16_t UDA1380_REG_Read(uint8_t reg);
-
-/**
- * @brief Writes a value to a UDA register, read back and verify the value
- * @param reg : Register to which the value be written
- * @param val : Value to be written
- * @return 1 On success, 0 on failure
- */
-int UDA1380_REG_WriteVerify(uint8_t reg, uint16_t val);
-
-/**
- * @brief Write multiple value to UDA1380 registers
- * @param buff : Pointer to buffer (See note section)
- * @param len : Number of bytes in buff
- * @return 1 on Success, 0 on failure
- * @note buff[0] must be the address of the register to which
- * the first data i.e, buff[1], buff[2] be written, the next bytes
- * buff[3], buff[4] be written to register buff[0]+1 and so on.
- */
-int UDA1380_REG_WriteMult(const uint8_t *buff, int len);
-
-/**
- * @brief Verify values in multiple UDA1380 registers
- * @param reg : Starting register from which data be read
- * @param value : Pointer to memory which contains values to be compared
- * @param buff : Pointer to memory to which data be read
- * @param len : Length of bytes in value @a buff
- * @return 1 on Success & Data is valid, 0 on Failure
- */
-int UDA1380_REG_VerifyMult(uint8_t reg, const uint8_t *value, uint8_t *buff, int len);
-
-/**
- * @brief Initialize UDA1380 to its default state
- * @param input : Audio input source (Must be one of #UDA1380_LINE_IN
- * or #UDA1380_MIC_IN_L or #UDA1380_MIC_IN_LR)
- * @return 1 on Success and 0 on failure
- */
-int UDA1380_Init(int input);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-#endif /* __UDA1380_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
deleted file mode 100644
index 81b779262..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_H_
-#define __BOARD_H_
-
-#include "board_ngx_xplorer_18304330.h"
-
-#endif /* __BOARD_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
deleted file mode 100644
index 75173f16c..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-#include "string.h"
-
-//#include "lpc_phy_smsc87x0.c"
-//#include "retarget.c"
-
-/** @ingroup BOARD_NGX_XPLORER_18304330
- * @{
- */
-
-void Board_UART_Init(LPC_USART_T *pUART)
-{
- if (pUART == LPC_USART0) {
- Chip_SCU_PinMuxSet(0x6, 4, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC2)); /* P6.5 : UART0_TXD */
- Chip_SCU_PinMuxSet(0x6, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));/* P6.4 : UART0_RXD */
- }
- else if (pUART == LPC_UART1) {
- Chip_SCU_PinMuxSet(0x1, 13, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC2)); /* P1.13 : UART1_TXD */
- Chip_SCU_PinMuxSet(0x1, 14, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); /* P1.14 : UART1_RX */
- }
-}
-
-/* Initialize debug output via UART for board */
-void Board_Debug_Init(void)
-{
-#if defined(DEBUG_UART)
- Board_UART_Init(DEBUG_UART);
-
- Chip_UART_Init(DEBUG_UART);
- Chip_UART_SetBaud(DEBUG_UART, 115200);
- Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);
-
- /* Enable UART Transmit */
- Chip_UART_TxCmd(DEBUG_UART, ENABLE);
-#endif
-}
-
-/* Sends a character on the UART */
-void Board_UARTPutChar(char ch)
-{
-#if defined(DEBUG_UART)
- while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}
-#endif
-}
-
-/* Gets a character from the UART, returns EOF if no character is ready */
-int Board_UARTGetChar(void)
-{
-#if defined(DEBUG_UART)
- uint8_t data;
-
- if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {
- return (int) data;
- }
-#endif
- return EOF;
-}
-
-/* Outputs a string on the debug UART */
-void Board_UARTPutSTR(char *str)
-{
-#if defined(DEBUG_UART)
- while (*str != '\0') {
- Board_UARTPutChar(*str++);
- }
-#endif
-}
-
-static void Board_LED_Init()
-{
- /* P2.12 : LED D2 as output */
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 1, 12, true);
-
- /* P2.11 : LED D3 as output */
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 1, 11, true);
-
- /* Set initial states to off (true to disable) */
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 12, (bool) true);
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 11, (bool) true);
-}
-
-void Board_LED_Set(uint8_t LEDNumber, bool On)
-{
- if (LEDNumber == 0) {
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 12, (bool) !On);
- }
- else if (LEDNumber == 1) {
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 11, (bool) !On);
- }
-}
-
-bool Board_LED_Test(uint8_t LEDNumber)
-{
- if (LEDNumber == 0) {
- return (bool) !Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 1, 12);
- }
- else if (LEDNumber == 1) {
- return (bool) !Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 1, 11);
- }
-
- return false;
-}
-
-void Board_Buttons_Init(void) // FIXME not functional ATM
-{
- Chip_SCU_PinMuxSet(0x2, 7, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)); // P2_7 as GPIO0[7]
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false); // input
-}
-
-uint32_t Buttons_GetStatus(void)
-{
- uint8_t ret = NO_BUTTON_PRESSED;
- if (Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {
- ret |= BUTTONS_BUTTON1;
- }
- return ret;
-}
-
-void Board_Joystick_Init(void)
-{}
-
-uint8_t Joystick_GetStatus(void)
-{
- return NO_BUTTON_PRESSED;
-}
-
-/*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock;
-
-/* Update system core clock rate, should be called if the system has
- a clock rate change */
-void SystemCoreClockUpdate(void)
-{
- /* CPU core speed */
- SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
-}
-
-/* Returns the MAC address assigned to this board */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr)
-{
- uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};
-
- memcpy(mcaddr, boardmac, 6);
-}
-
-/* Set up and initialize all required blocks and functions related to the
- board hardware */
-void Board_Init(void)
-{
- /* Sets up DEBUG UART */
- DEBUGINIT();
-
- /* Updates SystemCoreClock global var with current clock speed */
- SystemCoreClockUpdate();
-
- /* Initializes GPIO */
- Chip_GPIO_Init(LPC_GPIO_PORT);
-
- /* Setup GPIOs for USB demos */
- Chip_SCU_PinMuxSet(0x2, 6, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* P2_6 USB1_PWR_EN, USB1 VBus function */
- Chip_SCU_PinMuxSet(0x2, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */
- Chip_SCU_PinMuxSet(0x1, 7, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 5, 6, true); /* GPIO5[6] = USB1_PWR_EN */
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 5, 6, true); /* GPIO5[6] output high */
-
- /* Initialize LEDs */
- Board_LED_Init();
-}
-
-void Board_I2C_Init(I2C_ID_T id)
-{
- if (id == I2C1) {
- /* Configure pin function for I2C1*/
- Chip_SCU_PinMuxSet(0x2, 3, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.3 : I2C1_SDA */
- Chip_SCU_PinMuxSet(0x2, 4, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.4 : I2C1_SCL */
- }
- else {
- Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
- }
-}
-
-#ifndef CORE_M0
-/* PIN0 Interrupt not available in M0 core */
-void GPIO0_IRQHandler(void)
-{
- static bool On;
-
- if (Chip_GPIO_IntGetStatus(LPC_GPIO_PIN_INT, 0, 0, 0)) {
- Chip_GPIO_IntClear(LPC_GPIO_PIN_INT, 0, 0);
- On = (bool) !On;
- Board_LED_Set(1, On);
- }
-}
-
-void Board_GPIO_Int_Init()
-{
- Chip_SCU_PinMuxSet(0xF, 9, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)); /* PF.9 : POTI button */
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 7, 23, false); /* PF.9 -> GPIO7[23] : input */
- Chip_SCU_GPIOIntPinSel(0, 7, 23);
- Chip_GPIO_IntCmd(LPC_GPIO_PIN_INT, 0, 0, GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */
-
- NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */
-}
-
-#endif
-
-void Board_SDMMC_Init(void)
-{
- Chip_SCU_PinMuxSet(0x1, 9, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.9 connected to SDIO_D0 */
- Chip_SCU_PinMuxSet(0x1, 10, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.10 connected to SDIO_D1 */
- Chip_SCU_PinMuxSet(0x1, 11, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.11 connected to SDIO_D2 */
- Chip_SCU_PinMuxSet(0x1, 12, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.12 connected to SDIO_D3 */
-
- Chip_SCU_ClockPinMuxSet(2, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* CLK2 connected to SDIO_CLK */
- Chip_SCU_PinMuxSet(0x1, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.6 connected to SDIO_CMD */
-}
-
-void Board_SSP_Init(LPC_SSP_T *pSSP)
-{
- if (pSSP == LPC_SSP1) {
- /* Set up clock and power for SSP1 module */
- /* Configure SSP1 pins*/
- /* SCLK comes out pin CLK0 */
- Chip_SCU_ClockPinMuxSet(0, (SCU_PINIO_FAST | SCU_MODE_FUNC6)); /* CLK0 connected to CLK SCU_MODE_FUNC6=SSP1 CLK1 */
- Chip_SCU_PinMuxSet(0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC5)); /* P1.5 connected to nCS SCU_MODE_FUNC5=SSP1 SSEL1 */
- Chip_SCU_PinMuxSet(0x1, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5));/* P1.3 connected to SO SCU_MODE_FUNC5=SSP1 MISO1 */
- Chip_SCU_PinMuxSet(0x1, 4, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5));/* P1.4 connected to nSI SCU_MODE_FUNC5=SSP1 MOSI1 */
- }
- else {
- return;
- }
-}
-
-static void delay(uint32_t i) {
- while (i--) {}
-}
-
-/* Initialize Audio Codec */
-static Status Board_Audio_CodecInit(int micIn)
-{
- /* Reset UDA1380 on board NGX Xplorer */
- Chip_SCU_PinMuxSet(0x2, 10, (SCU_MODE_MODE_INACT | SCU_MODE_FUNC0));
- Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 0, 14, true);
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 0, 14, true);
- // delay 1us
- delay(100000);
- Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 0, 14, false);
- delay(100000);
-
- if (!UDA1380_Init(UDA1380_MIC_IN_LR & - (micIn != 0))) {
- return ERROR;
- }
-
- return SUCCESS;
-}
-
-/* Board Audio initialization */
-void Board_Audio_Init(LPC_I2S_T *pI2S, int micIn)
-{
- Chip_I2S_Audio_Format_T I2S_Config;
-
- I2S_Config.SampleRate = 48000;
- I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */
- I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */
- Chip_I2S_Init(pI2S);
- Chip_I2S_Config(pI2S, I2S_TX_MODE, &I2S_Config);
-
- /* Init UDA1380 CODEC */
- while (Board_Audio_CodecInit(micIn) != SUCCESS) {}
-}
-
-/* FIXME Should we remove this function? */
-void Serial_CreateStream(void *Stream)
-{}
-
-/**
- * @}
- */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
deleted file mode 100644
index 2db1c2e62..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * @brief NGX Xplorer 1830/4330 board file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __BOARD_NGX_XPLORER_18304330_H_
-#define __BOARD_NGX_XPLORER_18304330_H_
-
-#include "chip.h"
-#include "board_api.h"
-#include "lpc_phy.h"
-#include "uda1380.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions
- * @ingroup BOARDS_18XX_43XX
- * @{
- */
-
-/** @defgroup BOARD_NGX_XPLORER_1830_OPTIONS BOARD: LPC1830 NGX Xplorer board builds options
- * This board has options that configure its operation at build-time.
- *
- * For more information on driver options see
- * @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup BOARD_NGX_XPLORER_4330_OPTIONS BOARD: LPC4330 NGX Xplorer board builds options
- * This board has options that configure its operation at build-time.
- *
- * For more information on driver options see
- * @ref LPCOPEN_DESIGN_ARPPROACH
- * @{
- */
-
-/**
- * @}
- */
-
-#define BOARD_NGX_XPLORER_18304330
-
-#define I2CDEV_UDA1380_ADDR (0x34 >> 1)
-#define UDA1380_I2C_BUS I2C0
-
-/* For USBLIB examples */
-#define LEDS_LED1 0x01
-#define LEDS_LED2 0x02
-#define LEDS_LED3 0x04
-#define LEDS_LED4 0x08
-#define LEDS_NO_LEDS 0x00
-#define BUTTONS_BUTTON1 0x01
-#define JOY_UP 0x01
-#define JOY_DOWN 0x02
-#define JOY_LEFT 0x04
-#define JOY_RIGHT 0x08
-#define JOY_PRESS 0x10
-#define NO_BUTTON_PRESSED 0x00
-
-/*Define if use SDCARD for Mass Storage Example*/
-//#define CFG_SDCARD
-
-#define BUTTONS_BUTTON1_GPIO_PORT_NUM 0
-#define BUTTONS_BUTTON1_GPIO_BIT_NUM 7
-#define LED1_GPIO_PORT_NUM 1
-#define LED1_GPIO_BIT_NUM 11
-#define LED2_GPIO_PORT_NUM 1
-#define LED2_GPIO_BIT_NUM 12
-
-/**
- * @brief Sets up board specific I2C interface
- * @param id : I2C Peripheral ID (I2C0, I2C1)
- * @return Nothing
- */
-void Board_I2C_Init(I2C_ID_T id);
-
-/**
- * @brief Sets up I2C Fast Plus mode
- * @param id : Must always be I2C0
- * @return Nothing
- * @note This function must be called before calling
- * Chip_I2C_SetClockRate() to set clock rates above
- * normal range 100KHz to 400KHz. Only I2C0 supports
- * this mode.
- */
-STATIC INLINE void Board_I2C_EnableFastPlus(I2C_ID_T id)
-{
- Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS);
-}
-
-/**
- * @brief Disable I2C Fast Plus mode and enables default mode
- * @param id : Must always be I2C0
- * @return Nothing
- * @sa Board_I2C_EnableFastPlus()
- */
-STATIC INLINE void Board_I2C_DisableFastPlus(I2C_ID_T id)
-{
- Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
-}
-
-/**
- * @brief Initializes board specific GPIO Interrupt
- * @return Nothing
- */
-void Board_GPIO_Int_Init(void);
-
-/**
- * @brief Initialize pin muxing for SSP interface
- * @param pSSP : Pointer to SSP interface to initialize
- * @return Nothing
- */
-void Board_SSP_Init(LPC_SSP_T *pSSP);
-
-/**
- * @brief Returns the MAC address assigned to this board
- * @param mcaddr : Pointer to 6-byte character array to populate with MAC address
- * @return Nothing
- */
-void Board_ENET_GetMacADDR(uint8_t *mcaddr);
-
-/**
- * @brief Initialize pin muxing for a UART
- * @param pUART : Pointer to UART register block for UART pins to init
- * @return Nothing
- */
-void Board_UART_Init(LPC_USART_T *pUART);
-
-/**
- * @brief Initialize pin muxing for SDMMC interface
- * @return Nothing
- */
-void Board_SDMMC_Init(void);
-
-/**
- * @brief Initialize button(s) interface on board
- * @return Nothing
- */
-void Board_Buttons_Init(void);
-
-/**
- * @brief Initialize joystick interface on board
- * @return Nothing
- */
-void Board_Joystick_Init(void);
-
-/**
- * @brief Returns joystick states on board
- * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP
- */
-uint8_t Joystick_GetStatus(void);
-
-/**
- * @brief Returns button(s) state on board
- * @return Returns BUTTONS_BUTTON1 if button1 is pressed
- */
-uint32_t Buttons_GetStatus (void);
-
-/**
- * @brief Initialize I2S interface for the board and UDA1380
- * @param pI2S : Pointer to I2S register interface used on this board
- * @param micIn : If 1 MIC will be used as input, if 0 LINE_IN will be used
- * @return Nothing
- */
-void Board_Audio_Init(LPC_I2S_T *pI2S, int micIn);
-
-/**
- * @brief FIXME
- * @param Stream : FIXME
- * @return Nothing
- */
-void Serial_CreateStream(void *Stream);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __BOARD_NGX_XPLORER_18304330_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
deleted file mode 100644
index 6e21745c8..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SYS_CONFIG_H_
-#define __SYS_CONFIG_H_
-
-/** @ingroup BOARD_NGX_XPLORER_1830_OPTIONS
- * @{
- */
-
-/* Build for 18xx chip family */
-#define CHIP_LPC18XX
-
-/* Build for RMII interface */
-#define USE_RMII
-
-/* Un-comment DEBUG_ENABLE for IO support via the UART */
-// #define DEBUG_ENABLE
-
-/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support
- via semihosting */
-// #define DEBUG_SEMIHOSTING
-
-/* Board UART used for debug output */
-#define DEBUG_UART LPC_USART0 /* No port on Xplorer */
-
-/* Crystal frequency into device */
-#define CRYSTAL_MAIN_FREQ_IN 12000000
-
-/* Crystal frequency into device for RTC/32K input */
-#define CRYSTAL_32K_FREQ_IN 32768
-
-/* Frequency on external clock in pin */
-#define EXTERNAL_CLKIN_FREQ_IN 0
-
-/* Default CPU clock frequency */
-#define MAX_CLOCK_FREQ (180000000)
-
-/* Audio and USB default PLL rates (configured in SystemInit()) */
-#define CGU_AUDIO_PLL_RATE (0)
-#define CGU_USB_PLL_RATE (480000000)
-
-/**
- * @}
- */
-
-#endif /* __SYS_CONFIG_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
deleted file mode 100644
index 5706cee38..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "board.h"
-
-/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code
- * @ingroup BOARD_NGX_XPLORER_18304330
- * The System initialization code is called prior to the application and
- * initializes the board for run-time operation. Board initialization
- * for the NGX Xplorer boards includes clock setup and default pin muxing
- * configuration.
- *
- * With the exception of stack space, no RW memory is used for this call.
- *
- * LPC1830 and LPC4330 NGX Xplorer setup
- * Clocking:
- * All base clocks enabled by default (Save power by disabling un-needed clocks)
- * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
- * SPIFI FLASH clock setup for fastest speed
- * CGU Dividers A, C, D and E are used for the LCD, USB, and SPIFI.
- * Pin muxing:
- * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
- * Memory:
- * There is no memory setup for this board.
- * @{
- */
-
-#ifndef CORE_M0
-/* SCR pin definitions for pin muxing */
-typedef struct {
- uint8_t pingrp; /* Pin group */
- uint8_t pinnum; /* Pin number */
- uint16_t modefunc; /* Pin mode and function for SCU */
-} PINMUX_GRP_T;
-
-/* Structure for initial base clock states */
-struct CLK_BASE_STATES {
- CHIP_CGU_BASE_CLK_T clk; /* Base clock */
- CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
- bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
- bool powerdn; /* Set to true if the base clock is initially powered down */
-};
-
-/* Initial base clock states are mostly on */
-STATIC const struct CLK_BASE_STATES InitClkStates[] = {
- {CLK_BASE_SAFE, CLKIN_IRC, true, false},
- {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_USB0, CLKIN_USBPLL, true, true},
-#if defined(CHIP_LPC43XX)
- {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
- {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},
-#endif
- {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
-#if defined(USE_RMII)
- {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
-#else
- {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
-#endif
- {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
- {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
- {CLK_BASE_OUT, CLKINPUT_PD, true, false},
- {CLK_BASE_APLL, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
- {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},
-
- /* Clocks derived from dividers */
- {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
- {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
-};
-
-/* SPIFI high speed pin mode setup */
-STATIC const PINMUX_GRP_T spifipinmuxing[] = {
- {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
- {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
- {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
- {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
- {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
- {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
-};
-
-/* USB PLL pre-initialized setup values for 480MHz output rate */
-static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {
- 0x0000601D, /* Default control with main osc input, PLL disabled */
- 0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */
- 0x00000000, /* N-divider value */
- 0x00000000 /* Not applicable for USB PLL */
-};
-
-/* Audio PLL pre-initialized setup values for FIXME output rate */
-// static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {
-// 0x0000601D, /* Default control with main osc input, PLL disabled */
-// 0x06167FFA, /* M-divider value for FIXME output from 12MHz input */
-// 0x00000000, /* N-divider value */
-// 0x00000000 /* FIXME */
-// };
-
-/* Setup system clocking */
-STATIC void SystemSetupClocking(void)
-{
- int i;
-
- /* Switch main system clocking to crystal */
- Chip_Clock_EnableCrystal();
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
-
- /* Setup PLL for 100MHz and switch main system clocking */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
- Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
-
- /* Setup PLL for maximum clock */
- Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
-
- /* Setup system base clocks and initial states. This won't enable and
- disable individual clocks, but sets up the base clock sources for
- each individual peripheral clock. */
- for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
- Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
- InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
- }
-
- /* Reset and enable 32Khz oscillator */
- LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
- LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
-
- /* SPIFI pin setup is done prior to setting up system clocking */
- for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
- Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
- spifipinmuxing[i].modefunc);
- }
-
- /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
- Divide rate is based on CPU speed and speed of SPI FLASH part. */
-#if (MAX_CLOCK_FREQ > 180000000)
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
-#else
- Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
-#endif
- Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
-
- /* Attach main PLL clock to divider C with a divider of 2 */
- Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
-
- /* Setup default USB PLL state for a 480MHz output and attach */
- Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
-
- /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
- chained to make a divide by 8 function. Connect the output of
- divider D to the USB1 base clock. */
- Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
- Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
- Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
-
- /* Setup default audio PLL state for a FIXME output */
- // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
-}
-
-STATIC const PINMUX_GRP_T pinmuxing[] = {
- /* RMII pin group */
- {0x1, 15,
- (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
- {0x0, 0,
- (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
- {0x1, 16,
- (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
- {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
- {0x1, 19,
- (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
- {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
- {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
- {0x1, 17,
- (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
- {0x2, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
- /* Board LEDs */
- {0x2, 11, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},
- {0x2, 12, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},
- /* I2S */
- {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
- {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
- {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
- {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
- {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
- {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
-};
-
-/* Sets up system pin muxing */
-STATIC void SystemSetupMuxing(void)
-{
- int i;
-
- /* Setup system level pin muxing */
- for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
- Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
- pinmuxing[i].modefunc);
- }
-}
-
-/* Nothing to do for the Xplorer board */
-STATIC void SystemSetupMemory(void)
-{}
-
-#endif
-
-/**
- * @brief Setup the system
- * @return none
- * SystemInit() is called prior to the application and sets up system
- * clocking, memory, and any resources needed prior to the application
- * starting.
- */
-void SystemInit(void)
-{
-#if defined(CORE_M3) || defined(CORE_M4)
- unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-
-#if defined(__IAR_SYSTEMS_ICC__)
- extern void *__vector_table;
-
- *pSCB_VTOR = (unsigned int) &__vector_table;
-#elif defined(__CODE_RED)
- extern void *g_pfnVectors;
-
- *pSCB_VTOR = (unsigned int) &g_pfnVectors;
-#elif defined(__ARMCC_VERSION)
- extern void *__Vectors;
-
- *pSCB_VTOR = (unsigned int) &__Vectors;
-#endif
-
-#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
- fpuInit();
-#endif
-
- /* Setup system clocking and memory. This is done early to allow the
- application and tools to clear memory and use scatter loading to
- external memory. */
- SystemSetupClocking();
- SystemSetupMuxing();
- SystemSetupMemory();
-#endif
-}
-
-/**
- * @}
- */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
deleted file mode 100644
index 6e32a56c0..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * @brief LPC18xx/43xx A/D conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ADC_18XX_43XX_H_
-#define __ADC_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** The channels on one ADC peripheral*/
-typedef enum CHIP_ADC_CHANNEL {
- ADC_CH0 = 0, /**< ADC channel 0 */
- ADC_CH1, /**< ADC channel 1 */
- ADC_CH2, /**< ADC channel 2 */
- ADC_CH3, /**< ADC channel 3 */
- ADC_CH4, /**< ADC channel 4 */
- ADC_CH5, /**< ADC channel 5 */
- ADC_CH6, /**< ADC channel 6 */
- ADC_CH7, /**< ADC channel 7 */
-} CHIP_ADC_CHANNEL_T;
-
-/** The number of bits of accuracy of the result in the LS bits of ADDR*/
-typedef enum CHIP_ADC_RESOLUTION {
- ADC_10BITS = 0, /**< ADC 10 bits */
- ADC_9BITS, /**< ADC 9 bits */
- ADC_8BITS, /**< ADC 8 bits */
- ADC_7BITS, /**< ADC 7 bits */
- ADC_6BITS, /**< ADC 6 bits */
- ADC_5BITS, /**< ADC 5 bits */
- ADC_4BITS, /**< ADC 4 bits */
- ADC_3BITS, /**< ADC 3 bits */
-} CHIP_ADC_RESOLUTION_T;
-
-/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
-typedef enum CHIP_ADC_EDGE_CFG {
- ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
- ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
-} CHIP_ADC_EDGE_CFG_T;
-
-/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
-typedef enum CHIP_ADC_START_MODE {
- ADC_NO_START = 0,
- ADC_START_NOW, /*!< Start conversion now */
- ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
- ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
- ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
- ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
- ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-} CHIP_ADC_START_MODE_T;
-
-/** Clock setup structure for ADC controller passed to the initialize function */
-typedef struct {
- uint32_t adcRate; /*!< ADC rate */
- uint8_t bitsAccuracy; /*!< ADC bit accuracy */
- bool burstMode; /*!< ADC Burt Mode */
-} ADC_Clock_Setup_T;
-
-/**
- * @brief Read the ADC value from a channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param data : Pointer to where to put data
- * @return SUCCESS or ERROR if no conversion is ready
- */
-STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
-{
- return IP_ADC_Get_Val(pADC, channel, data);
-}
-
-/**
- * @brief Read the ADC channel status
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param StatusType : Status type of ADC_DR_*
- * @return SET or RESET
- */
-STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
-{
- return IP_ADC_GetStatus(pADC, channel, StatusType);
-}
-
-/**
- * @brief Enable/Disable interrupt for ADC channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : ADC channel to read
- * @param NewState : New state, ENABLE or DISABLE
- * @return SET or RESET
- */
-STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
-{
- IP_ADC_Int_Enable(pADC, channel, NewState);
-}
-
-/**
- * @brief Enable/Disable global interrupt for ADC channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_T *pADC, FunctionalState NewState)
-{
- IP_ADC_Int_Enable(pADC, 8, NewState);
-}
-
-/**
- * @brief Shutdown ADC
- * @param pADC : The base of ADC peripheral on the chip
- * @return Nothing
- */
-void Chip_ADC_DeInit(LPC_ADC_T *pADC);
-
-/**
- * @brief Initialize the ADC peripheral and the ADC setup structure to default value
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be set
- * @return Nothing
- * @note Default setting for ADC is 400kHz - 10bits
- */
-void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup);
-
-/**
- * @brief Select the mode starting the AD conversion
- * @param pADC : The base of ADC peripheral on the chip
- * @param mode : Stating mode, should be :
- * - ADC_NO_START : Must be set for Burst mode
- * - ADC_START_NOW : Start conversion now
- * - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
- * - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
- * - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
- * - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
- * - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
- * @param EdgeOption : Stating Edge Condition, should be :
- * - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
- * - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
- * @return Nothing
- */
-void Chip_ADC_Set_StartMode(LPC_ADC_T *pADC, CHIP_ADC_START_MODE_T mode, CHIP_ADC_EDGE_CFG_T EdgeOption);
-
-/**
- * @brief Set the ADC Sample rate
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be modified
- * @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
- * @return Nothing
- */
-void Chip_ADC_Set_SampleRate(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup, uint32_t rate);
-
-/**
- * @brief Set the ADC accuracy bits
- * @param pADC : The base of ADC peripheral on the chip
- * @param ADCSetup : ADC setup structure to be modified
- * @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS
- * @return Nothing
- */
-void Chip_ADC_Set_Resolution(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup, CHIP_ADC_RESOLUTION_T resolution);
-
-/**
- * @brief Enable or disable the ADC channel on ADC peripheral
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel to be enable or disable
- * @param NewState : New state, should be:
- * - ENABLE
- * - DISABLE
- * @return Nothing
- */
-void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, FunctionalState NewState);
-
-/**
- * @brief Enable burst mode
- * @param pADC : The base of ADC peripheral on the chip
- * @param NewState : New state, should be:
- * - ENABLE
- * - DISABLE
- * @return Nothing
- */
-void Chip_ADC_Burst_Cmd(LPC_ADC_T *pADC, FunctionalState NewState);
-
-/**
- * @brief Read the ADC value and convert it to 8bits value
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel: selected channel
- * @param data : Storage for data
- * @return Status : ERROR or SUCCESS
- */
-Status Chip_ADC_Read_Byte(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, uint8_t *data);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ADC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/aes_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/aes_18xx_43xx.h
deleted file mode 100644
index c109f690f..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/aes_18xx_43xx.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * @brief LPC18xx/43xx AES Engine driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __AES_18XX_43XX_H_
-#define __AES_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup AES_18XX_43XX CHIP: LPC18xx/43xx AES Engine driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief AES Engine operation mode
- */
-typedef enum CHIP_AES_OP_MODE {
- CHIP_AES_API_CMD_ENCODE_ECB, /*!< ECB Encode mode */
- CHIP_AES_API_CMD_DECODE_ECB, /*!< ECB Decode mode */
- CHIP_AES_API_CMD_ENCODE_CBC, /*!< CBC Encode mode */
- CHIP_AES_API_CMD_DECODE_CBC, /*!< CBC Decode mode */
-} CHIP_AES_OP_MODE_T;
-
-/**
- * @brief Initialize the AES Engine function
- * @return None
- * This function will initialise all the AES Engine driver function pointers
- * and call the AES Engine Initialisation function.
- */
-void Chip_AES_Init(void);
-
-/**
- * @brief Set operation mode in AES Engine
- * @param AesMode : AES Operation Mode
- * @return Status
- */
-uint32_t Chip_AES_SetMode(CHIP_AES_OP_MODE_T AesMode);
-
-/**
- * @brief Load 128-bit AES user key in AES Engine
- * @param keyNum: 0 - Load AES 128-bit user key 1, else load user key2
- * @return None
- */
-void Chip_AES_LoadKey(uint32_t keyNum);
-
-/**
- * @brief Load randomly generated key in AES engine
- * @return None
- * To update the RNG and load a new random number,
- * the API call Chip_OTP_GenRand should be used
- */
-void Chip_AES_LoadKeyRNG(void);
-
-/**
- * @brief Load 128-bit AES software defined user key in AES Engine
- * @param pKey : Pointer to 16 byte user key
- * @return None
- */
-void Chip_AES_LoadKeySW(uint8_t *pKey);
-
-/**
- * @brief Load 128-bit AES initialization vector in AES Engine
- * @param pVector : Pointer to 16 byte Initialisation vector
- * @return None
- */
-void Chip_AES_LoadIV_SW(uint8_t *pVector);
-
-/**
- * @brief Load IC specific 128-bit AES initialization vector in AES Engine
- * @return None
- * This loads 128-bit AES IC specific initialization vector,
- * which is used to decrypt a boot image
- */
-void Chip_AES_LoadIV_IC(void);
-
-/**
- * @brief Operate AES Engine
- * @param pDatOut : Pointer to output data stream
- * @param pDatIn : Pointer to input data stream
- * @param Size : Size of the data stream (128-bit)
- * @return Status
- * This function performs the AES operation after the AES mode
- * has been set using Chip_AES_SetMode and the appropriate keys
- * and init vectors have been loaded
- */
-uint32_t Chip_AES_Operate(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t Size);
-
-/**
- * @brief Program 128-bit AES Key in OTP
- * @param KeyNum : Key Number (Select 0 or 1)
- * @param pKey : Pointer to AES Key (16 bytes required)
- * @return Status
- * When calling the aes_ProgramKey2 function, ensure that VPP = 2.7 V to 3.6 V.
- */
-uint32_t Chip_AES_ProgramKey(uint32_t KeyNum, uint8_t *pKey);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AES_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
deleted file mode 100644
index b54b6f837..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * @brief LPC18xx/43xx ATimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ATIMER_18XX_43XX_H_
-#define __ATIMER_18XX_43XX_H_
-
-/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize Alarm Timer
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @param PresetValue : Count of 1 to 1024s for Alarm
- * @return None
- */
-void Chip_ATIMER_Init(LPC_ATIMER_T *pATIMER, uint32_t PresetValue);
-
-/**
- * @brief Close ATIMER device
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_DeInit(LPC_ATIMER_T *pATIMER)
-{
- IP_ATIMER_DeInit(pATIMER);
-}
-
-/**
- * @brief Enable ATIMER Interrupt
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_IntEnable(LPC_ATIMER_T *pATIMER)
-{
- IP_ATIMER_IntEnable(pATIMER);
-}
-
-/**
- * @brief Disable ATIMER Interrupt
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_IntDisable(LPC_ATIMER_T *pATIMER)
-{
- IP_ATIMER_IntDisable(pATIMER);
-}
-
-/**
- * @brief Clear ATIMER Interrupt Status
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_ClearIntStatus(LPC_ATIMER_T *pATIMER)
-{
- IP_ATIMER_ClearIntStatus(pATIMER);
-}
-
-/**
- * @brief Set ATIMER Interrupt Status
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_ATIMER_SetIntStatus(LPC_ATIMER_T *pATIMER)
-{
- IP_ATIMER_SetIntStatus(pATIMER);
-}
-
-/**
- * @brief Update Preset value
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @param PresetValue : updated preset value
- * @return Nothing
- */
-STATIC INLINE void Chip_ATIMER_UpdatePresetValue(LPC_ATIMER_T *pATIMER, uint32_t PresetValue)
-{
- IP_ATIMER_UpdatePresetValue(pATIMER, PresetValue);
-}
-
-/**
- * @brief Read value of preset register
- * @param pATIMER : The base of ATIMER peripheral on the chip
- * @return Value of capture register
- */
-STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(LPC_ATIMER_T *pATIMER)
-{
- return IP_ATIMER_GetPresetValue(pATIMER);
-}
-
-/**
- * @}
- */
-
- #endif /* __ATIMER_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ccan_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ccan_18xx_43xx.h
deleted file mode 100644
index d0b1e71a7..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ccan_18xx_43xx.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * @brief LPC18xx/43xx CCAN driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CCAN_18XX_43XX_H_
-#define __CCAN_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CCAN_SEG1_DEFAULT_VAL 5
-#define CCAN_SEG2_DEFAULT_VAL 4
-#define CCAN_SJW_DEFAULT_VAL 0
-
-/** @defgroup CCAN_18XX_43XX CHIP: LPC18xx/43xx CCAN driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Enable/Disable CCAN Interrupts
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-STATIC INLINE void Chip_CCAN_IntEnable(LPC_CCAN_T *pCCAN, FunctionalState NewState)
-{
- IP_CCAN_IntEnable(pCCAN, (IP_CCAN_INT_T) (CCAN_MODULE_INT | CCAN_STATUS_CHANGE_INT | CCAN_ERR_INT), NewState);
-}
-
-/**
- * @brief Get the source ID of an interrupt
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return Interrupt source ID
- */
-STATIC INLINE uint32_t Chip_CCAN_GetIntID(LPC_CCAN_T *pCCAN)
-{
- return IP_CCAN_Get_IntID(pCCAN);
-}
-
-/**
- * @brief Get the CCAN status register
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return CCAN status register
- */
-STATIC INLINE uint32_t Chip_CCAN_GetStatus(LPC_CCAN_T *pCCAN)
-{
- return IP_CCAN_GetStatus(pCCAN);
-}
-
-/**
- * @brief Get a message object in message RAM into the message buffer
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param msg_num : The number of message object in message RAM to be get
- * @param msg_buf : Pointer of the message buffer
- * @return Nothing
- */
-STATIC INLINE void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, uint8_t msg_num, message_object *msg_buf)
-{
- IP_CCAN_GetMsgObject(LPC_C_CAN0, IF2, msg_num, msg_buf);
-}
-
-/**
- * @brief Initialize the CCAN peripheral, free all message object in RAM
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return Nothing
- */
-void Chip_CCAN_Init(LPC_CCAN_T *pCCAN);
-
-/**
- * @brief De-initialize the CCAN peripheral
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return Nothing
- */
-void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN);
-
-/**
- * @brief Select bit rate for CCAN bus
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param bitRate : Bit rate to be set
- * @return Nothing
- */
-void Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate);
-
-/**
- * @brief Clear the status of CCAN bus
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param status : Status to be cleared
- * @return Nothing
- */
-void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, IP_CCAN_STATUS_T status);
-
-/**
- * @brief Clear the pending interrupt
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param msg_num : Message number
- * @param TRxMode : Select transmit or receive interrupt to be cleared
- * @return Nothing
- */
-void Chip_CCAN_ClearIntPend(LPC_CCAN_T *pCCAN, uint8_t msg_num, uint8_t TRxMode);
-
-/**
- * @brief Send a message
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param RemoteEnable: Enable/Disable passives transmit by using remote frame
- * @param msg_ptr : Message to be transmitted
- * @return Nothing
- */
-void Chip_CCAN_Send (LPC_CCAN_T *pCCAN, uint32_t RemoteEnable, message_object *msg_ptr);
-
-/**
- * @brief Register a message ID for receiving
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param rev_id : Received message ID
- * @return Nothing
- */
-void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, uint32_t rev_id);
-
-/**
- * @brief Remove a registered message ID from receiving
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param rev_id : Received message ID to be removed
- * @return Nothing
- */
-void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, uint32_t rev_id);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CCAN_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
deleted file mode 100644
index 460d45b47..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * @brief CGU/CCU registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CGUCCU_18XX_43XX_H_
-#define __CGUCCU_18XX_43XX_H_
-
-#include "cmsis.h"
-#include "chip_clocks.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * Audio or USB PLL selection
- */
-typedef enum CHIP_CGU_USB_AUDIO_PLL {
- CGU_USB_PLL,
- CGU_AUDIO_PLL
-} CHIP_CGU_USB_AUDIO_PLL_T;
-
-/**
- * PLL register block
- */
-typedef struct {
- __I uint32_t PLL_STAT; /*!< PLL status register */
- __IO uint32_t PLL_CTRL; /*!< PLL control register */
- __IO uint32_t PLL_MDIV; /*!< PLL M-divider register */
- __IO uint32_t PLL_NP_DIV; /*!< PLL N/P-divider register */
-} CGU_PLL_REG_T;
-
-/**
- * @brief LPC18XX/43XX CGU register block structure
- */
-typedef struct { /*!< (@ 0x40050000) CGU Structure */
- __I uint32_t RESERVED0[5];
- __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */
- __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */
- CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /*!< (@ 0x4005001C) USB and audio PLL blocks */
- __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */
- __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */
- __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */
- __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
- __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */
-} LPC_CGU_T;
-
-/**
- * @brief CCU clock config/status register pair
- */
-typedef struct {
- __IO uint32_t CFG; /*!< CCU clock configuration register */
- __I uint32_t STAT; /*!< CCU clock status register */
-} CCU_CFGSTAT_T;
-
-/**
- * @brief CCU1 register block structure
- */
-typedef struct { /*!< (@ 0x40051000) CCU1 Structure */
- __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */
-} LPC_CCU1_T;
-
-/**
- * @brief CCU2 register block structure
- */
-typedef struct { /*!< (@ 0x40052000) CCU2 Structure */
- __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */
-} LPC_CCU2_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CGUCCU_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip.h
deleted file mode 100644
index b64f2d111..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * @brief Chip inclusion selector file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_H_
-#define __CHIP_H_
-
-#include "sys_config.h"
-
-#if defined(CHIP_LPC18XX)
-#include "chip_lpc18xx.h"
-
-#elif defined(CHIP_LPC43XX)
-#include "chip_lpc43xx.h"
-
-#else
-#error CHIP_LPC18XX or CHIP_LPC43XX must be defined
-#endif
-
-#endif /* __CHIP_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_clocks.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_clocks.h
deleted file mode 100644
index c9a8d2bc0..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_clocks.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_CLOCKS_H_
-#define __CHIP_CLOCKS_H_
-
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup CLOCK_18XX_43XX
- * @{
- */
-
-/**
- * @brief CGU clock input list
- * These are possible input clocks for the CGU and can come
- * from both external (crystal) and internal (PLL) sources. These
- * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).
- */
-typedef enum CHIP_CGU_CLKIN {
- CLKIN_32K, /*!< External 32KHz input */
- CLKIN_IRC, /*!< Internal IRC (12MHz) input */
- CLKIN_ENET_RX, /*!< External ENET_RX pin input */
- CLKIN_ENET_TX, /*!< External ENET_TX pin input */
- CLKIN_CLKIN, /*!< External GPCLKIN pin input */
- CLKIN_RESERVED1,
- CLKIN_CRYSTAL, /*!< External (main) crystal pin input */
- CLKIN_USBPLL, /*!< Internal USB PLL input */
- CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */
- CLKIN_MAINPLL, /*!< Internal Main PLL input */
- CLKIN_RESERVED2,
- CLKIN_RESERVED3,
- CLKIN_IDIVA, /*!< Internal divider A input */
- CLKIN_IDIVB, /*!< Internal divider B input */
- CLKIN_IDIVC, /*!< Internal divider C input */
- CLKIN_IDIVD, /*!< Internal divider D input */
- CLKIN_IDIVE, /*!< Internal divider E input */
- CLKINPUT_PD /*!< External 32KHz input */
-} CHIP_CGU_CLKIN_T;
-
-/**
- * @brief CGU base clocks
- * CGU base clocks are clocks that are associated with a single input clock
- * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
- * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
- * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
- * CLK_PERIPH_SGPIO periphral clocks.
- */
-typedef enum CHIP_CGU_BASE_CLK {
- CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */
- CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_PERIPH, /*!< Base clock for SGPIO */
-#else
- CLK_BASE_RESERVED1,
-#endif
- CLK_BASE_USB1, /*!< Base USB clock for USB1 */
- CLK_BASE_MX, /*!< Base clock for CPU core */
- CLK_BASE_SPIFI, /*!< Base clock for SPIFI */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_SPI, /*!< Base clock for SPI */
-#else
- CLK_BASE_RESERVED2,
-#endif
- CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */
- CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */
- CLK_BASE_APB1, /*!< Base clock for APB1 group */
- CLK_BASE_APB3, /*!< Base clock for APB3 group */
- CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */
-#if defined(CHIP_LPC43XX)
- CLK_BASE_VADC, /*!< Base clock for VADC */
-#else
- CLK_BASE_RESERVED3,
-#endif
- CLK_BASE_SDIO, /*!< Base clock for SDIO */
- CLK_BASE_SSP0, /*!< Base clock for SSP0 */
- CLK_BASE_SSP1, /*!< Base clock for SSP1 */
- CLK_BASE_UART0, /*!< Base clock for UART0 */
- CLK_BASE_UART1, /*!< Base clock for UART1 */
- CLK_BASE_UART2, /*!< Base clock for UART2 */
- CLK_BASE_UART3, /*!< Base clock for UART3 */
- CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */
- CLK_BASE_RESERVED4,
- CLK_BASE_RESERVED5,
- CLK_BASE_RESERVED6,
- CLK_BASE_RESERVED7,
- CLK_BASE_APLL, /*!< Base clock for audio PLL */
- CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */
- CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */
- CLK_BASE_LAST,
- CLK_BASE_NONE = CLK_BASE_LAST
-} CHIP_CGU_BASE_CLK_T;
-
-/**
- * @brief CGU dividers
- * CGU dividers provide an extra clock state where a specific clock can be
- * divided before being routed to a peripheral group. A divider accepts an
- * input clock and then divides it. To use the divided clock for a base clock
- * group, use the divider as the input clock for the base clock (for example,
- * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
- */
-typedef enum CHIP_CGU_IDIV {
- CLK_IDIV_A, /*!< CGU clock divider A */
- CLK_IDIV_B, /*!< CGU clock divider B */
- CLK_IDIV_C, /*!< CGU clock divider A */
- CLK_IDIV_D, /*!< CGU clock divider D */
- CLK_IDIV_E, /*!< CGU clock divider E */
- CLK_IDIV_LAST
-} CHIP_CGU_IDIV_T;
-
-/**
- * @brief Peripheral clocks
- * Peripheral clocks are individual clocks routed to peripherals. Although
- * multiple peripherals may share a same base clock, each peripheral's clock
- * can be enabled or disabled individually. Some peripheral clocks also have
- * additional dividers associated with them.
- */
-typedef enum CHIP_CCU_CLK {
- /* CCU1 clocks */
- CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */
- CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
- CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
- CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
- CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */
- CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */
- CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */
- CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */
- CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */
- CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */
- CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */
- CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
- RESERVED_ALIGN = CLK_MX_MXCORE + 3,
- CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */
- CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */
- CLK_MX_VADC, /*!< VADC clock from base clock CLK_BASE_MX */
-#else
- CLK_RESERVED1,
- CLK_RESERVED2,
-#endif
- CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */
- CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */
- CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */
- CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */
- CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */
- CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
-#if defined(CHIP_LPC43XX)
- CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
- CLK_RESERVED3,
- CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
- CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */
-#else
- CLK_RESERVED3 = 192,
- CLK_RESERVED3A,
- CLK_RESERVED4,
- CLK_RESERVED5,
-#endif
- CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */
- CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */
-#if defined(CHIP_LPC43XX)
- CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */
- CLK_VADC, /*!< VADC clock from base clock CLK_BASE_VADC */
-#else
- CLK_RESERVED7 = 320,
- CLK_RESERVED8,
-#endif
- CLK_CCU1_LAST,
-
- /* CCU2 clocks */
- CLK_CCU2_START,
- CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */
- RESERVED_ALIGNB = CLK_CCU2_START + 31,
- CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */
- RESERVED_ALIGNC = CLK_CCU2_START + 63,
- CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */
- RESERVED_ALIGND = CLK_CCU2_START + 95,
- CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */
- RESERVED_ALIGNE = CLK_CCU2_START + 127,
- CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */
- RESERVED_ALIGNF = CLK_CCU2_START + 159,
- CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */
- RESERVED_ALIGNG = CLK_CCU2_START + 191,
- CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */
- RESERVED_ALIGNH = CLK_CCU2_START + 223,
- CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */
- CLK_CCU2_LAST
-} CHIP_CCU_CLK_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_CLOCKS_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
deleted file mode 100644
index 845743f1e..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * @brief LPC18xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC18XX_H_
-#define __CHIP_LPC18XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifndef CORE_M3
-#error CORE_M3 is not defined for the LPC18xx architecture
-#error CORE_M3 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC18XX
-#error The LPC18XX Chip include path is used for this build, but
-#error CHIP_LPC18XX is not defined!
-#endif
-
-/** @defgroup IP_LPC18XX_FILES CHIP: LPC18XX Chip layer required IP layer drivers
- * @ingroup CHIP_18XX_43XX_Drivers
- * This is a list of the IP drivers required for the LPC18XX device family.
- * (adc_001.c, adc_001.h) @ref IP_ADC_001
- * (atimer_001.c, atimer_001.h) @ref IP_ATIMER_001
- * (ccan_001.c, ccan_001.h) @ref IP_CCAN_001
- * (dac_001.c, dac_001.h) @ref IP_DAC_001
- * (emc_001.c, emc_001.h) @ref IP_EMC_001
- * (enet_001.c, enet_001.h) @ref IP_ENET_001
- * (gima_001.h) @ref IP_GIMA_001
- * (gpdma_001.c, gpdma_001.h) @ref IP_GPDMA_001
- * (gpiogrpint_001.c, gpiogrpint_001.h) @ref IP_GPIOGRPINT_001
- * (gpiopinint_001.c, gpiopinint_001.h) @ref IP_GPIOPININT_001
- * (gpio_001.h) @ref IP_GPIO_001
- * (i2c_001.c, i2c_001.h) @ref IP_I2C_001
- * (i2s_001.c, i2s_001.h) @ref IP_I2S_001
- * (lcd_001.c, lcd_001.h) @ref IP_LCD_001
- * (mcpwm_001.h) @ref IP_MCPWM_001
- * (pmc_001.h) @ref IP_PMC_001
- * (qei_001.h) @ref IP_QEI_001
- * (regfile_001.h) @ref IP_REGFILE_001
- * (ritimer_001.c, ritimer_001.h) @ref IP_RITIMER_001
- * (rtc_001.c, rtc_001.h) @ref IP_RTC_001
- * (sct_001.c, sct_001.h) @ref IP_SCT_001
- * (sdmmc_001.c, sdmmc_001.h) @ref IP_SDMMC_001
- * (ssp_001.c, ssp_001.h) @ref IP_SSP_001
- * (timer_001.c, timer_001.h) @ref IP_TIMER_001
- * (usart_001.c, usart_001.h) @ref IP_USART_001
- * (usbhs_001.h) @ref IP_USBHS_001
- * (wwdt_001.c, wwdt_001.h) @ref IP_WWDT_001
- * (eeprom_002.c, eeprom_002.h) @ref IP_EEPROM_002
- * @{
- */
-
-/**
- * @}
- */
-
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-#include "eeprom_002.h"
-
-/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE 0x40000000
-#define LPC_GPDMA_BASE 0x40002000
-#define LPC_SDMMC_BASE 0x40004000
-#define LPC_EMC_BASE 0x40005000
-#define LPC_USB0_BASE 0x40006000
-#define LPC_USB1_BASE 0x40007000
-#define LPC_LCD_BASE 0x40008000
-#define LPC_ETHERNET_BASE 0x40010000
-#define LPC_ATIMER_BASE 0x40040000
-#define LPC_REGFILE_BASE 0x40041000
-#define LPC_PMC_BASE 0x40042000
-#define LPC_CREG_BASE 0x40043000
-#define LPC_EVRT_BASE 0x40044000
-#define LPC_OTP_BASE 0x40045000
-#define LPC_RTC_BASE 0x40046000
-#define LPC_CGU_BASE 0x40050000
-#define LPC_CCU1_BASE 0x40051000
-#define LPC_CCU2_BASE 0x40052000
-#define LPC_RGU_BASE 0x40053000
-#define LPC_WWDT_BASE 0x40080000
-#define LPC_USART0_BASE 0x40081000
-#define LPC_USART2_BASE 0x400C1000
-#define LPC_USART3_BASE 0x400C2000
-#define LPC_UART1_BASE 0x40082000
-#define LPC_SSP0_BASE 0x40083000
-#define LPC_SSP1_BASE 0x400C5000
-#define LPC_TIMER0_BASE 0x40084000
-#define LPC_TIMER1_BASE 0x40085000
-#define LPC_TIMER2_BASE 0x400C3000
-#define LPC_TIMER3_BASE 0x400C4000
-#define LPC_SCU_BASE 0x40086000
-#define LPC_GPIO_PIN_INT_BASE 0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-#define LPC_MCPWM_BASE 0x400A0000
-#define LPC_I2C0_BASE 0x400A1000
-#define LPC_I2C1_BASE 0x400E0000
-#define LPC_I2S0_BASE 0x400A2000
-#define LPC_I2S1_BASE 0x400A3000
-#define LPC_C_CAN1_BASE 0x400A4000
-#define LPC_RITIMER_BASE 0x400C0000
-#define LPC_QEI_BASE 0x400C6000
-#define LPC_GIMA_BASE 0x400C7000
-#define LPC_DAC_BASE 0x400E1000
-#define LPC_C_CAN0_BASE 0x400E2000
-#define LPC_ADC0_BASE 0x400E3000
-#define LPC_ADC1_BASE 0x400E4000
-#define LPC_GPIO_PORT_BASE 0x400F4000
-#define LPC_SPI_BASE 0x40100000
-#define LPC_SGPIO_BASE 0x40101000
-#define LPC_EEPROM_BASE 0x4000E000
-
-/* Normalize types */
-typedef IP_SCT_001_T LPC_SCT_T;
-typedef IP_GPDMA_001_T LPC_GPDMA_T;
-typedef IP_SDMMC_001_T LPC_SDMMC_T;
-typedef IP_EMC_001_T LPC_EMC_T;
-typedef IP_USBHS_001_T LPC_USBHS_T;
-typedef IP_ENET_001_T LPC_ENET_T;
-typedef IP_ATIMER_001_T LPC_ATIMER_T;
-typedef IP_REGFILE_001_T LPC_REGFILE_T;
-typedef IP_PMC_001_T LPC_PMC_T;
-typedef IP_RTC_001_T LPC_RTC_T;
-typedef IP_WWDT_001_T LPC_WWDT_T;
-typedef IP_USART_001_T LPC_USART_T;
-typedef IP_SSP_001_T LPC_SSP_T;
-typedef IP_TIMER_001_T LPC_TIMER_T;
-typedef IP_GPIOPININT_001_T LPC_GPIOPININT_T;
-typedef IP_MCPWM_001_T LPC_MCPWM_T;
-typedef IP_I2C_001_T LPC_I2C_T;
-typedef IP_I2S_001_T LPC_I2S_T;
-typedef IP_CCAN_001_T LPC_CCAN_T;
-typedef IP_RITIMER_001_T LPC_RITIMER_T;
-typedef IP_QEI_001_T LPC_QEI_T;
-typedef IP_GIMA_001_T LPC_GIMA_T;
-typedef IP_DAC_001_T LPC_DAC_T;
-typedef IP_ADC_001_T LPC_ADC_T;
-typedef IP_GPIO_001_T LPC_GPIO_T;
-typedef IP_LCD_001_T LPC_LCD_T;
-typedef IP_EEPROM_002_T LPC_EEPROM_T;
-
-#define LPC_SCT ((IP_SCT_001_T *) LPC_SCT_BASE)
-#define LPC_GPDMA ((IP_GPDMA_001_T *) LPC_GPDMA_BASE)
-#define LPC_SDMMC ((IP_SDMMC_001_T *) LPC_SDMMC_BASE)
-#define LPC_EMC ((IP_EMC_001_T *) LPC_EMC_BASE)
-#define LPC_USB0 ((IP_USBHS_001_T *) LPC_USB0_BASE)
-#define LPC_USB1 ((IP_USBHS_001_T *) LPC_USB1_BASE)
-#define LPC_LCD ((IP_LCD_001_T *) LPC_LCD_BASE)
-#define LPC_ETHERNET ((IP_ENET_001_T *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((IP_ATIMER_001_T *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((IP_PMC_001_T *) LPC_PMC_BASE)
-#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
-#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((IP_WWDT_001_T *) LPC_WWDT_BASE)
-#define LPC_USART0 ((IP_USART_001_T *) LPC_USART0_BASE)
-#define LPC_USART2 ((IP_USART_001_T *) LPC_USART2_BASE)
-#define LPC_USART3 ((IP_USART_001_T *) LPC_USART3_BASE)
-#define LPC_UART1 ((IP_USART_001_T *) LPC_UART1_BASE)
-#define LPC_SSP0 ((IP_SSP_001_T *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((IP_SSP_001_T *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((IP_TIMER_001_T *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((IP_TIMER_001_T *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((IP_TIMER_001_T *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((IP_TIMER_001_T *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_T *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((IP_MCPWM_001_T *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((IP_I2C_001_T *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((IP_I2C_001_T *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((IP_I2S_001_T *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((IP_I2S_001_T *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((IP_CCAN_001_T *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((IP_RITIMER_001_T *) LPC_RITIMER_BASE)
-#define LPC_QEI ((IP_QEI_001_T *) LPC_QEI_BASE)
-#define LPC_GIMA ((IP_GIMA_001_T *) LPC_GIMA_BASE)
-#define LPC_DAC ((IP_DAC_001_T *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((IP_CCAN_001_T *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((IP_ADC_001_T *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((IP_ADC_001_T *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((IP_GPIO_001_T *) LPC_GPIO_PORT_BASE)
-#define LPC_EEPROM ((IP_EEPROM_002_T *) LPC_EEPROM_BASE)
-
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "dac_18xx_43xx.h"
-#include "sdif_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "creg_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-#include "sct_18xx_43xx.h"
-#include "ccan_18xx_43xx.h"
-#include "pmc_18xx_43xx.h"
-#include "otp_18xx_43xx.h"
-#include "aes_18xx_43xx.h"
-#include "eeprom_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC18XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
deleted file mode 100644
index 41e376489..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * @brief LPC43xx basic chip inclusion file
- *
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CHIP_LPC43XX_H_
-#define __CHIP_LPC43XX_H_
-
-#include "lpc_types.h"
-#include "sys_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(CORE_M4) && !defined(CORE_M0)
-#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture
-#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list
-#endif
-
-#ifndef CHIP_LPC43XX
-#error The LPC43XX Chip include path is used for this build, but
-#error CHIP_LPC43XX is not defined!
-#endif
-
-/** @defgroup IP_LPC43XX_FILES CHIP: LPC43XX Chip layer required IP layer drivers
- * @ingroup CHIP_18XX_43XX_Drivers
- * This is a list of the IP drivers required for the LPC43XX device family.
- * (adc_001.c, adc_001.h) @ref IP_ADC_001
- * (atimer_001.c, atimer_001.h) @ref IP_ATIMER_001
- * (ccan_001.c, ccan_001.h) @ref IP_CCAN_001
- * (dac_001.c, dac_001.h) @ref IP_DAC_001
- * (emc_001.c, emc_001.h) @ref IP_EMC_001
- * (enet_001.c, enet_001.h) @ref IP_ENET_001
- * (gima_001.h) @ref IP_GIMA_001
- * (gpdma_001.c, gpdma_001.h) @ref IP_GPDMA_001
- * (gpiogrpint_001.c, gpiogrpint_001.h) @ref IP_GPIOGRPINT_001
- * (gpiopinint_001.c, gpiopinint_001.h) @ref IP_GPIOPININT_001
- * (gpio_001.h) @ref IP_GPIO_001
- * (i2c_001.c, i2c_001.h) @ref IP_I2C_001
- * (i2s_001.c, i2s_001.h) @ref IP_I2S_001
- * (lcd_001.c, lcd_001.h) @ref IP_LCD_001
- * (mcpwm_001.h) @ref IP_MCPWM_001
- * (pmc_001.h) @ref IP_PMC_001
- * (qei_001.h) @ref IP_QEI_001
- * (regfile_001.h) @ref IP_REGFILE_001
- * (ritimer_001.c, ritimer_001.h) @ref IP_RITIMER_001
- * (rtc_001.c, rtc_001.h) @ref IP_RTC_001
- * (sct_001.c, sct_001.h) @ref IP_SCT_001
- * (sdmmc_001.c, sdmmc_001.h) @ref IP_SDMMC_001
- * (sgpio_001.h) @ref IP_SGPIO_001
- * (spi_001.h) @ref IP_SPI_001
- * (ssp_001.c, ssp_001.h) @ref IP_SSP_001
- * (timer_001.c, timer_001.h) @ref IP_TIMER_001
- * (usart_001.c, usart_001.h) @ref IP_USART_001
- * (usbhs_001.h) @ref IP_USBHS_001
- * (wwdt_001.c, wwdt_001.h) @ref IP_WWDT_001
- * (eeprom_002.c, eeprom_002.h) @ref IP_EEPROM_002
- * @{
- */
-
-/**
- * @}
- */
-
-
-#include "adc_001.h"
-#include "atimer_001.h"
-#include "ccan_001.h"
-#include "dac_001.h"
-#include "emc_001.h"
-#include "enet_001.h"
-#include "gima_001.h"
-#include "gpdma_001.h"
-#include "gpiogrpint_001.h"
-#include "gpiopinint_001.h"
-#include "gpio_001.h"
-#include "i2c_001.h"
-#include "i2s_001.h"
-#include "lcd_001.h"
-#include "mcpwm_001.h"
-#include "pmc_001.h"
-#include "qei_001.h"
-#include "regfile_001.h"
-#include "ritimer_001.h"
-#include "rtc_001.h"
-#include "sct_001.h"
-#include "sdmmc_001.h"
-#include "sgpio_001.h"
-#include "spi_001.h"
-#include "ssp_001.h"
-#include "timer_001.h"
-#include "usart_001.h"
-#include "usbhs_001.h"
-#include "wwdt_001.h"
-#include "rgu_18xx_43xx.h"
-#include "cguccu_18xx_43xx.h"
-#include "eeprom_002.h"
-
-/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define LPC_SCT_BASE 0x40000000
-#define LPC_GPDMA_BASE 0x40002000
-#define LPC_SDMMC_BASE 0x40004000
-#define LPC_EMC_BASE 0x40005000
-#define LPC_USB0_BASE 0x40006000
-#define LPC_USB1_BASE 0x40007000
-#define LPC_LCD_BASE 0x40008000
-#define LPC_ETHERNET_BASE 0x40010000
-#define LPC_ATIMER_BASE 0x40040000
-#define LPC_REGFILE_BASE 0x40041000
-#define LPC_PMC_BASE 0x40042000
-#define LPC_CREG_BASE 0x40043000
-#define LPC_EVRT_BASE 0x40044000
-#define LPC_RTC_BASE 0x40046000
-#define LPC_CGU_BASE 0x40050000
-#define LPC_CCU1_BASE 0x40051000
-#define LPC_CCU2_BASE 0x40052000
-#define LPC_RGU_BASE 0x40053000
-#define LPC_WWDT_BASE 0x40080000
-#define LPC_USART0_BASE 0x40081000
-#define LPC_USART2_BASE 0x400C1000
-#define LPC_USART3_BASE 0x400C2000
-#define LPC_UART1_BASE 0x40082000
-#define LPC_SSP0_BASE 0x40083000
-#define LPC_SSP1_BASE 0x400C5000
-#define LPC_TIMER0_BASE 0x40084000
-#define LPC_TIMER1_BASE 0x40085000
-#define LPC_TIMER2_BASE 0x400C3000
-#define LPC_TIMER3_BASE 0x400C4000
-#define LPC_SCU_BASE 0x40086000
-#define LPC_GPIO_PIN_INT_BASE 0x40087000
-#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-#define LPC_MCPWM_BASE 0x400A0000
-#define LPC_I2C0_BASE 0x400A1000
-#define LPC_I2C1_BASE 0x400E0000
-#define LPC_I2S0_BASE 0x400A2000
-#define LPC_I2S1_BASE 0x400A3000
-#define LPC_C_CAN1_BASE 0x400A4000
-#define LPC_RITIMER_BASE 0x400C0000
-#define LPC_QEI_BASE 0x400C6000
-#define LPC_GIMA_BASE 0x400C7000
-#define LPC_DAC_BASE 0x400E1000
-#define LPC_C_CAN0_BASE 0x400E2000
-#define LPC_ADC0_BASE 0x400E3000
-#define LPC_ADC1_BASE 0x400E4000
-#define LPC_GPIO_PORT_BASE 0x400F4000
-#define LPC_SPI_BASE 0x40100000
-#define LPC_SGPIO_BASE 0x40101000
-#define LPC_EEPROM_BASE 0x4000E000
-
-/* Normalize types */
-typedef IP_SCT_001_T LPC_SCT_T;
-typedef IP_GPDMA_001_T LPC_GPDMA_T;
-typedef IP_SDMMC_001_T LPC_SDMMC_T;
-typedef IP_EMC_001_T LPC_EMC_T;
-typedef IP_USBHS_001_T LPC_USBHS_T;
-typedef IP_ENET_001_T LPC_ENET_T;
-typedef IP_ATIMER_001_T LPC_ATIMER_T;
-typedef IP_REGFILE_001_T LPC_REGFILE_T;
-typedef IP_PMC_001_T LPC_PMC_T;
-typedef IP_RTC_001_T LPC_RTC_T;
-typedef IP_WWDT_001_T LPC_WWDT_T;
-typedef IP_USART_001_T LPC_USART_T;
-typedef IP_SSP_001_T LPC_SSP_T;
-typedef IP_TIMER_001_T LPC_TIMER_T;
-typedef IP_GPIOPININT_001_T LPC_GPIOPININT_T;
-typedef IP_MCPWM_001_T LPC_MCPWM_T;
-typedef IP_I2C_001_T LPC_I2C_T;
-typedef IP_I2S_001_T LPC_I2S_T;
-typedef IP_CCAN_001_T LPC_CCAN_T;
-typedef IP_RITIMER_001_T LPC_RITIMER_T;
-typedef IP_QEI_001_T LPC_QEI_T;
-typedef IP_GIMA_001_T LPC_GIMA_T;
-typedef IP_DAC_001_T LPC_DAC_T;
-typedef IP_ADC_001_T LPC_ADC_T;
-typedef IP_GPIO_001_T LPC_GPIO_T;
-typedef IP_SPI_001_T LPC_SPI_T;
-typedef IP_SGPIO_001_T LPC_SGPIO_T;
-typedef IP_LCD_001_T LPC_LCD_T;
-typedef IP_EEPROM_002_T LPC_EEPROM_T;
-
-#define LPC_SCT ((IP_SCT_001_T *) LPC_SCT_BASE)
-#define LPC_GPDMA ((IP_GPDMA_001_T *) LPC_GPDMA_BASE)
-#define LPC_SDMMC ((IP_SDMMC_001_T *) LPC_SDMMC_BASE)
-#define LPC_EMC ((IP_EMC_001_T *) LPC_EMC_BASE)
-#define LPC_USB0 ((IP_USBHS_001_T *) LPC_USB0_BASE)
-#define LPC_USB1 ((IP_USBHS_001_T *) LPC_USB1_BASE)
-#define LPC_LCD ((IP_LCD_001_T *) LPC_LCD_BASE)
-#define LPC_ETHERNET ((IP_ENET_001_T *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((IP_ATIMER_001_T *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((IP_PMC_001_T *) LPC_PMC_BASE)
-#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
-#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((IP_WWDT_001_T *) LPC_WWDT_BASE)
-#define LPC_USART0 ((IP_USART_001_T *) LPC_USART0_BASE)
-#define LPC_USART2 ((IP_USART_001_T *) LPC_USART2_BASE)
-#define LPC_USART3 ((IP_USART_001_T *) LPC_USART3_BASE)
-#define LPC_UART1 ((IP_USART_001_T *) LPC_UART1_BASE)
-#define LPC_SSP0 ((IP_SSP_001_T *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((IP_SSP_001_T *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((IP_TIMER_001_T *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((IP_TIMER_001_T *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((IP_TIMER_001_T *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((IP_TIMER_001_T *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_T *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((IP_MCPWM_001_T *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((IP_I2C_001_T *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((IP_I2C_001_T *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((IP_I2S_001_T *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((IP_I2S_001_T *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((IP_CCAN_001_T *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((IP_RITIMER_001_T *) LPC_RITIMER_BASE)
-#define LPC_QEI ((IP_QEI_001_T *) LPC_QEI_BASE)
-#define LPC_GIMA ((IP_GIMA_001_T *) LPC_GIMA_BASE)
-#define LPC_DAC ((IP_DAC_001_T *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((IP_CCAN_001_T *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((IP_ADC_001_T *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((IP_ADC_001_T *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((IP_GPIO_001_T *) LPC_GPIO_PORT_BASE)
-#define LPC_SPI ((IP_SPI_001_T *) LPC_SPI_BASE)
-#define LPC_SGPIO ((IP_SGPIO_001_T *) LPC_SGPIO_BASE)
-#define LPC_EEPROM ((IP_EEPROM_002_T *) LPC_EEPROM_BASE)
-/**
- * @}
- */
-
-#include "clock_18xx_43xx.h"
-#include "gpio_18xx_43xx.h"
-#include "scu_18xx_43xx.h"
-#include "sct_18xx_43xx.h"
-#include "uart_18xx_43xx.h"
-#include "gpdma_18xx_43xx.h"
-#include "enet_18xx_43xx.h"
-#include "rgu_18xx_43xx.h"
-#include "i2c_18xx_43xx.h"
-#include "i2s_18xx_43xx.h"
-#include "ssp_18xx_43xx.h"
-#include "rtc_18xx_43xx.h"
-#include "evrt_18xx_43xx.h"
-#include "atimer_18xx_43xx.h"
-#include "wwdt_18xx_43xx.h"
-#include "ritimer_18xx_43xx.h"
-#include "emc_18xx_43xx.h"
-#include "lcd_18xx_43xx.h"
-#include "adc_18xx_43xx.h"
-#include "dac_18xx_43xx.h"
-#include "timer_18xx_43xx.h"
-#include "sdif_18xx_43xx.h"
-#include "sdmmc_18xx_43xx.h"
-#include "fpu_init.h"
-#include "creg_18xx_43xx.h"
-#include "ccan_18xx_43xx.h"
-#include "pmc_18xx_43xx.h"
-#include "otp_18xx_43xx.h"
-#include "aes_18xx_43xx.h"
-#include "eeprom_18xx_43xx.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CHIP_LPC43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
deleted file mode 100644
index 2fb48c904..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "chip.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/* Maps a peripheral clock to it's base clock */
-typedef struct {
- CHIP_CCU_CLK_T clkstart;
- CHIP_CCU_CLK_T clkend;
- CHIP_CGU_BASE_CLK_T clkbase;
-} CLK_PERIPH_TO_BASE_T;
-static const CLK_PERIPH_TO_BASE_T periph_to_base[] = {
- {CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},
- {CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},
- {CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},
- {CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},
-#if 0
-#if defined(CHIP_LPC43XX)
- {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
-#endif
- {CLK_USB0, CLK_USB0, CLK_BASE_USB0},
- {CLK_USB1, CLK_USB1, CLK_BASE_USB1},
-#if defined(CHIP_LPC43XX)
- {CLK_SPI, CLK_SPI, CLK_BASE_SPI},
- {CLK_VADC, CLK_VADC, CLK_BASE_VADC},
-#endif
- {CLK_APLL, CLK_APLL, CLK_BASE_APLL},
- {CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},
- {CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},
- {CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1},
- {CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0},
- {CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},
- {CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0},
- {CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},
- {CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}
-#endif
-};
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/* Test PLL input values for a specific frequency range */
-static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)
-{
- uint32_t TestHz = TestMult * InputHz;
-
- if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
- TestHz = 0;
- }
-
- return TestHz;
-}
-
-/* Returns clock rate out of a divider */
-static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)
-{
- CHIP_CGU_CLKIN_T input;
- uint32_t div;
-
- input = Chip_Clock_GetDividerSource(divider);
- div = Chip_Clock_GetDividerDivisor(divider);
- return Chip_Clock_GetClockInputHz(input) / (div + 1);
-}
-
-/* Finds the base clock for the peripheral clock */
-static CHIP_CGU_BASE_CLK_T Chip_Clock_FindBaseClock(CHIP_CCU_CLK_T clk)
-{
- CHIP_CGU_BASE_CLK_T baseclk = CLK_BASE_NONE;
- int i = 0;
-
- while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
- if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
- baseclk = periph_to_base[i].clkbase;
- }
- else {
- i++;
- }
- }
-
- return baseclk;
-}
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Enables the crystal oscillator */
-void Chip_Clock_EnableCrystal(void)
-{
- uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL;
-
- /* Clear bypass mode */
- OldCrystalConfig &= (~2);
- if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) {
- LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
- }
-
- /* Enable crystal oscillator */
- OldCrystalConfig &= (~1);
- if (CRYSTAL_MAIN_FREQ_IN >= 20000000) {
- OldCrystalConfig |= 4; /* Set high frequency mode */
-
- }
- LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
-}
-
-/* Disables the crystal oscillator */
-void Chip_Clock_DisableCrystal(void)
-{
- /* Disable crystal oscillator */
- LPC_CGU->XTAL_OSC_CTRL &= (~1);
-}
-
-/* Configures the main PLL */
-uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
-{
- uint32_t freqin = Chip_Clock_GetClockInputHz(Input);
- uint32_t Mult, LastMult, MultEnd;
- uint32_t freqout, freqout2;
-
- if (DesiredHz != 0xFFFFFFFF) {
- /* Test DesiredHz rounded down */
- Mult = DesiredHz / freqin;
- freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- /* Test DesiredHz rounded up */
- Mult++;
- freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- if (freqout && !freqout2) { /* rounding up is no good? set first multiplier */
- Mult--;
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- if (!freqout && freqout2) { /* didn't work until rounded up? set 2nd multiplier */
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
-
- if (freqout && freqout2) { /* either multiplier okay? choose closer one */
- if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
- Mult--;
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- else {
- return Chip_Clock_SetupMainPLLMult(Input, Mult);
- }
- }
- }
-
- /* Neither multiplier okay? Try to start at MinHz and increment.
- This should find the highest multiplier that is still good */
- Mult = MinHz / freqin;
- MultEnd = MaxHz / freqin;
- LastMult = 0;
- while (1) {
- freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);
-
- if (freqout) {
- LastMult = Mult;
- }
-
- if (Mult >= MultEnd) {
- break;
- }
- Mult++;
- }
-
- if (LastMult) {
- return Chip_Clock_SetupMainPLLMult(Input, LastMult);
- }
-
- return 0;
-}
-
-/* Directly set the PLL multipler */
-uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult)
-{
- uint32_t freq = Chip_Clock_GetClockInputHz(Input);
- uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
- uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
-
- freq *= mult;
- msel = mult - 1;
-
- PLLReg &= ~(0x1F << 24);/* clear input source bits */
- PLLReg |= Input << 24; /* set input source bits to parameter */
-
- /* Clear other PLL input bits */
- PLLReg &= ~((1 << 6) | /* FBSEL */
- (1 << 1) | /* BYPASS */
- (1 << 7) | /* DIRECT */
- (0x03 << 8) | (0xFF << 16) | (0x03 << 12)); /* PSEL, MSEL, NSEL- divider ratios */
-
- if (freq < 156000000) {
- /* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */
- while ((2 * (pval) * freq) < 156000000) {
- psel++;
- pval *= 2;
- }
-
- PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6); /* dividers + FBSEL */
- }
- else if (freq < 320000000) {
- PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6); /* dividers + DIRECT + FBSEL */
- }
- else {
- Chip_Clock_DisableMainPLL();
- return 0;
- }
- LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
-
- return freq;
-}
-
-/* Returns the frequency of the main PLL */
-uint32_t Chip_Clock_GetMainPLLHz(void)
-{
- uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
- uint32_t freq = Chip_Clock_GetClockInputHz((CHIP_CGU_CLKIN_T) ((PLLReg >> 24) & 0xF));
- uint32_t msel, nsel, psel, direct, fbsel;
- uint32_t m, n, p;
- const uint8_t ptab[] = {1, 2, 4, 8};
-
- /* No lock? */
- if (!(LPC_CGU->PLL1_STAT & 1)) {
- return 0;
- }
-
- msel = (PLLReg >> 16) & 0xFF;
- nsel = (PLLReg >> 12) & 0x3;
- psel = (PLLReg >> 8) & 0x3;
- direct = (PLLReg >> 7) & 0x1;
- fbsel = (PLLReg >> 6) & 0x1;
-
- m = msel + 1;
- n = nsel + 1;
- p = ptab[psel];
-
- if (direct || fbsel) {
- return m * (freq / n);
- }
-
- return (m / (2 * p)) * (freq / n);
-}
-
-/* Disables the main PLL */
-void Chip_Clock_DisableMainPLL(void)
-{
- /* power down main PLL */
- LPC_CGU->PLL1_CTRL |= 1;
-}
-
-/* Disables the main PLL */
-void Chip_Clock_EnableMainPLL(void)
-{
- /* power down main PLL */
- LPC_CGU->PLL1_CTRL &= ~1;
-}
-
-/* Returns the lock status of the main PLL */
-bool Chip_Clock_MainPLLLocked(void)
-{
- /* Return true if locked */
- return (bool) (LPC_CGU->PLL1_STAT & 1);
-}
-
-/* Sets up a CGU clock divider and it's input clock */
-void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor)
-{
- uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
- Divisor--;
-
- if (Input != CLKINPUT_PD) {
- /* Mask off bits that need to changes */
- reg &= ~((0x1F << 24) | 1 | (0xF << 2));
-
- /* Enable autoblocking, clear PD, and set clock source & divisor */
- LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
- }
- else {
- LPC_CGU->IDIV_CTRL[Divider] = reg | 1; /* Power down this divider */
- }
-}
-
-/* Gets a CGU clock divider source */
-CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider)
-{
- uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];
-
- if (reg & 1) { /* divider is powered down */
- return CLKINPUT_PD;
- }
-
- return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Gets a CGU clock divider divisor */
-uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider)
-{
- return (CHIP_CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF);
-}
-
-/* Returns the frequency of the specified input clock source */
-uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input)
-{
- uint32_t rate = 0;
-
- switch (input) {
- case CLKIN_32K:
- rate = CRYSTAL_32K_FREQ_IN;
- break;
-
- case CLKIN_IRC:
- rate = CGU_IRC_FREQ;
- break;
-
- case CLKIN_ENET_RX:
-#if defined(USE_RMII)
- /* In RMII mode, this clock is not attached */
-#else
- /* MII mode requires 25MHz clock */
- rate = 25000000;
-#endif
- break;
-
- case CLKIN_ENET_TX:
-#if defined(USE_RMII)
- /* MII mode requires 50MHz clock */
- rate = 50000000;
-#else
- /* MII mode requires 25MHz clock */
- rate = 25000000;
-#endif
- break;
-
- case CLKIN_CLKIN:
-#if defined(EXTERNAL_CLKIN_FREQ_IN)
- rate = EXTERNAL_CLKIN_FREQ_IN;
-#else
- /* Assume no clock in if a rate wasn't defined */
-#endif
- break;
-
- case CLKIN_CRYSTAL:
- rate = CRYSTAL_MAIN_FREQ_IN;
- break;
-
- case CLKIN_USBPLL:
- rate = CGU_USB_PLL_RATE;
- break;
-
- case CLKIN_AUDIOPLL:
- rate = CGU_AUDIO_PLL_RATE;
- break;
-
- case CLKIN_MAINPLL:
- rate = Chip_Clock_GetMainPLLHz();
- break;
-
- case CLKIN_IDIVA:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A);
- break;
-
- case CLKIN_IDIVB:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B);
- break;
-
- case CLKIN_IDIVC:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C);
- break;
-
- case CLKIN_IDIVD:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D);
- break;
-
- case CLKIN_IDIVE:
- rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E);
- break;
-
- case CLKINPUT_PD:
- rate = 0;
- break;
-
- default:
- break;
- }
-
- return rate;
-}
-
-/* Returns the frequency of the specified base clock source */
-uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock)
-{
- return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock));
-}
-
-/* Sets a CGU Base Clock clock source */
-void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
-{
- uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
-
- if (BaseClock < CLK_BASE_NONE) {
- if (Input != CLKINPUT_PD) {
- /* Mask off fields we plan to update */
- reg &= ~((0x1F << 24) | 1 | (1 << 11));
-
- if (autoblocken) {
- reg |= (1 << 11);
- }
- if (powerdn) {
- reg |= (1 << 0);
- }
-
- /* Set clock source */
- reg |= (Input << 24);
-
- LPC_CGU->BASE_CLK[BaseClock] = reg;
- }
- }
- else {
- LPC_CGU->BASE_CLK[BaseClock] = reg | 1; /* Power down this base clock */
- }
-}
-
-/* Reads CGU Base Clock clock source information */
-void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,
- bool *powerdn)
-{
- uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];
- CHIP_CGU_CLKIN_T ClkIn = (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F );
-
- if (BaseClock < CLK_BASE_NONE) {
- /* Get settings */
- *Input = ClkIn;
- *autoblocken = (reg & (1 << 11)) ? true : false;
- *powerdn = (reg & (1 << 0)) ? true : false;
- }
- else {
- *Input = CLKINPUT_PD;
- *powerdn = true;
- *autoblocken = true;
- }
-}
-
-/*Enables a base clock source */
-void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)
-{
- if (BaseClock < CLK_BASE_NONE) {
- LPC_CGU->BASE_CLK[BaseClock] &= ~1;
- }
-}
-
-/* Disables a base clock source */
-void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)
-{
- if (BaseClock < CLK_BASE_NONE) {
- LPC_CGU->BASE_CLK[BaseClock] |= 1;
- }
-}
-
-/* Returns base clock enable state */
-bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock)
-{
- bool enabled;
-
- if (BaseClock < CLK_BASE_NONE) {
- enabled = (bool) ((LPC_CGU->BASE_CLK[BaseClock] & 1) == 0);
- }
- else {
- enabled = false;
- }
-
- return enabled;
-}
-
-/* Gets a CGU Base Clock clock source */
-CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)
-{
- uint32_t reg;
-
- if (BaseClock >= CLK_BASE_NONE) {
- return CLKINPUT_PD;
- }
-
- reg = LPC_CGU->BASE_CLK[BaseClock];
-
- /* base clock is powered down? */
- if (reg & 1) {
- return CLKINPUT_PD;
- }
-
- return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F);
-}
-
-/* Enables a peripheral clock and sets clock states */
-void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
-{
- uint32_t reg = 1;
-
- if (autoen) {
- reg |= (1 << 1);
- }
- if (wakeupen) {
- reg |= (1 << 2);
- }
-
- /* Not all clocks support a divider, but we won't check that here. Only
- dividers of 1 and 2 are allowed. Assume 1 if not 2 */
- if (div == 2) {
- reg |= (1 << 5);
- }
-
- /* Setup peripheral clock and start running */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG = reg;
- }
-}
-
-/* Enables a peripheral clock */
-void Chip_Clock_Enable(CHIP_CCU_CLK_T clk)
-{
- /* Start peripheral clock running */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG |= 1;
- }
-}
-
-/* Disables a peripheral clock */
-void Chip_Clock_Disable(CHIP_CCU_CLK_T clk)
-{
- /* Stop peripheral clock */
- if (clk >= CLK_CCU2_START) {
- LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1;
- }
- else {
- LPC_CCU1->CLKCCU[clk].CFG &= ~1;
- }
-}
-
-/**
- * Disable all branch output clocks with wake up mechanism enabled.
- * Only the clocks with wake up mechanism enabled will be disabled &
- * power down sequence started
- */
-void Chip_Clock_StartPowerDown(void)
-{
- /* Set Power Down bit */
- LPC_CCU1->PM = 1;
- LPC_CCU2->PM = 1;
-}
-
-/**
- * Enable all branch output clocks after the wake up event.
- * Only the clocks with wake up mechanism enabled will be enabled
- */
-void Chip_Clock_ClearPowerDown(void)
-{
- /* Clear Power Down bit */
- LPC_CCU1->PM = 0;
- LPC_CCU2->PM = 0;
-}
-
-/* Returns a peripheral clock rate */
-uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk)
-{
- CHIP_CGU_BASE_CLK_T baseclk;
- uint32_t reg, div, rate;
-
- /* Get CCU config register for clock */
- if (clk >= CLK_CCU2_START) {
- reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;
- }
- else {
- reg = LPC_CCU1->CLKCCU[clk].CFG;
- }
-
- /* Is the clock enabled? */
- if (reg & 1) {
- /* Get base clock for this peripheral clock */
- baseclk = Chip_Clock_FindBaseClock(clk);
-
- /* Get base clock rate */
- rate = Chip_Clock_GetBaseClocktHz(baseclk);
-
- /* Get divider for this clock */
- if (((reg >> 5) & 0x7) == 0) {
- div = 1;
- }
- else {
- div = 2;/* No other dividers supported */
-
- }
- rate = rate / div;
- }
- else {
- rate = 0;
- }
-
- return rate;
-}
-
-/* Sets up the audio or USB PLL */
-void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum,
- const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup)
-{
- uint32_t reg = pPLLSetup->ctrl | (Input << 24);
- /* Setup from passed values */
- LPC_CGU->PLL[pllnum].PLL_CTRL = reg;
- LPC_CGU->PLL[pllnum].PLL_MDIV = pPLLSetup->mdiv;
- LPC_CGU->PLL[pllnum].PLL_NP_DIV = pPLLSetup->ndiv;
-
- /* Fractional divider is for audio PLL only */
- if (pllnum == pllnum) {
- LPC_CGU->PLL0AUDIO_FRAC = pPLLSetup->fract;
- }
-}
-
-/* Enables the audio or USB PLL */
-void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum)
-{
- LPC_CGU->PLL[pllnum].PLL_CTRL &= ~1;
-}
-
-/* Disables the audio or USB PLL */
-void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum)
-{
- LPC_CGU->PLL[pllnum].PLL_CTRL |= 1;
-}
-
-/* Returns the PLL status */
-uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum)
-{
- return LPC_CGU->PLL[pllnum].PLL_STAT;
-}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
deleted file mode 100644
index dab6f1afe..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * @brief LPC18xx/43xx clock driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CLOCK_18XX_43XX_H_
-#define __CLOCK_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options
- * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
- * The clock driver has options that configure it's operation at build-time.
- *
- * MAX_CLOCK_FREQ
- * This define, when set, identifies the running CPU clock rate of the system
- * (change this to alter running CPU speed).
- * When this is not defined, The maximum clock rate for the CPU is used.
- *
- * CRYSTAL_MAIN_FREQ_IN
- * This define is the external crystal frequency used for the main oscillator.
- *
- * EXTCLKIN_FREQ_IN
- * This define is rate of the input clock signal on the CLKIN input of the device
- * (on some parts only).
- * @{
- */
-
-/**
- * @}
- */
-
-/* Internal oscillator frequency */
-#define CGU_IRC_FREQ (12000000)
-
-#ifndef MAX_CLOCK_FREQ
-#if defined(CHIP_LPC43XX)
-#define MAX_CLOCK_FREQ (204000000)
-#else
-#define MAX_CLOCK_FREQ (180000000)
-#endif
-#endif /* MAX_CLOCK_FREQ */
-
-/**
- * @brief Enables the crystal oscillator
- * @return Nothing
- */
-void Chip_Clock_EnableCrystal(void);
-
-/**
- * @brief Disables the crystal oscillator
- * @return Nothing
- */
-void Chip_Clock_DisableCrystal(void);
-
-/**
- * @brief Configures the main PLL
- * @param Input : Which clock input to use as the PLL input
- * @param MinHz : Minimum allowable PLL output frequency
- * @param DesiredHz : Desired PLL output frequency
- * @param MaxHz : Maximum allowable PLL output frequency
- * @return Frequency of the PLL in Hz
- * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz
- * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if
- * the PLL is locked.
- */
-uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
-
-/**
- * @brief Directly set the PLL multipler
- * @param Input : Which clock input to use as the PLL input
- * @param mult : How many times to multiply the input clock
- * @return Frequency of the PLL in Hz
- */
-uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult);
-
-/**
- * @brief Returns the frequency of the main PLL
- * @return Frequency of the PLL in Hz
- * Returns zero if the main PLL is not running.
- */
-uint32_t Chip_Clock_GetMainPLLHz(void);
-
-/**
- * @brief Disables the main PLL
- * @return none
- * Make sure the main PLL is not needed to clock the part before disabling it.
- * Saves power if the main PLL is not needed.
- */
-void Chip_Clock_DisableMainPLL(void);
-
-/**
- * @brief Enbles the main PLL
- * @return none
- * Make sure the main PLL is enabled.
- */
-void Chip_Clock_EnableMainPLL(void);
-
-/**
- * @brief Returns the lock status of the main PLL
- * @return true if the PLL is locked, otherwise false
- * The main PLL should be locked prior to using it as a clock input for a base clock.
- */
-bool Chip_Clock_MainPLLLocked(void);
-
-/**
- * @brief Sets up a CGU clock divider and it's input clock
- * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to configure
- * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
- * @param Divisor : value to divide Input clock by
- * @return Nothing
- * Maximum divider on A = 4, B/C/D = 16, E = 256.
- * See the user manual for allowable combinations for input clock.
- */
-void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor);
-
-/**
- * @brief Gets a CGU clock divider source
- * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of
- * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider);
-
-/**
- * @brief Gets a CGU clock divider divisor
- * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of
- * @return the divider value for the divider
- */
-uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider);
-
-/**
- * @brief Returns the frequency of the specified input clock source
- * @param input : Which clock input to return the frequency of
- * @return Frequency of input source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input);
-
-/**
- * @brief Returns the frequency of the specified base clock source
- * @param clock : which base clock to return the frequency of.
- * @return Frequency of base source in Hz
- * This function returns an ideal frequency and not the actual frequency. Returns
- * zero if the clock source is disabled.
- */
-uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock);
-
-/**
- * @brief Sets a CGU Base Clock clock source
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to set
- * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
- * @param autoblocken : Enables autoblocking during frequency change if true
- * @param powerdn : The clock base is setup, but powered down if true
- * @return Nothing
- */
-void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
-
-/**
- * @brief Get CGU Base Clock clock source information
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get
- * @param Input : Pointer to CHIP_CGU_CLKIN_T value of the base clock
- * @param autoblocken : Pointer to autoblocking value of the base clock
- * @param powerdn : Pointer to power down flag
- * @return Nothing
- */
-void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,
- bool *powerdn);
-
-/**
- * @brief Gets a CGU Base Clock clock source
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
- * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD
- */
-CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Enables a base clock source
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to enable
- * @return Nothing
- */
-void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Disables a base clock source
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to disable
- * @return Nothing
- */
-void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Returns base clock enable state
- * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to check
- * @return true if the base clock is enabled, false if disabled
- */
-bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock);
-
-/**
- * @brief Enables a peripheral clock and sets clock states
- * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable
- * @param autoen : true to enable autoblocking on a clock rate change, false to disable
- * @param wakeupen : true to enable wakeup mechanism, false to disable
- * @param div : Divider for the clock, must be 1 for most clocks, 2 supported on others
- * @return Nothing
- */
-void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
-
-/**
- * @brief Enables a peripheral clock
- * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable
- * @return Nothing
- */
-void Chip_Clock_Enable(CHIP_CCU_CLK_T clk);
-
-/**
- * @brief Disables a peripheral clock
- * @param clk : CHIP_CCU_CLK_T value indicating which clock to disable
- * @return Nothing
- */
-void Chip_Clock_Disable(CHIP_CCU_CLK_T clk);
-
-/**
- * @brief Returns a peripheral clock rate
- * @param clk : CHIP_CCU_CLK_T value indicating which clock to get rate for
- * @return 0 if the clock is disabled, or the rate of the clock
- */
-uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk);
-
-/**
- * @brief Start the power down sequence by disabling the branch output
- * clocks with wake up mechanism (Only the clocks which
- * wake up mechanism bit enabled will be disabled)
- * @return Nothing
- */
-void Chip_Clock_StartPowerDown(void);
-
-/**
- * @brief Clear the power down mode bit & proceed normal operation of branch output
- * clocks (Only the clocks which wake up mechanism bit enabled will be
- * enabled after the wake up event)
- * @return Nothing
- */
-void Chip_Clock_ClearPowerDown(void);
-
-/**
- * Structure for setting up the USB or audio PLL
- */
-typedef struct {
- uint32_t ctrl; /* Default control word for PLL */
- uint32_t mdiv; /* Default M-divider value for PLL */
- uint32_t ndiv; /* Default NP-divider value for PLL */
- uint32_t fract; /* Default fractional value for audio PLL only */
-} CGU_USBAUDIO_PLL_SETUP_T;
-
-/**
- * @brief Sets up the audio or USB PLL
- * @param Input : Input clock
- * @param pllnum : PLL identifier
- * @param pPLLSetup : Pointer to PLL setup structure
- * @return Nothing
- * Sets up the PLL with the passed structure values.
- */
-void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum,
- const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup);
-
-/**
- * @brief Enables the audio or USB PLL
- * @param pllnum : PLL identifier
- * @return Nothing
- */
-void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
-
-/**
- * @brief Disables the audio or USB PLL
- * @param pllnum : PLL identifier
- * @return Nothing
- */
-void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
-
-#define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */
-#define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */
-
-/**
- * @brief Returns the PLL status
- * @param pllnum : PLL identifier
- * @return An OR'ed value of CGU_PLL_LOCKED or CGU_PLL_FR
- */
-uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CLOCK_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cmsis.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cmsis.h
deleted file mode 100644
index 5ea244f08..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/cmsis.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * @brief Basic CMSIS include file
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CMSIS_H_
-#define __CMSIS_H_
-
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#if defined(__ARMCC_VERSION)
-// Kill warning "#pragma push with no matching #pragma pop"
- #pragma diag_suppress 2525
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
-/* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-// #pragma push // FIXME not usable for IAR
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-#if defined(CORE_M4)
-/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions
- * @{
- */
-
-#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#ifdef CHIP_LPC43XX
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-#else
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */
- PendSV_IRQn = -2,/*!< 14 Pendable request for system service */
- SysTick_IRQn = -1,/*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-
-#elif defined(CORE_M3)
-/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- RESERVED0_IRQn = 1,
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- RESERVED3_IRQn = 20,
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- RESERVED5_IRQn = 31,
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
-
-#elif defined(CORE_M0)
-/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions
- * @{
- */
-
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-
-/**
- * @}
- */
-
-/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers
- * @{
- */
-
-typedef enum {
- /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0_M4CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- FLASHEEPROM_IRQn = 4,/*!< 4 ORed Flash EEPROM Bank A, B, EEPROM */
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 ORed RITIMER, WDT */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- GINT1_IRQn = 13,/*!< 13 GINT1 */
- PIN_INT4_IRQn = 14,/*!< 14 GPIO 4 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 ORed I2C0, I2C1 */
- SGPIO_INT_IRQn = 19,/*!< 19 SGPIO */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */
- EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */
- C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED2_IRQn = 30,
- RESERVED3_IRQn = 31,
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */
-#else
-#error Please #define CORE_M0, CORE_M3, or CORE_M4
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMSIS_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
deleted file mode 100644
index 60320d708..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * @brief LPC18XX/43XX CREG control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CREG_18XX_43XX_H_
-#define __CREG_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief CREG Register Block
- */
-typedef struct { /*!< CREG Structure */
- __I uint32_t RESERVED0;
- __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
- __I uint32_t RESERVED1[62];
- __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED2[5];
-#else
- __I uint32_t RESERVED2;
- __I uint32_t CREG1; /*!< Configuration Register 1 */
- __I uint32_t CREG2; /*!< Configuration Register 2 */
- __I uint32_t CREG3; /*!< Configuration Register 3 */
- __I uint32_t CREG4; /*!< Configuration Register 4 */
-#endif
- __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */
- __IO uint32_t DMAMUX; /*!< DMA muxing control */
- __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */
- __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */
- __IO uint32_t ETBCFG; /*!< ETB RAM configuration */
- __IO uint32_t CREG6; /*!< Chip configuration register 6. */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED4[52];
-#else
- __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */
- __I uint32_t RESERVED4[51];
-#endif
- __I uint32_t CHIPID; /*!< Part ID */
-#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED5[191];
-#else
- __I uint32_t RESERVED5[127];
- __IO uint32_t M0TXEVENT; /*!< M0 IPC Event register */
- __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0 memory mapping */
- __I uint32_t RESERVED6[62];
-#endif
- __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */
- __I uint32_t RESERVED7[63];
- __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */
-} LPC_CREG_T;
-
-/**
- * @brief Identifies whether on-chip flash is present
- * @return true if on chip flash is available, otherwise false
- */
-STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)
-{
- return LPC_CREG->CHIPID != 0x3284E02B;
-}
-
-/**
- * @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.
- * @param Hz : Current frequency in Hz of the CPU
- * @return Nothing
- * This function should be called with the higher frequency before the clock frequency is
- * increased and it should be called with the new lower value after the clock frequency is
- * decreased.
- */
-STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)
-{
- uint32_t FAValue = Hz / 21510000;
-
- LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
- LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
-}
-
-/**
- * @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts
- * @param Enable : true to enable PHY, false to disable
- * @return Nothing
- * The USB0 PLL & clock should be configured before calling this function. This function
- * should be called before the USB0 registers are accessed.
- */
-STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)
-{
- if (Enable) {
- LPC_CREG->CREG0 &= ~(1 << 5);
- }
- else {
- LPC_CREG->CREG0 |= (1 << 5);
- }
-}
-
-/**
- * @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts.
- * @param BODVL : Brown-Out Detect voltage level (0-3)
- * @param BORVL : Brown-Out Reset voltage level (0-3)
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
-{
- LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
-}
-
-#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
-/**
- * @brief Configures base address of image to be run in the Cortex M0 Core.
- * @param memaddr : Address of the image (must be aligned to 4K)
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
-{
- LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
-}
-
-/**
- * @brief Clear M4 IPC Event
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM4Event(void)
-{
- LPC_CREG->M4TXEVENT = 0;
-}
-
-/**
- * @brief Clear M0 IPC Event
- * @return Nothing
- */
-STATIC INLINE void Chip_CREG_ClearM0Event(void)
-{
- LPC_CREG->M0TXEVENT = 0;
-}
-
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CREG_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/dac_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/dac_18xx_43xx.h
deleted file mode 100644
index 0db762c60..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/dac_18xx_43xx.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * @brief LPC18xx/43xx D/A conversion driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __DAC_18XX_43XX_H_
-#define __DAC_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup DAC_18XX_43XX CHIP: LPC18xx/43xx D/A conversion driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-// FIXME LPC_DAC_T *pDAC argument not needed for 18xx/43xx CHIP driver
-
-/**
- * @brief Initial DAC configuration
- * - Maximum current is 700 uA
- * - Value to AOUT is 0
- * @param pDAC : pointer to LPC_DAC_T
- * @return Nothing
- */
-void Chip_DAC_Init(LPC_DAC_T *pDAC);
-
-/**
- * @brief Shutdown DAC
- * @param pDAC : pointer to LPC_DAC_T
- * @return Nothing
- */
-void Chip_DAC_DeInit(LPC_DAC_T *pDAC);
-
-/**
- * @brief Update value to DAC buffer
- * @param pDAC : pointer to LPC_DAC_T
- * @param dac_value : value 10 bit to be converted to output
- * @return Nothing
- */
-STATIC INLINE void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value)
-{
- IP_DAC_UpdateValue(pDAC, dac_value);
-}
-
-/**
- * @brief Set maximum update rate for DAC
- * @param pDAC : pointer to LPC_DAC_T
- * @param bias : Using Bias value, should be:
- * - 0 is 1MHz
- * - 1 is 400kHz
- * @return Nothing
- */
-STATIC INLINE void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias)
-{
- IP_DAC_SetBias(pDAC, bias);
-}
-
-/**
- * @brief Enables the DMA operation and controls DMA timer
- * @param pDAC : pointer to the DAC peripheral block
- * @param dacFlags : An Or'ed value of the following DAC values:
- * - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature
- * - DAC_CNT_ENA :enable/disable timer out counter
- * - DAC_DMA_ENA :enable/disable DMA access
- * @return Nothing
- * @note Pass an Or'ed value of the DAC flags to enable those options.
- */
-STATIC INLINE void Chip_DAC_ConfigDAConverterControl(IP_DAC_001_T *pDAC, uint32_t dacFlags)
-{
- IP_DAC_ConfigDAConverterControl(pDAC, dacFlags);
-}
-
-/**
- * @brief Set reload value for interrupt/DMA counter
- * @param pDAC : pointer to LPC_DAC_T
- * @param time_out : time out to reload for interrupt/DMA counter
- * @return Nothing
- */
-STATIC INLINE void Chip_DAC_SetDMATimeOut(LPC_DAC_T *pDAC, uint32_t time_out)
-{
- IP_DAC_SetDMATimeOut(pDAC, time_out);
-}
-
-/**
- * @brief Get status for interrupt/DMA time out
- * @param pDAC : pointer to LPC_DAC_T
- * @return interrupt/DMA time out status, should be SET or RESET
- */
-STATIC INLINE IntStatus Chip_DAC_GetIntStatus(LPC_DAC_T *pDAC)
-{
- return IP_DAC_GetIntStatus(pDAC);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DAC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/eeprom_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/eeprom_18xx_43xx.h
deleted file mode 100644
index 8db485878..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/eeprom_18xx_43xx.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * @brief LPC18xx/40xx EEPROM driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef EEPROM_18XX_43XX_H_
-#define EEPROM_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EEPROM_18XX_43XX CHIP: LPC18xx/40xx EEPROM Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-/** EEPROM start address */
-#define EEPROM_START (0x20040000)
-/** EEPROM byes per page */
-#define EEPROM_PAGE_SIZE (128)
-/**The number of EEPROM pages. The last page is not writable.*/
-#define EEPROM_PAGE_NUM (128)
-/** Get the eeprom address */
-#define EEPROM_ADDRESS(page, offset) (EEPROM_START + (EEPROM_PAGE_SIZE * (page)) + offset)
-
-/**
- * @brief Initializes EEPROM
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return Nothing
- */
-void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM);
-
-/**
- * @brief De-initializes EEPROM
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_DeInit(LPC_EEPROM_T *pEEPROM)
-{
- IP_EEPROM_DeInit(pEEPROM);
-}
-
-/**
- * @brief Set Auto program mode
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mode : Auto Program Mode (One of EEPROM_AUTOPROG_* value)
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_SetAutoProg(LPC_EEPROM_T *pEEPROM, uint32_t mode)
-{
- IP_EEPROM_SetAutoProg(pEEPROM, mode);
-}
-
-/**
- * @brief Set EEPROM Read Wait State
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param ws : Wait State value
- * @return Nothing
- * @note Bits 7:0 represents wait state for Read Phase 2 and
- * Bits 15:8 represents wait state for Read Phase1
- */
-STATIC INLINE void Chip_EEPROM_SetReadWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
-{
- IP_EEPROM_SetReadWaitState(pEEPROM, ws);
-}
-
-/**
- * @brief Set EEPROM wait state
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param ws : Wait State value
- * @return Nothing
- * @note Bits 7:0 represents wait state for Phase 3,
- * Bits 15:8 represents wait state for Phase2, and
- * Bits 23:16 represents wait state for Phase1
- */
-STATIC INLINE void Chip_EEPROM_SetWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
-{
- IP_EEPROM_SetWaitState(pEEPROM, ws);
-}
-
-/**
- * @brief Select an EEPROM command
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param cmd : EEPROM command
- * @return Nothing
- * @note The cmd is OR-ed bits value of EEPROM_CMD_*
- */
-STATIC INLINE void Chip_EEPROM_SetCmd(LPC_EEPROM_T *pEEPROM, uint32_t cmd)
-{
- IP_EEPROM_SetCmd(pEEPROM, cmd);
-}
-
-/**
- * @brief Erase/Program an EEPROM page
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM)
-{
- IP_EEPROM_EraseProgramPage(pEEPROM);
-}
-
-/**
- * @brief Wait for interrupt occurs
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mask : Expected interrupt
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_WaitForIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
-{
- IP_EEPROM_WaitForIntStatus(pEEPROM, mask);
-}
-
-/**
- * @brief Put EEPROM device in power down mode
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_EnablePowerDown(LPC_EEPROM_T *pEEPROM)
-{
- IP_EEPROM_EnablePowerDown(pEEPROM);
-}
-
-/**
- * @brief Bring EEPROM device out of power down mode
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_DisablePowerDown(LPC_EEPROM_T *pEEPROM)
-{
- IP_EEPROM_DisablePowerDown(pEEPROM);
-}
-
-/**
- * @brief Enable EEPROM interrupt
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_EnableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
-{
- IP_EEPROM_EnableInt(pEEPROM, mask);
-}
-
-/**
- * @brief Disable EEPROM interrupt
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_DisableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
-{
- IP_EEPROM_DisableInt(pEEPROM, mask);
-}
-
-/**
- * @brief Get the value of the EEPROM interrupt enable register
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return OR-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t Chip_EEPROM_GetIntEnable(LPC_EEPROM_T *pEEPROM)
-{
- return IP_EEPROM_GetIntEnable(pEEPROM);
-}
-
-/**
- * @brief Get EEPROM interrupt status
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @return OR-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t Chip_EEPROM_GetIntStatus(LPC_EEPROM_T *pEEPROM)
-{
- return IP_EEPROM_GetIntStatus(pEEPROM);
-}
-
-/**
- * @brief Set EEPROM interrupt status
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_SetIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
-{
- IP_EEPROM_SetIntStatus(pEEPROM, mask);
-}
-
-/**
- * @brief Clear EEPROM interrupt status
- * @param pEEPROM : Pointer to EEPROM peripheral block structure
- * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void Chip_EEPROM_ClearIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
-{
- IP_EEPROM_ClearIntStatus(pEEPROM, mask);
-}
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* EEPROM_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
deleted file mode 100644
index 799cd73f7..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * @brief LPC18xx/43xx EMC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EMC_18XX_43XX_H_
-#define __EMC_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- * The EMC interface clocks must be enabled outside this driver prior to
- * calling any function of this driver with the
- * Chip_Clock_EnableOpts(CLK_MX_EMC_DIV) and Chip_Clock_Enable(CLK_MX_EMC)
- * functions.
- */
-
-/**
- * Dynamic Chip Select Address
- */
-#define EMC_ADDRESS_DYCS0 (0x28000000)
-#define EMC_ADDRESS_DYCS1 (0x30000000)
-#define EMC_ADDRESS_DYCS2 (0x60000000)
-#define EMC_ADDRESS_DYCS3 (0x70000000)
-
-/**
- * Static Chip Select Address
- */
-#define EMC_ADDRESS_CS0 (0x1C000000)
-#define EMC_ADDRESS_CS1 (0x1D000000)
-#define EMC_ADDRESS_CS2 (0x1E000000)
-#define EMC_ADDRESS_CS3 (0x1F000000)
-
-/**
- * @brief Dyanmic memory setup
- * @param Dynamic_Config : Pointer to dynamic memory setup data
- * @return None
- */
-void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config);
-
-/**
- * @brief Static memory setup
- * @param Static_Config : Pointer to static memory setup data
- * @return None
- */
-void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config);
-
-/**
- * @brief Enable Dynamic Memory Controller
- * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable
- * @return None
- */
-STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)
-{
- IP_EMC_Dynamic_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief Mirror CS1 to CS0 and DYCS0
- * @param Enable : 1 = Mirror, 0 = Normal Memory Map
- * @return None
- */
-STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)
-{
- IP_EMC_Mirror(LPC_EMC, Enable);
-}
-
-/**
- * @brief Enable EMC
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- */
-STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)
-{
- IP_EMC_Enable(LPC_EMC, Enable);
-}
-
-/**
- * @brief Set EMC LowPower Mode
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- * @note This function should only be called when the memory
- * controller is not busy (bit 0 of the status register is not set).
- */
-STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)
-{
- IP_EMC_LowPowerMode(LPC_EMC, Enable);
-}
-
-/**
- * @brief Initialize EMC
- * @param Enable : 1 = Enable, 0 = Disable
- * @param EndianMode : Endian Mode, 0 = Little, 1 = Big
- * @return None
- */
-STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t EndianMode)
-{
- IP_EMC_Init(LPC_EMC, Enable, 0, EndianMode);
-}
-
-/**
- * @brief Set Static Memory Extended Wait in Clock
- * @param Wait16Clks : Number of '16 clock' delay cycles
- * @return None
- */
-STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
-{
- IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EMC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
deleted file mode 100644
index b37213218..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "chip.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Basic Ethernet interface initialization */
-void Chip_ENET_Init(LPC_ENET_T *pENET)
-{
- LPC_CREG->CREG6 &= ~0x7;
-
- /* Enable ethernet clock */
- Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
-
- /* PHY TX/RX base clock routing is setup as part of SystemInit() */
-
-#if defined(USE_RMII)
- LPC_CREG->CREG6 |= 0x4;
-#endif
-
- /* Reset ethernet and wait for reset to complete */
- Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
- while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
-
- /* Reset ethernet peripheral */
- Chip_ENET_Reset(pENET);
-
- /* Setup MII link divider to /102 and PHY address 1 */
- Chip_ENET_SetupMII(pENET, 4, 1);
-
- IP_ENET_Init(pENET);
-}
-
-/* Ethernet interface shutdown */
-void Chip_ENET_DeInit(LPC_ENET_T *pENET)
-{
- IP_ENET_DeInit(pENET);
- Chip_Clock_Disable(CLK_MX_ETHERNET);
-}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
deleted file mode 100644
index 28525645d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * @brief LPC18xx/43xx ethernet driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ENET_18XX_43XX_H_
-#define __ENET_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options
- * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS
- * The ethernet driver has options that configure it's operation at build-time.
- *
- * USE_RMII
- * When defined, the driver will be built for RMII operation.
- * When not defined, the driver will be built for MII operation.
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @brief Resets the ethernet interface
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- * @note Resets the ethernet interface. This should be called prior to
- * Chip_ENET_Init with a small delay after this call.
- */
-STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET)
-{
- IP_ENET_Reset(pENET);
-}
-
-/**
- * @brief Sets the address of the interface
- * @param pENET : The base of ENET peripheral on the chip
- * @param macAddr : Pointer to the 6 bytes used for the MAC address
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr)
-{
- IP_ENET_SetADDR(pENET, macAddr);
-}
-
-/**
- * @brief Sets up the PHY link clock divider and PHY address
- * @param pENET : The base of ENET peripheral on the chip
- * @param div : Divider index, not a divider value, see user manual
- * @param addr : PHY address, used with MII read and write
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
-{
- IP_ENET_SetupMII(pENET, div, addr);
-}
-
-/**
- * @brief Starts a PHY write via the MII
- * @param pENET : The base of ENET peripheral on the chip
- * @param reg : PHY register to write
- * @param data : Data to write to PHY register
- * @return Nothing
- * @note Start a PHY write operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when write is complete.
- */
-STATIC INLINE void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
-{
- IP_ENET_StartMIIWrite(pENET, reg, data);
-}
-
-/**
- * @brief Starts a PHY read via the MII
- * @param pENET : The base of ENET peripheral on the chip
- * @param reg : PHY register to read
- * @return Nothing
- * @note Start a PHY read operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when read is complete and calling
- * IP_ENET_ReadMIIData to get the data.
- */
-STATIC INLINE void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)
-{
- IP_ENET_StartMIIRead(pENET, reg);
-}
-
-/**
- * @brief Returns MII link (PHY) busy status
- * @param pENET : The base of ENET peripheral on the chip
- * @return Returns true if busy, otherwise false
- */
-STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET)
-{
- return IP_ENET_IsMIIBusy(pENET);
-}
-
-/**
- * @brief Returns the value read from the PHY
- * @param pENET : The base of ENET peripheral on the chip
- * @return Read value from PHY
- */
-STATIC INLINE uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET)
-{
- return IP_ENET_ReadMIIData(pENET);
-}
-
-/**
- * @brief Enables ethernet transmit
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET)
-{
- IP_ENET_TXEnable(pENET);
-}
-
-/**
- * @brief Disables ethernet transmit
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET)
-{
- IP_ENET_TXDisable(pENET);
-}
-
-/**
- * @brief Enables ethernet packet reception
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET)
-{
- IP_ENET_RXEnable(pENET);
-}
-
-/**
- * @brief Disables ethernet packet reception
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
-{
- IP_ENET_RXDisable(pENET);
-}
-
-/**
- * @brief Sets full or half duplex for the interface
- * @param pENET : The base of ENET peripheral on the chip
- * @param full : true to selected full duplex, false for half
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full)
-{
- IP_ENET_SetDuplex(pENET, full);
-}
-
-/**
- * @brief Sets speed for the interface
- * @param pENET : The base of ENET peripheral on the chip
- * @param speed100 : true to select 100Mbps mode, false for 10Mbps
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100)
-{
- IP_ENET_SetSpeed(pENET, speed100);
-}
-
-/**
- * @brief Configures the initial ethernet descriptors
- * @param pENET : The base of ENET peripheral on the chip
- * @param pTXDescs : Pointer to TX descriptor list
- * @param pRXDescs : Pointer to RX descriptor list
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_InitDescriptors(LPC_ENET_T *pENET,
- IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs)
-{
- IP_ENET_InitDescriptors(pENET, pTXDescs, pRXDescs);
-}
-
-/**
- * @brief Starts receive polling of RX descriptors
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_RXStart(LPC_ENET_T *pENET)
-{
- IP_ENET_RXStart(pENET);
-}
-
-/**
- * @brief Starts transmit polling of TX descriptors
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_ENET_TXStart(LPC_ENET_T *pENET)
-{
- IP_ENET_TXStart(pENET);
-}
-
-/**
- * @brief Initialize ethernet interface
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- * @note Performs basic initialization of the ethernet interface in a default
- * state. This is enough to place the interface in a usable state, but
- * may require more setup outside this function.
- */
-void Chip_ENET_Init(LPC_ENET_T *pENET);
-
-/**
- * @brief De-initialize the ethernet interface
- * @param pENET : The base of ENET peripheral on the chip
- * @return Nothing
- */
-void Chip_ENET_DeInit(LPC_ENET_T *pENET);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENET_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
deleted file mode 100644
index a0d742000..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * @brief LPC18xx/43xx event router driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EVRT_18XX_43XX_H_
-#define __EVRT_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Event Router register structure
- */
-typedef struct { /*!< EVENTROUTER Structure */
- __IO uint32_t HILO; /*!< Level configuration register */
- __IO uint32_t EDGE; /*!< Edge configuration */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /*!< Event clear enable register */
- __O uint32_t SET_EN; /*!< Event set enable register */
- __I uint32_t STATUS; /*!< Status register */
- __I uint32_t ENABLE; /*!< Enable register */
- __O uint32_t CLR_STAT; /*!< Clear register */
- __O uint32_t SET_STAT; /*!< Set register */
-} LPC_EVRT_T;
-
-/**
- * @brief EVRT input sources
- */
-typedef enum CHIP_EVRT_SRC {
- EVRT_SRC_WAKEUP0, /*!< WAKEUP0 event router source */
- EVRT_SRC_WAKEUP1, /*!< WAKEUP1 event router source */
- EVRT_SRC_WAKEUP2, /*!< WAKEUP2 event router source */
- EVRT_SRC_WAKEUP3, /*!< WAKEUP3 event router source */
- EVRT_SRC_ATIMER, /*!< Alarm timer event router source */
- EVRT_SRC_RTC, /*!< RTC event router source */
- EVRT_SRC_BOD1, /*!< BOD event router source */
- EVRT_SRC_WWDT, /*!< WWDT event router source */
- EVRT_SRC_ETHERNET, /*!< Ethernet event router source */
- EVRT_SRC_USB0, /*!< USB0 event router source */
- EVRT_SRC_USB1, /*!< USB1 event router source */
- EVRT_SRC_SDIO, /*!< Reserved */
- EVRT_SRC_CCAN, /*!< C_CAN event router source */
- EVRT_SRC_COMBINE_TIMER2, /*!< Combined timer 2 event router source */
- EVRT_SRC_COMBINE_TIMER6, /*!< Combined timer 6 event router source */
- EVRT_SRC_QEI, /*!< QEI event router source */
- EVRT_SRC_COMBINE_TIMER14, /*!< Combined timer 14 event router source */
- EVRT_SRC_RESERVED1, /*!< Reserved */
- EVRT_SRC_RESERVED2, /*!< Reserved */
- EVRT_SRC_RESET /*!< Reset event router source */
-} CHIP_EVRT_SRC_T;
-
-/**
- * @brief Macro for checking for a valid EVRT source
- */
-#define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \
- || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \
- || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \
- || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \
- || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \
- || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \
- || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \
- || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \
- || (n == EVRT_SRC_RESET)) \
-
-/**
- * @brief EVRT input state detecting type
- */
-typedef enum CHIP_EVRT_SRC_ACTIVE {
- EVRT_SRC_ACTIVE_LOW_LEVEL, /*!< Active low level */
- EVRT_SRC_ACTIVE_HIGH_LEVEL, /*!< Active high level */
- EVRT_SRC_ACTIVE_FALLING_EDGE, /*!< Active falling edge */
- EVRT_SRC_ACTIVE_RISING_EDGE /*!< Active rising edge */
-} CHIP_EVRT_SRC_ACTIVE_T;
-
-/**
- * @brief Macro for checking for a valid EVRT state type
- */
-#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \
- || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))
-
-/**
- * @brief Initialize the EVRT
- * @return Nothing
- */
-void Chip_EVRT_Init (void);
-
-/**
- * @brief Set up the type of interrupt type for a source to EVRT
- * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type
- * @param type : EVRT type, should be one of CHIP_EVRT_SRC_ACTIVE_T type
- * @return Nothing
- */
-void Chip_EVRT_ConfigIntSrcActiveType(CHIP_EVRT_SRC_T EVRT_Src, CHIP_EVRT_SRC_ACTIVE_T type);
-
-/**
- * @brief Check if a source is sending interrupt to EVRT
- * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type
- * @return true if the interrupt from the source is pending, otherwise false
- */
-IntStatus Chip_EVRT_IsSourceInterrupting(CHIP_EVRT_SRC_T EVRT_Src);
-
-/**
- * @brief Enable or disable interrupt sources to EVRT
- * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type
- * @param state : ENABLE or DISABLE to enable or disable event router source
- * @return Nothing
- */
-void Chip_EVRT_SetUpIntSrc(CHIP_EVRT_SRC_T EVRT_Src, FunctionalState state);
-
-/**
- * @brief De-initializes the EVRT peripheral
- * @return Nothing
- */
-STATIC INLINE void Chip_EVRT_DeInit(void)
-{
- LPC_EVRT->CLR_EN = 0xFFFF;
- LPC_EVRT->CLR_STAT = 0xFFFF;
-}
-
-/**
- * @brief Clear pending interrupt EVRT source
- * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type
- * @return Nothing
- */
-STATIC INLINE void Chip_EVRT_ClrPendIntSrc(CHIP_EVRT_SRC_T EVRT_Src)
-{
- LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EVRT_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
deleted file mode 100644
index 1634aaafd..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * @brief LPC18xx/43xx DMA driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPDMA_18XX_43XX_H_
-#define __GPDMA_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Number of channels on GPDMA
- */
-#define GPDMA_NUMBER_CHANNELS 8
-
-/**
- * @brief GPDMA request connections
- */
-#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */
-#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
-#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
-#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
-#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
-#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
-#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
-#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
-#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
-#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
-#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
-#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
-#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
-#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
-#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
-#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
-#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
-#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
-#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
-#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
-#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S channel 0 */
-#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
-#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S channel 1 */
-#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
-#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
-#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
-#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
-#define GPDMA_CONN_DAC ((27UL)) /**< DAC */
-#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL)) /**< I2S channel 0 */
-#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL)) /**< I2S channel 0 */
-
-/**
- * @brief GPDMA Burst size in Source and Destination definitions
- */
-#define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */
-#define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */
-#define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */
-#define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */
-#define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */
-#define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */
-#define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */
-#define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */
-
-/**
- * @brief Width in Source transfer width and Destination transfer width definitions
- */
-#define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */
-#define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */
-#define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */
-
-/**
- * @brief Flow control definitions
- */
-#define DMA_CONTROLLER 0 /*!< Flow control is DMA controller*/
-#define SRC_PER_CONTROLLER 1 /*!< Flow control is Source peripheral controller*/
-#define DST_PER_CONTROLLER 2 /*!< Flow control is Destination peripheral controller*/
-
-/**
- * @brief DMA channel handle structure
- */
-typedef struct {
- FunctionalState ChannelStatus; /*!< DMA channel status */
-} DMA_ChannelHandle_t;
-
-/**
- * @brief Transfer Descriptor structure typedef
- */
-typedef struct DMA_TransferDescriptor {
- uint32_t src; /*!< Source address */
- uint32_t dst; /*!< Destination address */
- uint32_t lli; /*!< Pointer to next descriptor structure */
- uint32_t ctrl; /*!< Control word that has transfer size, type etc. */
-} DMA_TransferDescriptor_t;
-
-/**
- * @brief Read the status from different registers according to the type
- * @param pGPDMA : The base of GPDMA on the chip
- * @param type : Status mode, should be:
- * - GPDMA_STAT_INT : GPDMA Interrupt Status
- * - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status
- * - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status
- * - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status
- * - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status
- * - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
- * @param channel : The GPDMA channel : 0 - 7
- * @return SET is interrupt is pending or RESET if not pending
- */
-STATIC INLINE IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel)
-{
- return IP_GPDMA_IntGetStatus(pGPDMA, type, channel);
-}
-
-/**
- * @brief Clear the Interrupt Flag from different registers according to the type
- * @param pGPDMA : The base of GPDMA on the chip
- * @param type : Flag mode, should be:
- * - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request
- * - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
- * @param channel : The GPDMA channel : 0 - 7
- * @return Nothing
- */
-STATIC INLINE void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel)
-{
- IP_GPDMA_ClearIntPending(pGPDMA, type, channel);
-}
-
-/**
- * @brief Enable or Disable the GPDMA Channel
- * @param pGPDMA : The base of GPDMA on the chip
- * @param channelNum : The GPDMA channel : 0 - 7
- * @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA
- * @return Nothing
- */
-STATIC INLINE void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
-{
- IP_GPDMA_ChannelCmd(pGPDMA, channelNum, NewState);
-}
-
-/**
- * @brief Initialize the GPDMA
- * @param pGPDMA : The base of GPDMA on the chip
- * @return Nothing
- */
-void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
-
-/**
- * @brief Shutdown the GPDMA
- * @param pGPDMA : The base of GPDMA on the chip
- * @return Nothing
- */
-void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
-
-/**
- * @brief Stop a stream DMA transfer
- * @param pGPDMA : The base of GPDMA on the chip
- * @param ChannelNum : Channel Number to be closed
- * @return Nothing
- */
-void Chip_DMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
-
-/**
- * @brief The GPDMA stream interrupt status checking
- * @param pGPDMA : The base of GPDMA on the chip
- * @param ChannelNum : Channel Number to be checked on interruption
- * @return Status:
- * - SUCCESS : DMA transfer success
- * - ERROR : DMA transfer failed
- */
-Status Chip_DMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
-
-/**
- * @brief Get a free GPDMA channel for one DMA connection
- * @param pGPDMA : The base of GPDMA on the chip
- * @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )
- * @return The channel number which is selected
- */
-uint8_t Chip_DMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID);
-
-/**
- * @brief Do a DMA transfer M2M, M2P,P2M or P2P
- * @param pGPDMA : The base of GPDMA on the chip
- * @param ChannelNum : Channel used for transfer
- * @param src : Address of Memory or PeripheralConnection_ID which is the source
- * @param dst : Address of Memory or PeripheralConnection_ID which is the destination
- * @param TransferType: Select the transfer controller and the type of transfer. Should be:
- * - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
- * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
- * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
- * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
- * @param Size : The number of DMA transfers
- * @return ERROR on error, SUCCESS on success
- */
-Status Chip_DMA_Transfer(LPC_GPDMA_T *pGPDMA,
- uint8_t ChannelNum,
- uint32_t src,
- uint32_t dst,
- IP_GPDMA_FLOW_CONTROL_T TransferType,
- uint32_t Size);
-
-/**
- * @brief Do a DMA transfer using linked list of descriptors
- * @param pGPDMA : The base of GPDMA on the chip
- * @param ChannelNum : Channel used for transfer *must be obtained using Chip_DMA_GetFreeChannel()*
- * @param DMADescriptor : First node in the linked list of descriptors
- * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)
- * @return ERROR on error, SUCCESS on success
- */
-Status Chip_DMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
- uint8_t ChannelNum,
- const DMA_TransferDescriptor_t *DMADescriptor,
- IP_GPDMA_FLOW_CONTROL_T TransferType);
-
-/**
- * @brief Prepare a single DMA descriptor
- * @param pGPDMA : The base of GPDMA on the chip
- * @param DMADescriptor : DMA Descriptor to be initialized
- * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY
- * PeripheralConnection_ID @endlink, which is the source
- * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY
- * PeripheralConnection_ID @endlink, which is the destination
- * @param Size : The number of DMA transfers
- * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)
- * @param NextDescriptor : Pointer to next descriptor (0 if no more descriptors available)
- * @return ERROR on error, SUCCESS on success
- */
-Status Chip_DMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
- DMA_TransferDescriptor_t *DMADescriptor,
- uint32_t src,
- uint32_t dst,
- uint32_t Size,
- IP_GPDMA_FLOW_CONTROL_T TransferType,
- const DMA_TransferDescriptor_t *NextDescriptor);
-
-/**
- * @brief Initialize channel configuration strucutre
- * @param pGPDMA : The base of GPDMA on the chip
- * @param GPDMACfg : Pointer to configuration structure to be initialized
- * @param ChannelNum : Channel used for transfer *must be obtained using Chip_DMA_GetFreeChannel()*
- * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY
- * PeripheralConnection_ID @endlink, which is the source
- * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY
- * PeripheralConnection_ID @endlink, which is the destination
- * @param Size : The number of DMA transfers
- * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)
- * @return ERROR on error, SUCCESS on success
- */
-int Chip_DMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
- GPDMA_Channel_CFG_T *GPDMACfg,
- uint8_t ChannelNum,
- uint32_t src,
- uint32_t dst,
- uint32_t Size,
- IP_GPDMA_FLOW_CONTROL_T TransferType);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPDMA_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
deleted file mode 100644
index 3934b9040..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * @brief LPC18xx/43xx GPIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIO_18XX_43XX_H_
-#define __GPIO_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize GPIO block
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
-{
- IP_GPIO_Init(pGPIO);
-}
-
-/**
- * @brief Set a GPIO port/bit state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param port : GPIO port to set
- * @param bit : GPIO bit to set
- * @param setting : true for high, false for low
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
-{
- IP_GPIO_WritePortBit(pGPIO, port, bit, setting);
-}
-
-/**
- * @brief Seta GPIO direction
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param port : GPIO port to set
- * @param bit : GPIO bit to set
- * @param setting : true for output, false for input
- * @return Nothing
- */
-STATIC INLINE void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
-{
- IP_GPIO_WriteDirBit(pGPIO, port, bit, setting);
-}
-
-/**
- * @brief Read a GPIO state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param port : GPIO port to read
- * @param bit : GPIO bit to read
- * @return true of the GPIO is high, false if low
- */
-STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
-{
- return IP_GPIO_ReadPortBit(pGPIO, port, bit);
-}
-
-/**
- * @brief Read a GPIO direction (out or in)
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param port : GPIO port to read
- * @param bit : GPIO bit to read
- * @return true of the GPIO is an output, false if input
- */
-STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
-{
- return IP_GPIO_ReadDirBit(pGPIO, port, bit);
-}
-
-/**
- * @brief Enable GPIO Interrupt
- * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip
- * @param portNum : GPIO port number interrupt, should be: 0 to 7
- * @param bitValue : GPIO bit to enable (Not used)
- * @param intMode : Interrupt mode, should be:
- * 0: Rising edge interrupt mode
- * 1: Falling edge interrupt mode
- * 2: Active-High interrupt mode
- * 3: Active-Low interrupt mode
- * @return None
- */
-STATIC INLINE void Chip_GPIO_IntCmd(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t bitValue, IP_GPIOPININT_MODE_T intMode)
-{
- IP_GPIOPININT_IntCmd(pGPIOPinInt, portNum, intMode);
-}
-
-/**
- * @brief Get GPIO Interrupt Status
- * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip
- * @param portNum : GPIO port number interrupt, should be: 0 to 7
- * @param pinNum : GPIO pin to check (Not used)
- * @param intMode : Interrupt mode (Not used)
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIO_IntGetStatus(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t pinNum, uint8_t intMode)
-{
- return IP_GPIOPININT_IntGetStatus(pGPIOPinInt, portNum);
-}
-
-/**
- * @brief Clear GPIO Interrupt (Edge interrupt cases only)
- * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip
- * @param portNum : GPIO port number interrupt, should be: 0 to 7
- * @param bitValue : GPIO bit to clear (Not used)
- * @return None
- */
-STATIC INLINE void Chip_GPIO_IntClear(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t bitValue)
-{
- IP_GPIOPININT_IntClear(pGPIOPinInt, portNum);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Initialization
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
- * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
-{
- IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Add to Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_T *pGPIOGPINT,
- uint8_t PortNum,
- uint8_t PinNum,
- bool ActiveMode)
-{
- IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Remove from Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
-{
- IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum);
-}
-
-/**
- * @brief Get GPIO Group Interrupt Get Status
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_T *pGPIOGPINT)
-{
- return IP_GPIOGP_IntGetStatus(pGPIOGPINT);
-}
-
-/**
- * @brief Clear GPIO Group Interrupt
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return None
- */
-STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_T *pGPIOGPINT)
-{
- IP_GPIOGP_IntClear(pGPIOGPINT);
-}
-
-/**
- * @brief Set Direction for a GPIO port
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port Number
- * @param bitValue : GPIO bit to set
- * @param out : Direction value, 0 = input, !0 = output
- * @return None
- * @note Bits set to '0' are not altered.
- */
-void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);
-
-/**
- * @brief Set Direction for a GPIO port
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port Number
- * @param bitValue : GPIO bit to set
- * @param out : Direction value, 0 = input, !0 = output
- * @return None
- * @note Bits set to '0' are not altered.
- */
-STATIC INLINE void Chip_FIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
-{
- /* Same with Chip_GPIO_SetDir() */
- Chip_GPIO_SetDir(pGPIO, portNum, bitValue, out);
-}
-
-/**
- * @brief Set a GPIO port/bit to the high state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set high
- * @return None
- * @note Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
-{
- /* Same with GPIO_SetValue() */
- pGPIO->SET[portNum] = bitValue;
-}
-
-/**
- * @brief Set a GPIO port/bit to the low state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set low
- * @return None
- * @note Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_FIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
-{
- /* Same with GPIO_ClearValue() */
- pGPIO->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief Read current bit states for the selected port
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number to read
- * @return Current value of GPIO port
- * @note The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_FIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
-{
- /* Same with GPIO_ReadValue() */
- return pGPIO->PIN[portNum];
-}
-
-/**
- * @brief Set a GPIO port/bit to the high state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set high
- * @return None
- * @note Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
-{
- pGPIO->SET[portNum] = bitValue;
-}
-
-/**
- * @brief Set a GPIO port/bit to the low state
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number
- * @param bitValue : Bit(s) in the port to set low
- * @return None
- * @note Any bit set as a '0' will not have it's state changed. This only
- * applies to ports configured as an output.
- */
-STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
-{
- pGPIO->CLR[portNum] = bitValue;
-}
-
-/**
- * @brief Read current bit states for the selected port
- * @param pGPIO : The base of GPIO peripheral on the chip
- * @param portNum : Port number to read
- * @return Current value of GPIO port
- * @note The current states of the bits for the port are read, regardless of
- * whether the GPIO port bits are input or output.
- */
-STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
-{
- return pGPIO->PIN[portNum];
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
deleted file mode 100644
index a594d50b7..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2C driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2C_18XX_43XX_H_
-#define __I2C_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief I2C interface IDs
- * @note
- * All Chip functions will take this as the first parameter,
- * I2C_NUM_INTERFACE must never be used for calling any Chip
- * functions, it is only used to find the number of interfaces
- * available in the Chip.
- */
-typedef enum I2C_ID {
- I2C0, /**< ID I2C0 */
- I2C1, /**< ID I2C1 */
- I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */
-} I2C_ID_T;
-
-/**
- * @brief I2C master events
- */
-typedef enum {
- I2C_EVENT_WAIT = 1, /**< I2C Wait event */
- I2C_EVENT_DONE, /**< Done event that wakes up Wait event */
- I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */
- I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */
- I2C_EVENT_SLAVE_RX, /**< Slave receive event */
- I2C_EVENT_SLAVE_TX, /**< Slave transmit event */
-} I2C_EVENT_T;
-
-/**
- * @brief Event handler function type
- */
-typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
-
-/**
- * @brief Initializes the LPC_I2C peripheral with specified parameter.
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Nothing
- */
-void Chip_I2C_Init(I2C_ID_T id);
-
-/**
- * @brief De-initializes the I2C peripheral registers to their default reset values
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Nothing
- */
-void Chip_I2C_DeInit(I2C_ID_T id);
-
-/**
- * @brief Set up clock rate for LPC_I2C peripheral.
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)
- * @return Nothing
- * @note
- * Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
- * (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. I2C1 @a clockrate
- * should be within the range of 1000 to 400000 (1 KHz to 400 KHz). If
- * the frequency is above 400KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
- * must be called prior to calling this function (Only I2C0 supports frequency
- * above 400 KHz).
- */
-void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
-
-/**
- * @brief Get current clock rate for LPC_I2C peripheral.
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return The current I2C peripheral clock rate
- */
-uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
-
-/**
- * @brief Transmit and Receive data in master mode
- * @param id : I2C peripheral selected (I2C0, I2C1 etc)
- * @param xfer : Pointer to a I2C_XFER_T structure see notes below
- * @return
- * Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
- * not sent due to error, xfer->rxSz will have the number of bytes yet
- * to be received.
- * @note
- * The parameter @a xfer should have its member @a slaveAddr initialized
- * to the 7-Bit slave address to which the master will do the xfer, Bit0
- * to bit6 should have the address and Bit8 is ignored. During the transfer
- * no code (like event handler) must change the content of the memory
- * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
- * initialized to the memory from which the I2C must pick the data to be
- * transfered to slave and the number of bytes to send respectively, similarly
- * @a rxBuff and @a rxSz must have pointer to memroy where data received
- * from slave be stored and the number of data to get from slave respectilvely.
- */
-int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
-
-/**
- * @brief Transmit data to I2C slave using I2C Master mode
- * @param id : I2C peripheral ID (I2C0, I2C1 .. etc)
- * @param slaveAddr : Slave address to which the data be written
- * @param buff : Pointer to buffer having the array of data
- * @param len : Number of bytes to be transfered from @a buff
- * @return Number of bytes successfully transfered
- */
-int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
-
-/**
- * @brief Transfer a command to slave and receive data from slave after a repeated start
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param slaveAddr : Slave address of the I2C device
- * @param cmd : Command (Address/Register) to be written
- * @param buff : Pointer to memory that will hold the data received
- * @param len : Number of bytes to receive
- * @return Number of bytes successfully received
- */
-int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
-
-/**
- * @brief Get pointer to current function handling the events
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Pointer to function handing events of I2C
- */
-I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
-
-/**
- * @brief Set function that must handle I2C events
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param event : Pointer to function that will handle the event
- * (Should not be NULL)
- * @return 1 when successful, 0 when a transfer is on going with its own event handler
- */
-int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
-
-/**
- * @brief Set function that must handle I2C events
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param slaveAddr : Slave address from which data be read
- * @param buff : Pointer to memory where data read be stored
- * @param len : Number of bytes to read from slave
- * @return Number of bytes read successfully
- */
-int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
-
-/**
- * @brief Default event handler for polling operation
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param event : Event ID of the event that called the function
- * @return Nothing
- */
-void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
-
-/**
- * @brief Default event handler for interrupt base operation
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param event : Event ID of the event that called the function
- * @return Nothing
- */
-void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
-
-/**
- * @brief I2C Master transfer state change handler
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Nothing
- * @note Usually called from the appropriate Interrupt handler
- */
-void Chip_I2C_MasterStateHandler(I2C_ID_T id);
-
-/**
- * @brief Disable I2C peripheral's operation
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Nothing
- */
-void Chip_I2C_Disable(I2C_ID_T id);
-
-/**
- * @brief Checks if master xfer in progress
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return 1 if master xfer in progress 0 otherwise
- * @note
- * This API is generally used in interrupt handler
- * of the application to decide whether to call
- * master state handler or to call slave state handler
- */
-int Chip_I2C_IsMasterActive(I2C_ID_T id);
-
-/**
- * @brief Setup a slave I2C device
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
- * @param xfer : Pointer to transfer structure (see note below for more info)
- * @param event : Event handler for slave transfers
- * @param addrMask : Address mask to use along with slave address (see notes below for more info)
- * @return Nothing
- * @note
- * Parameter @a xfer should point to a valid I2C_XFER_T structure object
- * and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
- * Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
- * be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
- * where slave can receive or send the data from, size of which will be provided by
- * @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
- * for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
- * from the master and stored inside memory pointed by xfer->rxBuff, incremented
- * the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
- * data from xfer->txBuff was sent to master successfully, incremented the pointer
- * and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
- * with the slave).
- *
Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
- * to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
- * don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
- * 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
- * slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
- * address which was received from master.
- *
General Call Handling
- * Slave can receive data from master using general call address (0x00). General call
- * handling must be setup as given below
- * - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
- * - xfer->slaveAddr ignored, argument @a addrMask ignored
- * - function provided by @a event will registered to be called when slave received data using addr 0x00
- * - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
- * - To handle General Call only (No other slaves are configured)
- * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
- * - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
- * - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
- * - To handler General Call when other slave is active
- * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
- * - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
- * - Set Bit0 of @a xfer->slaveAddr as 1
- * - Provide appropriate @a addrMask
- * - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
- * @warning
- * If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
- * will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
- * then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
- * called to notify this. For more info see section below
- *
Last data handling in slave
- * If the user wants to implement a slave which will read a byte from a specific location over and over
- * again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
- * the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
- * xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
- * byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
- * occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
- * event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
- * and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
- * in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
- * the process repeats.
- */
-void Chip_I2C_SlaveSetup(I2C_ID_T id,
- I2C_SLAVE_ID sid,
- I2C_XFER_T *xfer,
- I2C_EVENTHANDLER_T event,
- uint8_t addrMask);
-
-/**
- * @brief I2C Slave event handler
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return Nothing
- */
-void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
-
-/**
- * @brief I2C peripheral state change checking
- * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
- * @return 1 if I2C peripheral @a id has changed its state,
- * 0 if there is no state change
- * @note This function must be used by the application when
- * the polling has to be done based on state change.
- */
-int Chip_I2C_IsStateChanged(I2C_ID_T id);
-
-/**
- * @}
- */
-
- #ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2C_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
deleted file mode 100644
index 992cf90ff..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * @brief LPC18xx/43xx I2S driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2S_18XX_43XX_H_
-#define __I2S_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1
-#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2
-
-/**
- * @brief I2S Audio Format Structure
- */
-typedef struct {
- uint32_t SampleRate; /*!< Sample Rate */
- uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */
- uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */
-} Chip_I2S_Audio_Format_T;
-
-/**
- * @brief Initialize for I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- */
-void Chip_I2S_Init(LPC_I2S_T *pI2S);
-
-/**
- * @brief Shutdown I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- * @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
- */
-void Chip_I2S_DeInit(LPC_I2S_T *pI2S);
-
-/**
- * @brief Send a 32-bit data to TXFIFO for transmition
- * @param pI2S : The base of I2S peripheral on the chip
- * @param data : Data to be transmited
- * @return Nothing
- * @note The function writes to TXFIFO without checking any condition.
- */
-STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data)
-{
- IP_I2S_Send(pI2S, data);
-}
-
-/**
- * @brief Get received data from RXFIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Data received in RXFIFO
- * @note The function reads from RXFIFO without checking any condition.
- */
-STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_T *pI2S)
-{
- return IP_I2S_Receive(pI2S);
-}
-
-/**
- * @brief Start the I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_Start(LPC_I2S_T *pI2S, uint8_t TRMode)
-{
- IP_I2S_Start(pI2S, TRMode);
-}
-
-/**
- * @brief Disables accesses on FIFOs, places the transmit channel in mute mode
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_Pause(LPC_I2S_T *pI2S, uint8_t TRMode)
-{
- IP_I2S_Pause(pI2S, TRMode);
-}
-
-/**
- * @brief Mute the Transmit channel
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- * @note The data output from I2S transmit channel is always zeroes
- */
-STATIC INLINE void Chip_I2S_EnableMute(LPC_I2S_T *pI2S)
-{
- IP_I2S_EnableMute(pI2S);
-}
-
-/**
- * @brief Un-Mute the I2S channel
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_I2S_DisableMute(LPC_I2S_T *pI2S)
-{
- IP_I2S_DisableMute(pI2S);
-}
-
-/**
- * @brief Stop I2S asynchronously
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- * @note Pause, resets the transmit channel and FIFO asynchronously
- */
-STATIC INLINE void Chip_I2S_Stop(LPC_I2S_T *pI2S, uint8_t TRMode)
-{
- IP_I2S_Stop(pI2S, TRMode);
-}
-
-/**
- * @brief Set the I2S operating modes
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param clksel : Clock source selection for the receive bit clock divider
- * @param fpin : Receive 4-pin mode selection
- * @param mcena : Enable for the RX_MCLK output
- * @return Nothing
- * @note In addition to master and slave modes, which are independently configurable for
- * the transmitter and the receiver, several different clock sources are possible,
- * including variations that share the clock and/or WS between the transmitter and
- * receiver. It also allows using I2S with fewer pins, typically four.
- */
-STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_T *pI2S,
- uint8_t TRMode,
- uint32_t clksel,
- uint32_t fpin,
- uint32_t mcena)
-{
- IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena);
-}
-
-/**
- * @brief Get the current level of the Transmit/Receive FIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Current level of the Transmit/Receive FIFO
- */
-STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_T *pI2S, uint8_t TRMode)
-{
- return IP_I2S_GetLevel(pI2S, TRMode);
-}
-
-/**
- * @brief Configure I2S for Audio Format input
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param audio_format : Audio Format
- * @return SUCCESS or ERROR
- */
-Status Chip_I2S_Config(LPC_I2S_T *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_T *audio_format);
-
-/**
- * @brief Enable/Disable Interrupt with a specific FIFO depth
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param NewState : ENABLE or DISABLE interrupt
- * @param FIFO_Depth : FIFO level creating an irq request
- * @return Nothing
- */
-void Chip_I2S_Int_Cmd(LPC_I2S_T *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @brief Enable/Disable DMA with a specific FIFO depth
- * @param pI2S : The base I2S peripheral on the chip
- * @param TRMode : Mode Rx/Tx
- * @param DMANum : Should be
- * - IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1
- * - IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2
- * @param NewState : ENABLE or DISABLE interrupt
- * @param FIFO_Depth : FIFO level creating an irq request
- * @return Nothing
- */
-void Chip_I2S_DMA_Cmd(LPC_I2S_T *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2S_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
deleted file mode 100644
index 2a9677612..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * @brief LPC18xx/43xx LCD chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LCD_18XX_43XX_H_
-#define __LCD_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the LCD controller
- * @param pLCD : The base of LCD peripheral on the chip
- * @param LCD_ConfigStruct : Pointer to LCD configuration
- * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
- */
-void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_Config_T *LCD_ConfigStruct);
-
-/**
- * @brief Shutdown the LCD controller
- * @param pLCD : The base of LCD peripheral on the chip
- * @return Nothing
- */
-void Chip_LCD_DeInit(LPC_LCD_T *pLCD);
-
-/**
- * @brief Power-on the LCD Panel (power pin)
- * @param pLCD : The base of LCD peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_LCD_PowerOn(LPC_LCD_T *pLCD)
-{
- IP_LCD_PowerOn(pLCD);
-}
-
-/**
- * @brief Power-off the LCD Panel (power pin)
- * @param pLCD : The base of LCD peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_LCD_PowerOff(LPC_LCD_T *pLCD)
-{
- IP_LCD_PowerOff(pLCD);
-}
-
-/**
- * @brief Enable/Disable the LCD Controller
- * @param pLCD : The base of LCD peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_LCD_Enable(LPC_LCD_T *pLCD)
-{
- IP_LCD_Enable(pLCD);
-}
-
-/**
- * @brief Enable/Disable the LCD Controller
- * @param pLCD : The base of LCD peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_LCD_Disable(LPC_LCD_T *pLCD)
-{
- IP_LCD_Disable(pLCD);
-}
-
-/**
- * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
- * Buffer for Dual Panel
- * @param pLCD : The base of LCD peripheral on the chip
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void Chip_LCD_SetUPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
-{
- IP_LCD_SetUPFrameBuffer(pLCD, buffer);
-}
-
-/**
- * @brief Set LCD Lower Panel Frame Buffer for Dual Panel
- * @param pLCD : The base of LCD peripheral on the chip
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void Chip_LCD_SetLPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
-{
- IP_LCD_SetLPFrameBuffer(pLCD, buffer);
-}
-
-/**
- * @brief Configure Cursor
- * @param pLCD : The base of LCD peripheral on the chip
- * @param cursor_size : specify size of cursor
- * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels
- * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels
- * @param sync : cursor sync mode
- * - TRUE :cursor sync to the frame sync pulse
- * - FALSE :cursor async mode
- * @return None
- */
-void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, IP_LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync);
-
-/**
- * @brief Enable Cursor
- * @param pLCD : The base of LCD peripheral on the chip
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_Enable(LPC_LCD_T *pLCD, uint8_t cursor_num)
-{
- IP_LCD_Cursor_Enable(pLCD, cursor_num);
-}
-
-/**
- * @brief Disable Cursor
- * @param pLCD : The base of LCD peripheral on the chip
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_Disable(LPC_LCD_T *pLCD, uint8_t cursor_num)
-{
- IP_LCD_Cursor_Disable(pLCD, cursor_num);
-}
-
-/**
- * @brief Load Cursor Palette
- * @param pLCD : The base of LCD peripheral on the chip
- * @param palette_color : cursor palette 0 value
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(LPC_LCD_T *pLCD, uint32_t palette_color)
-{
- IP_LCD_Cursor_LoadPalette0(pLCD, palette_color);
-}
-
-/**
- * @brief Load Cursor Palette
- * @param pLCD : The base of LCD peripheral on the chip
- * @param palette_color : cursor palette 1 value
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(LPC_LCD_T *pLCD, uint32_t palette_color)
-{
- IP_LCD_Cursor_LoadPalette1(pLCD, palette_color);
-}
-
-/**
- * @brief Set Cursor Position
- * @param pLCD : The base of LCD peripheral on the chip
- * @param x : horizontal position
- * @param y : vertical position
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetPos(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
-{
- IP_LCD_Cursor_SetPos(pLCD, x, y);
-}
-
-/**
- * @brief Set Cursor Clipping Position
- * @param pLCD : The base of LCD peripheral on the chip
- * @param x : horizontal position, should be in range: 0..63
- * @param y : vertical position, should be in range: 0..63
- * @return None
- */
-STATIC INLINE void Chip_LCD_Cursor_SetClip(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
-{
- IP_LCD_Cursor_SetClip(pLCD, x, y);
-}
-
-/**
- * @brief Enable Controller Interrupt
- * @param pLCD : The base of LCD peripheral on the chip
- * @param ints : OR'ed interrupt bits to enable
- * @return None
- */
-STATIC INLINE void Chip_LCD_EnableInts(LPC_LCD_T *pLCD, uint32_t ints)
-{
- IP_LCD_EnableInts(pLCD, ints);
-}
-
-/**
- * @brief Disable Controller Interrupt
- * @param pLCD : The base of LCD peripheral on the chip
- * @param ints : OR'ed interrupt bits to disable
- * @return None
- */
-STATIC INLINE void Chip_LCD_DisableInts(LPC_LCD_T *pLCD, uint32_t ints)
-{
- IP_LCD_DisableInts(pLCD, ints);
-}
-
-/**
- * @brief Clear Controller Interrupt
- * @param pLCD : The base of LCD peripheral on the chip
- * @param ints : OR'ed interrupt bits to clear
- * @return None
- */
-STATIC INLINE void Chip_LCD_ClearInts(LPC_LCD_T *pLCD, uint32_t ints)
-{
- IP_LCD_ClearInts(pLCD, ints);
-}
-
-/**
- * @brief Write Cursor Image into Internal Cursor Image Buffer
- * @param pLCD : The base of LCD peripheral on the chip
- * @param cursor_num : Cursor index
- * @param Image : Pointer to image data
- * @return None
- */
-void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image);
-
-/**
- * @brief Load LCD Palette
- * @param pLCD : The base of LCD peripheral on the chip
- * @param palette : Address of palette table to load
- * @return None
- */
-void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette);
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* __LCD_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/otp_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/otp_18xx_43xx.h
deleted file mode 100644
index 1a8be56e4..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/otp_18xx_43xx.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * @brief LPC18xx/43xx OTP Controller driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __OTP_18XX_43XX_H_
-#define __OTP_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup OTP_18XX_43XX CHIP: LPC18xx/43xx OTP Controller driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief OTP Register block
- */
-typedef struct {
- __IO uint32_t OTP0_0; /*!< (@ 0x40045000) OTP content */
- __IO uint32_t OTP0_1; /*!< (@ 0x40045004) OTP content */
- __IO uint32_t OTP0_2; /*!< (@ 0x40045008) OTP content */
- __IO uint32_t OTP0_3; /*!< (@ 0x4004500C) OTP content */
- __IO uint32_t OTP1_0; /*!< (@ 0x40045010) OTP content */
- __IO uint32_t OTP1_1; /*!< (@ 0x40045014) OTP content */
- __IO uint32_t OTP1_2; /*!< (@ 0x40045018) OTP content */
- __IO uint32_t OTP1_3; /*!< (@ 0x4004501C) OTP content */
- __IO uint32_t OTP2_0; /*!< (@ 0x40045020) OTP content */
- __IO uint32_t OTP2_1; /*!< (@ 0x40045024) OTP content */
- __IO uint32_t OTP2_2; /*!< (@ 0x40045028) OTP content */
- __IO uint32_t OTP2_3; /*!< (@ 0x4004502C) OTP content */
- uint32_t RESERVED0[4];
- __IO uint32_t UNIQUE_KEY0; /*!< (@ 0x40045040) Unique Key bit 31..0. R/W locked at default */
- __IO uint32_t UNIQUE_KEY1; /*!< (@ 0x40045044) Unique Key bit 63..32. R/W locked at default */
- __IO uint32_t UNIQUE_KEY2; /*!< (@ 0x40045048) Unique Key bit 95..64. R/W locked at default */
- __IO uint32_t UNIQUE_KEY3; /*!< (@ 0x4004504C) Unique Key bit 127..96. R/W locked at default */
- __IO uint32_t RANDOM_NUM0; /*!< (@ 0x40045050) Random number bit 31..0. R/W locked at default */
- __IO uint32_t RANDOM_NUM1; /*!< (@ 0x40045054) Random number bit 63..32. R/W locked at default */
- __IO uint32_t RANDOM_NUM2; /*!< (@ 0x40045058) Random number bit 95..64. R/W locked at default */
- __IO uint32_t RANDOM_NUM3; /*!< (@ 0x4004505C) Random number bit 127..96. R/W locked at default */
- __IO uint32_t USER_KEY0; /*!< (@ 0x40045060) User Key bit 31..0. R locked at default */
- __IO uint32_t USER_KEY1; /*!< (@ 0x40045064) User Key bit 63..32. R locked at default */
- __IO uint32_t USER_KEY2; /*!< (@ 0x40045068) User Key bit 95..64. R locked at default */
- __IO uint32_t USER_KEY3; /*!< (@ 0x4004506C) User Key bit 127..96. R locked at default */
- uint32_t RESERVED1[4];
- __IO uint32_t WRTMASK; /*!< (@ 0x40045080) Masks APB write to fuses */
- __O uint32_t STATUS; /*!< (@ 0x40045084) Indicates write status of fuses */
- uint32_t RESERVED2[2];
- __IO uint32_t PROGRAM; /*!< (@ 0x40045090) Enables write of Shuffled AES value to OTP1c */
- __IO uint32_t AES_SSEL; /*!< (@ 0x40045094) Controls selecting source for SKey output to AES Engine */
- __IO uint32_t SHUFFLE_CTRL; /*!< (@ 0x40045098) Shuffle block control */
- uint32_t RESERVED3;
- __IO uint32_t OTP0_WR_LOCK; /*!< (@ 0x400450A0) Locks write access to itself and OTP0 write access */
- __IO uint32_t OTP0_RD_LOCK; /*!< (@ 0x400450A4) Locks write access to itself and OTP0 read access */
- __IO uint32_t OTP1_WR_LOCK; /*!< (@ 0x400450A8) Locks write access to itself and OTP1 write access */
- __IO uint32_t OTP1_RD_LOCK; /*!< (@ 0x400450AC) Locks write access to itself and OTP1 read access */
- __IO uint32_t OTP2_WR_LOCK; /*!< (@ 0x400450B0) Locks write access to itself and OTP2 write access */
- __IO uint32_t OTP2_RD_LOCK; /*!< (@ 0x400450B4) Locks write access to itself and OTP2 read access */
- __IO uint32_t RESERVED4[2];
- __IO uint32_t UNIQUE_KEY_WR_LOCK; /*!< (@ 0x400450C0) Locks write access to itself and Unique Key write access */
- __IO uint32_t UNIQUE_KEY_RD_LOCK; /*!< (@ 0x400450C4) */
- __IO uint32_t RANDOM_NUM_WR_LOCK; /*!< (@ 0x400450C8) */
- __IO uint32_t RANDOM_NUM_RD_LOCK; /*!< (@ 0x400450CC) */
- __IO uint32_t RESERVED5; /*!< (@ 0x400450D0) */
- __IO uint32_t USER_KEY_RD_LOCK; /*!< (@ 0x400450D4) */
-} LPC_OTP_T;
-
-/**
- * @brief OTP Boot Source selection used in Chip driver
- */
-typedef enum CHIP_OTP_BOOT_SRC {
- CHIP_OTP_BOOTSRC_PINS, /*!< Boot source - External pins */
- CHIP_OTP_BOOTSRC_UART0, /*!< Boot source - UART0 */
- CHIP_OTP_BOOTSRC_SPIFI, /*!< Boot source - EMC 8-bit memory */
- CHIP_OTP_BOOTSRC_EMC8, /*!< Boot source - EMC 16-bit memory */
- CHIP_OTP_BOOTSRC_EMC16, /*!< Boot source - EMC 32-bit memory */
- CHIP_OTP_BOOTSRC_EMC32, /*!< Boot source - EMC 32-bit memory */
- CHIP_OTP_BOOTSRC_USB0, /*!< Boot source - DFU USB0 boot */
- CHIP_OTP_BOOTSRC_USB1, /*!< Boot source - DFU USB1 boot */
- CHIP_OTP_BOOTSRC_SPI, /*!< Boot source - SPI boot */
- CHIP_OTP_BOOTSRC_UART3 /*!< Boot source - UART3 */
-} CHIP_OTP_BOOT_SRC_T;
-
-/**
- * @brief Initialize for OTP Controller functions
- * @return Status of Otp_Init function
- * This function will initialise all the OTP driver function pointers
- * and call the ROM OTP Initialisation function.
- */
-uint32_t Chip_OTP_Init(void);
-
-/**
- * @brief Program boot source in OTP Controller
- * @param BootSrc : Boot Source enum value
- * @return Status
- */
-uint32_t Chip_OTP_ProgBootSrc(CHIP_OTP_BOOT_SRC_T BootSrc);
-
-/**
- * @brief Program the JTAG bit in OTP Controller
- * @return Status
- */
-uint32_t Chip_OTP_ProgJTAGDis(void);
-
-/**
- * @brief Program USB ID in OTP Controller
- * @param ProductID : USB Product ID
- * @param VendorID : USB Vendor ID
- * @return Status
- */
-uint32_t Chip_OTP_ProgUSBID(uint32_t ProductID, uint32_t VendorID);
-
-/**
- * @brief Program OTP GP Word memory
- * @param WordNum : Word Number (Select word 0 or word 1 or word 2)
- * @param Data : Data value
- * @param Mask : Mask value
- * @return Status
- * This function available in devices which are not AES capable
- */
-uint32_t Chip_OTP_ProgGPWord(uint32_t WordNum, uint32_t Data, uint32_t Mask);
-
-/**
- * @brief Program AES Key
- * @param KeyNum : Key Number (Select 0 or 1)
- * @param key : Pointer to AES Key (16 bytes required)
- * @return Status
- * This function available in devices which are AES capable
- */
-uint32_t Chip_OTP_ProgKey(uint32_t KeyNum, uint8_t *key);
-
-/**
- * @brief Generate Random Number using HW Random Number Generator
- * @return Random Number value
- */
-uint32_t Chip_OTP_GenRand(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __OTP_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/pmc_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/pmc_18xx_43xx.h
deleted file mode 100644
index d1fad169d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/pmc_18xx_43xx.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * @brief LPC18xx/43xx Power Management Controller driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __PMC_18XX_43XX_H_
-#define __PMC_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup PMC_18XX_43XX CHIP: LPC18xx/43xx Power Management Controller driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/*
- * @brief PMC power states
- */
-typedef enum CHIP_PMC_PWR_STATE {
- PMC_DeepSleep = PMC_PWR_DEEP_SLEEP_MODE, /*!< Deep sleep state */
- PMC_PowerDown = PMC_PWR_POWER_DOWN_MODE, /*!< Power Down state */
- PMC_DeepPowerDown = PMC_PWR_DEEP_POWER_DOWN_MODE, /*!< Power Down state */
-} CHIP_PMC_PWR_STATE_T;
-
-/**
- * @brief Set to sleep power state
- * @return Nothing
- */
-void Chip_PMC_Sleep(void);
-
-/**
- * @brief Set to sleep power mode
- * @param PwrState : Power State as specified in /a CHIP_PMC_PWR_STATE_T enum
- * @return Nothing
- */
-void Chip_PMC_Set_PwrState(CHIP_PMC_PWR_STATE_T PwrState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __PMC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
deleted file mode 100644
index 854f3793d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#include "chip.h"
-
-/*****************************************************************************
- * Private types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Public types/enumerations/variables
- ****************************************************************************/
-
-/*****************************************************************************
- * Private functions
- ****************************************************************************/
-
-/*****************************************************************************
- * Public functions
- ****************************************************************************/
-
-/* Trigger a peripheral reset for the selected peripheral */
-void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber)
-{
- volatile uint32_t *p;
-
- /* To trigger reset- write RESET_CTRLx with a 1 bit */
- p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
- /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
- p += ResetNumber / 32;
-
- /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
- after 1 clock cycle, so set the bit and return */
- *p = (1 << (ResetNumber % 32));
-}
-
-/* Clears reset for the selected peripheral */
-void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber)
-{
- volatile uint32_t *p;
-
- /* To trigger reset- write RESET_CTRLx with a 1 bit */
- p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);
-
- /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */
- p += ResetNumber / 32;
-
- /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear
- after 1 clock cycle, so set the bit and return */
- *p = 0;
-}
-
-/* Checks the reset status of a peripheral */
-bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber)
-{
- volatile uint32_t *read;
-
- read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);
- read += ResetNumber / 32;
-
- /* Reset not asserted if bit is set */
- return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);
-}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
deleted file mode 100644
index b3de14214..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * @brief LPC18xx/43xx Reset Generator Unit driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RGU_18XX_43XX_H_
-#define __RGU_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief RGU reset enumerations
- */
-typedef enum CHIP_RGU_RST {
- RGU_CORE_RST,
- RGU_PERIPH_RST,
- RGU_MASTER_RST,
- RGU_WWDT_RST = 4,
- RGU_CREG_RST,
- RGU_BUS_RST = 8,
- RGU_SCU_RST,
- RGU_M3_RST = 13,
- RGU_LCD_RST = 16,
- RGU_USB0_RST,
- RGU_USB1_RST,
- RGU_DMA_RST,
- RGU_SDIO_RST,
- RGU_EMC_RST,
- RGU_ETHERNET_RST,
- RGU_FLASHA_RST = 25,
- RGU_EEPROM_RST = 27,
- RGU_GPIO_RST,
- RGU_FLASHB_RST,
- RGU_TIMER0_RST = 32,
- RGU_TIMER1_RST,
- RGU_TIMER2_RST,
- RGU_TIMER3_RST,
- RGU_RITIMER_RST,
- RGU_SCT_RST,
- RGU_MOTOCONPWM_RST,
- RGU_QEI_RST,
- RGU_ADC0_RST,
- RGU_ADC1_RST,
- RGU_DAC_RST,
- RGU_UART0_RST = 44,
- RGU_UART1_RST,
- RGU_UART2_RST,
- RGU_UART3_RST,
- RGU_I2C0_RST,
- RGU_I2C1_RST,
- RGU_SSP0_RST,
- RGU_SSP1_RST,
- RGU_I2S_RST,
- RGU_SPIFI_RST,
- RGU_CAN1_RST,
- RGU_CAN0_RST,
-#ifdef CHIP_LPC43XX
- RGU_M0APP_RST,
- RGU_SGPIO_RST,
- RGU_SPI_RST,
-#endif
- RGU_LAST_RST = 63,
-} CHIP_RGU_RST_T;
-
-/**
- * @brief RGU register structure
- */
-typedef struct { /*!< RGU Structure */
- __I uint32_t RESERVED0[64];
- __O uint32_t RESET_CTRL0; /*!< Reset control register 0 */
- __O uint32_t RESET_CTRL1; /*!< Reset control register 1 */
- __I uint32_t RESERVED1[2];
- __IO uint32_t RESET_STATUS0; /*!< Reset status register 0 */
- __IO uint32_t RESET_STATUS1; /*!< Reset status register 1 */
- __IO uint32_t RESET_STATUS2; /*!< Reset status register 2 */
- __IO uint32_t RESET_STATUS3; /*!< Reset status register 3 */
- __I uint32_t RESERVED2[12];
- __I uint32_t RESET_ACTIVE_STATUS0; /*!< Reset active status register 0 */
- __I uint32_t RESET_ACTIVE_STATUS1; /*!< Reset active status register 1 */
- __I uint32_t RESERVED3[170];
- __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
-} LPC_RGU_T;
-
-/**
- * @brief Trigger a peripheral reset for the selected peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return Nothing
- */
-void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber);
-
-/**
- * @brief Checks the reset status of a peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return true if the periperal is still being reset
- */
-bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber);
-
-/**
- * @brief Clears reset for the selected peripheral
- * @param ResetNumber : Peripheral reset number to trigger
- * @return Nothing
- * Almost all peripherals will auto clear the reset bit. Only a few peripherals
- * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require
- * this function to clear the reset bit.
- */
-void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RGU_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
deleted file mode 100644
index 00e80cc71..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * @brief LPC18xx/43xx RITimer chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RITIMER_18XX_43XX_H_
-#define __RITIMER_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the RIT
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);
-
-/**
- * @brief Shutdown the RIT
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);
-
-/**
- * @brief Enable Timer
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)
-{
- IP_RIT_Enable(pRITimer);
-}
-
-/**
- * @brief Disable Timer
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)
-{
- IP_RIT_Disable(pRITimer);
-}
-
-/**
- * @brief Enable timer debug
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)
-{
- IP_RIT_TimerDebugEnable(pRITimer);
-}
-
-/**
- * @brief Disable timer debug
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)
-{
- IP_RIT_TimerDebugDisable(pRITimer);
-}
-
-/**
- * @brief Check whether interrupt flag is set or not
- * @param pRITimer : RITimer peripheral selected
- * @return Current interrupt status, either ET or UNSET
- */
-STATIC INLINE IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
-{
- return IP_RIT_GetIntStatus(pRITimer);
-}
-
-/**
- * @brief Set a tick value for the interrupt to time out
- * @param pRITimer : RITimer peripheral selected
- * @param val : value (in ticks) of the interrupt to be set
- * @return None
- */
-STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)
-{
- IP_RIT_SetCOMPVAL(pRITimer, val);
-}
-
-/**
- * @brief Enables or clears the RIT or interrupt
- * @param pRITimer : RITimer peripheral selected
- * @param val : RIT to be set, one or more RIT_CTRL_* values
- * @return None
- */
-STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)
-{
- IP_RIT_EnableCTRL(pRITimer, val);
-}
-
-/**
- * @brief Clears the RIT interrupt
- * @param pRITimer : RITimer peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)
-{
- IP_RIT_EnableCTRL(pRITimer, RIT_CTRL_INT);
-}
-
-/**
- * @brief Returns the current RIT Counter value
- * @param pRITimer : RITimer peripheral selected
- * @return the current timer counter value
- */
-STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)
-{
- return IP_RIT_GetCounter(pRITimer);
-}
-
-/**
- * @brief Set timer interval value
- * @param pRITimer : RITimer peripheral selected
- * @param time_interval : timer interval value (ms)
- * @return None
- */
-void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RITIMER_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
deleted file mode 100644
index f11df135a..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * @brief LPC18xx/43xx RTC driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RTC_18XX_43XX_H_
-#define __RTC_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @return None
- */
-void Chip_RTC_Init(LPC_RTC_T *pRTC);
-
-/**
- * @brief De-initialize the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RTC_DeInit(LPC_RTC_T *pRTC)
-{
- IP_RTC_DeInit(LPC_RTC);
-}
-
-/**
- * @brief Reset clock tick counter in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @return None
- */
-STATIC INLINE void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC)
-{
- IP_RTC_ResetClockTickCounter(LPC_RTC);
-}
-
-/**
- * @brief Start/Stop RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param NewState : New State of this function, should be:
- * - ENABLE :The time counters are enabled
- * - DISABLE :The time counters are disabled
- * @return None
- */
-STATIC INLINE void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState)
-{
- IP_RTC_Enable(LPC_RTC, NewState);
-}
-
-/**
- * @brief Enable/Disable Counter increment interrupt for a time type
- * in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-STATIC INLINE void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState)
-{
- IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState);
-}
-
-/**
- * @brief Enable/Disable Alarm interrupt for a time type
- * in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-STATIC INLINE void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState)
-{
- IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState);
-}
-
-/**
- * @brief Set current time value for a time type in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param Timetype : time field index type to set
- * @param TimeValue : Value to palce in time field
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
-{
- IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue);
-}
-
-/**
- * @brief Get current time value for a type time type
- * @param pRTC : RTC peripheral selected
- * @param Timetype : Time field index type to get
- * @return Value of time field according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)
-{
- return IP_RTC_GetTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief Set full time in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param pFullTime : Pointer to full time data
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_SetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Get full time from the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-STATIC INLINE void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_GetFullTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Set alarm time value for a time type
- * @param pRTC : RTC peripheral selected
- * @param Timetype : Time index field to set
- * @param ALValue : Alarm time value to set
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
-{
- IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue);
-}
-
-/**
- * @brief Get alarm time value for a time type
- * @param pRTC : RTC peripheral selected
- * @param Timetype : Time index field to get
- * @return Value of Alarm time according to specified time type
- */
-STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)
-{
- return IP_RTC_GetAlarmTime(LPC_RTC, Timetype);
-}
-
-/**
- * @brief Set full alarm time in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param pFullTime : Pointer to full time record to set alarm
- * @return None
- */
-STATIC INLINE void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Get full alarm time in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-STATIC INLINE void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)
-{
- IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime);
-}
-
-/**
- * @brief Write value to General purpose registers
- * @param pRegFile : RegFile peripheral selected
- * @param index : General purpose register index
- * @param Value : Value to write
- * @return None
- * @note These General purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are
- * powered in the RTC power domain.
- */
-STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t Value)
-{
- IP_REGFILE_Write(pRegFile, index, Value);
-}
-
-/**
- * @brief Read value from General purpose registers
- * @param pRegFile : RegFile peripheral selected
- * @param index : General purpose register index
- * @return Read Value
- * @note TheseGeneral purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are
- * powered in the RTC power domain.
- */
-STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index)
-{
- return IP_REGFILE_Read(pRegFile, index);
-}
-
-/**
- * @brief Enable/Disable calibration counter in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param NewState : New State of this function, should be:
- * - ENABLE :The calibration counter is enabled and counting
- * - DISABLE :The calibration counter is disabled and reset to zero
- * @return None
- */
-STATIC INLINE void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState)
-{
- IP_RTC_CalibCounterCmd(LPC_RTC, NewState);
-}
-
-/**
- * @brief Configures Calibration in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param CalibValue : Calibration value, should be in range from 0 to 131,072
- * @param CalibDir : Calibration Direction, should be:
- * - RTC_CALIB_DIR_FORWARD :Forward calibration
- * - RTC_CALIB_DIR_BACKWARD :Backward calibration
- * @return None
- */
-STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)
-{
- IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir);
-}
-
-/**
- * @brief Clear specified Location interrupt pending in the RTC peripheral
- * @param pRTC : RTC peripheral selected
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.
- * - RTC_INT_ALARM :Clear alarm interrupt pending
- * @return None
- */
-STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
-{
- IP_RTC_ClearIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @brief Check whether if specified location interrupt in the RTC peripheral is set or not
- * @param pRTC : RTC peripheral selected
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
- * - RTC_INT_ALARM: Alarm generated an interrupt.
- * @return New state of specified Location interrupt in RTC peripheral, SET OR RESET
- */
-STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
-{
- return IP_RTC_GetIntPending(LPC_RTC, IntType);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sct_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sct_18xx_43xx.h
deleted file mode 100644
index 6135c0dd0..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sct_18xx_43xx.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * @brief LPC18xx/43xx State Configurable Timer driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SCT_18XX_43XX_H_
-#define __SCT_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SCT_18XX_43XX CHIP: LPC18xx/43xx State Configurable Timer driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize SCT
- * @param pSCT : Pointer to SCT register block
- * @return Nothing
- */
-void Chip_SCT_Init(LPC_SCT_T *pSCT);
-
-/**
- * @brief Shutdown SCT
- * @param pSCT : Pointer to SCT register block
- * @return Nothing
- */
-void Chip_SCT_DeInit(LPC_SCT_T *pSCT);
-
-/**
- * @brief Configure SCT
- * @param pSCT : Pointer to SCT register block
- * @param value : SCT Configuration register value
- * @return Nothing
- * Initialise the SCT configuration register with \a value
- */
-STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value)
-{
- IP_SCT_Config(pSCT, value);
-}
-
-/**
- * @brief Set or Clear the Control register
- * @param pSCT : Pointer to SCT register block
- * @param value : SCT Control register value
- * @param ena : ENABLE - To set the fields specified by value
- * : DISABLE - To clear the field specified by value
- * @return Nothing
- * Set or clear the control register bits as specified by the \a value
- * parameter. If \a ena is set to ENABLE, the mentioned register fields
- * will be set. If \a ena is set to DISABLE, the mentioned register
- * fields will be cleared
- */
-STATIC INLINE void Chip_SCT_ControlSetClr(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena)
-{
- IP_SCT_ControlSetClr(pSCT, value, ena);
-}
-
-/**
- * @brief Set the conflict resolution
- * @param pSCT : Pointer to SCT register block
- * @param outnum : Output number
- * @param value : Output value
- * - SCT_RES_NOCHANGE :No change
- * - SCT_RES_SET_OUTPUT :Set output
- * - SCT_RES_CLEAR_OUTPUT :Clear output
- * - SCT_RES_TOGGLE_OUTPUT :Toggle output
- * : SCT_RES_NOCHANGE
- * : DISABLE - To clear the field specified by value
- * @return Nothing
- * Set conflict resolution for the output \a outnum
- */
-STATIC INLINE void Chip_SCT_ConflictResolutionSet(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value)
-{
- IP_SCT_ConflictResolutionSet(pSCT, outnum, value);
-}
-
-/**
- * @brief Clear the SCT event flag
- * @param pSCT : Pointer to SCT register block
- * @param even_num : SCT Event number
- * @return Nothing
- * Clear the SCT event flag for the specified event \a even_num
- */
-STATIC INLINE void Chip_SCT_EventFlagClear(LPC_SCT_T *pSCT, uint8_t even_num)
-{
- IP_SCT_EventFlagClear(pSCT, even_num);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SCT_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
deleted file mode 100644
index c58b66bd1..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SCU_18XX_43XX_H_
-#define __SCU_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief System Control Unit register block
- */
-typedef struct {
- __IO uint32_t SFSP[16][32];
- __I uint32_t RESERVED0[256];
- __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */
- __I uint32_t RESERVED16[28];
- __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */
- __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */
- __IO uint32_t ENAIO[3]; /*!< Analog function select registerS */
- __I uint32_t RESERVED17[27];
- __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */
- __I uint32_t RESERVED18[63];
- __IO uint32_t PINTSEL0; /*!< Pin interrupt select register for pin interrupts 0 to 3. */
- __IO uint32_t PINTSEL1; /*!< Pin interrupt select register for pin interrupts 4 to 7. */
-} LPC_SCU_T;
-
-/**
- * SCU function and mode selection definitions
- * See the User Manual for specific modes and functions supoprted by the
- * various LPC18xx/43xx devices. Functionality can vary per device.
- */
-#define SCU_MODE_MODE_INACT (0x0 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */
-#define SCU_MODE_MODE_PULLDOWN (0x1 << 3) /*!< Enable pull-down resistor at pad */
-#define SCU_MODE_MODE_PULLUP (0x2 << 3) /*!< Enable pull-up resistor at pad */
-#define SCU_MODE_MODE_REPEATER (0x3 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /*!< Enable high-speed slew */
-#define SCU_MODE_INBUFF_EN (0x1 << 6) /*!< Enable Input buffer */
-#define SCU_MODE_ZIF_DIS (0x1 << 7) /*!< Disable input glitch filter */
-#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /*!< Normal drive: 4mA drive strength */
-#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /*!< Medium drive: 8mA drive strength */
-#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /*!< High drive: 14mA drive strength */
-#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /*!< Ultra high- drive: 20mA drive strength */
-#define SCU_MODE_FUNC0 0x0 /*!< Selects pin function 0 */
-#define SCU_MODE_FUNC1 0x1 /*!< Selects pin function 1 */
-#define SCU_MODE_FUNC2 0x2 /*!< Selects pin function 2 */
-#define SCU_MODE_FUNC3 0x3 /*!< Selects pin function 3 */
-#define SCU_MODE_FUNC4 0x4 /*!< Selects pin function 4 */
-#define SCU_MODE_FUNC5 0x5 /*!< Selects pin function 5 */
-#define SCU_MODE_FUNC6 0x6 /*!< Selects pin function 6 */
-#define SCU_MODE_FUNC7 0x7 /*!< Selects pin function 7 */
-#define SCU_PINIO_FAST (SCU_MODE_MODE_PULLUP | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
-
-/**
- * SCU function and mode selection definitions (old)
- * For backwards compatibility.
- */
-#define MD_PUP (0x0 << 3) /** Disable pull-down and pull-up resistor at resistor at pad */
-#define MD_BUK (0x1 << 3) /** Enable pull-down resistor at pad */
-#define MD_PLN (0x2 << 3) /** Enable pull-up resistor at pad */
-#define MD_PDN (0x3 << 3) /** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define MD_EHS (0x1 << 5) /** Enable fast slew rate */
-#define MD_EZI (0x1 << 6) /** Input buffer enable */
-#define MD_ZI (0x1 << 7) /** Disable input glitch filter */
-#define MD_EHD0 (0x1 << 8) /** EHD driver strength low bit */
-#define MD_EHD1 (0x1 << 8) /** EHD driver strength high bit */
-#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
-#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /** Pin configuration for STANDARD/FAST mode I2C */
-#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /** Pin configuration for Fast-mode Plus I2C */
-#define FUNC0 0x0 /** Pin function 0 */
-#define FUNC1 0x1 /** Pin function 1 */
-#define FUNC2 0x2 /** Pin function 2 */
-#define FUNC3 0x3 /** Pin function 3 */
-#define FUNC4 0x4 /** Pin function 4 */
-#define FUNC5 0x5 /** Pin function 5 */
-#define FUNC6 0x6 /** Pin function 6 */
-#define FUNC7 0x7 /** Pin function 7 */
-
-#define PORT_OFFSET 0x80 /** Port offset definition */
-#define PIN_OFFSET 0x04 /** Pin offset definition */
-
-/** Returns the SFSP register address in the SCU for a pin and port, recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
-#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
-
-/** Returns the address in the SCU for a SFSCLK clock register, recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
-#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
-
-/**
- * @brief Sets I/O Control pin mux
- * @param port : Port number, should be: 0..15
- * @param pin : Pin number, should be: 0..31
- * @param modefunc : OR'ed values or type SCU_MODE_*
- * @return Nothing
- * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use
- * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins.
- */
-STATIC INLINE void Chip_SCU_PinMuxSet(uint8_t port, uint8_t pin, uint16_t modefunc)
-{
- LPC_SCU->SFSP[port][pin] = modefunc;
-}
-
-/**
- * @brief Configure pin function
- * @param port : Port number, should be: 0..15
- * @param pin : Pin number, should be: 0..31
- * @param mode : OR'ed values or type SCU_MODE_*
- * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7
- * @return Nothing
- * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use
- * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins.
- */
-STATIC INLINE void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
-{
- Chip_SCU_PinMuxSet(port, pin, (mode | (uint16_t) func));
-}
-
-/**
- * @brief Configure clock pin function (pins SFSCLKx)
- * @param clknum : Clock pin number, should be: 0..3
- * @param modefunc : OR'ed values or type SCU_MODE_*
- * @return Nothing
- */
-STATIC INLINE void Chip_SCU_ClockPinMuxSet(uint8_t clknum, uint16_t modefunc)
-{
- LPC_SCU->SFSCLK[clknum] = (uint32_t) modefunc;
-}
-
-/**
- * @brief Configure clock pin function (pins SFSCLKx)
- * @param clknum : Clock pin number, should be: 0..3
- * @param mode : OR'ed values or type SCU_MODE_*
- * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7
- * @return Nothing
- */
-STATIC INLINE void Chip_SCU_ClockPinMux(uint8_t clknum, uint16_t mode, uint8_t func)
-{
- LPC_SCU->SFSCLK[clknum] = ((uint32_t) mode | (uint32_t) func);
-}
-
-/**
- * @brief GPIO Interrupt Pin Select
- * @param PortSel : GPIO PINTSEL interrupt, should be: 0 to 7
- * @param PortNum : GPIO port number interrupt, should be: 0 to 7
- * @param PinNum : GPIO pin number Interrupt , should be: 0 to 31
- * @return Nothing
- */
-void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);
-
-/**
- * @brief I2C Pin Configuration
- * @param I2C0Mode : I2C0 mode, should be:
- * - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit
- * - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit
- * @return Nothing
- */
-STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
-{
- LPC_SCU->SFSI2C0 = I2C0Mode;
-}
-
-/**
- * @brief ADC Pin Configuration
- * @param ADC_ID : ADC number
- * @param channel : ADC channel
- * @return Nothing
- */
-STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
-{
- LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
-}
-
-/**
- * @brief DAC Pin Configuration
- * @return Nothing
- */
-STATIC INLINE void Chip_SCU_DAC_Analog_Config(void)
-{
- /*Enable analog function DAC on pin P4_4*/
- LPC_SCU->ENAIO[2] |= 1;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SCU_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdif_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdif_18xx_43xx.h
deleted file mode 100644
index ba47bd74d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdif_18xx_43xx.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/SDIO driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDIF_18XX_43XX_H_
-#define __SDIF_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SDIF_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** @brief Setup options for the SDIO driver
- */
-#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */
-#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/
-#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */
-#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */
-#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */
-#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */
-#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */
-#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */
-#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */
-#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */
-
-/**
- * @brief Detect if an SD card is inserted
- * @param pSDMMC : SDMMC peripheral selected
- * @return Returns 0 if a card is detected, otherwise 1
- * @note Detect if an SD card is inserted
- * (uses SD_CD pin, returns 0 on card detect)
- */
-STATIC INLINE int32_t Chip_SDIF_CardNDetect(LPC_SDMMC_T *pSDMMC)
-{
- return IP_SDMMC_CardNDetect(pSDMMC);
-}
-
-/**
- * @brief Detect if write protect is enabled
- * @param pSDMMC : SDMMC peripheral selected
- * @return Returns 1 if card is write protected, otherwise 0
- * @note Detect if write protect is enabled
- * (uses SD_WP pin, returns 1 if card is write protected)
- */
-STATIC INLINE int32_t Chip_SDIF_CardWpOn(LPC_SDMMC_T *pSDMMC)
-{
- return IP_SDMMC_CardWpOn(pSDMMC);
-}
-
-/**
- * @brief Initializes the SD/MMC card controller
- * @param pSDMMC : SDMMC peripheral selected
- * @return None
- */
-void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @brief Shutdown the SD/MMC card controller
- * @param pSDMMC : SDMMC peripheral selected
- * @return None
- */
-void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @brief Disable slot power
- * @param pSDMMC : SDMMC peripheral selected
- * @return None
- * @note Uses SD_POW pin, set to low.
- */
-STATIC INLINE void Chip_SDIF_PowerOff(LPC_SDMMC_T *pSDMMC)
-{
- IP_SDMMC_PowerOff(pSDMMC);
-}
-
-/**
- * @brief Enable slot power
- * @param pSDMMC : SDMMC peripheral selected
- * @return None
- * @note Uses SD_POW pin, set to high.
- */
-STATIC INLINE void Chip_SDIF_PowerOn(LPC_SDMMC_T *pSDMMC)
-{
- IP_SDMMC_PowerOn(pSDMMC);
-}
-
-/**
- * @brief Sets the SD interface interrupt mask
- * @param pSDMMC : SDMMC peripheral selected
- * @param iVal : Interrupts to enable, Or'ed values MCI_INT_*
- * @return None
- */
-STATIC INLINE void Chip_SDIF_SetIntMask(LPC_SDMMC_T *pSDMMC, uint32_t iVal)
-{
- IP_SDMMC_SetIntMask(pSDMMC, iVal);
-}
-
-/**
- * @brief Returns the current SD status, clears pending ints, and disables all ints
- * @param pSDMMC : SDMMC peripheral selected
- * @return Current pending interrupt status of Or'ed values MCI_INT_*
- */
-uint32_t Chip_SDIF_GetIntStatus(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDIF_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
deleted file mode 100644
index cd421c2aa..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * @brief LPC18xx/43xx SD/MMC card driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDMMC_18XX_43XX_H_
-#define __SDMMC_18XX_43XX_H_
-
-#include "lpc_sdmmc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/MMC driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-#define CMD_MASK_RESP (0x3UL << 28)
-#define CMD_RESP(r) (((r) & 0x3) << 28)
-#define CMD_RESP_R0 (0 << 28)
-#define CMD_RESP_R1 (1 << 28)
-#define CMD_RESP_R2 (2 << 28)
-#define CMD_RESP_R3 (3 << 28)
-#define CMD_BIT_AUTO_STOP (1 << 24)
-#define CMD_BIT_APP (1 << 23)
-#define CMD_BIT_INIT (1 << 22)
-#define CMD_BIT_BUSY (1 << 21)
-#define CMD_BIT_LS (1 << 20) /* Low speed, used during acquire */
-#define CMD_BIT_DATA (1 << 19)
-#define CMD_BIT_WRITE (1 << 18)
-#define CMD_BIT_STREAM (1 << 17)
-#define CMD_MASK_CMD (0xff)
-#define CMD_SHIFT_CMD (0)
-
-#define CMD(c, r) ( ((c) & CMD_MASK_CMD) | CMD_RESP((r)) )
-
-#define CMD_IDLE CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS | CMD_BIT_INIT
-#define CMD_SD_OP_COND CMD(SD_APP_OP_COND, 1) | CMD_BIT_LS | CMD_BIT_APP
-#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1) | CMD_BIT_LS
-#define CMD_MMC_OP_COND CMD(MMC_SEND_OP_COND, 3) | CMD_BIT_LS | CMD_BIT_INIT
-#define CMD_ALL_SEND_CID CMD(MMC_ALL_SEND_CID, 2) | CMD_BIT_LS
-#define CMD_MMC_SET_RCA CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS
-#define CMD_SD_SEND_RCA CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS
-#define CMD_SEND_CSD CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS
-#define CMD_SEND_EXT_CSD CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA
-#define CMD_DESELECT_CARD CMD(MMC_SELECT_CARD, 0)
-#define CMD_SELECT_CARD CMD(MMC_SELECT_CARD, 1)
-#define CMD_SET_BLOCKLEN CMD(MMC_SET_BLOCKLEN, 1)
-#define CMD_SEND_STATUS CMD(MMC_SEND_STATUS, 1)
-#define CMD_READ_SINGLE CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA
-#define CMD_READ_MULTIPLE CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP
-#define CMD_SD_SET_WIDTH CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP
-#define CMD_STOP CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY
-#define CMD_WRITE_SINGLE CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE
-#define CMD_WRITE_MULTIPLE CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP
-
-/* Card specific setup data */
-typedef struct _mci_card_struct {
- sdif_device sdif_dev;
- SDMMC_CARD_T card_info;
-} mci_card_struct;
-
-/**
- * @brief Get card's current state (idle, transfer, program, etc.)
- * @param pSDMMC : SDMMC peripheral selected
- * @return Current SD card transfer state
- */
-int32_t Chip_SDMMC_GetState(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @brief Function to enumerate the SD/MMC/SDHC/MMC+ cards
- * @param pSDMMC : SDMMC peripheral selected
- * @param pcardinfo : Pointer to pre-allocated card info structure
- * @return 1 if a card is acquired, otherwise 0
- */
-uint32_t Chip_SDMMC_Acquire(LPC_SDMMC_T *pSDMMC, mci_card_struct *pcardinfo);
-
-/**
- * @brief Get the device size of SD/MMC card (after enumeration)
- * @param pSDMMC : SDMMC peripheral selected
- * @return Card size in number of bytes (capacity)
- */
-int32_t Chip_SDMMC_GetDeviceSize(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @brief Get the number of device blocks of SD/MMC card (after enumeration)
- * Since Chip_SDMMC_GetDeviceSize is limited to 32 bits cards with greater than
- * 2 GBytes of data will not be correct, in such cases users can use this function
- * to get the size of the card in blocks.
- * @param pSDMMC : SDMMC peripheral selected
- * @return Number of 512 bytes blocks in the card
- */
-int32_t Chip_SDMMC_GetDeviceBlocks(LPC_SDMMC_T *pSDMMC);
-
-/**
- * @brief Performs the read of data from the SD/MMC card
- * @param pSDMMC : SDMMC peripheral selected
- * @param buffer : Pointer to data buffer to copy to
- * @param start_block : Start block number
- * @param num_blocks : Number of block to read
- * @return Bytes read, or 0 on error
- */
-int32_t Chip_SDMMC_ReadBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks);
-
-/**
- * @brief Performs write of data to the SD/MMC card
- * @param pSDMMC : SDMMC peripheral selected
- * @param buffer : Pointer to data buffer to copy to
- * @param start_block : Start block number
- * @param num_blocks : Number of block to write
- * @return Number of bytes actually written, or 0 on error
- */
-int32_t Chip_SDMMC_WriteBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDMMC_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h
deleted file mode 100644
index c236296ed..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * @brief LPC18xx/43xx SSP driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SSP_18XX_43XX_H_
-#define __SSP_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/*
- * @brief SSP clock format
- */
-typedef enum CHIP_SSP_CLOCK_FORMAT {
- SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */
- SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */
- SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */
- SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */
- SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
- SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
- SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
- SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
-} CHIP_SSP_CLOCK_MODE_T;
-
-/*
- * @brief SSP frame format
- */
-typedef enum CHIP_SSP_FRAME_FORMAT {
- SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */
- CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */
- SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */
-} CHIP_SSP_FRAME_FORMAT_T;
-
-/*
- * @brief Number of bits per frame
- */
-typedef enum CHIP_SSP_BITS {
- SSP_BITS_4 = (3u << 0), /**< 4 bits/frame */
- SSP_BITS_5 = (4u << 0), /**< 5 bits/frame */
- SSP_BITS_6 = (5u << 0), /**< 6 bits/frame */
- SSP_BITS_7 = (6u << 0), /**< 7 bits/frame */
- SSP_BITS_8 = (7u << 0), /**< 8 bits/frame */
- SSP_BITS_9 = (8u << 0), /**< 9 bits/frame */
- SSP_BITS_10 = (9u << 0), /**< 10 bits/frame */
- SSP_BITS_11 = (10u << 0), /**< 11 bits/frame */
- SSP_BITS_12 = (11u << 0), /**< 12 bits/frame */
- SSP_BITS_13 = (12u << 0), /**< 13 bits/frame */
- SSP_BITS_14 = (13u << 0), /**< 14 bits/frame */
- SSP_BITS_15 = (14u << 0), /**< 15 bits/frame */
- SSP_BITS_16 = (15u << 0), /**< 16 bits/frame */
-} CHIP_SSP_BITS_T;
-
-/*
- * @brief SSP config format
- */
-typedef struct SSP_ConfigFormat {
- CHIP_SSP_BITS_T bits; /**< Format config: bits/frame */
- CHIP_SSP_CLOCK_MODE_T clockMode;/**< Format config: clock phase/polarity */
- CHIP_SSP_FRAME_FORMAT_T frameFormat;/**< Format config: SPI/TI/Microwire */
-} SSP_ConfigFormat;
-
-/*
- * @brief SSP mode
- */
-typedef enum CHIP_SSP_MODE {
- SSP_MODE_MASTER = (0 << 2), /**< Master mode */
- SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */
-} CHIP_SSP_MODE_T;
-
-/*
- * @brief SPI address
- */
-typedef struct {
- uint8_t port;
- uint8_t pin;
-} SPI_Address_t;
-
-/*
- * @brief SSP data setup structure
- */
-typedef struct {
- void *tx_data; /**< Pointer to transmit data */
- uint32_t tx_cnt; /**< Transmit counter */
- void *rx_data; /**< Pointer to transmit data */
- uint32_t rx_cnt; /**< Receive counter */
- uint32_t length; /**< Length of transfer data */
-} Chip_SSP_DATA_SETUP_T;
-
-/** SSP configuration parameter defines */
-/** Clock phase control bit */
-#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
-#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
-
-/** Clock polarity control bit */
-/* There's no bug here!!!
- * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
- * That means the active clock is in HI state.
- * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
- * high between frames. That means the active clock is in LO state.
- */
-#define SSP_CPOL_HI SSP_CR0_CPOL_LO
-#define SSP_CPOL_LO SSP_CR0_CPOL_HI
-
-/** SSP master mode enable */
-#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
-#define SSP_MASTER_MODE SSP_CR1_MASTER_EN
-
-/**
- * @brief Get the current status of SSP controller
- * @param pSSP : The base of SSP peripheral on the chip
- * @param Stat : Type of status, should be :
- * - SSP_STAT_TFE
- * - SSP_STAT_TNF
- * - SSP_STAT_RNE
- * - SSP_STAT_RFF
- * - SSP_STAT_BSY
- * @return SSP controller status, SET or RESET
- */
-STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, IP_SSP_STATUS_T Stat)
-{
- return IP_SSP_GetStatus(pSSP, Stat);
-}
-
-/**
- * @brief Enable SSP operation
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
-{
- IP_SSP_Enable(pSSP);
-}
-
-/**
- * @brief Disable SSP operation
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
-{
- IP_SSP_Disable(pSSP);
-}
-
-/**
- * @brief Enable SSP DMA
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
-{
- IP_SSP_DMA_Enable(pSSP, SSP_DMA_BITMASK);
-}
-
-/**
- * @brief Disable SSP DMA
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
-{
- IP_SSP_DMA_Disable(pSSP, SSP_DMA_BITMASK);
-}
-
-/**
- * @brief Enable loopback mode
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- * @note Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
-{
- IP_SSP_EnableLoopBack(pSSP);
-}
-
-/**
- * @brief Disable loopback mode
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- * @note Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
-{
- IP_SSP_DisableLoopBack(pSSP);
-}
-
-/**
- * @brief Clean all data in RX FIFO of SSP
- * @param pSSP : The base SSP peripheral on the chip
- * @return Nothing
- */
-void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
-
-/**
- * @brief SSP Interrupt Read/Write with 8-bit frame width
- * @param pSSP : The base SSP peripheral on the chip
- * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
- * information about transmit/receive data configuration
- * @return SUCCESS or ERROR
- */
-Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
-
-/**
- * @brief SSP Interrupt Read/Write with 16-bit frame width
- * @param pSSP : The base SSP peripheral on the chip
- * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
- * information about transmit/receive data configuration
- * @return SUCCESS or ERROR
- */
-Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
-
-/**
- * @brief SSP Polling Read/Write in blocking mode
- * @param pSSP : The base SSP peripheral on the chip
- * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
- * information about transmit/receive data configuration
- * @return Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. It starts with writing phase and after that,
- * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
- * through xf_setup param.
- */
-uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
-
-/**
- * @brief SSP Polling Write in blocking mode
- * @param pSSP : The base SSP peripheral on the chip
- * @param buffer : Buffer address
- * @param buffer_len : Buffer length
- * @return Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. First, a writing operation will send
- * the needed data. After that, a dummy reading operation is generated to clear data buffer
- */
-uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
-
-/**
- * @brief Note here
- * @param pSSP : The base SSP peripheral on the chip
- * @param buffer : Buffer address
- * @param buffer_len : The length of buffer
- * @return Actual data length has been transferred
- *
- * This function can be used in both master and slave mode. First, a dummy writing operation is generated
- * to clear data buffer. After that, a reading operation will receive the needed data
- */
-uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
-
-/**
- * @brief Initialize the SSP
- * @param pSSP : The base SSP peripheral on the chip
- * @return Nothing
- */
-void Chip_SSP_Init(LPC_SSP_T *pSSP);
-
-/**
- * @brief Shutdown the SSP
- * @param pSSP : The base SSP peripheral on the chip
- * @return Nothing
- */
-void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
-
-/**
- * @brief Set the SSP operating modes, master or slave
- * @param pSSP : The base SSP peripheral on the chip
- * @param master : 1 to set master, 0 to set slave
- * @return Nothing
- */
-void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
-
-/**
- * @brief Set the clock frequency for SSP interface
- * @param pSSP : The base SSP peripheral on the chip
- * @param bitRate : The SSP bit rate
- * @return Nothing
- */
-void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
-
-/**
- * @brief Set up the SSP frame format
- * @param pSSP : The base SSP peripheral on the chip
- * @param format : Structure used to format frame
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, SSP_ConfigFormat *format)
-{
- IP_SSP_SetFormat(pSSP, format->bits, format->frameFormat, format->clockMode);
-}
-
-/**
- * @brief Enable SSP interrupt
- * @param pSSP : The base SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
-{
- IP_SSP_Int_Enable(pSSP, SSP_TXIM);
-}
-
-/**
- * @brief Disable SSP interrupt
- * @param pSSP : The base SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
-{
- IP_SSP_Int_Disable(pSSP, SSP_TXIM);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SSP_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h
deleted file mode 100644
index c620d54e8..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * @brief 18xx/43xx Timer/PWM control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __TIMER_18XX_43XX_H_
-#define __TIMER_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx Timer driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Initialize a timer
- * @param pTMR : Pointer to timer IP register address
- * @return Nothing
- */
-void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
-
-/**
- * @brief Shutdown a timer
- * @param pTMR : Pointer to timer IP register address
- * @return Nothing
- */
-void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
-
-/**
- * @brief Determine if a match interrupt is pending
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match interrupt number to check
- * @return false if the interrupt is not pending, otherwise true
- * Determine if the match interrupt for the passed timer and match
- * counter is pending.
- */
-STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- return IP_TIMER_MatchPending(pTMR, matchnum);
-}
-
-/**
- * @brief Determine if a capture interrupt is pending
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture interrupt number to check
- * @return false if the interrupt is not pending, otherwise true
- * Determine if the capture interrupt for the passed capture pin is
- * pending.
- */
-STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- return IP_TIMER_CapturePending(pTMR, capnum);
-}
-
-/**
- * @brief Clears a (pending) match interrupt
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match interrupt number to clear
- * @return Nothing
- * Clears a pending timer match interrupt.
- */
-STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_ClearMatch(pTMR, matchnum);
-}
-
-/**
- * @brief Clears a (pending) capture interrupt
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture interrupt number to clear
- * @return Nothing
- * Clears a pending timer capture interrupt.
- */
-STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_ClearCapture(pTMR, capnum);
-}
-
-/**
- * @brief Enables the timer (starts count)
- * @param pTMR : Pointer to timer IP register address
- * @return Nothing
- * Enables the timer to start counting.
- */
-STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
-{
- IP_TIMER_Enable(pTMR);
-}
-
-/**
- * @brief Disables the timer (stops count)
- * @param pTMR : Pointer to timer IP register address
- * @return Nothing
- * Disables the timer to stop counting.
- */
-STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
-{
- IP_TIMER_Disable(pTMR);
-}
-
-/**
- * @brief Returns the current timer count
- * @param pTMR : Pointer to timer IP register address
- * @return Current timer terminal count value
- * Returns the current timer terminal count.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
-{
- return IP_TIMER_ReadCount(pTMR);
-}
-
-/**
- * @brief Returns the current prescale count
- * @param pTMR : Pointer to timer IP register address
- * @return Current timer prescale count value
- * Returns the current prescale count.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
-{
- return IP_TIMER_ReadPrescale(pTMR);
-}
-
-/**
- * @brief Sets the prescaler value
- * @param pTMR : Pointer to timer IP register address
- * @param prescale : Prescale value to set the prescale register to
- * @return Nothing
- * Sets the prescale count value.
- */
-STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
-{
- IP_TIMER_PrescaleSet(pTMR, prescale);
-}
-
-/**
- * @brief Sets a timer match value
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer to set match count for
- * @param matchval : Match value for the selected match count
- * @return Nothing
- * Sets ones of the timer match values.
- */
-STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
-{
- IP_TIMER_SetMatch(pTMR, matchnum, matchval);
-}
-
-/**
- * @brief Reads a capture register
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture register to read
- * @return The selected capture register value
- * Returns the selected capture register value.
- */
-STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- return IP_TIMER_ReadCapture(pTMR, capnum);
-}
-
-/**
- * @brief Resets the timer terminal and prescale counts to 0
- * @param pTMR : Pointer to timer IP register address
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
-{
- IP_TIMER_Reset(pTMR);
-}
-
-/**
- * @brief Enables a match interrupt that fires when the terminal count
- * matches the match counter value.
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_MatchEnableInt(pTMR, matchnum);
-}
-
-/**
- * @brief Disables a match interrupt for a match counter.
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_MatchDisableInt(pTMR, matchnum);
-}
-
-/**
- * @brief For the specific match counter, enables reset of the terminal count register when a match occurs
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_ResetOnMatchEnable(pTMR, matchnum);
-}
-
-/**
- * @brief For the specific match counter, disables reset of the terminal count register when a match occurs
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_ResetOnMatchDisable(pTMR, matchnum);
-}
-
-/**
- * @brief Enable a match timer to stop the terminal count when a
- * match count equals the terminal count.
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_StopOnMatchEnable(pTMR, matchnum);
-}
-
-/**
- * @brief Disable stop on match for a match timer. Disables a match timer
- * to stop the terminal count when a match count equals the terminal count.
- * @param pTMR : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
-{
- IP_TIMER_StopOnMatchDisable(pTMR, matchnum);
-}
-
-/**
- * @brief Enables capture on on rising edge of selected CAP signal for the
- * selected capture register, enables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a rising edge.
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureRisingEdgeEnable(pTMR, capnum);
-}
-
-/**
- * @brief Disables capture on on rising edge of selected CAP signal. For the
- * selected capture register, disables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a rising edge.
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureRisingEdgeDisable(pTMR, capnum);
-}
-
-/**
- * @brief Enables capture on on falling edge of selected CAP signal. For the
- * selected capture register, enables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a falling edge.
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureFallingEdgeEnable(pTMR, capnum);
-}
-
-/**
- * @brief Disables capture on on falling edge of selected CAP signal. For the
- * selected capture register, disables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a falling edge.
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureFallingEdgeDisable(pTMR, capnum);
-}
-
-/**
- * @brief Enables interrupt on capture of selected CAP signal. For the
- * selected capture register, an interrupt will be generated when the enabled
- * rising or falling edge on CAPn.capnum is detected.
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureEnableInt(pTMR, capnum);
-}
-
-/**
- * @brief Disables interrupt on capture of selected CAP signal
- * @param pTMR : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
-{
- IP_TIMER_CaptureDisableInt(pTMR, capnum);
-}
-
-/**
- * @brief Sets external match control (MATn.matchnum) pin control
- * @param pTMR : Pointer to timer IP register address
- * @param initial_state : Initial state of the pin, high(1) or low(0)
- * @param matchState : Selects the match state for the pin
- * @param matchnum : MATn.matchnum signal to use
- * @return Nothing
- * For the pin selected with matchnum, sets the function of the pin that occurs on
- * a terminal count match for the match count.
- */
-STATIC INLINE void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
- IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
-{
- IP_TIMER_ExtMatchControlSet(pTMR, initial_state, matchState, matchnum);
-}
-
-/**
- * @brief Sets timer count source and edge with the selected passed from CapSrc
- * @param pTMR : Pointer to timer IP register address
- * @param capSrc : timer clock source and edge
- * @param capnum : CAPn.capnum pin to use (if used)
- * @return Nothing
- * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
- */
-STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
- IP_TIMER_CAP_SRC_STATE_T capSrc,
- int8_t capnum)
-{
- IP_TIMER_SetCountClockSrc(pTMR, capSrc, capnum);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIMER_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h
deleted file mode 100644
index 8397f3e94..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * @brief LPC18xx/43xx UART chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __UART_18XX_43XX_H_
-#define __UART_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup 18XX_43XX CHIP: LPC18xx/43xx UART Driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/**
- * @brief Configure data width, parity mode and stop bits
- * @param pUART : Pointer to selected pUART peripheral
- * @param Databits : UART Data width, should be:
- * UART_DATABIT_5: UART 5 bit data mode
- * UART_DATABIT_6: UART 6 bit data mode
- * UART_DATABIT_7: UART 7 bit data mode
- * UART_DATABIT_8: UART 8 bit data mode
- * @param Parity : UART Parity mode, should be:
- * UART_PARITY_NONE: No parity
- * UART_PARITY_ODD: Odd parity
- * UART_PARITY_EVEN: Even parity
- * UART_PARITY_SP_1: Forced "1" stick parity
- * UART_PARITY_SP_0: Forced "0" stick parity
- * @param Stopbits : Number of stop bits, should be:
- * UART_STOPBIT_1: One Stop Bit Select
- * UART_STOPBIT_2: Two Stop Bits Select
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART,
- IP_UART_DATABIT_T Databits,
- IP_UART_PARITY_T Parity,
- IP_UART_STOPBIT_T Stopbits)
-{
- IP_UART_ConfigData(pUART, Databits, Parity, Stopbits);
-}
-
-/**
- * @brief Send a block of data via UART peripheral
- * @param pUART : Pointer to selected pUART peripheral
- * @param txbuf : Pointer to Transmit buffer
- * @param buflen : Length of Transmit buffer
- * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING
- * @return Number of bytes sent
- */
-STATIC INLINE uint32_t Chip_UART_Send(LPC_USART_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag)
-{
- return IP_UART_Send(pUART, txbuf, buflen, flag);
-}
-
-/**
- * @brief Receive a block of data via UART peripheral
- * @param pUART : Pointer to selected pUART peripheral
- * @param rxbuf : Pointer to Received buffer
- * @param buflen : Length of Received buffer
- * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING
- * @return Number of bytes received
- */
-STATIC INLINE uint32_t Chip_UART_Receive(LPC_USART_T *pUART,
- uint8_t *rxbuf,
- uint32_t buflen,
- TRANSFER_BLOCK_T flag)
-{
- return IP_UART_Receive(pUART, rxbuf, buflen, flag);
-}
-
-/* UART FIFO functions ----------------------------------------------------------*/
-/**
- * @brief Configure FIFO function on selected UART peripheral
- * @param pUART : Pointer to selected pUART peripheral
- * @param FIFOCfg : Pointer to a UART_FIFO_CFG_T Structure that contains specified information about FIFO configuration
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_FIFOConfig(LPC_USART_T *pUART, UART_FIFO_CFG_T *FIFOCfg)
-{
- IP_UART_FIFOConfig(pUART, FIFOCfg);
-}
-
-/**
- * @brief Fills each UART_FIFOInitStruct member with its default value:
- * - FIFO_DMAMode = DISABLE
- * - FIFO_Level = UART_FIFO_TRGLEV0
- * - FIFO_ResetRxBuf = ENABLE
- * - FIFO_ResetTxBuf = ENABLE
- * - FIFO_State = ENABLE
- * @param pUART : Pointer to selected UART peripheral
- * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_T structure which will be initialized.
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_FIFOConfigStructInit(LPC_USART_T *pUART, UART_FIFO_CFG_T *UART_FIFOInitStruct)
-{
- IP_UART_FIFOConfigStructInit(UART_FIFOInitStruct);
-}
-
-/* UART operate functions -------------------------------------------------------*/
-/**
- * @brief Enable or disable specified UART interrupt.
- * @param pUART : Pointer to selected pUART peripheral
- * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following:
- * - UART_INTCFG_RBR : RBR Interrupt enable
- * - UART_INTCFG_THRE : THR Interrupt enable
- * - UART_INTCFG_RLS : RX line status interrupt enable
- * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
- * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
- * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
- * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
- * @param NewState : New state of specified UART interrupt type, should be ENALBE or DISALBE
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_IntConfig(LPC_USART_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState)
-{
- IP_UART_IntConfig(pUART, UARTIntCfg, NewState);
-}
-
-/**
- * @brief Get Source Interrupt
- * @param pUART : Pointer to selected pUART peripheral
- * @return Return the value of IIR register
- */
-STATIC INLINE uint32_t Chip_UART_IntGetStatus(LPC_USART_T *pUART)
-{
- return IP_UART_IntGetStatus(pUART);
-}
-
-/**
- * @brief Get current value of Line Status register in UART peripheral.
- * @param pUART : Pointer to selected pUART peripheral
- * @return Current value of Line Status register in UART peripheral
- */
-STATIC INLINE uint8_t Chip_UART_GetLineStatus(LPC_USART_T *pUART)
-{
- return IP_UART_GetLineStatus(pUART);
-}
-
-/**
- * @brief Check whether if UART is busy or not
- * @param pUART : Pointer to selected pUART peripheral
- * @return RESET if UART is not busy, otherwise return SET.
- */
-STATIC INLINE FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART)
-{
- return IP_UART_CheckBusy(pUART);
-}
-
-/**
- * @brief Force BREAK character on UART line, output pin pUART TXD is forced to logic 0
- * @param pUART : Pointer to selected pUART peripheral
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_ForceBreak(LPC_USART_T *pUART)
-{
- IP_UART_ForceBreak(pUART);
-}
-
-/**
- * @brief Transmit a single data through UART peripheral
- * @param pUART : Pointer to selected pUART peripheral
- * @param data : Data to transmit (must be 8-bit long)
- * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
- */
-STATIC INLINE Status Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
-{
- return IP_UART_SendByte(pUART, data);
-}
-
-/**
- * @brief Receive a single data from UART peripheral
- * @param pUART : Pointer to selected pUART peripheral
- * @param *Data : Pointer to Data to receive (must be 8-bit long)
- * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
- */
-STATIC INLINE Status Chip_UART_ReceiveByte(LPC_USART_T *pUART, uint8_t *Data)
-{
- return IP_UART_ReceiveByte(pUART, Data);
-}
-
-/**
- * @brief Initializes the pUART peripheral.
- * @param pUART : Pointer to selected pUART peripheral
- * @return Nothing
- */
-void Chip_UART_Init(LPC_USART_T *pUART);
-
-/**
- * @brief De-initializes the pUART peripheral.
- * @param pUART : Pointer to selected pUART peripheral
- * @return Nothing
- */
-void Chip_UART_DeInit(LPC_USART_T *pUART);
-
-/**
- * @brief Determines best dividers to get a target baud rate
- * @param pUART : Pointer to selected pUART peripheral
- * @param baudrate : Desired UART baud rate.
- * @return Error status, could be SUCCESS or ERROR
- */
-Status Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
-
-/**
- * @brief Enable/Disable transmission on UART TxD pin
- * @param pUART : Pointer to selected pUART peripheral
- * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE
- * @return Nothing
- */
-void Chip_UART_TxCmd(LPC_USART_T *pUART, FunctionalState NewState);
-
-/**
- * @brief Get Interrupt Stream Status
- * @param pUART : Pointer to selected pUART peripheral
- * @return Return the interrupt status, should be:
- * - UART_INTSTS_ERROR
- * - UART_INTSTS_RTR
- * - UART_INTSTS_RTS
- */
-IP_UART_INT_STATUS_T Chip_UART_GetIntStatus(LPC_USART_T *pUART);
-
-/**
- * @brief Uart interrupt service routine (chip layer)
- * @param pUART : Pointer to selected pUART peripheral
- * @return Nothing
- */
-void Chip_UART_Interrupt_Handler (LPC_USART_T *pUART);
-
-/**
- * @brief UART transmit function for interrupt mode (using ring buffers)
- * @param pUART : Selected UART peripheral used to send data, should be UART0
- * @param txbuf : Pointer to Transmit buffer
- * @param buflen : Length of Transmit buffer
- * @return Number of bytes actually sent to the ring buffer
- */
-uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_T *pUART, uint8_t *txbuf, uint8_t buflen);
-
-/**
- * @brief UART read function for interrupt mode (using ring buffers)
- * @param pUART : Selected UART peripheral used to send data, should be UART0
- * @param rxbuf : Pointer to Received buffer
- * @param buflen : Length of Received buffer
- * @return Number of bytes actually read from the ring buffer
- */
-uint32_t Chip_UART_Interrupt_Receive(LPC_USART_T *pUART, uint8_t *rxbuf, uint8_t buflen);
-
-/**
- * @brief Reset Tx and Rx ring buffer (head and tail)
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-void Chip_UART_InitRingBuffer(LPC_USART_T *pUART);
-
-/**
- * @brief Start/Stop Auto Baudrate activity
- * @param pUART : Pointer to selected pUART peripheral
- * @param ABConfigStruct : A pointer to UART_AB_CFG_T structure that
- * contains specified information about UAR auto baud configuration
- * @param NewState : New State of Auto baudrate activity, should be ENABLE or DISABLE
- * @return Nothing
- * @note Auto-baudrate mode enable bit will be cleared once this mode completed.
- */
-STATIC INLINE void Chip_UART_ABCmd(LPC_USART_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState)
-{
- IP_UART_ABCmd(pUART, ABConfigStruct, NewState);
-}
-
-/**
- * @brief Clear Autobaud Interrupt
- * @param pUART : Pointer to selected pUART peripheral
- * @param ABIntType : type of auto-baud interrupt, should be:
- * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
- * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
- * @return Nothing
- */
-STATIC INLINE void Chip_UART_ABClearIntPending(LPC_USART_T *pUART, IP_UART_INT_STATUS_T ABIntType)
-{
- IP_UART_ABClearIntPending(pUART, ABIntType);
-}
-
-// FIXME - this function is probably not interrupt related and needs a DoxyGen header
-/* UART interrupt service routine */
-FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART);
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-#endif /* __UART_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h
deleted file mode 100644
index e15a3523b..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * @brief LPC18xx/43xx WWDT chip driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __WWDT_18XX_43XX_H_
-#define __WWDT_18XX_43XX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver
- * @ingroup CHIP_18XX_43XX_Drivers
- * @{
- */
-
-/** WDT oscillator frequency value */
-#define WDT_OSC (CGU_IRC_FREQ)
-
-/** Minimum tick count for timer value and window value */
-#define WWDT_TICKS_MIN 0xFF
-
-/** Maximum tick count for timer value and window value */
-#define WWDT_TICKS_MAX 0xFFFFFF
-
-/**
- * @brief Initialize the Watchdog timer
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return None
- */
-void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
-
-/**
- * @brief Shutdown the Watchdog timer
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT)
-{
- IP_WWDT_DeInit(pWWDT);
-}
-
-/**
- * @brief Set WDT timeout constant value used for feed
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
- * @return none
- */
-STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
-{
- IP_WWDT_SetTimeOut(pWWDT, timeout);
-}
-
-/**
- * @brief Feed watchdog timer
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return None
- * @note If this function isn't called, a watchdog timer warning will occur.
- * After the warning, a timeout will occur if a feed has happened.
- */
-STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
-{
- IP_WWDT_Feed(pWWDT);
-}
-
-/**
- * @brief Set WWDT warning interrupt
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param timeout : WDT warning in ticks, between 0 and 1023
- * @return None
- * @note This is the number of ticks after the watchdog interrupt that the
- * warning interrupt will be generated.
- */
-STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
-{
- IP_WWDT_SetWarning(pWWDT, timeout);
-}
-
-/**
- * @brief Set WWDT window time
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param timeout : WDT window in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
- * @return none
- * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
- * function and this function, with this function defining the last tick before the
- * watchdog window interrupt occurs.
- */
-STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
-{
- IP_WWDT_SetWindow(pWWDT, timeout);
-}
-
-/**
- * @brief Enable watchdog timer options
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param options : An or'ed set of options of values
- * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return None
- * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
- * are set (or unset) with no other options.
- */
-STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
-{
- IP_WWDT_SetOption(pWWDT, options);
-}
-
-/**
- * @brief Disable/clear watchdog timer options
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param options : An or'ed set of options of values
- * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return None
- * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDTOF).
- */
-STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
-{
- IP_WWDT_UnsetOption(pWWDT, options);
-}
-
-/**
- * @brief Enable WWDT activity
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return None
- */
-STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
-{
- IP_WWDT_Start(pWWDT);
-}
-
-/**
- * @brief Read WWDT status flag
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return Watchdog status, an Or'ed value of WWDT_WDMOD_*
- */
-STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
-{
- return IP_WWDT_GetStatus(pWWDT);
-}
-
-/**
- * @brief Clear WWDT interrupt status flags
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @param status : Or'ed value of status flag(s) that you want to clear, should be:
- * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
- * - WWDT_WDMOD_WDINT: Clear watchdog warning flag
- * @return None
- */
-STATIC INLINE void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
-{
- IP_WWDT_ClearStatusFlag(pWWDT, status);
-}
-
-/**
- * @brief Get the current value of WDT
- * @param pWWDT : The base of WatchDog Timer peripheral on the chip
- * @return current value of WDT
- */
-STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
-{
- return IP_WWDT_GetCurrentCount(pWWDT);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WWDT_18XX_43XX_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_common/lpc_sdmmc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_common/lpc_sdmmc.h
deleted file mode 100644
index 8fd5b9fdb..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_common/lpc_sdmmc.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * @brief Common definitions used in SD/MMC cards
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LPC_SDMMC_H
-#define __LPC_SDMMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup CHIP_SDMMC_Definitions CHIP: Common SD/MMC definitions
- * @ingroup CHIP_Common
- * @{
- */
-
-/**
- * @brief OCR Register definitions
- */
-/** Support voltage range 2.0-2.1 (this bit is reserved in SDC)*/
-#define SDC_OCR_20_21 (((uint32_t) 1) << 8)
-/** Support voltage range 2.1-2.2 (this bit is reserved in SDC)*/
-#define SDC_OCR_21_22 (((uint32_t) 1) << 9)
-/** Support voltage range 2.2-2.3 (this bit is reserved in SDC)*/
-#define SDC_OCR_22_23 (((uint32_t) 1) << 10)
-/** Support voltage range 2.3-2.4 (this bit is reserved in SDC)*/
-#define SDC_OCR_23_24 (((uint32_t) 1) << 11)
-/** Support voltage range 2.4-2.5 (this bit is reserved in SDC)*/
-#define SDC_OCR_24_25 (((uint32_t) 1) << 12)
-/** Support voltage range 2.5-2.6 (this bit is reserved in SDC)*/
-#define SDC_OCR_25_26 (((uint32_t) 1) << 13)
-/** Support voltage range 2.6-2.7 (this bit is reserved in SDC)*/
-#define SDC_OCR_26_27 (((uint32_t) 1) << 14)
-/** Support voltage range 2.7-2.8 */
-#define SDC_OCR_27_28 (((uint32_t) 1) << 15)
-/** Support voltage range 2.8-2.9*/
-#define SDC_OCR_28_29 (((uint32_t) 1) << 16)
-/** Support voltage range 2.9-3.0 */
-#define SDC_OCR_29_30 (((uint32_t) 1) << 17)
-/** Support voltage range 3.0-3.1 */
-#define SDC_OCR_30_31 (((uint32_t) 1) << 18)
-/** Support voltage range 3.1-3.2 */
-#define SDC_OCR_31_32 (((uint32_t) 1) << 19)
-/** Support voltage range 3.2-3.3 */
-#define SDC_OCR_32_33 (((uint32_t) 1) << 20)
-/** Support voltage range 3.3-3.4 */
-#define SDC_OCR_33_34 (((uint32_t) 1) << 21)
-/** Support voltage range 3.4-3.5 */
-#define SDC_OCR_34_35 (((uint32_t) 1) << 22)
-/** Support voltage range 3.5-3.6 */
-#define SDC_OCR_35_36 (((uint32_t) 1) << 23)
-/** Support voltage range 2.7-3.6 */
-#define SDC_OCR_27_36 ((uint32_t) 0x00FF8000)
-/** Card Capacity Status (CCS). (this bit is reserved in MMC) */
-#define SDC_OCR_HC_CCS (((uint32_t) 1) << 30)
-/** Card power up status bit */
-#define SDC_OCR_IDLE (((uint32_t) 1) << 31)
-#define SDC_OCR_BUSY (((uint32_t) 0) << 31)
-
-/* SD/MMC commands - this matrix shows the command, response types, and
- supported card type for that command.
- Command Number Resp SD MMC
- ----------------------- ------ ----- --- ---
- Reset (go idle) CMD0 NA x x
- Send op condition CMD1 R3 x
- All send CID CMD2 R2 x x
- Send relative address CMD3 R1 x
- Send relative address CMD3 R6 x
- Program DSR CMD4 NA x
- Select/deselect card CMD7 R1b x
- Select/deselect card CMD7 R1 x
- Send CSD CMD9 R2 x x
- Send CID CMD10 R2 x x
- Read data until stop CMD11 R1 x x
- Stop transmission CMD12 R1/b x x
- Send status CMD13 R1 x x
- Go inactive state CMD15 NA x x
- Set block length CMD16 R1 x x
- Read single block CMD17 R1 x x
- Read multiple blocks CMD18 R1 x x
- Write data until stop CMD20 R1 x
- Setblock count CMD23 R1 x
- Write single block CMD24 R1 x x
- Write multiple blocks CMD25 R1 x x
- Program CID CMD26 R1 x
- Program CSD CMD27 R1 x x
- Set write protection CMD28 R1b x x
- Clear write protection CMD29 R1b x x
- Send write protection CMD30 R1 x x
- Erase block start CMD32 R1 x
- Erase block end CMD33 R1 x
- Erase block start CMD35 R1 x
- Erase block end CMD36 R1 x
- Erase blocks CMD38 R1b x
- Fast IO CMD39 R4 x
- Go IRQ state CMD40 R5 x
- Lock/unlock CMD42 R1b x
- Application command CMD55 R1 x
- General command CMD56 R1b x
-
- *** SD card application commands - these must be preceded with ***
- *** MMC CMD55 application specific command first ***
- Set bus width ACMD6 R1 x
- Send SD status ACMD13 R1 x
- Send number WR blocks ACMD22 R1 x
- Set WR block erase cnt ACMD23 R1 x
- Send op condition ACMD41 R3 x
- Set clear card detect ACMD42 R1 x
- Send CSR ACMD51 R1 x */
-
-/**
- * @brief SD/MMC application specific commands for SD cards only - these
- * must be preceded by the SDMMC CMD55 to work correctly
- */
-typedef enum {
- SD_SET_BUS_WIDTH, /*!< Set the SD bus width */
- SD_SEND_STATUS, /*!< Send the SD card status */
- SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */
- SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */
- SD_SENDOP_COND, /*!< Send the OCR register (init) */
- SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */
- SD_SEND_SCR, /*!< Send the SD configuration register */
- SD_INVALID_APP_CMD /*!< Invalid SD application command */
-} SD_APP_CMD_T;
-
-/**
- * @brief Possible SDMMC response types
- */
-typedef enum {
- SDMMC_RESPONSE_R1, /*!< Typical status */
- SDMMC_RESPONSE_R1B, /*!< Typical status with busy */
- SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */
- SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */
- SDMMC_RESPONSE_R4, /*!< Fast IO response word */
- SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */
- SDMMC_RESPONSE_R6, /*!< Published RCA response */
- SDMMC_RESPONSE_NONE /*!< No response expected */
-} SDMMC_RESPONSE_T;
-
-/**
- * @brief Possible SDMMC card state types
- */
-typedef enum {
- SDMMC_IDLE_ST = 0, /*!< Idle state */
- SDMMC_READY_ST, /*!< Ready state */
- SDMMC_IDENT_ST, /*!< Identification State */
- SDMMC_STBY_ST, /*!< standby state */
- SDMMC_TRAN_ST, /*!< transfer state */
- SDMMC_DATA_ST, /*!< Sending-data State */
- SDMMC_RCV_ST, /*!< Receive-data State */
- SDMMC_PRG_ST, /*!< Programming State */
- SDMMC_DIS_ST /*!< Disconnect State */
-} SDMMC_STATE_T;
-
-/* Function prototype for event setup function */
-typedef void (*SDMMC_EVSETUP_FUNC_T)(void *);
-
-/* Function prototype for wait for event function */
-typedef uint32_t (*SDMMC_EVWAIT_FUNC_T)(void);
-
-/* Function prototype for milliSecond delay function */
-typedef void (*SDMMC_MSDELAY_FUNC_T)(uint32_t);
-
-/**
- * @brief SD/MMC Card specific setup data structure
- */
-typedef struct {
- uint32_t response[4]; /*!< Most recent response */
- uint32_t cid[4]; /*!< CID of acquired card */
- uint32_t csd[4]; /*!< CSD of acquired card */
- uint32_t ext_csd[512 / 4]; /*!< Ext CSD */
- uint32_t card_type; /*!< Card Type */
- uint16_t rca; /*!< Relative address assigned to card */
- uint32_t speed; /*!< Speed */
- uint32_t block_len; /*!< Card sector size */
- uint32_t device_size; /*!< Device Size */
- uint32_t blocknr; /*!< Block Number */
- uint32_t clk_rate; /*! Clock rate */
- SDMMC_EVSETUP_FUNC_T evsetup_cb; /*!< Function to setup event information */
- SDMMC_EVWAIT_FUNC_T waitfunc_cb; /*!< Function to wait for event */
- SDMMC_MSDELAY_FUNC_T msdelay_func; /*!< Function to sleep in ms */
-} SDMMC_CARD_T;
-
-/**
- * @brief SD/MMC commands, arguments and responses
- * Standard SD/MMC commands (3.1) type argument response
- */
-/* class 1 */
-#define MMC_GO_IDLE_STATE 0 /* bc */
-#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
-#define MMC_ALL_SEND_CID 2 /* bcr R2 */
-#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
-#define MMC_SET_DSR 4 /* bc [31:16] RCA */
-#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
-#define MMC_SEND_EXT_CSD 8 /* bc R1 */
-#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
-#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
-#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
-#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
-#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
-
-/* class 2 */
-#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
-#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
-#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
-
-/* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
-
-/* class 4 */
-#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
-#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
-#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
-#define MMC_PROGRAM_CID 26 /* adtc R1 */
-#define MMC_PROGRAM_CSD 27 /* adtc R1 */
-
-/* class 6 */
-#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
-#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
-#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
-
-/* class 5 */
-#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
-#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
-#define MMC_ERASE 37 /* ac R1b */
-#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
-#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
-#define SD_ERASE 38 /* ac R1b */
-
-/* class 9 */
-#define MMC_FAST_IO 39 /* ac R4 */
-#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
-
-/* class 7 */
-#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
-
-/* class 8 */
-#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
-#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
-
-/* SD commands type argument response */
-/* class 8 */
-/* This is basically the same command as for MMC with some quirks. */
-#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */
-#define SD_CMD8 8 /* bcr [31:0] OCR R3 */
-
-/* Application commands */
-#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
-#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */
-#define SD_APP_SEND_SCR 51 /* adtc R1 */
-
-/**
- * @brief MMC status in R1
- * Type
- * e : error bit
- * s : status bit
- * r : detected and set for the actual command response
- * x : detected and set during command execution. the host must poll
- * the card by sending status command in order to read these bits.
- * Clear condition
- * a : according to the card state
- * b : always related to the previous command. Reception of
- * a valid command will clear it (with a delay of one command)
- * c : clear by read
- */
-
-#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */
-#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
-#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
-#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
-#define R1_ERASE_PARAM (1 << 27) /* ex, c */
-#define R1_WP_VIOLATION (1 << 26) /* erx, c */
-#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
-#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
-#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
-#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
-#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
-#define R1_CC_ERROR (1 << 20) /* erx, c */
-#define R1_ERROR (1 << 19) /* erx, c */
-#define R1_UNDERRUN (1 << 18) /* ex, c */
-#define R1_OVERRUN (1 << 17) /* ex, c */
-#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
-#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
-#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
-#define R1_ERASE_RESET (1 << 13) /* sr, c */
-#define R1_STATUS(x) (x & 0xFFFFE000)
-#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
-#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
-#define R1_APP_CMD (1 << 5) /* sr, c */
-
-/**
- * @brief SD/MMC card OCR register bits
- */
-#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */
-#define OCR_HC_CCS (1 << 30) /* High capacity card */
-#define OCR_VOLTAGE_RANGE_MSK (0x00FF8000)
-
-#define SD_SEND_IF_ARG 0x000001AA
-#define SD_SEND_IF_ECHO_MSK 0x000000FF
-#define SD_SEND_IF_RESP 0x000000AA
-
-/**
- * @brief R3 response definitions
- */
-#define CMDRESP_R3_OCR_VAL(n) (((uint32_t) n) & 0xFFFFFF)
-#define CMDRESP_R3_S18A (((uint32_t) 1 ) << 24)
-#define CMDRESP_R3_HC_CCS (((uint32_t) 1 ) << 30)
-#define CMDRESP_R3_INIT_COMPLETE (((uint32_t) 1 ) << 31)
-
-/**
- * @brief R6 response definitions
- */
-#define CMDRESP_R6_RCA_VAL(n) (((uint32_t) (n >> 16)) & 0xFFFF)
-#define CMDRESP_R6_CARD_STATUS(n) (((uint32_t) (n & 0x1FFF)) | \
- ((n & (1 << 13)) ? (1 << 19) : 0) | \
- ((n & (1 << 14)) ? (1 << 22) : 0) | \
- ((n & (1 << 15)) ? (1 << 23) : 0))
-
-/**
- * @brief R7 response definitions
- */
-/** Echo-back of check-pattern */
-#define CMDRESP_R7_CHECK_PATTERN(n) (((uint32_t) n ) & 0xFF)
-/** Voltage accepted */
-#define CMDRESP_R7_VOLTAGE_ACCEPTED (((uint32_t) 1 ) << 8)
-
-/**
- * @brief CMD3 command definitions
- */
-/** Card Address */
-#define CMD3_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
-
-/**
- * @brief CMD7 command definitions
- */
-/** Card Address */
-#define CMD7_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
-
-/**
- * @brief CMD8 command definitions
- */
-/** Check pattern */
-#define CMD8_CHECKPATTERN(n) (((uint32_t) (n & 0xFF) ) << 0)
-/** Recommended pattern */
-#define CMD8_DEF_PATTERN (0xAA)
-/** Voltage supplied.*/
-#define CMD8_VOLTAGESUPPLIED_27_36 (((uint32_t) 1 ) << 8)
-
-/**
- * @brief CMD9 command definitions
- */
-#define CMD9_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
-
-/**
- * @brief CMD13 command definitions
- */
-#define CMD13_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
-
-/**
- * @brief APP_CMD command definitions
- */
-#define CMD55_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
-
-/**
- * @brief ACMD41 command definitions
- */
-#define ACMD41_OCR(n) (((uint32_t) n) & 0xFFFFFF)
-#define ACMD41_S18R (((uint32_t) 1 ) << 24)
-#define ACMD41_XPC (((uint32_t) 1 ) << 28)
-#define ACMD41_HCS (((uint32_t) 1 ) << 30)
-
-/**
- * @brief ACMD6 command definitions
- */
-#define ACMD6_BUS_WIDTH(n) ((uint32_t) n & 0x03)
-#define ACMD6_BUS_WIDTH_1 (0)
-#define ACMD6_BUS_WIDTH_4 (2)
-
-/** @brief Card type defines
- */
-#define CARD_TYPE_SD (1 << 0)
-#define CARD_TYPE_4BIT (1 << 1)
-#define CARD_TYPE_8BIT (1 << 2)
-#define CARD_TYPE_HC (OCR_HC_CCS)/*!< high capacity card > 2GB */
-
-/**
- * @brief SD/MMC sector size in bytes
- */
-#define MMC_SECTOR_SIZE 512
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* __LPC_SDMMC_H */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/acmp_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/acmp_001.h
deleted file mode 100644
index 3893fd4b6..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/acmp_001.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief Analog comparator driver
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licenser disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ACMP_001_H_
-#define __ACMP_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ACMP_001 IP: Analog comparator driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief Analog Comparator register block structure
- */
-typedef struct { /*!< ACMP Structure */
- __IO uint32_t CTRL; /*!< Comparator control register */
- __IO uint32_t LAD; /*!< Voltage ladder register */
-} ACMP_001_T;
-
-#define ACMP_COMPSA_BIT (1 << 6) /* Comparator output control bit */
-#define ACMP_COMPSTAT_BIT (1 << 21) /* Comparator status, reflects the state of the comparator output */
-#define ACMP_COMPEDGE_BIT (1 << 23) /* Comparator edge-detect status */
-#define ACMP_LADENAB_BIT (1 << 0) /* Voltage ladder enable bit */
-
-/** Edge selection for comparator */
-typedef enum IP_ACMP_001_EDGESEL {
- ACMP_EDGESEL_FALLING = (0 << 3), /* Set the COMPEDGE bit on falling edge */
- ACMP_EDGESEL_RISING = (1 << 3), /* Set the COMPEDGE bit on rising edge */
- ACMP_EDGESEL_BOTH = (2 << 3) /* Set the COMPEDGE bit on falling and rising edges */
-} IP_ACMP_001_EDGESEL_T;
-
-/** Hysteresis selection for comparator */
-typedef enum IP_ACMP_HYS_001 {
- ACMP_HYS_NONE = (0 << 25), /* No hysteresis (the output will switch as the voltages cross) */
- ACMP_HYS_5MV = (1 << 25), /* 5mV hysteresis */
- ACMP_HYS_10MV = (2 << 25), /* 10mV hysteresis */
- ACMP_HYS_20MV = (3 << 25) /* 20mV hysteresis */
-} IP_ACMP_HYS_001_T;
-
-/**
- * @brief Initializes the ACMP
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_Init(ACMP_001_T *pACMP) {}
-
-/**
- * @brief De-initializes the ACMP
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_Deinit(ACMP_001_T *pACMP) {}
-
-/**
- * @brief Returns the current comparator status
- * @param pACMP : Pointer to Analog Comparator block
- * @return Status is an Or'ed value of ACMP_COMPSTAT_BIT or ACMP_COMPEDGE_BIT
- */
-STATIC INLINE uint32_t IP_ACMP_GetCompStatus(ACMP_001_T *pACMP)
-{
- return pACMP->CTRL & (ACMP_COMPSTAT_BIT | ACMP_COMPEDGE_BIT);
-}
-
-/**
- * @brief Clears the ACMP interrupt (EDGECLR bit)
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-void IP_ACMP_EdgeClear(ACMP_001_T *pACMP);
-
-/**
- * @brief Sets up ACMP edge selection
- * @param pACMP : Pointer to Analog Comparator block
- * @param edgeSel : Edge selection value
- * @return Nothing
- */
-void IP_ACMP_SetEdgeSelection(ACMP_001_T *pACMP, IP_ACMP_001_EDGESEL_T edgeSel);
-
-/**
- * @brief Synchronizes Comparator output to bus clock
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_EnableSyncCompOut(ACMP_001_T *pACMP)
-{
- pACMP->CTRL |= ACMP_COMPSA_BIT;
-}
-
-/**
- * @brief Sets comparator output to be used directly (no sync)
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_DisableSyncCompOut(ACMP_001_T *pACMP)
-{
- pACMP->CTRL &= ~ACMP_COMPSA_BIT;
-}
-
-/**
- * @brief Selects positive voltage input
- * @param pACMP : Pointer to Analog Comparator block
- * @param Posinput : one of the positive input voltage sources
- * @return Nothing
- * @note The caller must pre-shift the Posinput value to the
- * correct bitfield location in the CTRL register.
- */
-void IP_ACMP_SetPosVoltRef(ACMP_001_T *pACMP, uint32_t Posinput);
-
-/**
- * @brief Selects negative voltage input
- * @param pACMP : Pointer to Analog Comparator block
- * @param Neginput : one of the negative input voltage sources
- * @return Nothing
- * @note The caller must pre-shift the Neginput value to the
- * correct bitfield location in the CTRL register.
- */
-void IP_ACMP_SetNegVoltRef(ACMP_001_T *pACMP, uint32_t Neginput);
-
-/**
- * @brief Selects hysteresis level
- * @param pACMP : Pointer to Analog Comparator block
- * @param hys : Selected Hysteresis level
- * @return Nothing
- */
-void IP_ACMP_SetHysteresis(ACMP_001_T *pACMP, IP_ACMP_HYS_001_T hys);
-
-/**
- * @brief Helper function for setting up ACMP control
- * @param pACMP : Pointer to Analog Comparator block
- * @param edgeSel : Edge selection value
- * @param Posinput : one of the positive input voltage sources
- * @param Neginput : one of the negative input voltage sources
- * @param hys : Selected Hysteresis level
- * @return Nothing
- * @note The caller must pre-shift the Posinput and Neginput values to the
- * correct bitfield location in the CTRL register.
- */
-void IP_ACMP_SetupAMCPRefs(ACMP_001_T *pACMP, IP_ACMP_001_EDGESEL_T edgeSel,
- uint32_t Posinput, uint32_t Neginput, IP_ACMP_HYS_001_T hys);
-
-/**
- * @brief Sets up voltage ladder
- * @param pACMP : Pointer to Analog Comparator block
- * @param ladsel : Voltage ladder value
- * @param ladrefVDDCMP : Selects the reference voltage Vref for the voltage ladder
- * : false for VDD, true for VDDCMP pin
- * @return Nothing
- * @note The caller must pre-shift the ladsel value to the
- * correct bitfield location in the LAD register.
- */
-void IP_ACMP_SetupVoltLadder(ACMP_001_T *pACMP, uint32_t ladsel, bool ladrefVDDCMP);
-
-/**
- * @brief Enables voltage ladder
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_EnableVoltLadder(ACMP_001_T *pACMP)
-{
- pACMP->LAD |= ACMP_LADENAB_BIT;
-}
-
-/**
- * @brief Disables voltage ladder
- * @param pACMP : Pointer to Analog Comparator block
- * @return Nothing
- */
-STATIC INLINE void IP_ACMP_DisableVoltLadder(ACMP_001_T *pACMP)
-{
- pACMP->LAD &= ~ACMP_LADENAB_BIT;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ACMP_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/adc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/adc_001.h
deleted file mode 100644
index 0cdbd522e..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/adc_001.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * @brief ADC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ADC_001_H_
-#define __ADC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC1347) || defined(CHIP_LPC175X_6X)
-#define ADC_ACC_12BITS
-#define ADC_TRIM_SUPPORT
-#else
-#define ADC_ACC_10BITS
-#endif
-
-/**
- * @brief 10 or 12-bit ADC register block structure
- */
-typedef struct { /*!< ADCn Structure */
- __IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
- __I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
- __I uint32_t RESERVED0;
- __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
- __I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
- __I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-#if defined(ADC_TRIM_SUPPORT)
- __IO uint32_t ADTRM;
-#endif
-} IP_ADC_001_T;
-
-/**
- * @brief ADC register support bitfields and mask
- */
-#if defined(ADC_ACC_12BITS)
- #define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Mask for getting the 12 bits ADC data read value */
-#else
- #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
- #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
-#endif
-
-#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
-#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
-#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
-#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
-#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
-#if defined(CHIP_LPC1347)
-#define ADC_CR_LPWRMODE ((1UL << 22)) /*!ADC_10BITS.
- * ADC mode flag is or-ed bit values of the following flags:
- * - ADC_CR_PDN: The A/D converter is operational. If this flag isn't set, the ADC is in
- * power-down mode. This flag isn't available in LPC13xx.
- * - ADC_CR_LPWRMODE: The analog circuitry is automatically powered-down when no conversions
- * are taking place. This flag is only available in LPC1347.
- * - ADC_CR_MODE10BIT: Enable the 10-bit conversion rate mode with high conversion rate.
- * This flag is only available in LPC1347.
- */
-void IP_ADC_Init(IP_ADC_001_T *pADC, uint8_t div, uint8_t bitsAcc, uint32_t flag);
-
-/**
- * @brief Shutdown ADC
- * @param pADC : The base of ADC peripheral on the chip
- * @return Nothing
- * @note Reset the ADC control and INTEN Register to reset values (disabled)
- */
-void IP_ADC_DeInit(IP_ADC_001_T *pADC);
-
-/**
- * @brief Set burst mode for ADC
- * @param pADC : The base of ADC peripheral on the chip
- * @param NewState : ENABLE for burst mode, or DISABLE for normal mode
- * @return Nothing
- */
-void IP_ADC_SetBurstMode(IP_ADC_001_T *pADC, FunctionalState NewState);
-
-/**
- * @brief Get the ADC value
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel to be read value, should be 0..7
- * @param data : Data buffer to store the A/D value
- * @return Status : SUCCESS or ERROR
- */
-Status IP_ADC_Get_Val(IP_ADC_001_T *pADC, uint8_t channel, uint16_t *data);
-
-/**
- * @brief Get ADC Channel status from ADC data register
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel number, should be 0..7
- * @param StatusType : Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT
- * @return Channel status, SET or RESET
- */
-FlagStatus IP_ADC_GetStatus(IP_ADC_001_T *pADC, uint8_t channel, uint32_t StatusType);
-
-/**
- * @brief Set the edge start condition
- * @param pADC : The base of ADC peripheral on the chip
- * @param edge_mode : 0 = rising, !0 = falling
- * @return Nothing
- */
-void IP_ADC_EdgeStartConfig(IP_ADC_001_T *pADC, uint8_t edge_mode);
-
-/**
- * @brief Enable/Disable ADC channel number
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel number
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_ADC_SetChannelNumber(IP_ADC_001_T *pADC, uint8_t channel, FunctionalState NewState);
-
-/**
- * @brief Set start mode for ADC
- * @param pADC : The base of ADC peripheral on the chip
- * @param start_mode : Start mode choose one of modes in 'ADC_START_*' enumeration type definitions
- * @return Nothing
- */
-void IP_ADC_SetStartMode(IP_ADC_001_T *pADC, uint8_t start_mode);
-
-/**
- * @brief Enable/Disable interrupt for ADC channel
- * @param pADC : The base of ADC peripheral on the chip
- * @param channel : Channel assert the interrupt
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_ADC_Int_Enable(IP_ADC_001_T *pADC, uint8_t channel, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ADC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/atimer_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/atimer_001.h
deleted file mode 100644
index ed813a3d0..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/atimer_001.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * @brief Alarm Timer Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ATIMER_001_H_
-#define __ATIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver
- * @ingroup IP_Drivers
- * Alarm timer
- * @{
- */
-
-/**
- * @brief Alarm Timer register block structure
- */
-typedef struct { /*!< ATIMER Structure */
- __IO uint32_t DOWNCOUNTER; /*!< Downcounter register */
- __IO uint32_t PRESET; /*!< Preset value register */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /*!< Interrupt clear enable register */
- __O uint32_t SET_EN; /*!< Interrupt set enable register */
- __I uint32_t STATUS; /*!< Status register */
- __I uint32_t ENABLE; /*!< Enable register */
- __O uint32_t CLR_STAT; /*!< Clear register */
- __O uint32_t SET_STAT; /*!< Set register */
-} IP_ATIMER_001_T;
-
-/**
- * @brief Close ATIMER device
- * @param pATimer : Pointer to timer device
- * @return None
- * @note Important: 32KHz clock must be enabled in CREG prior to this call. See
- * the User Manual for more information.
- */
-void IP_ATIMER_DeInit(IP_ATIMER_001_T *pATimer);
-
-/**
- * @brief Clear ATIMER Interrupt Status
- * @param pATimer : Pointer to timer device
- * @return None
- */
-STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_T *pATimer)
-{
- pATimer->CLR_STAT = 1;
-}
-
-/**
- * @brief Set ATIMER Interrupt Status
- * @param pATimer : Pointer to timer device
- * @return None
- */
-STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_T *pATimer)
-{
- pATimer->SET_STAT = 1;
-}
-/**
- * @brief Enable ATIMER Interrupt
- * @param pATimer : Pointer to timer device
- * @return None
- */
-STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_T *pATimer)
-{
- pATimer->SET_EN = 1;
-}
-
-/**
- * @brief Disable ATIMER Interrupt
- * @param pATimer : Pointer to timer device
- * @return None
- */
-STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_T *pATimer)
-{
- pATimer->CLR_EN = 1;
-}
-
-/**
- * @brief Update Preset value
- * @param pATimer : Pointer to timer device
- * @param PresetValue updated preset value
- * @return Nothing
- */
-STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_T *pATimer, uint32_t PresetValue)
-{
- pATimer->PRESET = PresetValue;
-}
-
-/**
- * @brief Read value of preset register
- * @param pATimer : Pointer to timer/counter device
- * @return Value of capture register
- */
-STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_T *pATimer)
-{
- return pATimer->PRESET;
-}
-
-/**
- * @brief Returns enable state of ATimer interrupt
- * @param pATimer : Pointer to timer/counter device
- * @return !0 if the ATimer interrupt is enabled, otherwise 0
- */
-STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_T *pATimer)
-{
- return pATimer->ENABLE;
-}
-
-/**
- * @brief Returns current pending state of ATimer interrupt
- * @param pATimer : Pointer to timer/counter device
- * @return !0 if the ATimer interrupt is asserted, otherwise 0
- */
-STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_T *pATimer)
-{
- return pATimer->STATUS;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ATIMER_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/can_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/can_001.h
deleted file mode 100644
index bc60ba5aa..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/can_001.h
+++ /dev/null
@@ -1,1141 +0,0 @@
-/*
- * @brief CAN registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CAN_001_H_
-#define __CAN_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_CAN_001 IP: CAN register block and driver
- * @ingroup IP_Drivers
- * Controller Area Network
- * @{
- */
-
-/** The number of entry in AF RAM region */
-#define CANAF_RAM_ENTRY_NUM 512
-
-/**
- * @brief CAN AF RAM section definitions
- */
-typedef enum IP_CAN_AF_RAM_SECTION {
- CANAF_RAM_FULLCAN_SEC, /*!> 16) & 0xFF)
-
-/** CAN Current value of the Tx Error Counter */
-#define CAN_GSR_TXERR(n) ((uint32_t) ((n >> 24) & 0xFF)
-
-/**
- * @brief CAN Interrupt and Capture register definitions
- */
-/** CAN Interrupt and Capture Registe Bitmask */
-#define CAN_ICR_BITMASK (0xFFFF07FF)
-
-/** CAN Receive Interrupt (A new message was received)*/
-#define CAN_ICR_RI ((uint32_t) (1))
-
-/** CAN Transmit Interrupt (Transmit buffer 1 is available) */
-#define CAN_ICR_TI1 ((uint32_t) (1 << 1))
-
-/** CAN Error Warning Interrupt */
-#define CAN_ICR_EI ((uint32_t) (1 << 2))
-
-/** CAN Data Overrun Interrupt */
-#define CAN_ICR_DOI ((uint32_t) (1 << 3))
-
-/** CAN Wake-Up Interrupt */
-#define CAN_ICR_WUI ((uint32_t) (1 << 4))
-
-/** CAN Error Passive Interrupt */
-#define CAN_ICR_EPI ((uint32_t) (1 << 5))
-
-/** CAN Arbitration Lost Interrupt */
-#define CAN_ICR_ALI ((uint32_t) (1 << 6))
-
-/** CAN Bus Error Interrupt */
-#define CAN_ICR_BEI ((uint32_t) (1 << 7))
-
-/** CAN ID Ready Interrupt */
-#define CAN_ICR_IDI ((uint32_t) (1 << 8))
-
-/** CAN Transmit Interrupt 2 (Transmit buffer 2 is available) */
-#define CAN_ICR_TI2 ((uint32_t) (1 << 9))
-
-/** CAN Transmit Interrupt 3 (Transmit buffer 3 is available)*/
-#define CAN_ICR_TI3 ((uint32_t) (1 << 10))
-
-/** CAN Error Code Capture (Error Location)*/
-#define CAN_ICR_ERRBIT_VAL(n) ((uint32_t) (((n) >> 16) & 0x1F))
-/** Start of Frame error value */
-#define CAN_ICR_ERR_SOF (3)
-/** ID28...ID21 Error value */
-#define CAN_ICR_ERR_ID28_ID21 (2)
-/** ID28...ID21 Error value */
-#define CAN_ICR_ERR_ID20_ID18 (6)
-/**SRTR Bit Error value */
-#define CAN_ICR_ERR_SRTR (4)
-/**IDE Bit Error value */
-#define CAN_ICR_ERR_IDE (5)
-/** ID17...ID13 Error value */
-#define CAN_ICR_ERR_ID17_ID13 (7)
-/** ID12...ID15 Error value */
-#define CAN_ICR_ERR_ID12_ID5 (0x0F)
-/** ID4...ID0 Error value */
-#define CAN_ICR_ERR_ID4_ID0 (0x0E)
-/**RTR Bit Error value */
-#define CAN_ICR_ERR_RTR (0x0C)
-/**Reserved Bit 1 Error value */
-#define CAN_ICR_ERR_ReservedBit_1 (0x0D)
-/**Reserved Bit 0 Error value */
-#define CAN_ICR_ERR_ReservedBit_0 (0x09)
-/** DLC Error value */
-#define CAN_ICR_ERR_DLC (0x0B)
-/** Data Field Error value */
-#define CAN_ICR_ERR_DATA_FIELD (0x0A)
-/** CRC Sequence Error value */
-#define CAN_ICR_ERR_CRC_SEQ (0x08)
-/** CRC Delimiter Error value */
-#define CAN_ICR_ERR_CRC_DELIMITER (0x18)
-/** ACK Error value */
-#define CAN_ICR_ERR_ACK (0x19)
-/** ACK Delimiter Error value */
-#define CAN_ICR_ERR_ACK_DELIMITER (0x1B)
-/** EOF Error value */
-#define CAN_ICR_ERR_EOF (0x1A)
-/** Intermission Error value */
-#define CAN_ICR_ERR_INTERMISSION (0x12)
-
-/** CAN Error Direction */
-#define CAN_ICR_ERRDIR_RECEIVE ((uint32_t) (1 << 21))
-
-/** CAN Error Type Capture */
-#define CAN_ICR_ERRC_VAL(n) ((uint32_t) (((n) >> 22) & 0x3))
-#define CAN_ICR_BIT_ERROR (0)
-#define CAN_ICR_FORM_ERROR (1)
-#define CAN_ICR_STUFF_ERROR (2)
-#define CAN_ICR_OTHER_ERROR (3)
-
-/** CAN Arbitration Lost Capture */
-#define CAN_ICR_ALCBIT_VAL(n) ((uint32_t) (((n) >> 24) & 0xFF))
-
-/**
- * @brief CAN Interrupt Enable register definitions
- */
-/** CAN Interrupt Enable Register Bitmask */
-#define CAN_IER_BITMASK (0x7FF)
-
-/** CAN Receive Interrupt Enable */
-#define CAN_IER_RIE ((uint32_t) (1))
-
-/** CAN Transmit Interrupt Enable for buffer 1 */
-#define CAN_IER_TIE1 ((uint32_t) (1 << 1))
-
-/** CAN Error Warning Interrupt Enable */
-#define CAN_IER_EIE ((uint32_t) (1 << 2))
-
-/** CAN Data Overrun Interrupt Enable */
-#define CAN_IER_DOIE ((uint32_t) (1 << 3))
-
-/** CAN Wake-Up Interrupt Enable */
-#define CAN_IER_WUIE ((uint32_t) (1 << 4))
-
-/** CAN Error Passive Interrupt Enable */
-#define CAN_IER_EPIE ((uint32_t) (1 << 5))
-
-/** CAN Arbitration Lost Interrupt Enable */
-#define CAN_IER_ALIE ((uint32_t) (1 << 6))
-
-/** CAN Bus Error Interrupt Enable */
-#define CAN_IER_BEIE ((uint32_t) (1 << 7))
-
-/** CAN ID Ready Interrupt Enable */
-#define CAN_IER_IDIE ((uint32_t) (1 << 8))
-
-/** CAN Transmit Enable Interrupt for Buffer 2 */
-#define CAN_IER_TIE2 ((uint32_t) (1 << 9))
-
-/** CAN Transmit Enable Interrupt for Buffer 3 */
-#define CAN_IER_TIE3 ((uint32_t) (1 << 10))
-
-/**
- * @brief CAN Bus Timing register definitions
- */
-/** CAN Bus Timing Register Bitmask */
-#define CAN_BTR_BITMASK (0xFFC3FF)
-
-/** CAN Baudrate Prescaler */
-#define CAN_BTR_BRP(n) ((uint32_t) ((n) & 0x3FF))
-
-/** CAN Synchronization Jump Width */
-#define CAN_BTR_SJW(n) ((uint32_t) (((n) & 0x3) << 14))
-
-/** CAN Time Segment 1 */
-#define CAN_BTR_TESG1(n) ((uint32_t) (((n) & 0xF) << 16))
-
-/** CAN Time Segment 2 */
-#define CAN_BTR_TESG2(n) ((uint32_t) (((n) & 0xF) << 20))
-
-/** CAN Sampling */
-#define CAN_BTR_SAM ((uint32_t) (1 << 23))
-
-/**
- * @brief CAN Error Warning Limit register definitions
- */
-/** CAN Error Warning Limit Register Bitmask */
-#define CAN_EWL_BITMASK (0xFF)
-
-/** CAN Error Warning Limit */
-#define CAN_EWL_VAL(n) ((uint32_t) ((n) & 0xFF))
-
-/**
- * @brief CAN Status Registe definitions
- */
-/** CAN Status Registe Bitmask */
-#define CAN_SR_BITMASK (0xFFFFFF)
-
-/** CAN Receive Buffer Status (Bit 0, 8, 16 are the same)*/
-#define CAN_SR_RBS(n) ((uint32_t) (1 << ((n) * 8)))
-
-/** CAN Data Overrun Status (Bit 1, 9, 17 are the same)*/
-#define CAN_SR_DOS(n) ((uint32_t) (1 << (1 + (n) * 8)))
-
-/** CAN Transmit Buffer Status (Tx Buffer n=0/1/2 is available)*/
-#define CAN_SR_TBS(n) ((uint32_t) (1 << (2 + (n) * 8)))
-
-/** CAN Transmission Complete Status (The request on Tx Buffer n=0/1/2 has been completed) */
-#define CAN_SR_TCS(n) ((uint32_t) (1 << (3 + (n) * 8)))
-
-/** CAN Receive Status (Bit 4, 12, 20 are the same)*/
-#define CAN_SR_RS(n) ((uint32_t) (1 << (4 + (n) * 8)))
-
-/** CAN Transmit Status (The CAN controller is sending a message in Tx Buffer n=0/1/2) */
-#define CAN_SR_TS(n) ((uint32_t) (1 << (5 + (n) * 8)))
-
-/** CAN Error Status (Bit 6, 14, 22 are the same)*/
-#define CAN_SR_ES(n) ((uint32_t) (1 << (6 + (n) * 8)))
-
-/** CAN Bus Status (Bit 7, 15, 23 are the same)*/
-#define CAN_SR_BS(n) ((uint32_t) (1 << (7 + (n) * 8)))
-
-/**
- * @brief CAN Receive Frame Status register definitions
- */
-/** CAN Receive Frame Status Register Bitmask */
-#define CAN_RFS_BITMASK (0xC00F07FF)
-
-/** CAN ID Index */
-#define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))
-
-/** CAN Bypass */
-#define CAN_RFS_BP ((uint32_t) (1 << 10))
-
-/** CAN Data Length Code */
-#define CAN_RFS_DLC(n) ((uint32_t) ((n >> 16) & 0x0F))
-
-/** CAN Remote Transmission Request */
-#define CAN_RFS_RTR ((uint32_t) (1 << 30))
-
-/** CAN control 11 bit or 29 bit Identifier */
-#define CAN_RFS_FF ((uint32_t) ((uint32_t) 1 << 31))
-
-/**
- * @brief CAN Receive Identifier Register definitions
- */
-/** CAN 11 bit Identifier */
-#define CAN_RID_ID_11(n) ((uint32_t) ((n) & 0x7FF))
-
-/** CAN 29 bit Identifier */
-#define CAN_RID_ID_29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
-
-/**
- * @brief CAN Transmit Frame Information register definitions
- */
-/** CAN Transmit Frame Information Register Bitmask */
-#define CAN_TFI_BITMASK (0xC00F00FF)
-
-/** CAN Priority */
-#define CAN_TFI_PRIO(n) ((uint32_t) ((n) & 0xFF))
-
-/** CAN Data Length Code */
-#define CAN_TFI_DLC(n) ((uint32_t) (((n) & 0xF) << 16))
-
-/** CAN Remote Frame Transmission */
-#define CAN_TFI_RTR ((uint32_t) (1 << 30))
-
-/** CAN control 11-bit or 29-bit Identifier */
-#define CAN_TFI_FF ((uint32_t) ((uint32_t) 1 << 31))
-
-/**
- * @brief CAN Transfer Identifier register definitions
- */
-/** CAN 11-bit Identifier */
-#define CAN_TID_ID11(n) ((uint32_t) ((n) & 0x7FF))
-
-/** CAN 11-bit Identifier */
-#define CAN_TID_ID29(n) ((uint32_t) ((n) & 0x1FFFFFFF))
-
-/**
- * @brief CAN Central transmit Status register definitions
- */
-/** CAN Central transmit Status Register Bitmask */
-#define CAN_TSR_BITMASK (0x30303)
-
-/** Bit indicate CAN n (0/1) is sending a message */
-#define CAN_TSR_TS(n) ((uint32_t) (1 << (n + 0)))
-
-/** Bit indicate all 3 Tx buffer of CAN n (0/1) are available */
-#define CAN_TSR_TBS(n) ((uint32_t) (1 << (n + 8)))
-
-/** Bit indicate all requested transmissions have been completed successfully by the CAN n(0/1) */
-#define CAN_TSR_TCS(n) ((uint32_t) (1 << (n + 16)))
-
-/**
- * @brief CAN Central Receive Status register definitions
- */
-/** CAN Central Receive Status Register Bitmask */
-#define CAN_RSR_BITMASK (0x30303)
-
-/** Bit indicate CAN n (0/1) is receiving a message */
-#define CAN_RSR_RS(n) ((uint32_t) (1 << (n + 0)))
-
-/** Bit indicate a received message is available in CAN n (0/1) */
-#define CAN_RSR_RBS(n) ((uint32_t) (1 << (n + 8)))
-
-/** Bit indicate a message was lost because the preceding message to CAN n(0/1) controller was not
- read out quickly enough*/
-#define CAN_RSR_DOS(n) ((uint32_t) (1 << (n + 16)))
-
-/**
- * @brief CAN Central Miscellaneous Status register definitions
- */
-/** CAN Central Receive Status Register Bitmask */
-#define CAN_MSR_BITMASK (0x303)
-
-/** Bit indicate Tx/Rx Error Counter has reached the limit set in CAN n (0/1) */
-#define CAN_MSR_E(n) ((uint32_t) (1 << (n + 0)))
-
-/** Bit indicate CAN n (0/1) is currently involved in bus activities*/
-#define CAN_MSR_BS(n) ((uint32_t) (1 << (n + 8)))
-
-/**
- * @brief Acceptance Filter Mode register definitions
- */
-/** CAN Acceptance Filter Operation mode */
-#define CANAF_AFMR_OPERATION ((uint32_t) (0))
-
-/** CAN Acceptance Filter Off mode */
-#define CANAF_AFMR_ACCOFF ((uint32_t) (1))
-
-/** CAN Acceptance File Bypass mode */
-#define CANAF_AFMR_ACCBP ((uint32_t) (1 << 1))
-
-/** FullCAN Mode Enhancements */
-#define CANAF_AFMR_EFCAN ((uint32_t) (1 << 2))
-
-/**
- * @brief Extended Frame Group Start Address register definitions
- */
-/** The start address of the table of grouped Extended Identifier */
-#define CANAF_ENDADDR(n) ((uint32_t) (((n) & 0x3FF) << 2))
-#define CANAF_ENDADDR_VAL(n) ((uint32_t) ((n >> 2) & 0x3FF))
-
-/**
- * @brief LUT Error Address register definitions
- */
-/** CAN Look-Up Table Error Address */
-#define CANAF_LUTERRAD(n) ((uint32_t) (((n) & 0x1FF) << 2))
-
-/**
- * @brief LUT Error register definitions
- */
-/** CAN Look-Up Table Error */
-#define CANAF_LUTERR ((uint32_t) (1))
-
-/**
- * @brief Global FullCANInterrupt Enable register definitions
- */
-/** Global FullCANInterrupt Enable Register Bitmask */
-#define CANAF_FCANIE_BITMASK (0x01)
-
-/** Global FullCANInterrupt Enable */
-#define CANAF_FCANIE ((uint32_t) (1))
-
-/**
- * @brief FullCAN Message Layout definitions
- */
-
-/** FF Bit Position*/
-#define CANAF_FULLCAN_MSG_FF_POS (31)
-/** RTR Bit Position*/
-#define CANAF_FULLCAN_MSG_RTR_POS (30)
-/** Message Lost Bit Position*/
-#define CANAF_FULLCAN_MSG_LOST_POS (26)
-/** SEM Bit Position*/
-#define CANAF_FULLCAN_MSG_SEM_POS (24)
-/** SEM Bit Mask*/
-#define CANAF_FULLCAN_MSG_SEM_BITMASK (0x03)
-/** DLC Bit Position*/
-#define CANAF_FULLCAN_MSG_DLC_POS (16)
-/** DLC Bit Mask*/
-#define CANAF_FULLCAN_MSG_DLC_BITMASK (0x0F)
-/** SCC Bit Position*/
-#define CANAF_FULLCAN_MSG_SCC_POS (13)
-/** SCC Bit Mask*/
-#define CANAF_FULLCAN_MSG_SCC_BITMASK (0x07)
-/** 11bit-ID Bit Position*/
-#define CANAF_FULLCAN_MSG_ID11_POS (0)
-/** 11bit-ID Bit Mask*/
-#define CANAF_FULLCAN_MSG_ID11_BITMASK (0x7FF)
-
-/**
- * @brief FullCAN Message Status
- */
-/** AF is updating FullCAN Message*/
-#define CANAF_FULCAN_MSG_AF_UPDATING (0x01)
-/** AF has finished updating FullCAN Message*/
-#define CANAF_FULCAN_MSG_AF_FINISHED (0x03)
-/** CPU is in process of reading FullCAN Message*/
-#define CANAF_FULCAN_MSG_CPU_READING (0x0)
-
-/**
- * @brief FullCAN Interrupt and Capture register definitions
- */
-/** FullCAN Interrupt and Capture (0-31)*/
-#define CANAF_FCAN_IC_INTPND(n) ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))
-
-/**
- * @brief Standard ID Entry definitions
- */
-/** Start position of Controller Number Bits */
-#define CAN_STD_ENTRY_CTRL_NO_POS (13 )
-/** Mask of Controller Number Bits */
-#define CAN_STD_ENTRY_CTRL_NO_MASK (0x07)
-/** Start position of Disable bit */
-#define CAN_STD_ENTRY_DISABLE_POS (12 )
-/** Mask of Disable Bit */
-#define CAN_STD_ENTRY_DISABLE_MASK (0x01)
-/** Start position of Interrupt Enable bit (FullCAN entry only)*/
-#define CAN_STD_ENTRY_IE_POS (11 )
-/** Mask of Interrupt Enable bit (FullCAN entry only)*/
-#define CAN_STD_ENTRY_IE_MASK (0x01)
-/** Start position of ID bit */
-#define CAN_STD_ENTRY_ID_POS (0 )
-/** Mask of ID Bit */
-#define CAN_STD_ENTRY_ID_MASK (0x7FF)
-
-/**
- * @brief Extended ID Entry definitions
- */
-/** Start position of Controller Number Bits */
-#define CAN_EXT_ENTRY_CTRL_NO_POS (29 )
-/** Mask of Controller Number Bits */
-#define CAN_EXT_ENTRY_CTRL_NO_MASK (0x07)
-/** Start position of ID bit */
-#define CAN_EXT_ENTRY_ID_POS (0 )
-/** Mask of ID Bit */
-#define CAN_EXT_ENTRY_ID_MASK (0x1FFFFFFF)
-
-/**
- * @brief CAN Message Type definitions
- */
-
-/** Remote Message */
-#define CAN_REMOTE_MSG ((uint32_t) (1 << 0))
-
-/** Message use Extend ID*/
-#define CAN_EXTEND_ID_USAGE ((uint32_t) (1 << 30))
-
-/** The maximum data length in CAN Message */
-#define CAN_MSG_MAX_DATA_LEN (8)
-
-/**
- * @brief CAN Buffer ID definition
- */
-typedef enum IP_CAN_BUFFER_ID {
- CAN_BUFFER_1 = 0, /*!< Buffer 1 */
- CAN_BUFFER_2, /*!< Buffer 2 */
- CAN_BUFFER_3, /*!< Buffer 3 */
- CAN_BUFFER_LAST, /*!< Last Buffer */
-} IP_CAN_BUFFER_ID_T;
-
-/**
- * @brief CAN Message Object Structure
- */
-typedef struct /*!< Message structure */
-{
- uint32_t ID; /*!< Message Identifier. If 30th-bit is set, this is 29-bit ID, othewise 11-bit ID */
- uint32_t Type; /*!< Message Type. which can include: - CAN_REMOTE_MSG type*/
- uint32_t DLC; /*!< Message Data Length: 0~8 */
- uint8_t Data[CAN_MSG_MAX_DATA_LEN];/*!< Message Data */
-} IP_CAN_MSG_T;
-
-/**
- * @brief CAN Bus Timing Structure
- */
-typedef struct /*!< Bus Timing structure */
-{
- uint16_t BRP; /*!< Baud Rate Prescaler */
- uint8_t SJW; /*!< SJW value*/
- uint8_t TESG1; /*!< TESG1 value */
- uint8_t TESG2; /*!< TESG2 value */
- uint8_t SAM; /*!<0: The bus is sampled once, 1: sampled 3 times */
-} IP_CAN_BUS_TIMING_T;
-
-/**
- * @brief Standard ID Entry structure
- */
-typedef struct {
- uint8_t CtrlNo; /*!MOD & CAN_MOD_BITMASK;
-}
-
-/**
- * @brief Set the CAN command request
- * @param pCAN : Pointer to CAN peripheral block
- * @param command : Command request (Or'ed bit values of CAN_CMR_*).
- * @return None
- */
-STATIC INLINE void IP_CAN_SetCmd(IP_CAN_001_T *pCAN, uint32_t command)
-{
- pCAN->CMR = command;
-}
-
-/**
- * @brief Set Error Warning Limit for the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param ewl : expected limit
- * @return None
- */
-STATIC INLINE void IP_CAN_SetEWL(IP_CAN_001_T *pCAN, uint32_t ewl)
-{
- pCAN->EWL = ewl & CAN_EWL_BITMASK;
-}
-
-/**
- * @brief Get Error Warning Limit of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @return Error warning limit value
- */
-STATIC INLINE uint8_t IP_CAN_GetEWL(IP_CAN_001_T *pCAN)
-{
- return CAN_EWL_VAL(pCAN->EWL);
-}
-
-/**
- * @brief Get global status register contents of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @return Gloabl Status register contents (Or'ed bit values of CAN_GSR_*)
- */
-STATIC INLINE uint32_t IP_CAN_GetGlobalStatus(IP_CAN_001_T *pCAN)
-{
- return pCAN->GSR;
-}
-
-/**
- * @brief Get the status of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @return Status (Or'ed bit values of CAN_SR_*(n) with n = CAN_BUFFER_1/2/3).
- */
-STATIC INLINE uint32_t IP_CAN_GetStatus(IP_CAN_001_T *pCAN)
-{
- return pCAN->SR;
-}
-
-/**
- * @brief Enable the given interrupt of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).
- * @return Nothing
- */
-STATIC INLINE void IP_CAN_IntEnable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
- pCAN->IER |= IntMask;
-}
-
-/**
- * @brief Disable the given interrupt of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).
- * @return Nothing
- */
-STATIC INLINE void IP_CAN_IntDisable(IP_CAN_001_T *pCAN, uint32_t IntMask) {
- pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;
-}
-
-/**
- * @brief Get the interrupt status of the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @return Interrupt status (Or'ed bit values of CAN_ICR_* )
- */
-STATIC INLINE uint32_t IP_CAN_GetIntStatus(IP_CAN_001_T *pCAN)
-{
- return pCAN->ICR;
-}
-
-/**
- * @brief Set CAN AF Mode
- * @param pCanAF : Pointer to CAN AF Register block
- * @param AFMode : Mode selected (Bit values of CANAF_AFMR_*)
- * @return None
- */
-STATIC INLINE void IP_CAN_AF_SetMode(IP_CAN_001_AF_T *pCanAF, uint32_t AFMode)
-{
- pCanAF->AFMR = AFMode;
-}
-
-/**
- * @brief Get CAN AF Mode
- * @param pCanAF : Pointer to CAN AF Register block
- * @return Mode
- */
-STATIC INLINE uint32_t IP_CAN_AF_GetMode(IP_CAN_001_AF_T *pCanAF)
-{
- return pCanAF->AFMR;
-}
-
-/**
- * @brief Initialize the CAN peripheral
- * @param pCAN : Pointer to CAN peripheral block
- * @return None
- */
-void IP_CAN_Init(IP_CAN_001_T *pCAN);
-
-/**
- * @brief Enable/Disable the specified mode in CAN controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param Mode : Mode selected (Bit values of CAN_MOD_*)
- * @param NewState : ENABLE: Enable, DISABLE: Disable
- * @return None
- */
-void IP_CAN_SetMode(IP_CAN_001_T *pCAN, uint32_t Mode, FunctionalState NewState);
-
-/**
- * @brief Set Bus Timing for the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param pBusTiming : Bus Timing information
- * @return None
- */
-void IP_CAN_SetBusTiming(IP_CAN_001_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming);
-
-/**
- * @brief Get message received by the CAN Controller
- * @param pCAN : Pointer to CAN peripheral block
- * @param pMsg : Pointer to the buffer to store the received message
- * @return SUCCESS (message information saved) or ERROR (no message received)
- */
-Status IP_CAN_Receive(IP_CAN_001_T *pCAN, IP_CAN_MSG_T *pMsg);
-
-/**
- * @brief Request the CAN Controller to send message
- * @param pCAN : Pointer to CAN peripheral block
- * @param TxBufID : ID of buffer which will be used for transmit
- * @param pMsg : Pointer to the buffer of message which will be sent
- * @return SUCCESS (message information saved) or ERROR (no message received)
- */
-Status IP_CAN_Send(IP_CAN_001_T *pCAN, IP_CAN_BUFFER_ID_T TxBufID, IP_CAN_MSG_T *pMsg);
-
-/**
- * @brief Initialize CAN Acceptance Filter
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @return Nothing
- */
-void IP_CAN_AF_Init(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
-
-/**
- * @brief Enable/Disable the interrupts of the CAN Controller in FullCAN Mode
- * @param pCanAF : Pointer to CAN AF Register block
- * @param NewState : ENABLE to enable/DISABLE to Disable
- * @return Nothing
- */
-void IP_CAN_FullCANIntConfig(IP_CAN_001_AF_T *pCanAF, FunctionalState NewState);
-
-/**
- * @brief Get FullCAN interrupt status of the object
- * @param pCanAF : Pointer to CAN AF Register block
- * @param ObjID : Object ID
- * @return Interrupt Status
- */
-uint32_t IP_CAN_GetFullCANIntStatus(IP_CAN_001_AF_T *pCanAF, uint8_t ObjID);
-
-/**
- * @brief Get FULLCANmessage automatically received by the AF
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param ObjID : Object ID
- * @param pMsg : Pointer to the buffer storing the received message
- * @param pSCC : Pointer to the buffer storing the controller ID of the received message
- * @return SUCCESS (message information saved) or ERROR (no message received)
- */
-Status IP_CAN_FullCANReceive(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint8_t ObjID, IP_CAN_MSG_T *pMsg, uint8_t *pSCC);
-
-/**
- * @brief Clear CAN AF LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @return None
- */
-void IP_CAN_ClearAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);
-
-/**
- * @brief Set CAN AF LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pAFSections : Pointer to buffer storing AF Section Data
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_SetAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam, IP_CAN_AF_LUT_T *pAFSections);
-
-/**
- * @brief Insert a FullCAN Entry into the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_InsertFullCANEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_STD_ID_Entry_T *pEntry);
-
-/**
- * @brief Insert an individual Standard Entry into the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_InsertIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_STD_ID_Entry_T *pEntry);
-
-/**
- * @brief Insert an Group Standard Entry into the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_InsertGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
-
-/**
- * @brief Insert an individual Extended Entry into the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_InsertIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_EXT_ID_Entry_T *pEntry);
-
-/**
- * @brief Insert an Group Extended Entry into the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_InsertGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
-
-/**
- * @brief Remove a FullCAN Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the Full CAN section (started from 0)
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_RemoveFullCANEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- int16_t Position);
-
-/**
- * @brief Remove an individual Standard Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the Individual STD section (started from 0)
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_RemoveIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- int16_t Position);
-
-/**
- * @brief Remove an Group Standard Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the Group STD section (started from 0)
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_RemoveGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- int16_t Position);
-
-/**
- * @brief Remove an individual Extended Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the Individual EXT section (started from 0)
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_RemoveIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- int16_t Position);
-
-/**
- * @brief Remove an Group Extended Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the Group EXT section (started from 0)
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_RemoveGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- int16_t Position);
-
-/**
- * @brief Get the number of entries of the given section
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param SectionID : Section ID
- * @return Number of entries
- */
-uint16_t IP_CAN_GetEntriesNum(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- IP_CAN_AF_RAM_SECTION_T SectionID);
-
-/**
- * @brief Read a FullCAN Entry into from current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the given section (started from 0)
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_ReadFullCANEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint16_t Position,
- IP_CAN_STD_ID_Entry_T *pEntry);
-
-/**
- * @brief Read an individual Standard Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the given section (started from 0)
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_ReadIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint16_t Position,
- IP_CAN_STD_ID_Entry_T *pEntry);
-
-/**
- * @brief Read an Group Standard Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the given section (started from 0)
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_ReadGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint16_t Position,
- IP_CAN_STD_ID_RANGE_Entry_T *pEntry);
-
-/**
- * @brief Read an individual Extended Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the given section (started from 0)
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_ReadIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint16_t Position,
- IP_CAN_EXT_ID_Entry_T *pEntry);
-
-/**
- * @brief Read an Group Extended Entry from the current LUT
- * @param pCanAF : Pointer to CAN AF Register block
- * @param pCanAFRam : Pointer to CAN AF RAM Register block
- * @param Position : Position of the entry in the given section (started from 0)
- * @param pEntry : Pointer to the entry which will be inserted
- * @return SUCCESS/ERROR
- */
-Status IP_CAN_ReadGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,
- IP_CAN_001_AF_RAM_T *pCanAFRam,
- uint16_t Position,
- IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CAN_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ccan_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ccan_001.h
deleted file mode 100644
index 82da44229..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ccan_001.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * @brief CCAN registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CCAN_001_H_
-#define __CCAN_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_CCAN_001 IP: CCAN register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief CCAN message interface register block structure
- */
-typedef struct { /*!< C_CAN message interface Structure */
- __IO uint32_t IF_CMDREQ; /*!< Message interface command request */
- union {
- __IO uint32_t IF_CMDMSK_R; /*!< Message interface command mask (read direction) */
- __IO uint32_t IF_CMDMSK_W; /*!< Message interface command mask (write direction) */
- };
-
- __IO uint32_t IF_MSK1; /*!< Message interface mask 1 */
- __IO uint32_t IF_MSK2; /*!< Message interface mask 2 */
- __IO uint32_t IF_ARB1; /*!< Message interface arbitration 1 */
- __IO uint32_t IF_ARB2; /*!< Message interface arbitration 2 */
- __IO uint32_t IF_MCTRL; /*!< Message interface message control */
- __IO uint32_t IF_DA1; /*!< Message interface data A1 */
- __IO uint32_t IF_DA2; /*!< Message interface data A2 */
- __IO uint32_t IF_DB1; /*!< Message interface data B1 */
- __IO uint32_t IF_DB2; /*!< Message interface data B2 */
- __I uint32_t RESERVED[13];
-} IP_CCAN_001_IF_T;
-
-/**
- * @brief CCAN Controller Area Network register block structure
- */
-typedef struct { /*!< C_CAN Structure */
- __IO uint32_t CNTL; /*!< CAN control */
- __IO uint32_t STAT; /*!< Status register */
- __I uint32_t EC; /*!< Error counter */
- __IO uint32_t BT; /*!< Bit timing register */
- __I uint32_t INT; /*!< Interrupt register */
- __IO uint32_t TEST; /*!< Test register */
- __IO uint32_t BRPE; /*!< Baud rate prescaler extension register */
- __I uint32_t RESERVED0;
- IP_CCAN_001_IF_T IF[2];
- __I uint32_t RESERVED2[8];
- __I uint32_t TXREQ1; /*!< Transmission request 1 */
- __I uint32_t TXREQ2; /*!< Transmission request 2 */
- __I uint32_t RESERVED3[6];
- __I uint32_t ND1; /*!< New data 1 */
- __I uint32_t ND2; /*!< New data 2 */
- __I uint32_t RESERVED4[6];
- __I uint32_t IR1; /*!< Interrupt pending 1 */
- __I uint32_t IR2; /*!< Interrupt pending 2 */
- __I uint32_t RESERVED5[6];
- __I uint32_t MSGV1; /*!< Message valid 1 */
- __I uint32_t MSGV2; /*!< Message valid 2 */
- __I uint32_t RESERVED6[6];
- __IO uint32_t CLKDIV; /*!< CAN clock divider register */
-} IP_CCAN_001_T;
-
-typedef enum IP_CCAN_TEST_MODE {
- CCAN_BASIC_TEST_MODE = 1 << 2,
- CCAN_SILENT_TEST_MODE = 1 << 3,
- CCAN_LOOPBACK_TEST_MODE = 1 << 4
-} IP_CCAN_TEST_MODE_T;
-
-typedef enum IP_CCAN_INT {
- CCAN_MODULE_INT = 1 << 1,
- CCAN_STATUS_CHANGE_INT = 1 << 2,
- CCAN_ERR_INT = 1 << 3
-} IP_CCAN_INT_T;
-
-/**
- * @brief CAN message object structure
- */
-typedef struct {
- uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */
- uint32_t dlc; /**< Message data length */
- uint8_t data[8]; /**< Message data */
-} message_object;
-typedef enum IP_CCAN_MSG_INTERFACE {
- IF1 = 0x00,
- IF2 = 1,
-} IP_CCAN_MSG_INTERFACE_T;
-typedef enum IP_CCAN_STATUS {
- CCAN_STAT_LEC = (0x7 << 0),
- CCAN_STAT_TXOK = (1 << 3),
- CCAN_STAT_RXOK = (1 << 4),
- CCAN_STAT_EPASS = (1 << 5),
- CCAN_STAT_EWARN = (1 << 6),
- CCAN_STAT_BOFF = (1 << 7)
-} IP_CCAN_STATUS_T;
-
-/**
- * @brief I2S transmit/receive mode for configuration
- */
-typedef enum IP_CCAN_TRX_MODE {
- CCAN_TX_MODE,
- CCAN_RX_MODE,
-} IP_CCAN_TRX_MODE_T;
-/* Private Macros ---------------------------------------------------------- */
-#ifndef __GNUC__
-/* Macro for reading and writing to CCAN IF registers */
-#define CCAN_IF_Read(LPCx, reg, IFsel) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg))
-#define CCAN_IF_Write(LPCx, reg, IFsel, val) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg) = (val))
-#else
-#define CCAN_IF_Read(LPCx, reg, IFsel) (LPCx->IF[IFsel].IF ## _ ## reg)
-#define CCAN_IF_Write(LPCx, reg, IFsel, val) (LPCx->IF[IFsel].IF ## _ ## reg = val)
-#endif
-
-#define CCAN_STATUS_INT 0x8000
-
-#define CCAN_TX_DIR 1UL
-#define CCAN_RX_DIR 0UL
-
-/* bit field of IF command mask register */
-#define CCAN_DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */
-#define CCAN_DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */
-#define CCAN_NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */
-#define CCAN_CLRINTPND (1 << 3)
-#define CCAN_CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */
-#define CCAN_ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */
-#define CCAN_MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */
-#define CCAN_RW(n) (((n) & 1UL) << 7) /* 0 is READ, 1 is WRITE */
-#define CCAN_WR 1UL
-#define CCAN_RD 0UL
-
-/* bit field of IF mask 2 register */
-#define CCAN_MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
-#define CCAN_MASK_MDIR(n) (((n) & 0x01) << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */
-
-/* bit field of IF identifier 2 register */
-#define CCAN_ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
-#define CCAN_ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */
-#define CCAN_ID_DIR(n) (((n) & 0x01) << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */
-
-/* bit field of IF message control register */
-#define CCAN_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
-#define CCAN_MLST (1 << 14) /* 1 indicates a message loss. */
-#define CCAN_INTP (1 << 13) /* 1 indicates message object is an interrupt source */
-#define CCAN_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
-#define CCAN_TXIE (1 << 11) /* 1 is TX interrupt enabled */
-#define CCAN_RXIE (1 << 10) /* 1 is RX interrupt enabled */
-
-#define CCAN_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */
-
-#define CCAN_TXRQ (1 << 8) /* 1 is TxRqst enabled */
-#define CCAN_EOB (1 << 7) /* End of buffer, always write to 1 */
-#define CCAN_DLC 0x000F /* bit mask for DLC */
-
-#define CCAN_ID_STD_MASK 0x07FF
-#define CCAN_ID_EXT_MASK 0x1FFFFFFF
-#define CCAN_DLC_MASK 0x0F
-
-/* bit field of IF command request n register */
-#define CCAN_IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when
- RD/WR done */
-/* CAN CTRL register */
-#define CCAN_CTRL_INIT (1 << 0)
-#define CCAN_CTRL_IE (1 << 1)
-#define CCAN_CTRL_SIE (1 << 2)
-#define CCAN_CTRL_EIE (1 << 3)
-#define CCAN_CTRL_DAR (1 << 5)
-#define CCAN_CTRL_CCE (1 << 6)
-#define CCAN_CTRL_TEST (1 << 7)
-
-/**
- * @brief Configure the bit timing for CCAN bus
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param ClkDiv : Set the clock divider
- * @param BaudRatePrescaler : Set the baud rate Prescaler
- * @param SynJumpWidth : Set the synchronization jump width
- * @param Tseg1 : Set the Phase buffer segment 1
- * @param Tseg2 : Set the Phase buffer segment 2
- * @return Nothing
- */
-void IP_CCAN_TimingCfg (IP_CCAN_001_T *pCCAN,
- uint32_t ClkDiv,
- uint32_t BaudRatePrescaler,
- uint8_t SynJumpWidth,
- uint8_t Tseg1,
- uint8_t Tseg2);
-
-/**
- * @brief Initialize the CAN controller
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param NewState : New state, ENABLE for starting initialization, DISABLE for normal operation
- * @return Nothing
- */
-void IP_CCAN_SWInit (IP_CCAN_001_T *pCCAN, FunctionalState NewState);
-
-/**
- * @brief Enable/Disable CCAN Interrupts
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param Int_type : Type of interrupt
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_CCAN_IntEnable (IP_CCAN_001_T *pCCAN, IP_CCAN_INT_T Int_type, FunctionalState NewState);
-
-/**
- * @brief Enable/Disable automatic retransmission
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_CCAN_AutoRetransmitEnable (IP_CCAN_001_T *pCCAN, FunctionalState NewState);
-
-/**
- * @brief Get the current value of the transmit/receive error counter
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be CCAN_TX_MODE or CCAN_RX_MODE
- * @return Current value of the transmit/receive error counter
- */
-uint8_t IP_CCAN_GetErrCounter (IP_CCAN_001_T *pCCAN, IP_CCAN_TRX_MODE_T TRMode);
-
-/**
- * @brief Get the CCAN status register
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return CCAN status register
- */
-uint32_t IP_CCAN_GetStatus (IP_CCAN_001_T *pCCAN);
-
-/**
- * @brief Set the CCAN status
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param val : Value to be set for status register
- * @return Nothing
- */
-void IP_CCAN_SetStatus (IP_CCAN_001_T *pCCAN, uint32_t val);
-
-/**
- * @brief Get the source ID of an interrupt
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return Interrupt source ID
- */
-uint32_t IP_CCAN_Get_IntID (IP_CCAN_001_T *pCCAN);
-
-/**
- * @brief Enable/Disable test mode in CCAN
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param test_mode : Selected mode, the different test functions may be combined
- * @param NewState : New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_CCAN_TestModeEnable(IP_CCAN_001_T *pCCAN, IP_CCAN_TEST_MODE_T test_mode, FunctionalState NewState);
-
-/**
- * @brief Clear interrupt pending bit in the message object
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param IFsel : The Message interface to be used
- * @param msg_num : Message number
- * @return Nothing
- */
-void IP_CCAN_ClearIntPend (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);
-
-/**
- * @brief Clear new data flag bit in the message object
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param IFsel : The Message interface to be used
- * @param msg_num : Message number
- * @return Nothing
- */
-void IP_CCAN_Clear_NewDataFlag (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);
-
-/**
- * @brief Enable/Disable the message object to valid
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param IFsel : The Message interface to be used
- * @param msg_num : Message number
- * @param NewState: New state, ENABLE or DISABLE
- * @return Nothing
- */
-void IP_CCAN_SetValidMsg(IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num, FunctionalState NewState);
-
-/**
- * @brief Check the message objects is valid or not
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return A 32 bits value, each bit corresponds to a message objects form 0 to 31 (1 is valid, 0 is invalid)
- */
-uint32_t IP_CCAN_GetValidMsg(IP_CCAN_001_T *pCCAN);
-
-/**
- * @brief Get the transmit repuest bit in all message objects
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @return A 32 bits value, each bit corresponds to transmit request bit in message objects
- */
-uint32_t IP_CCAN_GetTxRQST(IP_CCAN_001_T *pCCAN);
-
-/**
- * @brief Set a message into the message object in message RAM
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param IFsel : The Message interface to be used
- * @param direction : Select the message object is used for transmiting or receiving, should be CCAN_TX_DIR or CCAN_RX_DIR
- * @param RemoteEnable: Enable/Disable passives transmit by using remote frame
- * @param msg_num : Message number
- * @param msg_ptr : Pointer of message to be set
- * @return Nothing
- */
-void IP_CCAN_SetMsgObject (IP_CCAN_001_T *pCCAN,
- IP_CCAN_MSG_INTERFACE_T IFsel,
- uint8_t direction,
- uint32_t RemoteEnable,
- uint8_t msg_num,
- const message_object *msg_ptr);
-
-/**
- * @brief Get a message object in message RAM into the message buffer
- * @param pCCAN : The base of CCAN peripheral on the chip
- * @param IFsel : The Message interface to be used
- * @param msg_num : The number of message object in message RAM to be get
- * @param msg_buf : Pointer of the message buffer
- * @return Nothing
- */
-void IP_CCAN_GetMsgObject (IP_CCAN_001_T *pCCAN,
- IP_CCAN_MSG_INTERFACE_T IFsel,
- uint8_t msg_num,
- message_object *msg_buf);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CCAN_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/cmp_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/cmp_001.h
deleted file mode 100644
index 6a842b324..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/cmp_001.h
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * @brief CMP Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CMP_001_H_
-#define __CMP_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_CMP_001 IP: Comparator register block and driver
- * @ingroup IP_Drivers
- * Comparator
- * @{
- */
-/** The number of embeded comparators supported */
-#define CMP_NUM 2
-
-/**
- * @brief Comparator (CMP) register block structure
- */
-typedef struct { /*!< Comparator structure */
- __IO uint32_t CMP_CTRL; /*!< Comparator block control register */
- __IO uint32_t CMP_CTRLx[CMP_NUM]; /*!< Specific comparator control register */
-} IP_CMP_001_T;
-
-/**
- * @brief Comparator control definition
- */
-typedef enum IP_CMP_ENCTRL {
- CMP_ENCTRL_DISABLE, /*!< Disable */
- CMP_ENCTRL_DIS_IN_DS_PWD, /*!< Disable in deep sleep mode and power down mode*/
- CMP_ENCTRL_DIS_IN_PWD, /*!< Disable in power down mode*/
- CMP_ENCTRL_ENABLE, /*!< Enable/Power-up*/
-} IP_CMP_ENCTRL_T;
-
-/*!< Comparator control register Bitmask */
-#define CMP_CTRL_BITMASK (0xF30F)
-/*!< The comparator current source control bitmask*/
-#define CMP_CTRL_PD_IREF_BITMASK (0x03)
-/*!< Control the comparator current source (n is IP_CMP_ENCTRL_T value)*/
-#define CMP_CTRL_PD_IREF(n) ((((uint32_t) (n)) & 0x03))
-/*!< The comparator bandgap reference control bitmask*/
-#define CMP_CTRL_PD_VBG_BITMASK (((uint32_t) 0x03) << 2)
-/*!< Control the comparator bandgap reference (n is IP_CMP_ENCTRL_T value)*/
-#define CMP_CTRL_PD_VBG(n) ((((uint32_t) (n)) & 0x03) << 2)
-/*!< The CMP_ROSC ouput control bitmask */
-#define CMP_CTRL_ROSC_BITMASK ((uint32_t) 0x300)
-/*!< The CMP_ROSC output is set by CMP1, reset by CMP0 */
-#define CMP_CTRL_ROSCCTL_CMP1 (0x00)
-/*!< The CMP_ROSC output is set by CMP0, reset by CMP1 */
-#define CMP_CTRL_ROSCCTL_CMP0 (((uint32_t) 0x01) << 8)
-/*!< The CMP_ROSC output is reset by the internal chip reset */
-#define CMP_CTRL_EXT_RESET_INTERNAL (0x00)
-/*!< The CMP_ROSC output is reset by the CMP_RESET input */
-#define CMP_CTRL_EXT_RESET_CMPRESET (((uint32_t) 0x01) << 9)
-/*!< Timer Capture input control bitmask */
-#define CMP_CTRL_TIMERCAPTURE_BITMASK ((uint32_t) 0xF000)
-/*!< Selects the comparator 0 level output as the input for Timer0 capture input 2 */
-#define CMP_CTRL_T0CAP2_0LEVEL (0x00)
-/*!< Selects the comparator 1 level output as the input for Timer0 capture input 2 */
-#define CMP_CTRL_T0CAP2_1LEVEL (((uint32_t) 0x01) << 12)
-/*!< Selects the comparator 0 edge output as the input for Timer0 capture input 3 */
-#define CMP_CTRL_T0CAP3_0EDGE (0x00)
-/*!< Selects the comparator 1 edge output as the input for Timer0 capture input 3 */
-#define CMP_CTRL_T0CAP3_1EDGE (((uint32_t) 0x01) << 13)
-/*!< Selects the comparator 1 edge output as the input for Timer1 capture input 2 */
-#define CMP_CTRL_T1CAP2_1EDGE (0x00)
-/*!< Selects the comparator 0 level output as the input for Timer1 capture input 2 */
-#define CMP_CTRL_T1CAP2_0LEVEL (((uint32_t) 0x01) << 14)
-/*!< Selects the comparator 1 level output as the input for Timer1 capture input 3 */
-#define CMP_CTRL_T1CAP3_1LEVEL (0x00)
-/*!< Selects the comparator 0 edge output as the input for Timer1 capture input 3 */
-#define CMP_CTRL_T1CAP3_0EDGE (((uint32_t) 0x01) << 15)
-
-/*!< The comparator x control register Bitmask */
-#define CMP_CTRLx_BITMASK ((uint32_t) 0x1F7FF77F)
-/*!< The comparator x enable bitmask*/
-#define CMP_CTRLx_EN_BITMASK (0x03)
-/*!< Control the comparator x (n is IP_CMP_ENCTRL_T value)*/
-#define CMP_CTRLx_EN(n) ((((uint32_t) (n)) & 0x03))
-/*!< Enable the output of compartor x */
-#define CMP_CTRLx_OE (((uint32_t) 0x01) << 2)
-/*!< The status of compartor x, reflects the comparator x output*/
-#define CMP_CTRLx_STAT (((uint32_t) 0x01) << 3)
-/*!< Comparator VM input control bitmask */
-#define CMP_CTRLx_VM_BITMASK (((uint32_t) 0x07) << 4)
-/*!< Select the VM input*/
-#define CMP_CTRLx_VM(n) ((((uint32_t) (n)) & 0x07) << 4)
-/*!< Comparator VP input control bitmask */
-#define CMP_CTRLx_VP_BITMASK (((uint32_t) 0x07) << 8)
-/*!< Select the VP input */
-#define CMP_CTRLx_VP(n) ((((uint32_t) (n)) & 0x07) << 8)
-/*!< Synchronize the Comparator x output with the internal bus clock for outpur to other peripherals */
-#define CMP_CTRLx_SYNC (((uint32_t) 0x01) << 12)
-/*!< Comparator Hysteresis control bitmask */
-#define CMP_CTRLx_HYS_BITMASK (((uint32_t) 0x03) << 13)
-/*!< Determine the difference required between the comparator inputs before the comparator output switch*/
-#define CMP_CTRLx_HYS(n) ((((uint32_t) (n)) & 0x03) << 13)
-/*!< Interrupt control bitmask */
-#define CMP_CTRLx_INTCTRL_BITMASK ((uint32_t) 0x78000)
-/*!< Comparator output is used as-is for generating interrupts. */
-#define CMP_CTRLx_INTPOL_NORMAL (0x00)
-/*!< Comparator output is used inverted for generating interrupts. */
-#define CMP_CTRLx_INTPOL_INV (((uint32_t) 0x01) << 15)
-/*!< Comparator x interrupt is edge triggered. */
-#define CMP_CTRLx_INTTYPE_EDGE (0x00)
-/*!< Comparator x interrupt is level triggered.*/
-#define CMP_CTRLx_INTTYPE_LEVEL (((uint32_t) 0x01) << 16)
-/*!< Comparator x interrupt edge control bitmask */
-#define CMP_CTRLx_INTEDGE_BITMASK (((uint32_t) 0x03) << 17)
-/*!< Select edge on which triggered interrupt is active*/
-#define CMP_CTRLx_INTEDGE(n) ((((uint32_t) (n)) & 0x03) << 17)
-/*!< Comparator interrupt flag */
-#define CMP_CTRLx_INTFLAG (((uint32_t) 0x01) << 19)
-/*!< The VLAD Enable bitmask*/
-#define CMP_CTRLx_VLADEN_BITMASK (((uint32_t) 0x03) << 20)
-/*!< Control the comparator x (n is IP_CMP_ENCTRL_T value)*/
-#define CMP_CTRLx_VLADEN(n) ((((uint32_t) (n)) & 0x03) << 20)
-/*!< Select VREF_CMP pin as voltage reference for comparator voltage ladder */
-#define CMP_CTRLx_VLADREF_VREFCMP (0x00)
-/*!< Select VDDA pin as voltage reference for comparator voltage ladder */
-#define CMP_CTRLx_VLADREF_VDDA (((uint32_t) 0x01) << 22)
-/*!< Volatge ladder value bitmask */
-#define CMP_CTRLx_VSEL_BITMASK ((uint32_t) ((0x1F) << 24))
-/*!< Voltage ladder value for Comparator */
-#define CMP_CTRLx_VSEL(n) ((((uint32_t) (n)) & 0x1F) << 24)
-
-/**
- * @brief Comparator VM/VP input definitions
- */
-typedef enum IP_CMP_INPUT {
- CMP_INPUT_VREF_DIV, /*!< Vref divider.*/
- CMP_INPUT_CMPx_IN0, /*!< Use the input 0 of the comparator*/
- CMP_INPUT_CMPx_IN1, /*!< Use the input 1 of the comparator*/
- CMP_INPUT_CMPx_IN2, /*!< Use the input 2 of the comparator*/
- CMP_INPUT_CMPx_IN3, /*!< Use the input 3 of the comparator*/
- CMP_INPUT_CMP_OTHER_IN0, /*!< Use the input 0 of the other comparator.*/
- CMP_INPUT_INTERNAL_09VBG, /*!< internal 0.9 V band gap reference.*/
-} IP_CMP_INPUT_T;
-
-/**
- * @brief Comparator hysteresis selection definitions
- */
-typedef enum IP_CMP_HYS {
- CMP_HYS_NONE = CMP_CTRLx_HYS(0), /*!CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_PD_IREF_BITMASK)) | CMP_CTRL_PD_IREF(en);
-}
-
-/**
- * @brief Enables comparator bandgap reference
- * @param pCMP : Pointer to Comparator Register block
- * @param en : Enable mode
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_EnableBandGap(IP_CMP_001_T *pCMP, IP_CMP_ENCTRL_T en)
-{
- pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_PD_VBG_BITMASK)) | CMP_CTRL_PD_VBG(en);
-}
-
-/**
- * @brief Control CMP_ROSC
- * @param pCMP : Pointer to Comparator Register block
- * @param flag : Or-ed bit value of CMP_CTRL_ROSCCTL_* and CMP_CTRL_EXT_RESET_*
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_ControlROSC(IP_CMP_001_T *pCMP, uint32_t flag)
-{
- pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_ROSC_BITMASK)) | flag;
-}
-
-/**
- * @brief Control CMP_ROSC
- * @param pCMP : Pointer to Comparator Register block
- * @param flag : Or-ed bit value of CMP_CTRL_T*CAP*
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_SetTimerCapInput(IP_CMP_001_T *pCMP, uint32_t flag)
-{
- pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_TIMERCAPTURE_BITMASK)) | flag;
-}
-
-/**
- * @brief Sets up voltage ladder
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param ladSel : Voltage ladder value (0~31).
- * @param flag :0(CMP_VREF used)/CMP_CTRLx_VLADREF_VDDA (VDDA used)
- * @return Nothing
- * @note VREF divider 0 = ladSel*VRef0/31
- */
-STATIC INLINE void IP_CMP_SetupVoltLadder(IP_CMP_001_T *pCMP, uint8_t id,
- uint16_t ladSel, uint32_t flag)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~(CMP_CTRLx_VSEL_BITMASK | CMP_CTRLx_VLADREF_VDDA))) | CMP_CTRLx_VSEL(
- ladSel) | flag;
-}
-
-/**
- * @brief Enables voltage ladder
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param en : Enable mode
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_EnableVoltLadder(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_ENCTRL_T en)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VLADEN_BITMASK)) | CMP_CTRLx_VLADEN(en);
-}
-
-/**
- * @brief Selects positive voltage input
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param input : Selected input
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_SetPosVoltRef(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_INPUT_T input)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VP_BITMASK)) | CMP_CTRLx_VP(input);
-}
-
-/**
- * @brief Selects negative voltage input
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param input : Selected input
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_SetNegVoltRef(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_INPUT_T input)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VM_BITMASK)) | CMP_CTRLx_VM(input);
-}
-
-/**
- * @brief Selects hysteresis level
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param hys : Selected Hysteresis level
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_SetHysteresis(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_HYS_T hys)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_HYS_BITMASK)) | hys;
-}
-
-/**
- * @brief Enables specified comparator
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param en : Enable mode
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_Enable(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_ENCTRL_T en)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_EN_BITMASK)) | CMP_CTRLx_EN(en);
-}
-
-/**
- * @brief Returns the current comparator status
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator Id (0/1)
- * @return SET/RESET
- */
-STATIC INLINE FlagStatus IP_CMP_GetCmpStatus(IP_CMP_001_T *pCMP, uint8_t id)
-{
- return (pCMP->CMP_CTRLx[id] & CMP_CTRLx_STAT) ? SET : RESET;
-}
-
-/**
- * @brief Enable comparator output
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_EnableOuput(IP_CMP_001_T *pCMP, uint8_t id)
-{
- pCMP->CMP_CTRLx[id] |= CMP_CTRLx_OE;
-}
-
-/**
- * @brief Disable comparator output
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_DisableOutput(IP_CMP_001_T *pCMP, uint8_t id)
-{
- pCMP->CMP_CTRLx[id] &= ~CMP_CTRLx_OE;
-}
-
-/**
- * @brief Synchronizes Comparator output to bus clock
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_EnableSyncCmpOut(IP_CMP_001_T *pCMP, uint8_t id)
-{
- pCMP->CMP_CTRLx[id] |= CMP_CTRLx_SYNC;
-}
-
-/**
- * @brief Sets comparator output to be used directly (no sync)
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_DisableSyncCmpOut(IP_CMP_001_T *pCMP, uint8_t id)
-{
- pCMP->CMP_CTRLx[id] &= ~CMP_CTRLx_SYNC;
-}
-
-/**
- * @brief Sets up comparator interrupt
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @param intFlag : Or-ed value of CMP_CTRLx_INTTYPE_*, CMP_CTRLx_INTPOL_*
- * @param edgeSel : the edge on which interrupt occurs.
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_ConfigInt(IP_CMP_001_T *pCMP, uint8_t id,
- uint32_t intFlag,
- IP_CMP_INTEDGE_T edgeSel)
-{
- pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_INTCTRL_BITMASK)) | intFlag | edgeSel;
-}
-
-/**
- * @brief Get the CMP interrupt status
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return SET/RESET
- */
-STATIC INLINE FlagStatus IP_CMP_GetIntStatus(IP_CMP_001_T *pCMP, uint8_t id)
-{
- return (pCMP->CMP_CTRLx[id] & CMP_CTRLx_INTFLAG) ? SET : RESET;
-}
-
-/**
- * @brief Clears the CMP interrupt status
- * @param pCMP : Pointer to Comparator Register block
- * @param id : Comparator ID
- * @return Nothing
- */
-STATIC INLINE void IP_CMP_CMP_ClearIntStatus(IP_CMP_001_T *pCMP, uint8_t id)
-{
- pCMP->CMP_CTRLx[id] |= CMP_CTRLx_INTFLAG;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMP_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/crc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/crc_001.h
deleted file mode 100644
index 2f3a875cd..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/crc_001.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * @brief Cyclic Redundancy Check (CRC) registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __CRC_001_H_
-#define __CRC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_CRC_001 IP: CRC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief CRC register block structure
- */
-typedef struct { /*!< CRC Structure */
- __IO uint32_t MODE; /*!< CRC Mode Register */
- __IO uint32_t SEED; /*!< CRC SEED Register */
- union {
- __I uint32_t SUM; /*!< CRC Checksum Register. */
- __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/
- __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/
- __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/
- };
-
-} IP_CRC_001_T;
-
-/**
- * @brief CRC MODE register description
- */
-#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */
-#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */
-#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */
-#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */
-#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */
-#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */
-#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */
-#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */
-#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */
-#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */
-
-#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */
-#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */
-#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */
-
-#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */
-#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */
-#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */
-
-/*
- * @brief CRC polynomial
- */
-typedef enum IP_CRC_001_POLY {
- CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */
- CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */
- CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */
- CRC_POLY_LAST,
-} IP_CRC_001_POLY_T;
-
-/**
- * @brief Initializes the CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_Init(IP_CRC_001_T *pCRC) {}
-
-/**
- * @brief De-initializes the CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_DeInit(IP_CRC_001_T *pCRC) {}
-
-/**
- * @brief Select polynomial for CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param poly : CRC polynomial selection
- * @param flags : An Or'ed value of flags that setup the mode
- * @return Nothing
- * @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS,
- * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL.
- */
-STATIC INLINE void IP_CRC_SetPoly(IP_CRC_001_T *pCRC, IP_CRC_001_POLY_T poly,
- uint32_t flags)
-{
- pCRC->MODE = (uint32_t) poly | flags;
-}
-
-/**
- * @brief Sets up the CRC engine with defaults based on the polynomial to be used
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param poly : The enumerated polynomial to be used
- * @return Nothing
- */
-void IP_CRC_UseDefaultConfig(IP_CRC_001_T *pCRC, IP_CRC_001_POLY_T poly);
-
-/**
- * @brief Get mode register of CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @return Current CRC Mode register (Or-ed bits value of CRC_MODE_*)
- */
-STATIC INLINE uint32_t IP_CRC_GetMode(IP_CRC_001_T *pCRC)
-{
- return pCRC->MODE;
-}
-
-/**
- * @brief Set mode register of CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param mode : mode value to be set in mode register
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_SetMode(IP_CRC_001_T *pCRC, uint32_t mode)
-{
- pCRC->MODE = mode;
-}
-
-/**
- * @brief Set Seed value
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param Seed : selected seed value
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_SetSeed(IP_CRC_001_T *pCRC, uint32_t Seed)
-{
- pCRC->SEED = Seed;
-}
-
-/**
- * @brief Get Seed value.
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @return current seed value
- */
-STATIC INLINE uint32_t IP_CRC_GetSeed(IP_CRC_001_T *pCRC)
-{
- return pCRC->SEED;
-}
-
-/**
- * @brief Write 8-bit data to CRC WR Data register.
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : data to be written
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_Write8(IP_CRC_001_T *pCRC, uint8_t data)
-{
- pCRC->WRDATA8 = data;
-}
-
-/**
- * @brief Write 16-bit data to CRC WR Data register.
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : data to be written
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_Write16(IP_CRC_001_T *pCRC, uint16_t data)
-{
- pCRC->WRDATA16 = (uint32_t) data;
-}
-
-/**
- * @brief Write 32-bit data to CRC WR Data register.
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : data to be written
- * @return Nothing
- */
-STATIC INLINE void IP_CRC_Write32(IP_CRC_001_T *pCRC, uint32_t data)
-{
- pCRC->WRDATA32 = data;
-}
-
-/**
- * @brief Read current calculated checksum from CRC Engine
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @return Check sum value
- */
-STATIC INLINE uint32_t IP_CRC_ReadSum(IP_CRC_001_T *pCRC)
-{
- return pCRC->SUM;
-}
-
-/**
- * @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : Pointer to the block of 8 bit data
- * @param bytes : The number of bytes pointed to by data
- * @return Computed checksum for the block
- */
-uint32_t IP_CRC_CRC8(IP_CRC_001_T *pCRC, const uint8_t *data, uint32_t bytes);
-
-/**
- * @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : Pointer to the block of 16-bit data
- * @param hwords : The number of halfword entries pointed to by data
- * @return Computed checksum for the block
- */
-uint32_t IP_CRC_CRC16(IP_CRC_001_T *pCRC, const uint16_t *data, uint32_t hwords);
-
-/**
- * @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block
- * @param pCRC : Pointer to selected CRC Engine register block structure
- * @param data : Pointer to the block of 32-bit data
- * @param words : The number of 32-bit entries pointed to by data
- * @return Computed checksum for the block
- */
-uint32_t IP_CRC_CRC32(IP_CRC_001_T *pCRC, const uint32_t *data, uint32_t words);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CRC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/dac_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/dac_001.h
deleted file mode 100644
index 32b498ee5..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/dac_001.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * @brief DAC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __DAC_001_H_
-#define __DAC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_DAC_001 IP: DAC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief DAC register block structure
- */
-typedef struct { /*!< DAC Structure */
- __IO uint32_t CR; /*!< DAC register. Holds the conversion data. */
- __IO uint32_t CTRL; /*!< DAC control register. */
- __IO uint32_t CNTVAL; /*!< DAC counter value register. */
-} IP_DAC_001_T;
-
-/** After the selected settling time after this field is written with a
- new VALUE, the voltage on the AOUT pin (with respect to VSSA)
- is VALUE/1024 � VREF */
-#define DAC_VALUE(n) ((uint32_t) ((n & 0x3FF) << 6))
-/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
- * and the maximum current is 700 microAmpere
- * If this bit = 1: The settling time of the DAC is 2.5 microsecond
- * and the maximum current is 350 microAmpere
- */
-#define DAC_BIAS_EN ((uint32_t) (1 << 16))
-/** Value to reload interrupt DMA counter */
-#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
-
-/** DCAR double buffering */
-#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
-/** DCAR Time out count enable */
-#define DAC_CNT_ENA ((uint32_t) (1 << 2))
-/** DCAR DMA access */
-#define DAC_DMA_ENA ((uint32_t) (1 << 3))
-/** DCAR DACCTRL mask bit */
-#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
-
-/**
- * @brief Current option in DAC configuration option
- */
-typedef enum IP_DAC_CURRENT_OPT {
- DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption;
- allows for a maximum update rate of 1 MHz */
- DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption;
- allows for a maximum update rate of 400 kHz */
-} IP_DAC_CURRENT_OPT_T;
-
-/**
- * @brief Initial DAC configuration
- * - Maximum update rate is 1MHz
- * - Value to AOUT is 0
- * @param pDAC : pointer to the DAC peripheral block
- * @return Nothing
- */
-void IP_DAC_Init(IP_DAC_001_T *pDAC);
-
-/**
- * @brief Update value to DAC buffer
- * @param pDAC : pointer to the DAC peripheral block
- * @param dac_value : value 10 bit to be converted to output
- * @return Nothing
- */
-void IP_DAC_UpdateValue (IP_DAC_001_T *pDAC, uint32_t dac_value);
-
-/**
- * @brief Set maximum update rate for DAC
- * @param pDAC : pointer to the DAC peripheral block
- * @param bias : Using Bias value, should be:
- * - 0 is 1MHz
- * - 1 is 400kHz
- * @return Nothing
- */
-void IP_DAC_SetBias (IP_DAC_001_T *pDAC, uint32_t bias);
-
-/**
- * @brief Enables the DMA operation and controls DMA timer
- * @param pDAC : pointer to the DAC peripheral block
- * @param dacFlags : An Or'ed value of the following DAC values:
- * - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature
- * - DAC_CNT_ENA :enable/disable timer out counter
- * - DAC_DMA_ENA :enable/disable DMA access
- * @return Nothing
- * @note Pass an Or'ed value of the DAC flags to enable those options.
- */
-STATIC INLINE void IP_DAC_ConfigDAConverterControl(IP_DAC_001_T *pDAC, uint32_t dacFlags)
-{
- uint32_t temp;
-
- temp = pDAC->CTRL & ~DAC_DACCTRL_MASK;
- pDAC->CTRL = temp | dacFlags;
-}
-
-/**
- * @brief Set reload value for interrupt/DMA counter
- * @param pDAC : pointer to the DAC peripheral block
- * @param time_out : time out to reload for interrupt/DMA counter
- * @return Nothing
- */
-void IP_DAC_SetDMATimeOut(IP_DAC_001_T *pDAC, uint32_t time_out);
-
-/**
- * @brief Get status for interrupt/DMA time out
- * @param pDAC : pointer to the DAC peripheral block
- * @return interrupt/DMA time out status, should be SET or RESET
- */
-IntStatus IP_DAC_GetIntStatus(IP_DAC_001_T *pDAC);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DAC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_001.h
deleted file mode 100644
index 56e4a0242..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_001.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * @brief EEPROM registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EEPROM_001_H_
-#define __EEPROM_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_EEPROM_001 IP: EEPROM register block and driver
- * @ingroup IP_Drivers
- * Supports 4032 byte EEPROM devices.
- * @{
- */
-
-/**
- * @brief EEPROM register block structure
- */
-typedef struct { /* EEPROM Structure */
- __IO uint32_t CMD; /*!< EEPROM command register */
- __IO uint32_t ADDR; /*!< EEPROM address register */
- __O uint32_t WDATA; /*!< EEPROM write data register */
- __I uint32_t RDATA; /*!< EEPROM read data register */
- __IO uint32_t WSTATE; /*!< EEPROM wait state register */
- __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */
- __IO uint32_t PWRDWN; /*!< EEPROM power-down register */
- uint32_t RESERVED0[975];
- __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */
- __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */
- __I uint32_t INTSTAT; /*!< EEPROM interrupt status */
- __I uint32_t INTEN; /*!< EEPROM interrupt enable */
- __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */
- __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */
-} IP_EEPROM_001_T;
-
-#define EEPROM_PAGE_SIZE 64 /*!< EEPROM byes per page */
-#define EEPROM_PAGE_NUM 63 /*!< EEPROM pages */
-
-/*
- * @brief Macro defines for EEPROM command register
- */
-#define EEPROM_CMD_8BITS_READ (0) /*!< EEPROM 8-bit read command */
-#define EEPROM_CMD_16BITS_READ (1) /*!< EEPROM 16-bit read command */
-#define EEPROM_CMD_32BITS_READ (2) /*!< EEPROM 32-bit read command */
-#define EEPROM_CMD_8BITS_WRITE (3) /*!< EEPROM 8-bit write command */
-#define EEPROM_CMD_16BITS_WRITE (4) /*!< EEPROM 16-bit write command */
-#define EEPROM_CMD_32BITS_WRITE (5) /*!< EEPROM 32-bit write command */
-#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */
-#define EEPROM_CMD_RDPREFETCH (1 << 3)/*!< EEPROM read pre-fetch enable */
-
-/*
- * @brief Macro defines for EEPROM power down register
- */
-#define EEPROM_PWRDWN (1 << 0)
-
-/*
- * @brief Macro defines for EEPROM interrupt related registers
- */
-#define EEPROM_INT_ENDOFRW (1 << 26)
-#define EEPROM_INT_ENDOFPROG (1 << 28)
-
-/**
- * @brief EEPROM Mode type definition
- */
-typedef enum IP_EEPROM_RWSIZE {
- EEPROM_RWSIZE_8BITS = 1,
- EEPROM_RWSIZE_16BITS = 2,
- EEPROM_RWSIZE_32BITS = 4
-} IP_EEPROM_RWSIZE_T;
-
-/**
- * @brief Select an EEPROM command
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param cmd : EEPROM command.
- * @return Nothing
- * @note cmd is or-ed bits value of EEPROM_CMD_[8|16|32]BITS_READ/EEPROM_CMD_[8|16|32]BITS_WRITE
- * with EEPROM_CMD_RDPREFETCH flag.
- * Read and erase/program operations are started on the EEPROM device as a side-effect of calling this function.
- * Write operations are started as a side-effect of writing data to data register.
- */
-STATIC INLINE void IP_EEPROM_SetCmd(IP_EEPROM_001_T *pEEPROM, uint32_t cmd)
-{
- pEEPROM->CMD = cmd;
-}
-
-/**
- * @brief Set EEPROM address
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageAddr : Page address.
- * @param pageOffset : Page address.
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetAddr(IP_EEPROM_001_T *pEEPROM, uint32_t pageAddr, uint32_t pageOffset)
-{
- pEEPROM->ADDR = (pageAddr << 6) | pageOffset;
-}
-
-/**
- * @brief Write EEPROM data
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param data : EEPROM data.
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_WriteData(IP_EEPROM_001_T *pEEPROM, uint32_t data)
-{
- pEEPROM->WDATA = data;
-}
-
-/**
- * @brief Read EEPROM data
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return data
- */
-STATIC INLINE uint32_t IP_EEPROM_ReadData(IP_EEPROM_001_T *pEEPROM)
-{
- return pEEPROM->RDATA;
-}
-
-/**
- * @brief Set EEPROM wait state
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param ws : Wait State value.
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetWaitState(IP_EEPROM_001_T *pEEPROM, uint32_t ws)
-{
- pEEPROM->WSTATE = ws;
-}
-
-/**
- * @brief Put EEPROM device in power down mode
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_EnablePowerDown(IP_EEPROM_001_T *pEEPROM)
-{
- pEEPROM->PWRDWN = EEPROM_PWRDWN;
-}
-
-/**
- * @brief Bring EEPROM device out of power down mode
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- * @note Any EEPROM operation has to be suspended for 100us while the EEPROM wakes up.
- */
-STATIC INLINE void IP_EEPROM_DisablePowerDown(IP_EEPROM_001_T *pEEPROM)
-{
- pEEPROM->PWRDWN = 0;
-}
-
-/**
- * @brief Enable EEPROM interrupt
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_EnableInt(IP_EEPROM_001_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTENSET = mask;
-}
-
-/**
- * @brief Disable EEPROM interrupt
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_DisableInt(IP_EEPROM_001_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTENCLR = mask;
-}
-
-/**
- * @brief Get the value of the EEPROM interrupt enable register
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Or-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t IP_EEPROM_GetIntEnable(IP_EEPROM_001_T *pEEPROM)
-{
- return pEEPROM->INTEN;
-}
-
-/**
- * @brief Get EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Or-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t IP_EEPROM_GetIntStatus(IP_EEPROM_001_T *pEEPROM)
-{
- return pEEPROM->INTSTAT;
-}
-
-/**
- * @brief Set EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTSTATSET = mask;
-}
-
-/**
- * @brief Clear EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_ClearIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTSTATCLR = mask;
-}
-
-/**
- * @brief Initializes EEPROM
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param div : clock divide value (pre-minus 1)
- * @return Nothing
- */
-void IP_EEPROM_Init(IP_EEPROM_001_T *pEEPROM, uint32_t div);
-
-/**
- * @brief De-initializes EEPROM
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_DeInit(IP_EEPROM_001_T *pEEPROM)
-{
- /* Enable EEPROM power down mode */
- IP_EEPROM_EnablePowerDown(pEEPROM);
-}
-
-/**
- * @brief Erase data in page register
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-void IP_EEPROM_ErasePageRegister(IP_EEPROM_001_T *pEEPROM);
-
-/**
- * @brief Write data to page register
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)
- * @param pData : buffer that contain data that will be written to buffer
- * @param wsize : The number of bytes in each writting (1/2/4 bytes)
- * @param byteNum : number written data (bytes)
- * @return The bumber of byte written
- * @note The pageOffset must be aligned following selected mode.
- */
-uint32_t IP_EEPROM_WritePageRegister(IP_EEPROM_001_T *pEEPROM, uint16_t pageOffset,
- uint8_t *pData, uint8_t wsize, uint32_t byteNum);
-
-/**
- * @brief Read data from non-volatile memory
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)
- * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )
- * @param pData : buffer that contain data read from read data register
- * @param rsize : The number of bytes in each reading (1/2/4 bytes)
- * @param byteNum : number of read data (bytes)
- * @return The bumber of byte read
- * @note The pageOffset must be aligned following selected mode.
- */
-uint32_t IP_EEPROM_ReadPage(IP_EEPROM_001_T *pEEPROM,
- uint16_t pageOffset,
- uint16_t pageAddr,
- uint8_t *pData,
- uint8_t rsize,
- uint32_t byteNum);
-
-/**
- * @brief Erase/Program an EEPROM page
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageAddr : EEPROM page address (0-62)
- * @return Nothing
- */
-void IP_EEPROM_EraseProgramPage(IP_EEPROM_001_T *pEEPROM, uint16_t pageAddr);
-
-/**
- * @brief Wait for interrupt occurs
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : expected interrupt
- * @return Nothing
- */
-void IP_EEPROM_WaitForIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask);
-
-/**
- * @brief Write data to EEPROM at specific address
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)
- * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )
- * @param pData : buffer that contain data that will be written to buffer
- * @param wsize : Write size:
- * - EEPROM_RWSIZE_8BITS : 8-bit read/write mode
- * - EEPROM_RWSIZE_16BITS : 16-bit read/write mode
- * - EEPROM_RWSIZE_32BITS : 32-bit read/write mode
- * @param byteNum : number written data (bytes)
- * @return SUCCESS on successful write of data, or ERROR
- * @note The pageOffset must be aligned following selected mode.
- * This function actually write data into EEPROM memory and automatically
- * write into next page if current page is overflowed
- */
-Status IP_EEPROM_Write(IP_EEPROM_001_T *pEEPROM,
- uint16_t pageOffset,
- uint16_t pageAddr,
- void *pData,
- IP_EEPROM_RWSIZE_T wsize,
- uint32_t byteNum);
-
-/**
- * @brief Read data to EEPROM at specific address
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)
- * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )
- * @param pData : buffer that contain data read from read data register
- * @param rsize : Read size:
- * - EEPROM_RWSIZE_8BITS : 8-bit read/write mode
- * - EEPROM_RWSIZE_16BITS : 16-bit read/write mode
- * - EEPROM_RWSIZE_32BITS : 32-bit read/write mode
- * @param byteNum : number read data (bytes)
- * @return SUCCESS on successful write of data, or ERROR
- * @note The pageOffset must be aligned following selected mode.
- */
-Status IP_EEPROM_Read(IP_EEPROM_001_T *pEEPROM,
- uint16_t pageOffset,
- uint16_t pageAddr,
- void *pData,
- IP_EEPROM_RWSIZE_T rsize,
- uint32_t byteNum);
-
-/**
- * @brief Erase a page at the specific address
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param pageAddr : EEPROM page address (0-62)
- * @return Nothing
- */
-void IP_EEPROM_Erase(IP_EEPROM_001_T *pEEPROM, uint16_t pageAddr);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EEPROM_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_002.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_002.h
deleted file mode 100644
index 8e46ba2a1..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/eeprom_002.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * @brief EEPROM registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EEPROM_002_H_
-#define __EEPROM_002_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_EEPROM_002 IP: EEPROM register block and driver (002)
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief EEPROM register block structure
- */
-typedef struct { /* EEPROM Structure */
- __IO uint32_t CMD; /*!< EEPROM command register */
- uint32_t RESERVED0;
- __IO uint32_t RWSTATE; /*!< EEPROM read wait state register */
- __IO uint32_t AUTOPROG; /*!< EEPROM auto programming register */
- __IO uint32_t WSTATE; /*!< EEPROM wait state register */
- __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */
- __IO uint32_t PWRDWN; /*!< EEPROM power-down register */
- uint32_t RESERVED2[1007];
- __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */
- __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */
- __I uint32_t INTSTAT; /*!< EEPROM interrupt status */
- __I uint32_t INTEN; /*!< EEPROM interrupt enable */
- __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */
- __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */
-} IP_EEPROM_002_T;
-
-/*
- * @brief Macro defines for EEPROM command register
- */
-#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */
-
-/*
- * @brief Macro defines for EEPROM Auto Programming register
- */
-#define EEPROM_AUTOPROG_OFF (0) /*!CMD = cmd;
-}
-
-/**
- * @brief Set Auto programming mode
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mode : Auto programming Mode (Value of EEPROM_AUTOPROG_).
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetAutoProg(IP_EEPROM_002_T *pEEPROM, uint32_t mode)
-{
- pEEPROM->AUTOPROG = mode;
-}
-
-/**
- * @brief Set EEPROM Read Wait State value
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param ws : Wait State value.
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetReadWaitState(IP_EEPROM_002_T *pEEPROM, uint32_t ws)
-{
- pEEPROM->RWSTATE = ws;
-}
-
-/**
- * @brief Set EEPROM Wait State value
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param ws : Wait State value.
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetWaitState(IP_EEPROM_002_T *pEEPROM, uint32_t ws)
-{
- pEEPROM->WSTATE = ws;
-}
-
-/**
- * @brief Put EEPROM device in power down mode
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_EnablePowerDown(IP_EEPROM_002_T *pEEPROM)
-{
- pEEPROM->PWRDWN = EEPROM_PWRDWN;
-}
-
-/**
- * @brief Bring EEPROM device out of power down mode
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- * @note Any EEPROM operation has to be suspended for 100us while the EEPROM wakes up.
- */
-STATIC INLINE void IP_EEPROM_DisablePowerDown(IP_EEPROM_002_T *pEEPROM)
-{
- pEEPROM->PWRDWN = 0;
-}
-
-/**
- * @brief Enable EEPROM interrupt
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_EnableInt(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTENSET = mask;
-}
-
-/**
- * @brief Disable EEPROM interrupt
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_DisableInt(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTENCLR = mask;
-}
-
-/**
- * @brief Get the value of the EEPROM interrupt enable register
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Or-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t IP_EEPROM_GetIntEnable(IP_EEPROM_002_T *pEEPROM)
-{
- return pEEPROM->INTEN;
-}
-
-/**
- * @brief Get EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Or-ed bits value of EEPROM_INT_*
- */
-STATIC INLINE uint32_t IP_EEPROM_GetIntStatus(IP_EEPROM_002_T *pEEPROM)
-{
- return pEEPROM->INTSTAT;
-}
-
-/**
- * @brief Set EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_SetIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTSTATSET = mask;
-}
-
-/**
- * @brief Clear EEPROM interrupt status
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_ClearIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
-{
- pEEPROM->INTSTATCLR = mask;
-}
-
-/**
- * @brief Initializes EEPROM
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param div : clock divide value (pre-minus 1)
- * @return Nothing
- */
-void IP_EEPROM_Init(IP_EEPROM_002_T *pEEPROM, uint32_t div);
-
-/**
- * @brief De-initializes EEPROM
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-STATIC INLINE void IP_EEPROM_DeInit(IP_EEPROM_002_T *pEEPROM)
-{
- /* Enable EEPROM power down mode */
- IP_EEPROM_EnablePowerDown(pEEPROM);
-}
-
-/**
- * @brief Erase/Program an EEPROM page
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @return Nothing
- */
-void IP_EEPROM_EraseProgramPage(IP_EEPROM_002_T *pEEPROM);
-
-/**
- * @brief Wait for interrupt occurs
- * @param pEEPROM : pointer to EEPROM peripheral block
- * @param mask : expected interrupt
- * @return Nothing
- */
-void IP_EEPROM_WaitForIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EEPROM_002_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/emc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/emc_001.h
deleted file mode 100644
index 785a6c15d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/emc_001.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * @brief EMC Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __EMC_001_H_
-#define __EMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_EMC_001 IP: EMC register block and driver
- * @ingroup IP_Drivers
- * External Memory Controller
- * @{
- */
-
-/**
- * @brief External Memory Controller (EMC) register block structure
- */
-typedef struct { /*!< EMC Structure */
- __IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */
- __I uint32_t STATUS; /*!< Provides EMC status information. */
- __IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */
- __I uint32_t RESERVED0[5];
- __IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */
- __IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */
- __IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */
- __I uint32_t RESERVED1;
- __IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */
- __IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */
- __IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */
- __IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */
- __IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */
- __IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */
- __IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */
- __IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */
- __IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */
- __IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */
- __IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */
- __I uint32_t RESERVED2[9];
- __IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */
- __I uint32_t RESERVED3[31];
- __IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED4[6];
- __IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED5[6];
- __IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED6[6];
- __IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED7[38];
- __IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED8;
- __IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED9;
- __IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED10;
- __IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */
-} IP_EMC_001_T;
-
-/**
- * @brief EMC register support bitfields and mask
- */
-/* Reserve for extending support to ARM9 or nextgen LPC */
-#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */
-
-#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */
-#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */
-
-#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
-#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */
-
-/* Dynamic Memory Configuration Register Bit Definitions */
-#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
-
-#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
-#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
-
-/*!< Memory configuration values in EMC Dynamic Configuration Register */
-#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
-#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
-#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
-#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
-#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
-#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
-#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
-#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
-#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
-#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
-#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
-#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
-#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
-
-/*!< Dynamic Memory Mode Register Bit Definition */
-#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
-
-#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */
-#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */
-
-/*!< CAS Latency in Dynamic Mode Register */
-#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */
-#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */
-#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */
-#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */
-
-/*!< Operation Mode in Dynamic Mode register */
-#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */
-#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */
-
-/*!< Write Burst Mode in Dynamic Mode register */
-#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */
-#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */
-#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */
-
-/*!< Dynamic Memory Control Register Bit Definitions */
-#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */
-
-/*!< Static Memory Configuration Register Bit Definitions */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */
-#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */
-
-#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */
-#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */
-
-#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */
-#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */
-#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */
-
-#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */
-#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */
-#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */
-
-#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */
-#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */
-#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */
-
-/*!< Q24.8 Fixed Point Helper */
-#define Q24_8_FP(x) ((x) * 256)
-#define EMC_NANOSECOND(x) Q24_8_FP(x)
-#define EMC_CLOCK(x) Q24_8_FP(-(x))
-
-/**
- * @brief EMC Dynamic Device Configuration structure used for IP drivers
- */
-typedef struct {
- uint32_t BaseAddr; /*!< Base Address */
- uint8_t RAS; /*!< RAS value */
- uint32_t ModeRegister; /*!< Mode Register value */
- uint32_t DynConfig; /*!< Dynamic Configuration value */
-} IP_EMC_DYN_DEVICE_CONFIG_T;
-
-/**
- * @brief EMC Dynamic Configure Struct
- */
-typedef struct {
- int32_t RefreshPeriod; /*!< Refresh period */
- uint32_t ReadConfig; /*!< Clock*/
- int32_t tRP; /*!< Precharge Command Period */
- int32_t tRAS; /*!< Active to Precharge Command Period */
- int32_t tSREX; /*!< Self Refresh Exit Time */
- int32_t tAPR; /*!< Last Data Out to Active Time */
- int32_t tDAL; /*!< Data In to Active Command Time */
- int32_t tWR; /*!< Write Recovery Time */
- int32_t tRC; /*!< Active to Active Command Period */
- int32_t tRFC; /*!< Auto-refresh Period */
- int32_t tXSR; /*!< Exit Selt Refresh */
- int32_t tRRD; /*!< Active Bank A to Active Bank B Time */
- int32_t tMRD; /*!< Load Mode register command to Active Command */
- IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4]; /*!< Device Configuration array */
-} IP_EMC_DYN_CONFIG_T;
-
-/**
- * @brief EMC Static Configure Structure
- */
-typedef struct {
- uint8_t ChipSelect; /*!< Chip select */
- uint32_t Config; /*!< Configuration value */
- int32_t WaitWen; /*!< Write Enable Wait */
- int32_t WaitOen; /*!< Output Enable Wait */
- int32_t WaitRd; /*!< Read Wait */
- int32_t WaitPage; /*!< Page Access Wait */
- int32_t WaitWr; /*!< Write Wait */
- int32_t WaitTurn; /*!< Turn around wait */
-} IP_EMC_STATIC_CONFIG_T;
-
-/**
- * @brief Initializes the Dynamic Controller
- * @param pEMC : Pointer to EMC peripheral
- * @param Dynamic_Config : Dynamic Memory Configure Struct
- * @param EMC_Clock : Frequency of EMC Clock Out
- * @return None
- * @note Initializes the Dynamic Controller according to the specified parameters
- * in the IP_EMC_DYN_CONFIG_T
- */
-void IP_EMC_Dynamic_Init(IP_EMC_001_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock);
-
-/**
- * @brief Enable Dynamic Memory Controller
- * @param pEMC : Pointer to EMC peripheral
- * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable
- * @return None
- */
-void IP_EMC_Dynamic_Enable(IP_EMC_001_T *pEMC, uint8_t Enable);
-
-/**
- * @brief Initializes the Static Controller according to the specified
- * parameters in the IP_EMC_STATIC_CONFIG_T
- * @param pEMC : Pointer to EMC peripheral
- * @param Static_Config : Static Memory Configure Struct
- * @param EMC_Clock : Frequency of EMC Clock Out
- * @return None
- */
-void IP_EMC_Static_Init(IP_EMC_001_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock);
-
-/**
- * @brief Mirror CS1 to CS0 and DYCS0
- * @param pEMC : Pointer to EMC peripheral
- * @param Enable : 1 = Mirror, 0 = Normal Memory Map
- * @return None
- */
-void IP_EMC_Mirror(IP_EMC_001_T *pEMC, uint32_t Enable);
-
-/**
- * @brief Enable EMC
- * @param pEMC : Pointer to EMC peripheral
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- */
-void IP_EMC_Enable(IP_EMC_001_T *pEMC, uint32_t Enable);
-
-/**
- * @brief Set EMC LowPower Mode
- * @param pEMC : Pointer to EMC peripheral
- * @param Enable : 1 = Enable, 0 = Disable
- * @return None
- * @note This function should only be called when the memory
- * controller is not busy (bit 0 of the status register is not set).
- */
-void IP_EMC_LowPowerMode(IP_EMC_001_T *pEMC, uint32_t Enable);
-
-/**
- * @brief Initialize EMC
- * @param pEMC : Pointer to EMC peripheral
- * @param Enable : 1 = Enable, 0 = Disable
- * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2
- * @param EndianMode : Endian Mode, 0 = Little, 1 = Big
- * @return None
- */
-void IP_EMC_Init(IP_EMC_001_T *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
-
-/**
- * @brief Set Static Memory Extended Wait in Clock
- * @param pEMC : Pointer to EMC peripheral
- * @param Wait16Clks : Number of '16 clock' delay cycles
- * @return None
- */
-void IP_EMC_SetStaticExtendedWait(IP_EMC_001_T *pEMC, uint32_t Wait16Clks);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __EMC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/enet_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/enet_001.h
deleted file mode 100644
index 569940673..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/enet_001.h
+++ /dev/null
@@ -1,634 +0,0 @@
-/*
- * @brief Ethernet control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __ENET_001_H_
-#define __ENET_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_ENET_001 IP: Ethernet register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief 10/100 MII & RMII Ethernet with timestamping register block structure
- */
-typedef struct { /*!< ETHERNET Structure */
- __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */
- __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */
- __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */
- __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */
- __IO uint32_t MAC_MII_ADDR; /*!< MII address register */
- __IO uint32_t MAC_MII_DATA; /*!< MII data register */
- __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */
- __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */
- __I uint32_t RESERVED0;
- __I uint32_t MAC_DEBUG; /*!< Debug register */
- __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */
- __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */
- __I uint32_t RESERVED1[2];
- __I uint32_t MAC_INTR; /*!< Interrupt status register */
- __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */
- __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */
- __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */
- __I uint32_t RESERVED2[430];
- __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */
- __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */
- __I uint32_t SECONDS; /*!< System time seconds register */
- __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */
- __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */
- __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */
- __IO uint32_t ADDEND; /*!< Time stamp addend register */
- __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */
- __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */
- __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */
- __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */
- __IO uint32_t PPSCTRL; /*!< PPS control register */
- __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */
- __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */
- __I uint32_t RESERVED3[562];
- __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */
- __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */
- __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */
- __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */
- __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */
- __IO uint32_t DMA_STAT; /*!< Status register */
- __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */
- __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */
- __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */
- __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */
- __I uint32_t RESERVED4[8];
- __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */
- __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */
- __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */
- __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */
-} IP_ENET_001_T;
-
-/**
- * @brief MAC_CONFIG register bit defines
- */
-#define MAC_CFG_RE (1 << 2) /*!< Receiver enable */
-#define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */
-#define MAC_CFG_DF (1 << 4) /*!< Deferral Check */
-#define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */
-#define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */
-#define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */
-#define MAC_CFG_DR (1 << 9) /*!< Disable Retry */
-#define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */
-#define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */
-#define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */
-#define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */
-#define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */
-#define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */
-#define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */
-#define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */
-#define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */
-#define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */
-#define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */
-
-/**
- * @brief MAC_FRAME_FILTER register bit defines
- */
-#define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */
-#define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */
-#define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */
-#define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */
-#define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */
-#define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */
-#define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */
-#define MAC_FF_RA (1UL << 31) /*!< Receive all */
-
-/**
- * @brief MAC_MII_ADDR register bit defines
- */
-#define MAC_MIIA_GB (1 << 0) /*!< MII busy */
-#define MAC_MIIA_W (1 << 1) /*!< MII write */
-#define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */
-#define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */
-#define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */
-
-/**
- * @brief MAC_MII_DATA register bit defines
- */
-#define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */
-
-/**
- * @brief MAC_FLOW_CONTROL register bit defines
- */
-#define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */
-#define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */
-#define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */
-#define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */
-#define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */
-#define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */
-#define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */
-
-/**
- * @brief MAC_VLAN_TAG register bit defines
- */
-#define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */
-#define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */
-
-/**
- * @brief MAC_PMT_CTRL_STAT register bit defines
- */
-#define MAC_PMT_PD (1 << 0) /*!< Power-down */
-#define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */
-#define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */
-#define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */
-#define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */
-#define MAC_PMT_GU (1 << 9) /*!< Global Unicast */
-#define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */
-
-/**
- * @brief MAC_INTR_MASK register bit defines
- */
-#define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */
-
-/**
- * @brief MAC_ADDR0_HIGH register bit defines
- */
-#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
-
-/**
- * @brief MAC_ADDR0_HIGH register bit defines
- */
-#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */
-
-/**
- * @brief MAC_TIMESTAMP register bit defines
- */
-#define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */
-#define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */
-#define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */
-#define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */
-#define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */
-#define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */
-#define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */
-#define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */
-#define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */
-#define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */
-#define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */
-#define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */
-#define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */
-#define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */
-#define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */
-#define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */
-
-/**
- * @brief DMA_BUS_MODE register bit defines
- */
-#define DMA_BM_SWR (1 << 0) /*!< Software reset */
-#define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */
-#define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */
-#define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */
-#define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */
-#define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */
-#define DMA_BM_FB (1 << 16) /*!< Fixed burst */
-#define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */
-#define DMA_BM_USP (1 << 23) /*!< Use separate PBL */
-#define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */
-#define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */
-#define DMA_BM_MB (1 << 26) /*!< Mixed burst */
-#define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */
-
-/**
- * @brief DMA_STAT register bit defines
- */
-#define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */
-#define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */
-#define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */
-#define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */
-#define DMA_ST_OVF (1 << 4) /*!< Receive overflow */
-#define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */
-#define DMA_ST_RI (1 << 6) /*!< Receive interrupt */
-#define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */
-#define DMA_ST_RPS (1 << 8) /*!< Received process stopped */
-#define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */
-#define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */
-#define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */
-#define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */
-#define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */
-#define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */
-#define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */
-
-/**
- * @brief DMA_OP_MODE register bit defines
- */
-#define DMA_OM_SR (1 << 1) /*!< Start/stop receive */
-#define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */
-#define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */
-#define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */
-#define DMA_OM_FEF (1 << 7) /*!< Forward error frames */
-#define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */
-#define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */
-#define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */
-#define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */
-#define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */
-#define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */
-#define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */
-
-/**
- * @brief DMA_INT_EN register bit defines
- */
-#define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */
-#define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */
-#define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */
-#define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */
-#define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */
-#define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */
-#define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */
-#define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */
-#define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */
-#define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */
-#define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */
-#define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */
-#define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */
-#define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */
-#define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */
-
-/**
- * @brief DMA_MFRM_BUFOF register bit defines
- */
-#define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */
-#define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */
-#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */
-#define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */
-
-/**
- * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines
- */
-#define TDES_DB (1 << 0) /*!< Deferred Bit */
-#define TDES_UF (1 << 1) /*!< Underflow Error */
-#define TDES_ED (1 << 2) /*!< Excessive Deferral */
-#define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */
-#define TDES_VF (1 << 7) /*!< VLAN Frame */
-#define TDES_EC (1 << 8) /*!< Excessive Collision */
-#define TDES_LC (1 << 9) /*!< Late Collision */
-#define TDES_NC (1 << 10) /*!< No Carrier */
-#define TDES_LCAR (1 << 11) /*!< Loss of Carrier */
-#define TDES_IPE (1 << 12) /*!< IP Payload Error */
-#define TDES_FF (1 << 13) /*!< Frame Flushed */
-#define TDES_JT (1 << 14) /*!< Jabber Timeout */
-#define TDES_ES (1 << 15) /*!< Error Summary */
-#define TDES_IHE (1 << 16) /*!< IP Header Error */
-#define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */
-#define TDES_OWN (1UL << 31) /*!< Own Bit */
-
-/**
- * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines
- */
-#define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */
-#define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */
-#define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */
-#define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */
-#define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */
-#define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */
-#define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */
-#define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */
-#define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */
-
-/**
- * @brief TRAN_DESC_T only BSIZE field bit defines
- */
-#define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */
-#define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */
-#define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */
-#define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */
-#define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */
-#define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */
-#define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */
-#define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */
-#define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */
-#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
-#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
-
-/**
- * @brief TRAN_DESC_ENH_T only BSIZE field bit defines
- */
-#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
-#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
-
-/**
- * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines
- */
-#define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */
-#define RDES_CE (1 << 1) /*!< CRC Error */
-#define RDES_DRE (1 << 2) /*!< Dribble Bit Error */
-#define RDES_RE (1 << 3) /*!< Receive Error */
-#define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */
-#define RDES_FT (1 << 5) /*!< Frame Type */
-#define RDES_LC (1 << 6) /*!< Late Collision */
-#define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */
-#define RDES_LS (1 << 8) /*!< Last Descriptor */
-#define RDES_FS (1 << 9) /*!< First Descriptor */
-#define RDES_VLAN (1 << 10) /*!< VLAN Tag */
-#define RDES_OE (1 << 11) /*!< Overflow Error */
-#define RDES_LE (1 << 12) /*!< Length Error */
-#define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */
-#define RDES_DE (1 << 14) /*!< Descriptor Error */
-#define RDES_ES (1 << 15) /*!< ES: Error Summary */
-#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */
-#define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */
-#define RDES_OWN (1UL << 31) /*!< Own Bit */
-
-/**
- * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines
- */
-#define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */
-
-/**
- * @brief REC_DESC_T pnly CTRL field bit defines
- */
-#define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */
-#define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */
-#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */
-#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */
-
-/**
- * @brief REC_DESC_ENH_T only CTRL field bit defines
- */
-#define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */
-#define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */
-#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */
-#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */
-
-/**
- * @brief REC_DESC_ENH_T only EXTSTAT field bit defines
- */
-#define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */
-#define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */
-#define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */
-#define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */
-#define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */
-#define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */
-#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */
-
-/**
- * @brief Maximum size of an ethernet buffer
- */
-#define EMAC_ETH_MAX_FLEN (1536)
-
-/**
- * @brief Structure of a transmit descriptor (without timestamp)
- */
-typedef struct {
- __IO uint32_t CTRLSTAT; /*!< TDES control and status word */
- __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
- __IO uint32_t B1ADD; /*!< Buffer 1 address */
- __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
-} IP_ENET_001_TXDESC_T;
-
-/**
- * @brief Structure of a enhanced transmit descriptor (with timestamp)
- */
-typedef struct {
- __IO uint32_t CTRLSTAT; /*!< TDES control and status word */
- __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */
- __IO uint32_t B1ADD; /*!< Buffer 1 address */
- __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
- __IO uint32_t TDES4; /*!< Reserved */
- __IO uint32_t TDES5; /*!< Reserved */
- __IO uint32_t TTSL; /*!< Timestamp value low */
- __IO uint32_t TTSH; /*!< Timestamp value high */
-} IP_ENET_001_ENHTXDESC_T;
-
-/**
- * @brief Structure of a receive descriptor (without timestamp)
- */
-typedef struct {
- __IO uint32_t STATUS; /*!< RDES status word */
- __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */
- __IO uint32_t B1ADD; /*!< Buffer 1 address */
- __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
-} IP_ENET_001_RXDESC_T;
-
-/**
- * @brief Structure of a enhanced receive descriptor (with timestamp)
- */
-typedef struct {
- __IO uint32_t STATUS; /*!< RDES status word */
- __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */
- __IO uint32_t B1ADD; /*!< Buffer 1 address */
- __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */
- __IO uint32_t EXTSTAT; /*!< Extended Status */
- __IO uint32_t RDES5; /*!< Reserved */
- __IO uint32_t RTSL; /*!< Timestamp value low */
- __IO uint32_t RTSH; /*!< Timestamp value high */
-} IP_ENET_001_ENHRXDESC_T;
-
-/**
- * @brief Resets the ethernet interface
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- * @note Resets the ethernet interface. This should be called prior to
- * IP_ENET_Init with a small delay after this call.
- */
-void IP_ENET_Reset(IP_ENET_001_T *pENET);
-
-/**
- * @brief Sets the address of the interface
- * @param pENET : Pointer to selected ENET peripheral
- * @param macAddr : Pointer to the 6 bytes used for the MAC address
- * @return Nothing
- */
-void IP_ENET_SetADDR(IP_ENET_001_T *pENET, const uint8_t *macAddr);
-
-/**
- * @brief Initialize ethernet interface
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- * @note Performs basic initialization of the ethernet interface in a default
- * state. This is enough to place the interface in a usable state, but
- * may require more setup outside this function.
- */
-void IP_ENET_Init(IP_ENET_001_T *pENET);
-
-/**
- * @brief Sets up the PHY link clock divider and PHY address
- * @param pENET : Pointer to selected ENET peripheral
- * @param div : Divider value, may vary per chip
- * @param addr : PHY address, used with MII read and write
- * @return Nothing
- */
-void IP_ENET_SetupMII(IP_ENET_001_T *pENET, uint32_t div, uint8_t addr);
-
-/**
- * @brief De-initialize the ethernet interface
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-void IP_ENET_DeInit(IP_ENET_001_T *pENET);
-
-/**
- * @brief Starts a PHY write via the MII
- * @param pENET : Pointer to selected ENET peripheral
- * @param reg : PHY register to write
- * @param data : Data to write to PHY register
- * @return Nothing
- * @note Start a PHY write operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when write is complete.
- */
-void IP_ENET_StartMIIWrite(IP_ENET_001_T *pENET, uint8_t reg, uint16_t data);
-
-/**
- * @brief Starts a PHY read via the MII
- * @param pENET : Pointer to selected ENET peripheral
- * @param reg : PHY register to read
- * @return Nothing
- * @note Start a PHY read operation. Does not block, requires calling
- * IP_ENET_IsMIIBusy to determine when read is complete and calling
- * IP_ENET_ReadMIIData to get the data.
- */
-void IP_ENET_StartMIIRead(IP_ENET_001_T *pENET, uint8_t reg);
-
-/**
- * @brief Returns MII link (PHY) busy status
- * @param pENET : Pointer to selected ENET peripheral
- * @return Returns true if busy, otherwise false
- */
-bool IP_ENET_IsMIIBusy(IP_ENET_001_T *pENET);
-
-/**
- * @brief Returns the value read from the PHY
- * @param pENET : Pointer to selected ENET peripheral
- * @return Read value from PHY
- */
-STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_T *pENET)
-{
- return pENET->MAC_MII_DATA;
-}
-
-/**
- * @brief Enables ethernet transmit
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_TXEnable(IP_ENET_001_T *pENET)
-{
- pENET->MAC_CONFIG |= MAC_CFG_TE;
- pENET->DMA_OP_MODE |= DMA_OM_ST;
-}
-
-/**
- * @brief Disables ethernet transmit
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_TXDisable(IP_ENET_001_T *pENET)
-{
- pENET->MAC_CONFIG &= ~MAC_CFG_TE;
-}
-
-/**
- * @brief Enables ethernet packet reception
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_RXEnable(IP_ENET_001_T *pENET)
-{
- pENET->MAC_CONFIG |= MAC_CFG_RE;
- pENET->DMA_OP_MODE |= DMA_OM_SR;
-}
-
-/**
- * @brief Disables ethernet packet reception
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_RXDisable(IP_ENET_001_T *pENET)
-{
- pENET->MAC_CONFIG &= ~MAC_CFG_RE;
-}
-
-/**
- * @brief Sets full or half duplex for the interface
- * @param pENET : Pointer to selected ENET peripheral
- * @param full : true to selected full duplex, false for half
- * @return Nothing
- */
-void IP_ENET_SetDuplex(IP_ENET_001_T *pENET, bool full);
-
-/**
- * @brief Sets speed for the interface
- * @param pENET : Pointer to selected ENET peripheral
- * @param speed100 : true to select 100Mbps mode, false for 10Mbps
- * @return Nothing
- */
-void IP_ENET_SetSpeed(IP_ENET_001_T *pENET, bool speed100);
-
-/**
- * @brief Configures the initial ethernet descriptors
- * @param pENET : Pointer to selected ENET peripheral
- * @param pTXDescs : Pointer to TX descriptor list
- * @param pRXDescs : Pointer to RX descriptor list
- * @return Nothing
- */
-void IP_ENET_InitDescriptors(IP_ENET_001_T *pENET,
- IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs);
-
-/**
- * @brief Starts receive polling of RX descriptors
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_T *pENET)
-{
- /* Start receive polling */
- pENET->DMA_REC_POLL_DEMAND = 1;
-}
-
-/**
- * @brief Starts transmit polling of TX descriptors
- * @param pENET : Pointer to selected ENET peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_T *pENET)
-{
- /* Start transmit polling */
- pENET->DMA_TRANS_POLL_DEMAND = 1;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ENET_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/flash_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/flash_001.h
deleted file mode 100644
index eb23e7938..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/flash_001.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * @brief Flash/EEPROM programming
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __FLASH_EEPROM_001_H
-#define __FLASH_EEPROM_001_H
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_FLASH_EEPROM_001 IP: Flash/EEPROM programming
- * @ingroup IP_Drivers
- * @{
- */
-
-#if defined(CHIP_LPC1347)
-#define ERASE_PAGE_SUPPORT
-#define EEPROM_RW_SUPPORT
-#endif
-
-/** The maximum number of flash programing parameters */
-#define FLASH_PARAMETER_NUM (5)
-
-/** The maximum number of flash programing results */
-#define FLASH_RESULT_NUM (4)
-
-/** Flash programming function type */
-typedef void (*FLASH_ENTRY_T)(unsigned int[], unsigned int[]);
-
-/**
- * @brief Flash command code definitions
- */
-typedef enum {
- FLASH_PREPARE = 50, /*!< Prepare sector(s) for write operation */
- FLASH_COPY_RAM_TO_FLASH = 51, /*!< Copy RAM to Flash */
- FLASH_ERASE = 52, /*!< Erase sector(s) */
- FLASH_BLANK_CHECK = 53, /*!< Blank check sector(s) */
- FLASH_READ_PART_ID = 54, /*!< Read chip part ID */
- FLASH_READ_BOOT_VER = 55, /*!< Read chip boot code version */
- FLASH_COMPARE = 56, /*!< Compare memory areas */
- FLASH_REINVOKE_ISP = 57, /*!< Reinvoke ISP */
- FLASH_READ_UID = 58, /*!< Read UID */
-#if defined(ERASE_PAGE_SUPPORT)
- FLASH_ERASE_PAGE = 59, /*!< Erase page */
-#endif
-#if defined(EEPROM_RW_SUPPORT)
- FLASH_EEPROM_WRITE = 61, /*!< EEPROM Write */
- FLASH_EEPROM_READ = 62, /*!< EEPROM Read */
-#endif
-} FLASH_CMD_CODE_T;
-
-/**
- * @brief Flash status code definitions
- */
-typedef enum {
- CMD_SUCCESS, /*!< Command is executed successfully. */
- INVALID_COMMAND, /*!< Invalid command. */
- SRC_ADDR_ERROR, /*!< Source address is not on a word boundary. */
- DST_ADDR_ERROR, /*!< Destination address is not on a correct boundary. */
- SRC_ADDR_NOT_MAPPED, /*!< Source address is not mapped in the memory map. */
- DST_ADDR_NOT_MAPPED, /*!< Destination address is not mapped in the memory map. */
- COUNT_ERROR, /*!< Byte count is not multiple of 4 or is not a permitted value. */
- INVALID_SECTOR, /*!< Sector number is invalid. */
- SECTOR_NOT_BLANK, /*!< Sector is not blank. */
- SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, /*!< Command to prepare sector for write operation was not executed. */
- COMPARE_ERROR, /*!< Source and destination data is not same. */
- BUSY, /*!< Flash programming hardware interface is busy. */
-} FLASH_STATUS_CODE_T;
-
-/**
- * @brief Command parameter table structure
- */
-typedef struct {
- uint32_t cmd; /*!< Command code */
- uint32_t pParams[FLASH_PARAMETER_NUM]; /*!< Parameters*/
-} FLASH_COMMAND_T;
-
-/**
- * @brief Command result table structure
- */
-typedef struct {
- uint32_t status; /*!< Status code */
- uint32_t pResult[FLASH_RESULT_NUM]; /*!< Results*/
-} FLASH_OUTPUT_T;
-
-/* Flash Programming Command Description
- Command Parameters Return Code Result
- ----------------------------------------------------------------------------------------------------------
- FLASH_PREPARE Start Sector Number CMD_SUCCESS None
- End Sector Number BUSY
- INVALID_SECTOR
- FLASH_COPY_RAM2FLASH Destination Flash Addr CMD_SUCCESS None
- Source RAM Addr SRC_ADDR_ERROR
- Number of bytes written SRC_ADDR_NOT_MAPPED
- CCLK in kHz DST_ADDR_NOT_MAPPED
- COUNT_ERROR
- SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
- BUSY
- FLASH_ERASE Start Sector Number CMD_SUCCESS None
- Emd Sector Number BUSY
- CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
- INVALID_SECTOR
- FLASH_BLANK_CHECK Start Sector Number CMD_SUCCESS Non Blank Sector Offset(if Status code is SECTOR_NOT_BLANK)
- End Sector Number BUSY Content of non blank word location
- SECTOR_NOT_BLANK
- INVALID_SECTOR
- FLASH_READ_PART_ID None CMD_SUCCESS Part ID
- FLASH_READ_BOOT_VER None CMD_SUCCESS .
- FLASH_COMPARE Destination Addr CMD_SUCCESS Offset of the first mismatch
- Source Address COMPARE_ERROR
- Number of bytes compared COUNT_ERROR
- ADDR_ERROR
- ADDR_NOT_MAPPED
- FLASH_REINVOKE_ISP None None None
- FLASH_READ_UID None CMD_SUCCESS The first 32-bit word
- The second 32-bit word.
- The third 32-bit word.
- The fourth 32-bit word
- FLASH_ERASE_PAGE Start Page Number CMD_SUCCESS None
- End Page Number BUSY
- CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
- INVALID_SECTOR
- FLASH_EEPROM_WRITE EEPROM Addr CMD_SUCCESS None
- RAM Addr SRC_ADDR_NOT_MAPPED
- Number of bytes written DST_ADDR_NOT_MAPPED
- CCLK in kHz
- FLASH_EEPROM_READ EEPROM Addr CMD_SUCCESS None
- RAM Addr SRC_ADDR_NOT_MAPPED
- Number of bytes read DST_ADDR_NOT_MAPPED
- CCLK in kHz
- */
-
-/**
- * @brief Execute flash programming command
- * @param entry : Flash Programing entry
- * @param pCommand : Command information
- * @param pOutput : Output information
- * @return Nothing
- */
-STATIC INLINE void IP_FLASH_Execute(FLASH_ENTRY_T entry, FLASH_COMMAND_T *pCommand, FLASH_OUTPUT_T *pOutput)
-{
- (entry) ((unsigned int *) pCommand, (unsigned int *) pOutput);
-}
-
-/**
- * @brief [Prepare sectors] command parameter table structure
- */
-typedef struct {
- uint32_t cmd; /*!< Command code */
- uint32_t start; /*!< Start Sector Number */
- uint32_t end; /*!B[Port][Bit] = Setting;
-}
-
-/**
- * @brief Set a GPIO direction
- * @param pGPIO : The Base Address of the GPIO block
- * @param Port : GPIO port to set
- * @param Bit : GPIO bit to set
- * @param Setting : true for output, false for input
- * @return Nothing
- */
-STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit, bool Setting)
-{
- if (Setting) {
- pGPIO->DIR[Port] |= 1UL << Bit;
- }
- else {
- pGPIO->DIR[Port] &= ~(1UL << Bit);
- }
-}
-
-/**
- * @brief Read a GPIO state
- * @param pGPIO : The Base Address of the GPIO block
- * @param Port : GPIO port to read
- * @param Bit : GPIO bit to read
- * @return true of the GPIO is high, false if low
- */
-STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit)
-{
- return (bool) pGPIO->B[Port][Bit];
-}
-
-/**
- * @brief Read a GPIO direction (out or in)
- * @param pGPIO : The Base Address of the GPIO block
- * @param Port : GPIO port to read
- * @param Bit : GPIO bit to read
- * @return true of the GPIO is an output, false if input
- */
-STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit)
-{
- return (bool) (((pGPIO->DIR[Port]) >> Bit) & 1);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpio_003.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpio_003.h
deleted file mode 100644
index d49ca0759..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpio_003.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * @brief GPIO Registers and Functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIO_003_H_
-#define __GPIO_003_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIO_003 IP: GPIO register block and driver (003)
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO port register block structure
- */
-typedef struct { /*!< GPIO_PORT Structure */
- __IO uint32_t DATA[4096]; /*!< Offset: 0x0000 to 0x3FFC Data address masking register (R/W) */
- uint32_t RESERVED1[4096];
- __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction register (R/W) */
- __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense register (R/W) */
- __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges register (R/W) */
- __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event register (R/W) */
- __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask register (R/W) */
- __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status register (R/ ) */
- __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status register (R/ ) */
- __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear register (W) */
-} IP_GPIO_003_T;
-
-/**
- * @brief Initialize GPIO block
- * @param pGPIO : the base address of the GPIO block
- * @return Nothing
- */
-STATIC INLINE void IP_GPIO_Init(IP_GPIO_003_T *pGPIO)
-{}
-
-/**
- * @brief Write data to port
- * @param pGPIO : the base address of the GPIO block
- * @param mask : determines which pins will be written. bits [11:0] address pins PIOn.0~PIOn.11.
- * If bit's value is 1, the state of the relevant pin is updated. Otherwise, it is unchanged.
- * @param val : bit values.
- * @return Nothing
- * @note mask is in range 0~4095.
- */
-STATIC INLINE void IP_GPIO_WritePort(IP_GPIO_003_T *pGPIO, uint16_t mask, uint16_t val)
-{
- pGPIO->DATA[mask] = val;
-}
-
-/**
- * @brief Set state of pin
- * @param pGPIO : the base address of the GPIO block
- * @param pin : pin number (0-11)
- * @param val : true for high, false for low
- * @return Nothing
- */
-STATIC INLINE void IP_GPIO_WritePortBit(IP_GPIO_003_T *pGPIO, uint8_t pin, bool val)
-{
- pGPIO->DATA[1 << pin] = val << pin;
-}
-
-/**
- * @brief Read port state
- * @param pGPIO : the base address of the GPIO block
- * @return Port value. A 1-bit indicate the relevant pins is high.
- */
-STATIC INLINE uint32_t IP_GPIO_ReadPort(IP_GPIO_003_T *pGPIO)
-{
- return pGPIO->DATA[4095];
-}
-
-/**
- * @brief Read pin state
- * @param pGPIO : the base address of the GPIO block
- * @param pin : pin number (0-11)
- * @return true of the GPIO is high, false if low
- */
-STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_003_T *pGPIO, uint8_t pin)
-{
- return (bool) ((pGPIO->DATA[1 << pin] >> pin) & 1);
-}
-
-/**
- * @brief Set GPIO direction for a pin
- * @param pGPIO : the base address of the GPIO block
- * @param pin : pin number (0-11)
- * @param dir : true for output, false for input
- * @return Nothing
- */
-STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_003_T *pGPIO, uint8_t pin, bool dir)
-{
- if (dir) {
- pGPIO->DIR |= 1UL << pin;
- }
- else {
- pGPIO->DIR &= ~(1UL << pin);
- }
-}
-
-/**
- * @brief Set GPIO direction for a port
- * @param pGPIO : the base address of the GPIO block
- * @param bitVal : bit value
- * @param dir : true for output, false for input
- * @return Nothing
- */
-STATIC INLINE void IP_GPIO_SetDir(IP_GPIO_003_T *pGPIO, uint32_t bitVal, bool dir)
-{
- if (dir) {
- pGPIO->DIR |= bitVal;
- }
- else {
- pGPIO->DIR &= ~bitVal;
- }
-}
-
-/**
- * @brief Read a GPIO direction (out or in)
- * @param pGPIO : the base address of the GPIO block
- * @param pin : pin number (0-11)
- * @return true of the GPIO is an output, false if input
- */
-STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_003_T *pGPIO, uint8_t pin)
-{
- return (bool) (((pGPIO->DIR) >> pin) & 1);
-}
-
-typedef enum {
- GPIOPININT_FALLING_EDGE = 0, /*!RIS) >> pin) & 0x01);
-}
-
-/**
- * @brief Clear GPIO Interrupt (Edge interrupt cases only)
- * @param pGPIO : pointer to GPIO interrupt register block
- * @param pin : pin number
- * @return None
- */
-STATIC INLINE void IP_GPIO_IntClear(IP_GPIO_003_T *pGPIO, uint8_t pin)
-{
- pGPIO->IC |= (1 << pin);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIO_003_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiogrpint_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiogrpint_001.h
deleted file mode 100644
index ba3e0d650..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiogrpint_001.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * @brief GPIO Group Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOGRPINT_001_H_
-#define __GPIOGRPINT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOGRPINT_001 IP: GPIO Grouped Interrupts register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO grouped interrupt register block structure
- */
-typedef struct { /*!< GPIO_GROUP_INTn Structure */
- __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
- __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
-} IP_GPIOGROUPINT_001_T;
-
-/**
- * @brief GPIO Group Interrupt Pin Initialization
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)
- * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)
- * @return None
- */
-STATIC INLINE void IP_GPIOGP_IntInit(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)
-{
- pGPIOGPINT->CTRL = ((PortTrigger & 0x1) << 2) | ((PortComb & 0x1) << 1);
-}
-
-/**
- * @brief GPIO Group Interrupt Pin Add to Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)
- * @return None
- */
-void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode);
-
-/**
- * @brief GPIO Group Interrupt Pin Remove from Group
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @param PortNum : GPIO port number, should be 0 to 7
- * @param PinNum : GPIO pin number, should be 0 to 31
- * @return None
- */
-STATIC INLINE void IP_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)
-{
- /* configure to PORT_ENA register */
- pGPIOGPINT->PORT_ENA[PortNum] &= ~(1 << PinNum);
-}
-
-/**
- * @brief Get GPIO Group Interrupt Get Status
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool IP_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_T *pGPIOGPINT)
-{
- return (bool) (pGPIOGPINT->CTRL & 0x01);
-}
-
-/**
- * @brief Clear GPIO Group Interrupt
- * @param pGPIOGPINT : Pointer to GPIOIR register block
- * @return None
- */
-STATIC INLINE void IP_GPIOGP_IntClear(IP_GPIOGROUPINT_001_T *pGPIOGPINT)
-{
- pGPIOGPINT->CTRL |= 0x01;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOGRPINT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpioint_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpioint_001.h
deleted file mode 100644
index 303466816..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpioint_001.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * @brief GPIO Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOINT_001_H_
-#define __GPIOINT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOINT_001 IP: GPIO Interrupt register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO Interrupt register block structure
- */
-typedef struct {
- __I uint32_t Status; /*!< GPIO overall Interrupt Status Register */
- __I uint32_t StatR0; /*!< GPIO Interrupt Status Register 0 for Rising edge */
- __I uint32_t StatF0; /*!< GPIO Interrupt Status Register 0 for Falling edge */
- __O uint32_t Clr0; /*!< GPIO Interrupt Clear Register 0 */
- __IO uint32_t EnR0; /*!< GPIO Interrupt Enable Register 0 for Rising edge */
- __IO uint32_t EnF0; /*!< GPIO Interrupt Enable Register 0 for Falling edge */
- uint32_t RESERVED0[3];
- __I uint32_t StatR2; /*!< GPIO Interrupt Status Register 2 for Rising edge */
- __I uint32_t StatF2; /*!< GPIO Interrupt Status Register 2 for Falling edge */
- __O uint32_t Clr2; /*!< GPIO Interrupt Clear Register 2 */
- __IO uint32_t EnR2; /*!< GPIO Interrupt Enable Register 2 for Rising edge */
- __IO uint32_t EnF2; /*!< GPIO Interrupt Enable Register 2 for Falling edge */
-} IP_GPIOINT_001_T;
-
-typedef enum IP_GPIOPININT_MODE {
- GPIOPININT_RISING_EDGE = 0x01,
- GPIOPININT_FALLING_EDGE = 0x02
-} IP_GPIOPININT_MODE_T;
-
-/**
- * @brief Enable GPIO Interrupt
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF
- * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge
- * @return None
- */
-void IP_GPIOINT_IntCmd(IP_GPIOINT_001_T *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, IP_GPIOPININT_MODE_T IntMode);
-
-/**
- * @brief Get GPIO Interrupt Status
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param PinNum : Pin number, should be: 0..30(with port 0) and 0..13 (with port 2)
- * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge
- * @return true if interrupt is pending, otherwise false
- */
-bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_T *pGPIOPININT,
- uint8_t PortNum,
- uint32_t PinNum,
- IP_GPIOPININT_MODE_T IntMode);
-
-/**
- * @brief Clear GPIO Interrupt (Edge interrupt cases only)
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)
- * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF
- * @return None
- */
-void IP_GPIOINT_IntClear(IP_GPIOINT_001_T *pGPIOPININT, uint8_t PortNum, uint32_t BitValue);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOINT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiopinint_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiopinint_001.h
deleted file mode 100644
index 041b5f640..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/gpiopinint_001.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * @brief GPIO Pin Interrupt Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __GPIOPININT_001_H_
-#define __GPIOPININT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_GPIOPININT_001 IP: GPIO Pin Interrupt register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief GPIO pin interrupt register block structure
- */
-typedef struct { /*!< GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
- __O uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
- __O uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< Pin Interrupt Status register */
-} IP_GPIOPININT_001_T;
-
-typedef enum IP_GPIOPININT_MODE {
- GPIOPININT_RISING_EDGE = 0x01,
- GPIOPININT_FALLING_EDGE = 0x02,
- GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
- GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
-} IP_GPIOPININT_MODE_T;
-
-/**
- * @brief Enable GPIO Interrupt
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt
- * @param IntMode : Interrupt mode, should be:
- * 0: Rising edge interrupt mode
- * 1: Falling edge interrupt mode
- * 2: Active-High interrupt mode
- * 3: Active-Low interrupt mode
- * @return None
- */
-void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum, IP_GPIOPININT_MODE_T IntMode);
-
-/**
- * @brief Get GPIO Interrupt Status
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt
- * @return true if interrupt is pending, otherwise false
- */
-STATIC INLINE bool IP_GPIOPININT_IntGetStatus(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum)
-{
- return (bool) (((pGPIOPININT->IST) >> PortNum) & 0x01);
-}
-
-/**
- * @brief Clear GPIO Interrupt (Edge interrupt cases only)
- * @param pGPIOPININT : Pointer to GPIO interrupt register block
- * @param PortNum : GPIO port number interrupt
- * @return None
- */
-STATIC INLINE void IP_GPIOPININT_IntClear(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum)
-{
- if (!(pGPIOPININT->ISEL & (1 << PortNum))) {
- pGPIOPININT->IST |= (1 << PortNum);
- }
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GPIOPININT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2c_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2c_001.h
deleted file mode 100644
index 5e36f5532..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2c_001.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * @brief I2C registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2C_001_H_
-#define __I2C_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_I2C_001 IP: I2C register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief I2C register block structure
- */
-typedef struct { /* I2C0 Structure */
- __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
- __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
- __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
- __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
- __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
- __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
- __IO uint32_t MASK[4]; /*!< I2C Slave address mask register */
-} IP_I2C_001_T;
-
-/**
- * @brief Return values for SLAVE handler
- * @note
- * Chip drivers will usally be designed to match their events with this value
- */
-#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */
-#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */
-#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */
-#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */
-
-/**
- * @brief I2C state handle return values
- */
-#define I2C_STA_STO_RECV 0x20
-
-/*
- * @brief I2C Control Set register description
- */
-#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */
-#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */
-#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */
-#define I2C_I2CONSET_STA ((0x20))/*!< START flag */
-#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */
-
-/*
- * @brief I2C Control Clear register description
- */
-#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */
-#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */
-#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */
-#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */
-#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */
-
-/*
- * @brief I2C Common Control register description
- */
-#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */
-#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */
-#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */
-#define I2C_CON_STA (1UL << 5) /*!< START flag bit */
-#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */
-
-/*
- * @brief I2C Status Code definition (I2C Status register)
- */
-#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */
-#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */
-
-/*
- * @brief I2C return status code definitions
- */
-#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */
-#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */
-
-/*
- * @brief I2C Master transmit mode
- */
-#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */
-#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
-
-/*
- * @brief I2C Master receive mode
- */
-#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */
-#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */
-#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */
-#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */
-
-/*
- * @brief I2C Slave receive mode
- */
-#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */
-// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */
-#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
-// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
-#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
- SLV/TRX (Slave Transmit) */
-
-/*
- * @brief I2C Slave transmit mode
- */
-#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
-#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
-// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
-#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
-#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */
-
-/*
- * @brief I2C Data register definition
- */
-#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */
-#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
- its sending data length that can be supported */
-
-/*
- * @brief I2C Monitor mode control register description
- */
-#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */
-#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */
-#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */
-#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
-
-/*
- * @brief I2C Data buffer register description
- */
-#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */
-
-/*
- * @brief I2C Slave Address registers definition
- */
-#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */
-#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */
-
-/*
- * @brief I2C Mask Register definition
- */
-#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */
-
-/*
- * @brief I2C SCL HIGH duty cycle Register definition
- */
-#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */
-
-/*
- * @brief I2C SCL LOW duty cycle Register definition
- */
-#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */
-
-/*
- * @brief I2C status values
- */
-#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */
-#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */
-#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */
-
-/*
- * @brief I2C state handle return values
- */
-#define I2C_OK 0x00
-#define I2C_BYTE_SENT 0x01
-#define I2C_BYTE_RECV 0x02
-#define I2C_LAST_BYTE_RECV 0x04
-#define I2C_SEND_END 0x08
-#define I2C_RECV_END 0x10
-#define I2C_STA_STO_RECV 0x20
-
-#define I2C_ERR (0x10000000)
-#define I2C_NAK_RECV (0x10000000 | 0x01)
-
-#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
-
-/*
- * @brief I2C monitor control configuration defines
- */
-#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
-#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
-
-/**
- * @brief I2C Slave Identifiers
- */
-typedef enum {
- I2C_SLAVE_GENERAL, /**< Slave ID for general calls */
- I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */
- I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */
- I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */
- I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */
- I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */
-} I2C_SLAVE_ID;
-
-/**
- * @brief I2C transfer status
- */
-typedef enum {
- I2C_STATUS_DONE, /**< Transfer done successfully */
- I2C_STATUS_NAK, /**< NAK received during transfer */
- I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */
- I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */
- I2C_STATUS_BUSY, /**< I2C is busy doing transfer */
-} I2C_STATUS_T;
-
-/**
- * @brief Master transfer data structure definitions
- */
-typedef struct {
- uint8_t slaveAddr; /**< 7-bit I2C Slave address */
- const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */
- int txSz; /**< Number of bytes in transmit array,
- if 0 only receive transfer will be carried on */
- uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */
- int rxSz; /**< Number of bytes to received,
- if 0 only transmission we be carried on */
- I2C_STATUS_T status; /**< Status of the current I2C transfer */
-} I2C_XFER_T;
-
-/**
- * @brief Initializes the pI2C peripheral.
- * @param pI2C : Pointer to selected I2Cx peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_Init(IP_I2C_001_T *pI2C)
-{
- /* Set I2C operation to default */
- pI2C->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
-}
-
-/**
- * @brief De-initializes the I2C peripheral registers to their default reset values.
- * @param pI2C : Pointer to selected I2Cx peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_DeInit(IP_I2C_001_T *pI2C)
-{
- /* Disable I2C control */
- pI2C->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
-}
-
-/**
- * @brief Set up clock rate for I2Cx.
- * @param pI2C : Pointer to selected I2Cx peripheral
- * @param SCLValue : Value of I2CSCL register
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_SetClockRate(IP_I2C_001_T *pI2C, uint32_t SCLValue)
-{
- pI2C->SCLH = (uint32_t) (SCLValue >> 1);
- pI2C->SCLL = (uint32_t) (SCLValue - pI2C->SCLH);
-}
-
-/**
- * @brief Get current divisor clock value
- * @param pI2C : Pointer to selected I2Cx peripheral
- * @return Clock value divider used by I2C peripheral
- */
-STATIC INLINE uint32_t IP_I2C_GetClockDiv(IP_I2C_001_T *pI2C)
-{
- return pI2C->SCLH + pI2C->SCLL;
-}
-
-/**
- * @brief Enable I2C and start master transfer
- * @param pI2C : Pointer to selected I2C peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_Master_StartXfer(IP_I2C_001_T *pI2C)
-{
- /* Reset STA, STO, SI */
- pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
-
- /* Enter to Master Transmitter mode */
- pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
-}
-
-/**
- * @brief Master transfer state change handler
- * @param pI2C : Pointer to selected I2C peripheral
- * @param xfer : Pointer to transfer structure
- * @return
- * 0 when transfer is done, non-zero when transfer is still going on.
- * @note
- * Values pointed to by @a xfer will be changed based on the state
- * that was handled.
- */
-int IP_I2C_MasterXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);
-
-/**
- * @brief I2C State change checking
- * @param pI2C : Pointer to selected I2C peripheral
- * @return 1 when there is a state change, else 0
- */
-STATIC INLINE int IP_I2C_IsStateChanged(IP_I2C_001_T *pI2C)
-{
- return (pI2C->CONSET & I2C_CON_SI) != 0;
-}
-
-/**
- * @brief Disable I2C peripheral's operation
- * @param pI2C : Pointer to selected I2C peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_Disable(IP_I2C_001_T *pI2C)
-{
- pI2C->CONCLR = I2C_I2CONCLR_I2ENC;
-}
-
-/**
- * @brief Set OWN slave address for specific slave ID
- * @param pI2C : Pointer to selected I2C peripheral
- * @param sid : Slave ID (see #I2C_SLAVE_ID)
- * @param addr : 7-bit slave address from bits (1 - 7)
- * bit 0 having 1 to enable general call, 0 to disable it.
- * @param mask : Address mask
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_SetSlaveAddress(IP_I2C_001_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
-{
- uint32_t index = (uint32_t) sid - 1;
- pI2C->MASK[index] = mask;
- if (sid == I2C_SLAVE_0) {
- pI2C->ADR0 = addr;
- }
- else {
- volatile uint32_t *abase = &pI2C->ADR1;
- abase[index - 1] = addr;
- }
-}
-
-/**
- * @brief Get current state of the I2C peripheral
- * @param pI2C : Pointer to selected I2C peripheral
- * @return Current state code of I2C peripheral
- */
-STATIC INLINE int IP_I2C_GetCurrentState(IP_I2C_001_T *pI2C)
-{
- return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
-}
-
-/**
- * @brief Get the slave ID of the active slave
- * @param pI2C : Pointer to selected I2C peripheral
- * @return Current active slave id
- */
-I2C_SLAVE_ID IP_I2C_GetSlaveIndex(IP_I2C_001_T *pI2C);
-
-/**
- * @brief Slave transfer state change handler
- * @param pI2C : Pointer to selected I2C peripheral
- * @param xfer : Pointer to transfer structure
- * @return
- * #RET_SLAVE_BUSY when transfer is in progress, #RET_SLAVE_IDLE when
- * transfer done and slave enters idle mode, #RET_SLAVE_RX when a byte
- * is received from master, #RET_SLAVE_TX when a byte is sent to master.
- * @note
- * Argument @a xfer must have txBuff and rxBuff pointing to a valid memory
- * except for General call handler which can have txBuff as NULL as the
- * slave will not transfer anything to master using General call address.
- * Structure pointed by @a xfer will have its values changed based on the
- * event that was handled.
- */
-int IP_I2C_SlaveXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);
-
-/**
- * @brief Enable I2C and enable slave transfers
- * @param pI2C : Pointer to selected I2C peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_I2C_Slave_StartXfer(IP_I2C_001_T *pI2C)
-{
- /* Reset STA, STO, SI */
- pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
-
- /* Enter to Master Transmitter mode */
- pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
-}
-
-/**
- * @brief Check if I2C bus is free
- * @param pI2C : Pointer to selected I2C peripheral
- * @return 1 if I2C bus is free, 0 if busy
- */
-STATIC INLINE int IP_I2C_BusFree(IP_I2C_001_T *pI2C)
-{
- return !(pI2C->CONSET & I2C_CON_STO);
-}
-
-/**
- * @brief Check if the active state belongs to master mode
- * @param pI2C : Pointer to selected I2C peripheral
- * @return 1 if the I2C is in master mode, 0 if I2C is in slave mode
- */
-STATIC INLINE int IP_I2C_IsMasterState(IP_I2C_001_T *pI2C)
-{
- return IP_I2C_GetCurrentState(pI2C) < 0x60;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2C_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2s_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2s_001.h
deleted file mode 100644
index a3e87cedc..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/i2s_001.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * @brief I2S Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __I2S_001_H_
-#define __I2S_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_I2S_001 IP: I2S register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief I2S register block structure
- */
-typedef struct { /*!< I2S Structure */
- __IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
- __IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
- __O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
- __I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
- __I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */
- __IO uint32_t DMA1; /*!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
- __IO uint32_t DMA2; /*!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
- __IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
- __IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
- __IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
- __IO uint32_t TXMODE; /*!< I2S Transmit mode control */
- __IO uint32_t RXMODE; /*!< I2S Receive mode control */
-} IP_I2S_001_T;
-
-/**
- * @brief I2S configuration parameter defines
- */
-/** I2S Wordwidth bit */
-#define I2S_WORDWIDTH_8 (0UL << 0) /*!< 8 bit Word */
-#define I2S_WORDWIDTH_16 (1UL << 0) /*!< 16 bit word */
-#define I2S_WORDWIDTH_32 (3UL << 0) /*!< 32 bit word */
-
-/** I2S Channel bit */
-#define I2S_STEREO (0UL << 2) /*!< Stereo audio */
-#define I2S_MONO (1UL << 2) /*!< Mono audio */
-
-/** I2S Master/Slave mode bit */
-#define I2S_MASTER_MODE (0UL << 5) /*!< I2S in master mode */
-#define I2S_SLAVE_MODE (1UL << 5) /*!< I2S in slave mode */
-
-/** I2S Stop bit */
-#define I2S_STOP_ENABLE (0UL << 3) /*!< I2S stop enable mask */
-#define I2S_STOP_DISABLE (1UL << 3) /*!< I2S stop disable mask */
-
-/** I2S Reset bit */
-#define I2S_RESET_ENABLE (1UL << 4) /*!< I2S reset enable mask */
-#define I2S_RESET_DISABLE (0UL << 4) /*!< I2S reset disable mask */
-
-/** I2S Mute bit */
-#define I2S_MUTE_ENABLE (1UL << 15) /*!< I2S mute enable mask */
-#define I2S_MUTE_DISABLE (0UL << 15) /*!< I2S mute disbale mask */
-
-/**
- * @brief Macro defines for DAO-Digital Audio Output register
- */
-/** I2S wordwide - the number of bytes in data*/
-#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAO 8 bit */
-#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAO 16 bit */
-#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAO 32 bit */
-#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
-
-/** I2S control mono or stereo format */
-#define I2S_DAO_MONO ((uint32_t) (1 << 2)) /*!< DAO mono audio mask */
-
-/** I2S control stop mode */
-#define I2S_DAO_STOP ((uint32_t) (1 << 3)) /*!< DAO stop mask */
-
-/** I2S control reset mode */
-#define I2S_DAO_RESET ((uint32_t) (1 << 4)) /*!< DAO reset mask */
-
-/** I2S control master/slave mode */
-#define I2S_DAO_SLAVE ((uint32_t) (1 << 5)) /*!< DAO slave mode mask */
-
-/** I2S word select half period minus one */
-#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) /*!< DAO Word select set macro */
-#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAO Word select mask */
-
-/** I2S control mute mode */
-#define I2S_DAO_MUTE ((uint32_t) (1 << 15)) /*!< DAO mute mask */
-
-/**
- * @brief Macro defines for DAI-Digital Audio Input register
- */
-/** I2S wordwide - the number of bytes in data*/
-#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAI 8 bit */
-#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAI 16 bit */
-#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAI 32 bit */
-#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3)) /*!< DAI word wide mask */
-
-/** I2S control mono or stereo format */
-#define I2S_DAI_MONO ((uint32_t) (1 << 2)) /*!< DAI mono mode mask */
-
-/** I2S control stop mode */
-#define I2S_DAI_STOP ((uint32_t) (1 << 3)) /*!< DAI stop bit mask */
-
-/** I2S control reset mode */
-#define I2S_DAI_RESET ((uint32_t) (1 << 4)) /*!< DAI reset bit mask */
-
-/** I2S control master/slave mode */
-#define I2S_DAI_SLAVE ((uint32_t) (1 << 5)) /*!< DAI slave mode mask */
-
-/** I2S word select half period minus one (9 bits)*/
-#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) /*!< DAI Word select set macro */
-#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAI Word select mask */
-
-/**
- * @brief Macro defines for STAT register (Status Feedback register)
- */
-#define I2S_STATE_IRQ ((uint32_t) (1))/*!< I2S Status Receive or Transmit Interrupt */
-#define I2S_STATE_DMA1 ((uint32_t) (1 << 1)) /*!< I2S Status Receive or Transmit DMA1 */
-#define I2S_STATE_DMA2 ((uint32_t) (1 << 2)) /*!< I2S Status Receive or Transmit DMA2 */
-#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))/*!< I2S Status Current level of the Receive FIFO (5 bits)*/
-#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16)) /*!< I2S Status Current level of the Transmit FIFO (5 bits)*/
-
-/**
- * @brief Macro defines for DMA1 register (DMA1 Configuration register)
- */
-#define I2S_DMA1_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA1 for I2S receive */
-#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */
-#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-
-/**
- * @brief Macro defines for DMA2 register (DMA2 Configuration register)
- */
-#define I2S_DMA2_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA2 for I2S receive */
-#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */
-#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-
-/**
- * @brief Macro defines for IRQ register (Interrupt Request Control register)
- */
-
-#define I2S_IRQ_RX_ENABLE ((uint32_t) (1))/*!< I2S control I2S receive interrupt */
-#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control I2S transmit interrupt */
-#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8)) /*!< I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
-#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16)) /*!< I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
-
-/**
- * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
- */
-#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Transmit MCLK rate denominator */
-#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Transmit MCLK rate denominator */
-#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Receive MCLK rate denominator */
-#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Receive MCLK rate denominator */
-
-/**
- * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
- */
-#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
-#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
-
-/**
- * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
- */
-#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Transmit select clock source (2 bits)*/
-#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Transmit control 4-pin mode */
-#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Transmit control the TX_MCLK output */
-#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Receive select clock source */
-#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Receive control 4-pin mode */
-#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Receive control the TX_MCLK output */
-
-/**
- * @brief I2S transmit/receive mode for configuration
- */
-typedef enum IP_I2S_TRxMode {
- I2S_TX_MODE, /*!< Transmit mode */
- I2S_RX_MODE, /*!< Receive mode */
-} IP_I2S_TRxMode_T;
-
-/**
- * @brief I2S DMA request channel define
- */
-typedef enum IP_I2S_DMARequestNumber {
- IP_I2S_DMA_REQUEST_NUMBER_1, /*!< DMA request channel 1 */
- IP_I2S_DMA_REQUEST_NUMBER_2, /*!< DMA request channel 2 */
-} IP_I2S_DMARequestNumber_T;
-
-/**********************************************************************************
- * I2S Init/DeInit functions
- *********************************************************************************/
-
-/**
- * @brief Initialize for I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- */
-void IP_I2S_Init(IP_I2S_001_T *pI2S);
-
-/**
- * @brief Shutdown I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- * @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
- */
-void IP_I2S_DeInit(IP_I2S_001_T *pI2S);
-
-/**********************************************************************************
- * I2S configuration functions
- *********************************************************************************/
-
-/**
- * @brief Set the data width for the specified mode
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param wordwidth : Data width, should be :
- * - I2S_WORDWIDTH_8
- * - I2S_WORDWIDTH_16
- * - I2S_WORDWIDTH_32
- * @return Nothing
- */
-void IP_I2S_SetWordWidth(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t wordwidth);
-
-/**
- * @brief Set I2S data format to mono or stereo
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param mono : Data channel, should be
- * - I2S_STEREO
- * - I2S_MONO
- * @return Nothing
- */
-void IP_I2S_SetMono(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mono);
-
-/**
- * @brief Set I2S interface in master/slave mode
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param mode : Interface mode, should be
- * - I2S_MASTER_MODE
- * - I2S_SLAVE_MODE
- * @return Nothing
- */
-void IP_I2S_SetMasterSlaveMode(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mode);
-
-/**
- * @brief Set the clock frequency for I2S interface
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param mclk_divider : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
- * @return Nothing
- * @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
- * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
- */
-void IP_I2S_SetBitRate(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mclk_divider);
-
-/**
- * @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param x_divider : I2S transmit MCLK rate numerator
- * @param y_devider : I2S transmit MCLK rate denominator
- * @return Nothing
- * @note Values of the numerator (X) and the denominator (Y) must be chosen to
- * produce a frequency twice that desired for the transmitter MCLK, which
- * must be an integer multiple of the transmitter bit clock rate.
- * The equation for the fractional rate generator is:
- * MCLK = PCLK * (X/Y) /2
- * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
- * greater than or equal to X.
- */
-void IP_I2S_SetXYDivider(IP_I2S_001_T *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);
-
-/**
- * @brief Set word select (WS) half period
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param ws_halfperiod : I2S word select half period minus one
- * @return Nothing
- * @note The Word Select period is configured separately for I2S input and I2S output.
- * For example: if the WS is 64clk period -> ws_halfperiod = 31
- */
-void IP_I2S_SetWS_Halfperiod(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t ws_halfperiod);
-
-/**
- * @brief Set the I2S operating modes
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param clksel : Clock source selection for the receive bit clock divider
- * @param fpin : Receive 4-pin mode selection
- * @param mcena : Enable for the RX_MCLK output
- * @return Nothing
- * @note In addition to master and slave modes, which are independently configurable for
- * the transmitter and the receiver, several different clock sources are possible,
- * including variations that share the clock and/or WS between the transmitter and
- * receiver. It also allows using I2S with fewer pins, typically four.
- */
-void IP_I2S_ModeConfig(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena);
-
-/**
- * @brief Get the current level of the Transmit/Receive FIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Current level of the Transmit/Receive FIFO
- */
-uint8_t IP_I2S_GetLevel(IP_I2S_001_T *pI2S, uint8_t TRMode);
-
-/**********************************************************************************
- * I2S operate functions
- *********************************************************************************/
-
-/**
- * @brief Send a 32-bit data to TXFIFO for transmition
- * @param pI2S : The base of I2S peripheral on the chip
- * @param data : Data to be transmited
- * @return Nothing
- * @note The function writes to TXFIFO without checking any condition.
- */
-void IP_I2S_Send(IP_I2S_001_T *pI2S, uint32_t data);
-
-/**
- * @brief Get received data from RXFIFO
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Data received in RXFIFO
- * @note The function reads from RXFIFO without checking any condition.
- */
-uint32_t IP_I2S_Receive(IP_I2S_001_T *pI2S);
-
-/**
- * @brief Start the I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-void IP_I2S_Start(IP_I2S_001_T *pI2S, uint8_t TRMode);
-
-/**
- * @brief Disables accesses on FIFOs, places the transmit channel in mute mode
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- */
-void IP_I2S_Pause(IP_I2S_001_T *pI2S, uint8_t TRMode);
-
-/**
- * @brief Transmit channel sends only zeroes
- * @param pI2S : The base of I2S peripheral on the chip
- * @return Nothing
- * @note The data output from I2S transmit channel is always zeroes
- */
-STATIC INLINE void IP_I2S_EnableMute(IP_I2S_001_T *pI2S)
-{
- pI2S->DAO |= I2S_DAO_MUTE;
-}
-
-/**
- * @brief Un-Mute the I2S channel
- * @return Nothing
- */
-STATIC INLINE void IP_I2S_DisableMute(IP_I2S_001_T *pI2S)
-{
- pI2S->DAO &= ~I2S_DAO_MUTE;
-}
-
-/**
- * @brief Stop I2S asynchronously
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return Nothing
- * @note Pause, resets the transmit channel and FIFO asynchronously
- */
-void IP_I2S_Stop(IP_I2S_001_T *pI2S, uint8_t TRMode);
-
-/**********************************************************************************
- * I2S DMA functions
- *********************************************************************************/
-
-/**
- * @brief Set the FIFO level on which to create an DMA request
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param DMANum : I2S DMA request number, should be
- * - IP_I2S_DMA_REQUEST_NUMBER_1
- * - IP_I2S_DMA_REQUEST_NUMBER_2
- * @param depth : FIFO level on which to create an DMA request
- * @return Nothing
- * @note DMA request is generated when rx_depth_dma <= rx_level or tx_depth_dma >= tx_level
- */
-void IP_I2S_SetFIFODepthDMA(IP_I2S_001_T *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_T DMANum, uint32_t depth);
-
-/**
- * @brief Enable/Disable DMA for the I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param DMANum : I2S DMA request number, should be
- * - IP_I2S_DMA_REQUEST_NUMBER_1
- * - IP_I2S_DMA_REQUEST_NUMBER_2
- * @param NewState : ENABLE or DISABLE DMA
- * @return Nothing
- */
-void IP_I2S_DMACmd(IP_I2S_001_T *pI2S, IP_I2S_DMARequestNumber_T DMANum, uint8_t TRMode, FunctionalState NewState);
-
-/**********************************************************************************
- * I2S IRQ functions
- *********************************************************************************/
-
-/**
- * @brief Enable/Disable interrupt for the I2S
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param NewState : ENABLE or DISABLE Interrupt
- * @return Nothing
- * @note Interrupt request is generated when rx_depth_irq <= rx_level or tx_depth_irq >= tx_level
- */
-void IP_I2S_InterruptCmd(IP_I2S_001_T *pI2S, uint8_t TRMode, FunctionalState NewState);
-
-/**
- * @brief Set the FIFO level on which to create an irq request
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @param depth : FIFO level on which to create an irq request
- * @return Nothing
- */
-void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t depth);
-
-/**
- * @brief Get the status of I2S interrupt
- * @param pI2S : The base of I2S peripheral on the chip
- * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE
- * @return I2S interrupt status, SET or RESET
- */
-Status IP_I2S_GetIntStatus(IP_I2S_001_T *pI2S, uint8_t TRMode);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __I2S_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lcd_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lcd_001.h
deleted file mode 100644
index 7c88231cb..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lcd_001.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * @brief LCD controller Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LCD_001_H_
-#define __LCD_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_LCD_001 IP: LCD register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief LCD Controller register block structure
- */
-typedef struct { /*!< LCD Structure */
- __IO uint32_t TIMH; /*!< Horizontal Timing Control register */
- __IO uint32_t TIMV; /*!< Vertical Timing Control register */
- __IO uint32_t POL; /*!< Clock and Signal Polarity Control register */
- __IO uint32_t LE; /*!< Line End Control register */
- __IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */
- __IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */
- __IO uint32_t CTRL; /*!< LCD Control register */
- __IO uint32_t INTMSK; /*!< Interrupt Mask register */
- __I uint32_t INTRAW; /*!< Raw Interrupt Status register */
- __I uint32_t INTSTAT; /*!< Masked Interrupt Status register */
- __O uint32_t INTCLR; /*!< Interrupt Clear register */
- __I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */
- __I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */
- __I uint32_t RESERVED0[115];
- __IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */
- __I uint32_t RESERVED1[256];
- __IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */
- __IO uint32_t CRSR_CTRL; /*!< Cursor Control register */
- __IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */
- __IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */
- __IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */
- __IO uint32_t CRSR_XY; /*!< Cursor XY Position register */
- __IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */
- __I uint32_t RESERVED2[2];
- __IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */
- __O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */
- __I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */
- __I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */
-} IP_LCD_001_T;
-
-/**
- * @brief LCD Palette entry format
- */
-typedef struct {
- uint32_t Rl : 5;
- uint32_t Gl : 5;
- uint32_t Bl : 5;
- uint32_t Il : 1;
- uint32_t Ru : 5;
- uint32_t Gu : 5;
- uint32_t Bu : 5;
- uint32_t Iu : 1;
-} LCD_PALETTE_ENTRY_T;
-
-/**
- * @brief LCD Panel type
- */
-typedef enum IP_LCD_PANEL_OPT {
- LCD_TFT = 0x02, /*!< standard TFT */
- LCD_MONO_4 = 0x01, /*!< 4-bit STN mono */
- LCD_MONO_8 = 0x05, /*!< 8-bit STN mono */
- LCD_CSTN = 0x00 /*!< color STN */
-} IP_LCD_PANEL_OPT_T;
-
-/**
- * @brief LCD Color Format
- */
-typedef enum IP_LCD_COLOR_FORMAT_OPT {
- LCD_COLOR_FORMAT_RGB = 0,
- LCD_COLOR_FORMAT_BGR
-} IP_LCD_COLOR_FORMAT_OPT_T;
-
-/** LCD Interrupt control mask register bits */
-#define LCD_INTMSK_FUFIM 0x2 /*!< FIFO underflow interrupt enable */
-#define LCD_INTMSK_LNBUIM 0x4 /*!< LCD next base address update interrupt enable */
-#define LCD_INTMSK_VCOMPIM 0x8 /*!< Vertical compare interrupt enable */
-#define LCD_INTMSK_BERIM 0x10 /*!< AHB master error interrupt enable */
-
-#define CLCDC_LCDCTRL_ENABLE _BIT(0) /*!< LCD control enable bit */
-#define CLCDC_LCDCTRL_PWR _BIT(11) /*!< LCD control power enable bit */
-
-/**
- * @brief A structure for LCD Configuration
- */
-typedef struct {
- uint8_t HBP; /*!< Horizontal back porch in clocks */
- uint8_t HFP; /*!< Horizontal front porch in clocks */
- uint8_t HSW; /*!< HSYNC pulse width in clocks */
- uint16_t PPL; /*!< Pixels per line */
- uint8_t VBP; /*!< Vertical back porch in clocks */
- uint8_t VFP; /*!< Vertical front porch in clocks */
- uint8_t VSW; /*!< VSYNC pulse width in clocks */
- uint16_t LPP; /*!< Lines per panel */
- uint8_t IOE; /*!< Invert output enable, 1 = invert */
- uint8_t IPC; /*!< Invert panel clock, 1 = invert */
- uint8_t IHS; /*!< Invert HSYNC, 1 = invert */
- uint8_t IVS; /*!< Invert VSYNC, 1 = invert */
- uint8_t ACB; /*!< AC bias frequency in clocks (not used) */
- uint8_t BPP; /*!< Maximum bits per pixel the display supports */
- IP_LCD_PANEL_OPT_T LCD; /*!< LCD panel type */
- IP_LCD_COLOR_FORMAT_OPT_T color_format; /*!INTMSK = ints;
-}
-
-/**
- * @brief Disable Controller Interrupt
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param ints : OR'ed interrupt bits to disable
- * @return None
- */
-STATIC INLINE void IP_LCD_DisableInts(IP_LCD_001_T *pLCD, uint32_t ints)
-{
- pLCD->INTMSK = pLCD->INTMSK & ~(ints);
-}
-
-/**
- * @brief Clear Controller Interrupt
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param ints : OR'ed interrupt bits to clear
- * @return None
- */
-STATIC INLINE void IP_LCD_ClearInts(IP_LCD_001_T *pLCD, uint32_t ints)
-{
- pLCD->INTCLR = pLCD->INTMSK & (ints);
-}
-
-/**
- * @brief Power-on the LCD Panel (power pin)
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @return None
- */
-STATIC INLINE void IP_LCD_PowerOn(IP_LCD_001_T *pLCD) {
- volatile int i;
- pLCD->CTRL |= CLCDC_LCDCTRL_PWR;
- for (i = 0; i < 1000000; i++) {}
- pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
-}
-
-/**
- * @brief Power-off the LCD Panel (power pin)
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @return None
- */
-STATIC INLINE void IP_LCD_PowerOff(IP_LCD_001_T *pLCD) {
- volatile int i;
- pLCD->CTRL &= ~CLCDC_LCDCTRL_PWR;
- for (i = 0; i < 1000000; i++) {}
- pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
-}
-
-/**
- * @brief Enable the LCD Controller
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @return None
- */
-STATIC INLINE void IP_LCD_Enable(IP_LCD_001_T *pLCD) {
- pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
-}
-
-/**
- * @brief Enable the LCD Controller
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @return None
- */
-STATIC INLINE void IP_LCD_Disable(IP_LCD_001_T *pLCD) {
- pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
-}
-
-/**
- * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
- * Buffer for Dual Panel
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void IP_LCD_SetUPFrameBuffer(IP_LCD_001_T *pLCD, void *buffer)
-{
- pLCD->UPBASE = (uint32_t) buffer;
-}
-
-/**
- * @brief Set LCD Lower Panel Frame Buffer for Dual Panel
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param buffer : address of buffer
- * @return None
- */
-STATIC INLINE void IP_LCD_SetLPFrameBuffer(IP_LCD_001_T *pLCD, void *buffer)
-{
- pLCD->LPBASE = (uint32_t) buffer;
-}
-
-/**
- * @brief Configure Cursor
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param cursor_size : specify size of cursor
- * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels
- * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels
- * @param sync : cursor sync mode
- * - TRUE :cursor sync to the frame sync pulse
- * - FALSE :cursor async mode
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_Config(IP_LCD_001_T *pLCD, IP_LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync)
-{
- pLCD->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size;
-}
-
-/**
- * @brief Get Internal Cursor Image Buffer Address
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @return Cursor Image Buffer Address
- */
-STATIC INLINE void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_T *pLCD, uint8_t cursor_num)
-{
- return (void *) &(pLCD->CRSR_IMG[cursor_num * 64]);
-}
-
-/**
- * @brief Enable Cursor
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_Enable(IP_LCD_001_T *pLCD, uint8_t cursor_num) {
- pLCD->CRSR_CTRL = (cursor_num << 4) | 1;
-}
-
-/**
- * @brief Disable Cursor
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param cursor_num : specify number of cursor is going to be written
- * this param must < 4
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_Disable(IP_LCD_001_T *pLCD, uint8_t cursor_num) {
- pLCD->CRSR_CTRL = (cursor_num << 4);
-}
-
-/**
- * @brief Load Cursor Palette
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param palette_color : cursor palette 0 value
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_T *pLCD, uint32_t palette_color)
-{
- /* 7:0 - Red
- 15:8 - Green
- 23:16 - Blue
- 31:24 - Not used*/
- pLCD->CRSR_PAL0 = (uint32_t) palette_color;
-}
-
-/**
- * @brief Load Cursor Palette
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param palette_color : cursor palette 1 value
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_T *pLCD, uint32_t palette_color)
-{
- /* 7:0 - Red
- 15:8 - Green
- 23:16 - Blue
- 31:24 - Not used*/
- pLCD->CRSR_PAL1 = (uint32_t) palette_color;
-
-}
-
-/**
- * @brief Set Cursor Position
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param x : horizontal position
- * @param y : vertical position
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_SetPos(IP_LCD_001_T *pLCD, uint16_t x, uint16_t y)
-{
- pLCD->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);
-}
-
-/**
- * @brief Set Cursor Clipping Position
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param x : horizontal position, should be in range: 0..63
- * @param y : vertical position, should be in range: 0..63
- * @return None
- */
-STATIC INLINE void IP_LCD_Cursor_SetClip(IP_LCD_001_T *pLCD, uint16_t x, uint16_t y)
-{
- pLCD->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);
-}
-
-/**
- * @brief Load a color Palette entry
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param palette_addr : Address of palette table to load from
- * @param index : palette entry index to load
- * @return None
- */
-STATIC INLINE void IP_LCD_Color_LoadPalette(IP_LCD_001_T *pLCD, uint32_t *palette_addr, uint32_t index)
-{
- pLCD->PAL[index] = *(uint32_t *) palette_addr;
-}
-
-/**
- * @brief Initialize the LCD controller
- * @param pLCD : pointer to LCD Controller Reg Struct
- * @param LCD_ConfigStruct : Pointer to LCD configuration
- * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
- */
-void IP_LCD_Init(IP_LCD_001_T *pLCD, LCD_Config_T *LCD_ConfigStruct);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LCD_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lpc_types.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lpc_types.h
deleted file mode 100644
index 05e0d66cb..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/lpc_types.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * @brief Common types used in LPC functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __LPC_TYPES_H_
-#define __LPC_TYPES_H_
-
-#include
-#include
-
-/** @defgroup LPC_Types IP: LPC Common Types
- * @ingroup IP_Drivers
- * @{
- */
-
-/** @defgroup LPC_Types_Public_Types LPC Public Types
- * @{
- */
-
-/**
- * @brief Boolean Type definition
- */
-typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
-
-/**
- * @brief Boolean Type definition
- */
-#if !defined(__cplusplus)
-// typedef enum {false = 0, true = !false} bool;
-#endif
-
-/**
- * @brief Flag Status and Interrupt Flag Status type definition
- */
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
-#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
-
-/**
- * @brief Functional State Definition
- */
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
-
-/**
- * @ Status type definition
- */
-typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
-
-/**
- * Read/Write transfer type mode (Block or non-block)
- */
-typedef enum {
- NONE_BLOCKING = 0, /**< None Blocking type */
- BLOCKING, /**< Blocking type */
-} TRANSFER_BLOCK_T;
-
-/** Pointer to Function returning Void (any number of parameters) */
-typedef void (*PFV)();
-
-/** Pointer to Function returning int32_t (any number of parameters) */
-typedef int32_t (*PFI)();
-
-/**
- * @}
- */
-
-/** @defgroup LPC_Types_Public_Macros LPC Public Macros
- * @{
- */
-
-/* _BIT(n) sets the bit at position "n"
- * _BIT(n) is intended to be used in "OR" and "AND" expressions:
- * e.g., "(_BIT(3) | _BIT(7))".
- */
-#undef _BIT
-/* Set bit macro */
-#define _BIT(n) (1 << (n))
-
-/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
- * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
- * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
- */
-#undef _SBF
-/* Set bit field macro */
-#define _SBF(f, v) ((v) << (f))
-
-/* _BITMASK constructs a symbol with 'field_width' least significant
- * bits set.
- * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
- * The symbol is intended to be used to limit the bit field width
- * thusly:
- * = (any_expression) & _BITMASK(x), where 0 < x <= 32.
- * If "any_expression" results in a value that is larger than can be
- * contained in 'x' bits, the bits above 'x - 1' are masked off. When
- * used with the _SBF example above, the example would be written:
- * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
- * This ensures that the value written to a_reg is no wider than
- * 16 bits, and makes the code easier to read and understand.
- */
-#undef _BITMASK
-/* Bitmask creation macro */
-#define _BITMASK(field_width) ( _BIT(field_width) - 1)
-
-/* NULL pointer */
-#ifndef NULL
-#define NULL ((void *) 0)
-#endif
-
-/* Number of elements in an array */
-#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
-
-/* Static data/function define */
-#define STATIC static
-/* External data/function define */
-#define EXTERN extern
-
-#if !defined(MAX)
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-#endif
-#if !defined(MIN)
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-
-/**
- * @}
- */
-
-/* Old Type Definition compatibility */
-/** @addtogroup LPC_Types_Public_Types
- * @{
- */
-
-/** LPC type for character type */
-typedef char CHAR;
-
-/** LPC type for 8 bit unsigned value */
-typedef uint8_t UNS_8;
-
-/** LPC type for 8 bit signed value */
-typedef int8_t INT_8;
-
-/** LPC type for 16 bit unsigned value */
-typedef uint16_t UNS_16;
-
-/** LPC type for 16 bit signed value */
-typedef int16_t INT_16;
-
-/** LPC type for 32 bit unsigned value */
-typedef uint32_t UNS_32;
-
-/** LPC type for 32 bit signed value */
-typedef int32_t INT_32;
-
-/** LPC type for 64 bit signed value */
-typedef int64_t INT_64;
-
-/** LPC type for 64 bit unsigned value */
-typedef uint64_t UNS_64;
-
-#ifdef __CODE_RED
-#define BOOL_32 bool
-#define BOOL_16 bool
-#define BOOL_8 bool
-#else
-/** 32 bit boolean type */
-typedef bool BOOL_32;
-
-/** 16 bit boolean type */
-typedef bool BOOL_16;
-
-/** 8 bit boolean type */
-typedef bool BOOL_8;
-#endif
-
-#ifdef __CC_ARM
-#define INLINE __inline
-#else
-#define INLINE inline
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* __LPC_TYPES_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mcpwm_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mcpwm_001.h
deleted file mode 100644
index 8416699de..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mcpwm_001.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * @brief Motor Control PWM registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __MCPWM_001_H_
-#define __MCPWM_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_MCPWM_001 IP: MCPWM register block and driver
- * @ingroup IP_Drivers
- * Motor Control PWM
- * @{
- */
-
-/**
- * @brief Motor Control PWM register block structure
- */
-typedef struct { /*!< MCPWM Structure */
- __I uint32_t CON; /*!< PWM Control read address */
- __O uint32_t CON_SET; /*!< PWM Control set address */
- __O uint32_t CON_CLR; /*!< PWM Control clear address */
- __I uint32_t CAPCON; /*!< Capture Control read address */
- __O uint32_t CAPCON_SET; /*!< Capture Control set address */
- __O uint32_t CAPCON_CLR; /*!< Event Control clear address */
- __IO uint32_t TC[3]; /*!< Timer Counter register */
- __IO uint32_t LIM[3]; /*!< Limit register */
- __IO uint32_t MAT[3]; /*!< Match register */
- __IO uint32_t DT; /*!< Dead time register */
- __IO uint32_t CCP; /*!< Communication Pattern register */
- __I uint32_t CAP[3]; /*!< Capture register */
- __I uint32_t INTEN; /*!< Interrupt Enable read address */
- __O uint32_t INTEN_SET; /*!< Interrupt Enable set address */
- __O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */
- __I uint32_t CNTCON; /*!< Count Control read address */
- __O uint32_t CNTCON_SET; /*!< Count Control set address */
- __O uint32_t CNTCON_CLR; /*!< Count Control clear address */
- __I uint32_t INTF; /*!< Interrupt flags read address */
- __O uint32_t INTF_SET; /*!< Interrupt flags set address */
- __O uint32_t INTF_CLR; /*!< Interrupt flags clear address */
- __O uint32_t CAP_CLR; /*!< Capture clear address */
-} IP_MCPWM_001_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MCPWM_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mrt_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mrt_001.h
deleted file mode 100644
index c582f66e9..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/mrt_001.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * @brief Multi-Rate Timer (MRT) registers and driver functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __MRT_001_H_
-#define __MRT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_MRT_001 IP: MRT register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief MRT register block structure
- */
-typedef struct {
- __IO uint32_t INTVAL; /*!< Timer interval register */
- __O uint32_t TIMER; /*!< Timer register */
- __IO uint32_t CTRL; /*!< Timer control register */
- __IO uint32_t STAT; /*!< Timer status register */
-} IP_MRT_001_T;
-
-/**
- * @brief MRT register bit fields & masks
- */
-/* MRT Time interval register bit fields */
-#define IP_MRT_001_INTVAL_IVALUE (0xFFFFFF)
-#define IP_MRT_001_INTVAL_LOAD (1 << 31)
-
-/* MRT Control register bit fields & masks */
-#define IP_MRT_001_CTRL_MODE_REPEAT (0x00)
-#define IP_MRT_001_CTRL_MODE_ONESHOT (0x01)
-#define IP_MRT_001_CTRL_INTEN_MASK (0x01)
-#define IP_MRT_001_CTRL_MODE_POS (0x01)
-#define IP_MRT_001_CTRL_MODE_MASK (0x06)
-#define IP_MRT_001_CTRL_MODE_SHIFT(x) (x << 1)
-
-/* MRT Status register bit fields & masks */
-#define IP_MRT_001_STAT_INTFLAG (0x01)
-#define IP_MRT_001_STAT_RUNNING (0x02)
-
-/**
- * @brief MRT Interrupt Modes enum
- */
-typedef enum IP_MRT_001_MODE {
- MRT_MODE_REPEAT = 0, /*!< MRT Repeat interrupt mode */
- MRT_MODE_ONESHOT = 1 /*!< MRT One-shot interrupt mode */
-} IP_MRT_001_MODE_T;
-
-/**
- * @brief Initializes the MRT
- * @return Nothing
- */
-STATIC INLINE void IP_MRT_Init(void)
-{}
-
-/**
- * @brief De-initializes the MRT Channel
- * @return Nothing
- */
-STATIC INLINE void IP_MRT_DeInit(void)
-{}
-
-/**
- * @brief Returns the timer time interval value
- * @param pMRT : Pointer to selected MRT Channel
- * @return The time interval value
- */
-STATIC INLINE uint32_t IP_MRT_GetInterval(IP_MRT_001_T *pMRT)
-{
- return (uint32_t) pMRT->INTVAL;
-}
-
-/**
- * @brief Sets the timer time interval value
- * @param pMRT : Pointer to selected MRT Channel
- * @param interval : Time interval value (24-bits)
- * @return Nothing
- * @note Setting bit 31 in time interval register causes the time interval
- * to load immediately, otherwise the load will occur on the
- * next timer cycle
- */
-STATIC INLINE void IP_MRT_SetInterval(IP_MRT_001_T *pMRT, uint32_t interval)
-{
- pMRT->INTVAL = interval;
-}
-
-/**
- * @brief Returns the current timer value
- * @param pMRT : Pointer to selected MRT Channel
- * @return The current timer value
- */
-STATIC INLINE uint32_t IP_MRT_GetTimer(IP_MRT_001_T *pMRT)
-{
- return (uint32_t) pMRT->TIMER;
-}
-
-/**
- * @brief Returns true if the timer is enabled
- * @param pMRT : Pointer to selected MRT Channel
- * @return True if enabled, False if not enabled
- */
-STATIC INLINE bool IP_MRT_GetEnabled(IP_MRT_001_T *pMRT)
-{
- return (bool) (pMRT->CTRL & IP_MRT_001_CTRL_INTEN_MASK);
-}
-
-/**
- * @brief Enables the timer
- * @param pMRT : Pointer to selected MRT Channel
- * @return Nothing
- */
-STATIC INLINE void IP_MRT_SetEnabled(IP_MRT_001_T *pMRT)
-{
- pMRT->CTRL |= IP_MRT_001_CTRL_INTEN_MASK;
-}
-
-/**
- * @brief Returns the timer mode (repeat or one-shot).
- * @param pMRT : Pointer to selected MRT Channel
- * @return The mode (repeat or one-shot).
- */
-STATIC INLINE IP_MRT_001_MODE_T IP_MRT_GetMode(IP_MRT_001_T *pMRT)
-{
- return (IP_MRT_001_MODE_T) ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) >> 1);
-}
-
-/**
- * @brief Sets the timer mode to be repeat or one-shot.
- * @param pMRT : Pointer to selected MRT Channel
- * @param mode : 0 = repeat, 1 = one-shot
- * @return Nothing
- */
-STATIC INLINE void IP_MRT_SetMode(IP_MRT_001_T *pMRT, IP_MRT_001_MODE_T mode)
-{
- pMRT->CTRL |= IP_MRT_001_CTRL_MODE_SHIFT(mode);
-}
-
-/**
- * @brief Returns true if the timer is configured in repeat mode.
- * @param pMRT : Pointer to selected MRT Channel
- * @return True if in repeat mode, False if in one-shot mode
- */
-STATIC INLINE bool IP_MRT_IsRepeatMode(IP_MRT_001_T *pMRT)
-{
- return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? false : true;
-}
-
-/**
- * @brief Returns true if the timer is configured in one-shot mode.
- * @param pMRT : Pointer to selected MRT Channel
- * @return True if in one-shot mode, False if in repeat mode.
- */
-STATIC INLINE bool IP_MRT_IsOneShotMode(IP_MRT_001_T *pMRT)
-{
- return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? true : false;
-}
-
-/**
- * @brief Returns true if the timer has an interrupt pending.
- * @param pMRT : Pointer to selected MRT Channel
- * @return True if interrupt is pending, False if no interrupt is pending.
- */
-STATIC INLINE bool IP_MRT_IntPending(IP_MRT_001_T *pMRT)
-{
- return (bool) (pMRT->STAT & IP_MRT_001_STAT_INTFLAG);
-}
-
-/**
- * @brief Clears the pending interrupt (if any).
- * @param pMRT : Pointer to selected MRT Channel
- * @return Nothing
- */
-STATIC INLINE void IP_MRT_IntClear(IP_MRT_001_T *pMRT)
-{
- pMRT->STAT |= IP_MRT_001_STAT_INTFLAG;
-}
-
-/**
- * @brief Returns true if the timer is running.
- * @param pMRT : Pointer to selected MRT Channel
- * @return True if running, False if stopped.
- */
-STATIC INLINE bool IP_MRT_Running(IP_MRT_001_T *pMRT)
-{
- return (bool) (pMRT->STAT & IP_MRT_001_STAT_RUNNING);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MRT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/pmc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/pmc_001.h
deleted file mode 100644
index ec9fd3bce..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/pmc_001.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * @brief Power Management Controller registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __PMC_001_H_
-#define __PMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_PMC_001 IP: PMC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief Power Management Controller register block structure
- */
-typedef struct { /*!< PMC Structure */
- __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< Hardware sleep event enable register */
- __I uint32_t RESERVED0[6];
- __IO uint32_t PD0_SLEEP0_MODE; /*!< Sleep power mode register */
-} IP_PMC_001_T;
-
-/**
- * @brief Power Management Controller power modes
- */
-#define PMC_PWR_DEEP_SLEEP_MODE 0x3F00AA
-#define PMC_PWR_POWER_DOWN_MODE 0x3FFCBA
-#define PMC_PWR_DEEP_POWER_DOWN_MODE 0x3FFF7F
-
-/**
- * @brief Set power mode in PMC block
- * @param pPMC : Pointer to PMC register block
- * @param PwrMode : Power mode value (PMC_PWR_DEEP_SLEEP_MODE/PMC_PWR_POWER_DOWN_MODE/PMC_PWR_DEEP_POWER_DOWN_MODE)
- * @return Nothing
- */
-STATIC INLINE void IP_PMC_SetPowerMode(IP_PMC_001_T *pPMC, uint32_t PwrMode)
-{
- pPMC->PD0_SLEEP0_MODE = PwrMode;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __PMC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/qei_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/qei_001.h
deleted file mode 100644
index 406ba7de8..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/qei_001.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * @brief Quadrature Encoder Interface Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __QEI_001_H_
-#define __QEI_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_QEI_001 IP: QEI register block and driver
- * @ingroup IP_Drivers
- * Quadrature Encoder Interface
- * @{
- */
-
-/**
- * @brief Quadrature Encoder Interface register block structure
- */
-typedef struct { /*!< QEI Structure */
- __O uint32_t CON; /*!< Control register */
- __I uint32_t STAT; /*!< Encoder status register */
- __IO uint32_t CONF; /*!< Configuration register */
- __I uint32_t POS; /*!< Position register */
- __IO uint32_t MAXPOS; /*!< Maximum position register */
- __IO uint32_t CMPOS0; /*!< position compare register 0 */
- __IO uint32_t CMPOS1; /*!< position compare register 1 */
- __IO uint32_t CMPOS2; /*!< position compare register 2 */
- __I uint32_t INXCNT; /*!< Index count register */
- __IO uint32_t INXCMP0; /*!< Index compare register 0 */
- __IO uint32_t LOAD; /*!< Velocity timer reload register */
- __I uint32_t TIME; /*!< Velocity timer register */
- __I uint32_t VEL; /*!< Velocity counter register */
- __I uint32_t CAP; /*!< Velocity capture register */
- __IO uint32_t VELCOMP; /*!< Velocity compare register */
- __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
- __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
- __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
- __IO uint32_t WINDOW; /*!< Index acceptance window register */
- __IO uint32_t INXCMP1; /*!< Index compare register 1 */
- __IO uint32_t INXCMP2; /*!< Index compare register 2 */
- __I uint32_t RESERVED0[993];
- __O uint32_t IEC; /*!< Interrupt enable clear register */
- __O uint32_t IES; /*!< Interrupt enable set register */
- __I uint32_t INTSTAT; /*!< Interrupt status register */
- __I uint32_t IE; /*!< Interrupt enable register */
- __O uint32_t CLR; /*!< Interrupt status clear register */
- __O uint32_t SET; /*!< Interrupt status set register */
-} IP_QEI_001_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __QEI_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/regfile_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/regfile_001.h
deleted file mode 100644
index 021b05f09..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/regfile_001.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * @brief Register File registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __REGFILE_001_H_
-#define __REGFILE_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_REGFILE_001 IP: REGFILE register block and driver
- * @ingroup IP_Drivers
- * Register File
- * @{
- */
-
-/**
- * @brief Register File register block structure
- */
-typedef struct {
-#if defined(CHIP_LPC18XX)|| defined(CHIP_LPC43XX)
- __IO uint32_t REGFILE[64]; /*!< General purpose storage register */
-#elif defined(CHIP_LPC175X_6X)|| defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)
- __IO uint32_t REGFILE[5]; /*!< General purpose storage register */
-#endif
-} IP_REGFILE_001_T;
-
-/**
- * @brief Write value to General purpose registers
- * @param pREG : Pointer to regfile block
- * @param index : General purpose register index
- * @param value : Value to write
- * @return None
- * @note These General purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are usually
- * powered in the RTC power domain.
- */
-STATIC INLINE void IP_REGFILE_Write(IP_REGFILE_001_T *pREG, int index, uint32_t value)
-{
- pREG->REGFILE[index] = value;
-}
-
-/**
- * @brief Read value from General purpose registers
- * @param pREG : Pointer to regfile block
- * @param index : General purpose register index
- * @return Read value
- * @note These General purpose registers can be used to store important
- * information when the main power supply is off. The value in these
- * registers is not affected by chip reset. These registers are usually
- * powered in the RTC power domain.
- */
-STATIC INLINE uint32_t IP_REGFILE_Read(IP_REGFILE_001_T *pREG, int index)
-{
- return pREG->REGFILE[index];
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __REGFILE_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ritimer_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ritimer_001.h
deleted file mode 100644
index f85eac708..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ritimer_001.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * @brief Repetitive Interrupt Timer registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RITIMER_001_H_
-#define __RITIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_RITIMER_001 IP: RITimer register block and driver
- * @ingroup IP_Drivers
- * Repetitive Interrupt Timer
- * @{
- */
-
-/**
- * @brief Repetitive Interrupt Timer register block structure
- */
-typedef struct { /*!< RITIMER Structure */
- __IO uint32_t COMPVAL; /*!< Compare register */
- __IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
- __IO uint32_t CTRL; /*!< Control register. */
- __IO uint32_t COUNTER; /*!< 32-bit counter */
-#if defined(CHIP_LPC1347)
- __IO uint32_t COMPVAL_H; /*!< Compare upper register */
- __IO uint32_t MASK_H; /*!< Mask upper register */
- __I uint32_t RESERVED0[1];
- __IO uint32_t COUNTER_H; /*!< Counter upper register */
-#endif
-} IP_RITIMER_001_T;
-
-/**
- * @brief RITIMER register support bitfields and mask
- */
-
-/*
- * RIT control register
- */
-/** Set by H/W when the counter value equals the masked compare value */
-#define RIT_CTRL_INT ((uint32_t) (1))
-/** Set timer enable clear to 0 when the counter value equals the masked compare value */
-#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
-/** Set timer enable on debug */
-#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
-/** Set timer enable */
-#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
-
-/**
- * @brief Initialize the RIT
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-void IP_RIT_Init(IP_RITIMER_001_T *pRITimer);
-
-/**
- * @brief DeInitialize the RIT
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-void IP_RIT_DeInit(IP_RITIMER_001_T *pRITimer);
-
-/**
- * @brief Enable Timer
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-STATIC INLINE void IP_RIT_Enable(IP_RITIMER_001_T *pRITimer)
-{
- pRITimer->CTRL |= RIT_CTRL_TEN;
-}
-
-/**
- * @brief Disable Timer
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-STATIC INLINE void IP_RIT_Disable(IP_RITIMER_001_T *pRITimer)
-{
- pRITimer->CTRL &= ~RIT_CTRL_TEN;
-}
-
-
-/**
- * @brief Timer Enable on debug
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-STATIC INLINE void IP_RIT_TimerDebugEnable(IP_RITIMER_001_T *pRITimer)
-{
- pRITimer->CTRL |= RIT_CTRL_ENBR;
-}
-
-/**
- * @brief Timer Disable on debug
- * @param pRITimer : RIT peripheral selected
- * @return None
- */
-STATIC INLINE void IP_RIT_TimerDebugDisable(IP_RITIMER_001_T *pRITimer)
-{
- pRITimer->CTRL &= ~RIT_CTRL_ENBR;
-}
-
-
-/**
- * @brief Check whether interrupt flag is set or not
- * @param pRITimer : RIT peripheral selected
- * @return Current interrupt status, could be SET or UNSET
- */
-IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_T *pRITimer);
-
-/**
- * @brief Set a tick value for the interrupt to time out
- * @param pRITimer : RIT peripheral selected
- * @param val : value (in ticks) of the interrupt to be set
- * @return None
- */
-STATIC INLINE void IP_RIT_SetCOMPVAL(IP_RITIMER_001_T *pRITimer, uint32_t val)
-{
- pRITimer->COMPVAL = val;
-}
-
-/**
- * @brief Enables or clears the RIT or interrupt
- * @param pRITimer : RIT peripheral selected
- * @param val : RIT to be set, one or more RIT_CTRL_* values
- * @return None
- */
-STATIC INLINE void IP_RIT_EnableCTRL(IP_RITIMER_001_T *pRITimer, uint32_t val)
-{
- pRITimer->CTRL |= val;
-}
-
-/**
- * @brief Get the RIT Counter value
- * @param pRITimer : RIT peripheral selected
- * @return the counter value
- */
-STATIC INLINE uint32_t IP_RIT_GetCounter(IP_RITIMER_001_T *pRITimer)
-{
- return pRITimer->COUNTER;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RITIMER_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/rtc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/rtc_001.h
deleted file mode 100644
index 1de536e47..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/rtc_001.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * @brief Real Time Clock registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __RTC_001_H_
-#define __RTC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_RTC_001 IP: RTC register block and driver
- * @ingroup IP_Drivers
- * Real Time Clock
- * @{
- */
-
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
-#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
-#endif
-/**
- * @brief RTC time type option
- */
-typedef enum IP_RTC_TIMEINDEX {
- RTC_TIMETYPE_SECOND, /*!< Second */
- RTC_TIMETYPE_MINUTE, /*!< Month */
- RTC_TIMETYPE_HOUR, /*!< Hour */
- RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */
- RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */
- RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */
- RTC_TIMETYPE_MONTH, /*!< Month */
- RTC_TIMETYPE_YEAR, /*!< Year */
- RTC_TIMETYPE_LAST
-} IP_RTC_TIMEINDEX_T;
-
-#if RTC_EV_SUPPORT
-/**
- * @brief Event Channel Identifier definitions
- */
-typedef enum IP_RTC_EV_CHANNEL {
- RTC_EV_CHANNEL_1 = 0,
- RTC_EV_CHANNEL_2,
- RTC_EV_CHANNEL_3,
- RTC_EV_CHANNEL_NUM,
-} IP_RTC_EV_CHANNEL_T;
-#endif /*RTC_EV_SUPPORT*/
-
-/**
- * @brief Real Time Clock register block structure
- */
-typedef struct { /*!< RTC Structure */
- __IO uint32_t ILR; /*!< Interrupt Location Register */
- __I uint32_t RESERVED0;
- __IO uint32_t CCR; /*!< Clock Control Register */
- __IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */
- __IO uint32_t AMR; /*!< Alarm Mask Register */
- __I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */
- __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */
- __IO uint32_t CALIBRATION; /*!< Calibration Value Register */
-#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC175X_6X)
- __IO uint32_t GPREG[5]; /*!< General Purpose Storage Registers */
- __IO uint32_t RTC_AUXEN; /*!< RTC Auxiliary Enable register */
- __IO uint32_t RTC_AUX; /*!< RTC Auxiliary control register*/
-#else
- __I uint32_t RESERVED1[7];
-#endif
- __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */
-#if RTC_EV_SUPPORT
- __IO uint32_t ERSTATUS; /*!< Event Monitor/Recorder Status register*/
- __IO uint32_t ERCONTROL; /*!< Event Monitor/Recorder Control register*/
- __I uint32_t ERCOUNTERS; /*!< Event Monitor/Recorder Counters register*/
- __I uint32_t RESERVED2;
- __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /*!> (8 * ch)) & 0x07))
-
-/**
- * @brief Event Monitor/Recorder TimeStamp register
- */
-#define RTC_ER_TIMESTAMP_SEC(n) ((uint32_t) (n & 0x3F))
-#define RTC_ER_TIMESTAMP_MIN(n) ((uint32_t) ((n >> 6) & 0x3F))
-#define RTC_ER_TIMESTAMP_HOUR(n) ((uint32_t) ((n >> 12) & 0x1F))
-#define RTC_ER_TIMESTAMP_DOY(n) ((uint32_t) ((n >> 17) & 0x1FF))
-
-/**
- * @brief Event Monitor/Recorder Mode definition
- */
-typedef enum IP_RTC_EV_MODE {
- RTC_EV_MODE_DISABLE = 0, /*!< Event Monitor/Recoder is disabled */
- RTC_EV_MODE_ENABLE_16HZ = 1, /*!< Event Monitor/Recoder is enabled and use 16Hz sample clock for event input */
- RTC_EV_MODE_ENABLE_64HZ = 2, /*!< Event Monitor/Recoder is enabled and use 64Hz sample clock for event input */
- RTC_EV_MODE_ENABLE_1KHZ = 3, /*!< Event Monitor/Recoder is enabled and use 1kHz sample clock for event input */
- RTC_EV_MODE_LAST,
-} IP_RTC_EV_MODE_T;
-
-/**
- * @brief Event Monitor/Recorder Timestamp structure
- */
-typedef struct {
- uint8_t sec; /*!< Second */
- uint8_t min; /*!< Minute */
- uint8_t hour; /*!< Hour */
- uint16_t dayofyear; /*!< Day of year */
-} IP_RTC_EV_TIMESTAMP_T;
-
-#endif /*RTC_EV_SUPPORT*/
-
-/**
- * @brief RTC enumeration
- */
-
-/** @brief RTC interrupt source */
-typedef enum IP_RTC_INT_OPT {
- RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
- RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
-} IP_RTC_INT_OPT_T;
-
-typedef struct {
- uint32_t time[RTC_TIMETYPE_LAST];
-} IP_RTC_TIME_T;
-
-/**
- * @brief Initialize the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @return None
- */
-void IP_RTC_Init(IP_RTC_001_T *pRTC);
-
-/**
- * @brief De-initialize the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @return None
- */
-STATIC INLINE void IP_RTC_DeInit(IP_RTC_001_T *pRTC)
-{
- pRTC->CCR = 0x00;
-}
-
-/**
- * @brief Reset clock tick counter in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @return None
- */
-void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC);
-
-/**
- * @brief Start/Stop RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState);
-
-/**
- * @brief Enable/Disable Counter increment interrupt for a time type in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask, FunctionalState NewState);
-
-/**
- * @brief Enable/Disable Alarm interrupt for a time type in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
- * @param NewState : ENABLE or DISABLE
- * @return None
- */
-void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask, FunctionalState NewState);
-
-/**
- * @brief Set current time value for a time type in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param Timetype : time field index type to set
- * @param TimeValue : Value to palce in time field
- * @return None
- */
-void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue);
-
-/**
- * @brief Get current time value for a type time type
- * @param pRTC : pointer to RTC peripheral block
- * @param Timetype : Time field index type to get
- * @return Value of time field according to specified time type
- */
-uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);
-
-/**
- * @brief Set full time in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param pFullTime : Pointer to full time data
- * @return None
- */
-void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief Get full time from the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief Set alarm time value for a time type
- * @param pRTC : pointer to RTC peripheral block
- * @param Timetype : Time index field to set
- * @param ALValue : Alarm time value to set
- * @return None
- */
-void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue);
-
-/**
- * @brief Get alarm time value for a time type
- * @param pRTC : pointer to RTC peripheral block
- * @param Timetype : Time index field to get
- * @return Value of Alarm time according to specified time type
- */
-uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);
-
-/**
- * @brief Set full alarm time in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param pFullTime : Pointer to full time record to set alarm
- * @return None
- */
-void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief Get full alarm time in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param pFullTime : Pointer to full time record to fill
- * @return None
- */
-void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);
-
-/**
- * @brief Enable/Disable calibration counter in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param NewState : New State of this function, should be:
- * - ENABLE :The calibration counter is enabled and counting
- * - DISABLE :The calibration counter is disabled and reset to zero
- * @return None
- */
-void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState);
-
-/**
- * @brief Configures Calibration in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param CalibValue : Calibration value, should be in range from 0 to 131,072
- * @param CalibDir : Calibration Direction, should be:
- * - RTC_CALIB_DIR_FORWARD :Forward calibration
- * - RTC_CALIB_DIR_BACKWARD :Backward calibration
- * @return None
- */
-void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir);
-
-/**
- * @brief Clear specified Location interrupt pending in the RTC peripheral
- * @param pRTC : pointer to RTC peripheral block
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.
- * - RTC_INT_ALARM :Clear alarm interrupt pending
- * @return None
- */
-STATIC INLINE void IP_RTC_ClearIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)
-{
- pRTC->ILR = IntType;
-}
-
-/**
- * @brief Check whether if specified location interrupt in the
- * RTC peripheral is set or not
- * @param pRTC : pointer to RTC peripheral block
- * @param IntType : Interrupt location type, should be:
- * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
- * - RTC_INT_ALARM: Alarm generated an interrupt.
- * @return Current state of specified interrupt in RTC peripheral, SET or RESET
- */
-STATIC INLINE IntStatus IP_RTC_GetIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)
-{
- return (pRTC->ILR & IntType) ? SET : RESET;
-}
-
-#if RTC_EV_SUPPORT
-
-/**
- * @brief Configure a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @param flag : configuration flag
- * @return None
- * @note Flags is or-ed bit values of RTC_ERCTRL_INTWAKE_EN,RTC_ERCTRL_GPCLEAR_EN,
- * RTC_ERCTRL_POL_POSITIVE and RTC_ERCTRL_INPUT_EN.
- */
-STATIC INLINE void IP_RTC_EV_Config(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, uint32_t flag)
-{
- uint32_t temp;
-
- temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK;
- pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK);
-}
-
-/**
- * @brief Enable/Disable Event Monitor/Recorder and select its operating clock
- * @param pRTC : pointer to RTC peripheral block
- * @param mode : selected mode
- * @return None
- */
-STATIC INLINE void IP_RTC_EV_SetMode(IP_RTC_001_T *pRTC, IP_RTC_EV_MODE_T mode)
-{
- uint32_t temp;
-
- temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK;
- pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode);
-}
-
-/**
- * @brief Get Event Monitor/Recorder Status
- * @param pRTC : pointer to RTC peripheral block
- * @return Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
- */
-STATIC INLINE uint32_t IP_RTC_EV_GetStatus(IP_RTC_001_T *pRTC)
-{
- return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
-}
-
-/**
- * @brief Clear Event Monitor/Recorder Status
- * @param pRTC : pointer to RTC peripheral block
- * @param flag : Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
- * @return Nothing
- */
-STATIC INLINE void IP_RTC_EV_ClearStatus(IP_RTC_001_T *pRTC, uint32_t flag)
-{
- pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
-}
-
-/**
- * @brief Get status of a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @return SET (At least 1 event occurred on the channel), RESET: no event occured.
- */
-STATIC INLINE FlagStatus IP_RTC_EV_GetChannelStatus(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)
-{
- return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET;
-}
-
-/**
- * @brief Clear status of a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @return Nothing.
- */
-STATIC INLINE void IP_RTC_EV_ClearChannelStatus(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)
-{
- pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch);
-}
-
-/**
- * @brief Get counter value of a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @return counter value
- */
-STATIC INLINE uint8_t IP_RTC_EV_GetCounter(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)
-{
- return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS);
-}
-
-/**
- * @brief Get first time stamp of a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @param pTimeStamp : pointer to Timestamp buffer
- * @return Nothing.
- */
-void IP_RTC_EV_GetFirstTimeStamp(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, IP_RTC_EV_TIMESTAMP_T *pTimeStamp);
-
-/**
- * @brief Get last time stamp of a specific event channel
- * @param pRTC : pointer to RTC peripheral block
- * @param ch : channel number
- * @param pTimeStamp : pointer to Timestamp buffer
- * @return Nothing.
- */
-void IP_RTC_EV_GetLastTimeStamp(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, IP_RTC_EV_TIMESTAMP_T *pTimeStamp);
-
-#endif /*RTC_EV_SUPPORT*/
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sct_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sct_001.h
deleted file mode 100644
index 415b93b93..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sct_001.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * @brief State Configurable Timer registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SCT_001_H_
-#define __SCT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SCT_001 IP: SCT register block and driver
- * @ingroup IP_Drivers
- * State Configurable Timer
- * @{
- */
-
-/**
- * @brief SCT Module configuration
- */
-#define CONFIG_SCT_nEV (16) /*!< Number of events */
-#define CONFIG_SCT_nRG (16) /*!< Number of match/compare registers */
-#define CONFIG_SCT_nOU (16) /*!< Number of outputs */
-
-/**
- * @brief State Configurable Timer register block structure
- */
-typedef struct {
- __IO uint32_t CONFIG; /*!< Configuration Register */
- union {
- __IO uint32_t CTRL_U; /*!< Control Register */
- struct {
- __IO uint16_t CTRL_L; /*!< Low control register */
- __IO uint16_t CTRL_H; /*!< High control register */
- };
-
- };
-
- __IO uint16_t LIMIT_L; /*!< limit register for counter L */
- __IO uint16_t LIMIT_H; /*!< limit register for counter H */
- __IO uint16_t HALT_L; /*!< halt register for counter L */
- __IO uint16_t HALT_H; /*!< halt register for counter H */
- __IO uint16_t STOP_L; /*!< stop register for counter L */
- __IO uint16_t STOP_H; /*!< stop register for counter H */
- __IO uint16_t START_L; /*!< start register for counter L */
- __IO uint16_t START_H; /*!< start register for counter H */
- uint32_t RESERVED1[10]; /*!< 0x03C reserved */
- union {
- __IO uint32_t COUNT_U; /*!< counter register */
- struct {
- __IO uint16_t COUNT_L; /*!< counter register for counter L */
- __IO uint16_t COUNT_H; /*!< counter register for counter H */
- };
-
- };
-
- __IO uint16_t STATE_L; /*!< state register for counter L */
- __IO uint16_t STATE_H; /*!< state register for counter H */
- __I uint32_t INPUT; /*!< input register */
- __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */
- __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */
- __IO uint32_t OUTPUT; /*!< output register */
- __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */
- __IO uint32_t RES; /*!< conflict resolution register */
- __IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */
- __IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */
- uint32_t RESERVED2[35];
- __IO uint32_t EVEN; /*!< event enable register */
- __IO uint32_t EVFLAG; /*!< event flag register */
- __IO uint32_t CONEN; /*!< conflict enable register */
- __IO uint32_t CONFLAG; /*!< conflict flag register */
- union {
- __IO union { /*!< ... Match / Capture value */
- uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTMATCH[i].L Access to L value */
- uint16_t H; /*!< SCTMATCH[i].H Access to H value */
- };
-
- } MATCH[CONFIG_SCT_nRG];
-
- __I union {
- uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTCAP[i].L Access to L value */
- uint16_t H; /*!< SCTCAP[i].H Access to H value */
- };
-
- } CAP[CONFIG_SCT_nRG];
-
- };
-
- uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /*!< ...-0x17C reserved */
- union {
- __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /*!< 0x180-... Match Value L counter */
- __I uint16_t CAP_L[CONFIG_SCT_nRG]; /*!< 0x180-... Capture Value L counter */
- };
-
- uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /*!< ...-0x1BE reserved */
- union {
- __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Match Value H counter */
- __I uint16_t CAP_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Capture Value H counter */
- };
-
- uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /*!< ...-0x1FE reserved */
- union {
- __IO union { /*!< 0x200-... Match Reload / Capture Control value */
- uint32_t U; /*!< SCTMATCHREL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTMATCHREL[i].L Access to L value */
- uint16_t H; /*!< SCTMATCHREL[i].H Access to H value */
- };
-
- } MATCHREL[CONFIG_SCT_nRG];
-
- __IO union {
- uint32_t U; /*!< SCTCAPCTRL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTCAPCTRL[i].L Access to L value */
- uint16_t H; /*!< SCTCAPCTRL[i].H Access to H value */
- };
-
- } CAPCTRL[CONFIG_SCT_nRG];
-
- };
-
- uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /*!< ...-0x27C reserved */
- union {
- __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Match Reload value L counter */
- __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Capture Control value L counter */
- };
-
- uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /*!< ...-0x2BE reserved */
- union {
- __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Match Reload value H counter */
- __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Capture Control value H counter */
- };
-
- uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /*!< ...-0x2FE reserved */
- __IO struct { /*!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
- uint32_t STATE; /*!< Event State Register */
- uint32_t CTRL; /*!< Event Control Register */
- } EVENT[CONFIG_SCT_nEV];
-
- uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */
- __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
- uint32_t SET; /*!< Output n Set Register */
- uint32_t CLR; /*!< Output n Clear Register */
- } OUT[CONFIG_SCT_nOU];
-
- uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */
- __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */
-} IP_SCT_001_T;
-
-/**
- * @brief Macro defines for SCT configuration register
- */
-#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */
-#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */
-
-#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */
-#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */
-#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */
-#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */
-
-#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */
-#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */
-
-/*
- * @brief Macro defines for SCT control register
- */
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
-
-#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */
-#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */
-#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */
-#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */
-#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */
-
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
-#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */
-#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */
-#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */
-#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
-#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */
-
-/*
- * @brief Macro defines for SCT Conflict resolution register
- */
-#define SCT_RES_NOCHANGE (0)
-#define SCT_RES_SET_OUTPUT (1)
-#define SCT_RES_CLEAR_OUTPUT (2)
-#define SCT_RES_TOGGLE_OUTPUT (3)
-
-/**
- * @brief Set the value in SCT unified count register
- * @param pSCT : Pointer to SCT register block
- * @param count : SCT count value
- * @return Nothing
- * @note Writes 32-bit value into SCT unified count register
- */
-STATIC INLINE void IP_SCT_SetCount(IP_SCT_001_T *pSCT, uint32_t count)
-{
- pSCT->COUNT_U = count;
-}
-
-/**
- * @brief Set the value in SCT Lower count register
- * @param pSCT : Pointer to SCT register block
- * @param count : SCT count value
- * @return Nothing
- * @note Writes 16-bit value into SCT Lower count register
- */
-STATIC INLINE void IP_SCT_SetCountL(IP_SCT_001_T *pSCT, uint16_t count)
-{
- pSCT->COUNT_L = count;
-}
-
-/**
- * @brief Set the value in SCT Higher count register
- * @param pSCT : Pointer to SCT register block
- * @param count : SCT count value
- * @return Nothing
- * @note Writes 16-bit value into SCT Higher count register
- */
-STATIC INLINE void IP_SCT_SetCountH(IP_SCT_001_T *pSCT, uint16_t count)
-{
- pSCT->COUNT_H = count;
-}
-
-/**
- * @brief Set the match value in SCT Unified match register
- * @param pSCT : Pointer to SCT register block
- * @param n : Match register number
- * @param count : SCT match count value
- * @return Nothing
- * @note Writes 32-bit value into SCT unified match register
- */
-STATIC INLINE void IP_SCT_SetMatchCount(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)
-{
- pSCT->MATCH[n].U = count;
-}
-
-/**
- * @brief Set the match reload value in SCT Unified match reload register
- * @param pSCT : Pointer to SCT register block
- * @param n : Match register number
- * @param count : SCT match reload count value
- * @return Nothing
- */
-STATIC INLINE void IP_SCT_SetMatchReload(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)
-{
- pSCT->MATCHREL[n].U = count;
-}
-
-/**
- * @brief Enable the interrupt for the specified event
- * @param pSCT : Pointer to SCT register block
- * @param evt : Event value
- * @return Nothing
- */
-STATIC INLINE void IP_SCT_EventIntEnable(IP_SCT_001_T *pSCT, uint32_t evt)
-{
- pSCT->EVEN |= evt;
-}
-
-/**
- * @brief Disable the interrupt for the specified event
- * @param pSCT : Pointer to SCT register block
- * @param evt : Event value
- * @return Nothing
- */
-STATIC INLINE void IP_SCT_EventIntDisable(IP_SCT_001_T *pSCT, uint32_t evt)
-{
- pSCT->EVEN &= ~(evt);
-}
-
-/**
- * @brief Clear the specified event flag
- * @param pSCT : Pointer to SCT register block
- * @param evt : Event value
- * @return Nothing
- */
-STATIC INLINE void IP_SCT_ClearEventFlag(IP_SCT_001_T *pSCT, uint32_t evt)
-{
- pSCT->EVFLAG |= evt;
-}
-
-/**
- * @brief Configure SCT
- * @param pSCT : Pointer to SCT register block
- * @param value : SCT Configuration register value
- * @return Nothing
- * @note Initialise the SCT configuration register with the \a value
- */
-void IP_SCT_Config(IP_SCT_001_T *pSCT, uint32_t value);
-
-/**
- * @brief Set or Clear the Control register
- * @param pSCT : Pointer to SCT register block
- * @param value : SCT Control register value
- * @param ena : ENABLE - To set the fields specified by value
- * : DISABLE - To clear the field specified by value
- * @return Nothing
- * @note Set or clear the control register bits as specified by \a value.
- * If \a ena is set to ENABLE, the mentioned register fields
- * will be set. If a\ ena is set to DISABLE, the mentioned register
- * fields will be cleared
- */
-void IP_SCT_ControlSetClr(IP_SCT_001_T *pSCT, uint32_t value, FunctionalState ena);
-
-/**
- * @brief Set the conflict resolution
- * @param pSCT : Pointer to SCT register block
- * @param outnum : Output number
- * @param value : Output value
- * - SCT_RES_NOCHANGE :No change
- * - SCT_RES_SET_OUTPUT :Set output
- * - SCT_RES_CLEAR_OUTPUT :Clear output
- * - SCT_RES_TOGGLE_OUTPUT :Toggle output
- * : SCT_RES_NOCHANGE
- * : DISABLE - To clear the field specified by value
- * @return Nothing
- * @note Set conflict resolution value for the output \a outnum
- */
-void IP_SCT_ConflictResolutionSet(IP_SCT_001_T *pSCT, uint8_t outnum, uint8_t value);
-
-/**
- * @brief Clear the SCT event flag
- * @param pSCT : Pointer to SCT register block
- * @param even_num : SCT Event number
- * @return Nothing
- * @note Clear the SCT event flag for the event \a even_num
- */
-void IP_SCT_EventFlagClear(IP_SCT_001_T *pSCT, uint8_t even_num);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SCT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdc_001.h
deleted file mode 100644
index 1831d5dc8..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdc_001.h
+++ /dev/null
@@ -1,555 +0,0 @@
-/*
- * @brief SD Card Interface Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDC_001_H_
-#define __SDC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SDC_001 IP: SDC register block and driver
- * @ingroup IP_Drivers
- * SD/MMC card Interface
- * @{
- */
-
-/**
- * @brief SD/MMC card Interface (SDC) register block structure
- */
-typedef struct {
- __IO uint32_t POWER; /*!< Power Control register */
- __IO uint32_t CLOCK; /*!< Clock control regsiter */
- __IO uint32_t ARGUMENT; /*!< Command argument register */
- __IO uint32_t COMMAND; /*!< Command register */
- __I uint32_t RESPCMD; /*!< Command response register */
- __I uint32_t RESPONSE[4]; /*!< Response registers */
- __IO uint32_t DATATIMER; /*!< Data timer register */
- __IO uint32_t DATALENGTH; /*!< Data length register */
- __IO uint32_t DATACTRL; /*!< Data control register */
- __I uint32_t DATACNT; /*!< Data count register */
- __I uint32_t STATUS; /*!< Status register */
- __O uint32_t CLEAR; /*!< Clear register */
- __IO uint32_t MASK0; /*!< Mask 0 register */
- uint32_t RESERVED0[2];
- __I uint32_t FIFOCNT; /*!< FIFO count register */
- uint32_t RESERVED1[13];
- __IO uint32_t FIFO[16]; /*!< FIFO registers */
-} IP_SDC_001_T;
-
-/**
- * @brief SDC Power Control Register bit definitions
- */
-/** SDC Power Control Register Bitmask */
-#define SDC_PWR_BITMASK ((uint32_t) 0xC3)
-/** SDC Power Control Bit Mask */
-#define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
-/** SDC Power Control */
-#define SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
-/** SD_CMD Output Control */
-#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
-/** Rod Control */
-#define SDC_PWR_ROD (((uint32_t) 1) << 7)
-
-/**
- * @brief SDC Clock Control Register bit definitions
- */
-/** SDC Clock Control Register Bitmask */
-#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
-/** SDC Clock Divider Bitmask */
-#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
-/** Set SDC Clock Divide value */
-#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
-
-/**
- * @brief SDC Command Register bit definitions
- */
-/** SDC Command Register Bitmask */
-#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
-/** SDC Command Index Bitmask */
-#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
-/** Set SDC Command Index */
-#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
-/** No response is expected */
-#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
-/** Short response is expected */
-#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
-/** Long response is expected */
-#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
-/** Response bit mask */
-#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
-/** Mark that command timer is disabled and CPSM waits for interrupt request */
-#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
-/** Mark that CPSM waits for CmdPend before starting sending a command*/
-#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
-/** Enable CPSM */
-#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
-
-/**
- * @brief SDC Command Response Register bit definitions
- */
-/** SDC Command Response value */
-#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
-
-/**
- * @brief SDC Data Length Register bit definitions
- */
-/** SDC Data Length set */
-#define SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
-
-/**
- * @brief SDC Data Control Register bit definitions
- */
-/** SDC Data Control Register Bitmask */
-#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
-/** Enable Data Transfer */
-#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
-/** Mark that Data is transfer from card to controller */
-#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
-/** Mark that Data is transfer from controller to card */
-#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
-/** Mark that the transfer mode is Stream Data Transfer */
-#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
-/** Mark that the transfer mode is Block Data Transfer */
-#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
-/** Enable DMA */
-#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
-/** Set Data Block size */
-#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
-/** Get Data Block size value */
-#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
-
-/**
- * @brief SDC Data Counter Register bit definitions
- */
-#define SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
-
-/**
- * @brief SDC Status Register bit definitions
- */
-/** Command Response received (CRC check failed) */
-#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
-/** Data block sent/received (CRC check failed). */
-#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
-/** Command response timeout.. */
-#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
-/** Data timeout. */
-#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
-/** Transmit FIFO underrun error. */
-#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
-/** Receive FIFO overrun error. */
-#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
-/** Command response received (CRC check passed). */
-#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
-/** Command sent (no response required).*/
-#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
-/** Data end (data counter is zero).*/
-#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
-/** Start bit not detected on all data signals in wide bus mode..*/
-#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
-/** Data block sent/received (CRC check passed).*/
-#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
-/** Command transfer in progress.*/
-#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
-/** Data transmit in progress.*/
-#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
-/** Data receive in progress.*/
-#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
-/** Transmit FIFO half empty.*/
-#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
-/** Receive FIFO half full.*/
-#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
-/** Transmit FIFO full.*/
-#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
-/** Receive FIFO full.*/
-#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
-/** Transmit FIFO empty.*/
-#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
-/** Receive FIFO empty.*/
-#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
-/** Data available in transmit FIFO.*/
-#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
-/** Data available in receive FIFO.*/
-#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
-/** Command Error Status */
-#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
-/** Data Error Status */
-#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
- | SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
-/** FIFO Status*/
-#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
- | SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
- | SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
- | SDC_STATUS_DATABLOCKEND)
-
-/** Data Transfer Status*/
-#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
-
-/**
- * @brief SDC Clear Register bit definitions
- */
-/** Clear all status flag*/
-#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
-/** Clears CmdCrcFail flag.*/
-#define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
-/** Clears DataCrcFail flag. */
-#define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
-/** Clears CmdTimeOut flag. */
-#define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
-/** Clears DataTimeOut flag. */
-#define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
-/** Clears TxUnderrun flag. */
-#define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
-/**Clears RxOverrun flag. */
-#define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
-/** Clears CmdRespEnd flag. */
-#define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
-/** Clears CmdSent flag.*/
-#define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
-/**Clears DataEnd flag.*/
-#define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
-/** Clears StartBitErr flag.*/
-#define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
-/** Clears DataBlockEnd flag.*/
-#define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
-
-/**
- * @brief SDC Interrupt Mask Register bit definitions
- */
-/** Mask CmdCrcFail flag.*/
-#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
-/** Mask DataCrcFail flag. */
-#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
-/** Mask CmdTimeOut flag. */
-#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
-/** Mask DataTimeOut flag. */
-#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
-/** Mask TxUnderrun flag. */
-#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
-/** Mask RxOverrun flag. */
-#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
-/** Mask CmdRespEnd flag. */
-#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
-/** Mask CmdSent flag.*/
-#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
-/** Mask DataEnd flag.*/
-#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
-/** Mask StartBitErr flag.*/
-#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
-/** Mask DataBlockEnd flag.*/
-#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
-/** Mask CmdActive flag.*/
-#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
-/** Mask TxActive flag.*/
-#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
-/** Mask RxActive flag.*/
-#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
-/** Mask TxFifoHalfEmpty flag.*/
-#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
-/** Mask RxFifoHalfFull flag.*/
-#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
-/** Mask TxFifoFull flag.*/
-#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
-/** Mask RxFifoFull flag.*/
-#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
-/** Mask TxFifoEmpty flag.*/
-#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
-/** Mask RxFifoEmpty flag.*/
-#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
-/** Mask TxDataAvlbl flag.*/
-#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
-/** Mask RxDataAvlbl flag.*/
-#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
-/** CMD error interrupt mask */
-#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
-/** Data Transmit Error interrupt mask */
-#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
- SDC_MASK0_STARTBITERR)
-
-/** Data Receive Error interrupt mask */
-#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
- SDC_MASK0_STARTBITERR)
-/** TX FIFO interrupt mask*/
-#define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
-/** RX FIFO interrupt mask*/
-#define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
-
-/** Data Transfer interrupt mask*/
-#define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
-
-/**
- * @brief SDC FIFO Counter Register bit definitions
- */
-#define SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
-
-/* The number of bytes used to store card status*/
-#define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)
-
-/**
- * @brief SDC Power Control Options
- */
-typedef enum IP_SDC_001_PWR_CTRL {
- SDC_POWER_OFF = 0, /*!< Power-off */
- SDC_POWER_UP = 2, /*!< Power-up */
- SDC_POWER_ON = 3, /*!< Power-on */
-} IP_SDC_001_PWR_CTRL_T;
-
-/**
- * @brief SDC Clock Control Options
- */
-typedef enum IP_SDC_001_CLOCK_CTRL {
- SDC_CLOCK_ENABLE = 8, /*!< Enable SD Card Bus Clock */
- SDC_CLOCK_POWER_SAVE = 9, /*!< Disable SD_CLK output when bus is idle */
- SDC_CLOCK_DIVIDER_BYPASS = 10, /*!< Enable bypass of clock divide logic */
- SDC_CLOCK_WIDEBUS_MODE = 11, /*!< Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0]) */
-} IP_SDC_001_CLOCK_CTRL_T;
-
-/**
- * @brief SDC Response type
- */
-typedef enum IP_SDC_001_RESPONSE {
- SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, /*!< No response */
- SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, /*!< Short response */
- SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP, /*!< Long response */
-} IP_SDC_001_RESPONSE_T;
-
-/**
- * @brief SDC Data Transfer Direction definitions
- */
-typedef enum IP_SDC_001_TRANSFER_DIR {
- SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, /*!< Transfer from card */
- SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD, /*!< Transfer to card */
-} IP_SDC_001_TRANSFER_DIR_T;
-
-/**
- * @brief SDC Data Transfer Mode definitions
- */
-typedef enum IP_SDC_001_TRANSFER_MODE {
- SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, /*!< Stream transfer mode */
- SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK, /*!< Block transfer mode */
-} IP_SDC_001_TRANSFER_MODE_T;
-
-/**
- * @brief SDC Data Block size definitions (in bytes)
- */
-typedef enum IP_SDC_001_BLOCK_SIZE {
- SDC_BLOCK_SIZE_1 = 0, /*!< Block size - 1 byte */
- SDC_BLOCK_SIZE_2, /*!< Block size - 2 bytes */
- SDC_BLOCK_SIZE_4, /*!< Block size - 4 bytes */
- SDC_BLOCK_SIZE_8, /*!< Block size - 8 bytes */
- SDC_BLOCK_SIZE_16, /*!< Block size - 16 bytes */
- SDC_BLOCK_SIZE_32, /*!< Block size - 32 bytes */
- SDC_BLOCK_SIZE_64, /*!< Block size - 64 bytes */
- SDC_BLOCK_SIZE_128, /*!< Block size - 128 bytes */
- SDC_BLOCK_SIZE_256, /*!< Block size - 256 bytes */
- SDC_BLOCK_SIZE_512, /*!< Block size - 512 bytes */
- SDC_BLOCK_SIZE_1024, /*!< Block size - 1024 bytes */
- SDC_BLOCK_SIZE_2048, /*!< Block size - 2048 bytes */
-} IP_SDC_001_BLOCK_SIZE_T;
-
-/**
- * @brief SDC Command Response structure
- */
-typedef struct {
- uint8_t CmdIndex; /*!< Command Index of the command response received */
- uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
-} IP_SDC_001_RESP_T;
-
-/**
- * @brief SDC Data Transfer Setup structure
- */
-typedef struct {
- uint16_t BlockNum; /*!< The number of block which will be transfered */
- IP_SDC_001_BLOCK_SIZE_T BlockSize; /*!< Data Block Length */
- IP_SDC_001_TRANSFER_DIR_T Dir; /*!< Direction */
- IP_SDC_001_TRANSFER_MODE_T Mode; /*!< Mode */
- bool DMAUsed; /*!< true: DMA used */
- uint32_t Timeout; /*!< Data Transfer timeout periods (in Card Bus Clock)*/
-} IP_SDC_001_DATA_TRANSFER_T;
-
-/**
- * @brief Set the power state of SDC peripheral
- * @param pSDC : Pointer to SDC register block
- * @param pwrMode : Power mode
- * @param flag : Output control flag
- * @return Nothing
- * @note When the external power supply is switched on, the software first enters the power-up
- * state, and waits until the supply output is stable before moving to the power-on state.
- * During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled
- * during both states.
- * flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD
- */
-void IP_SDC_PowerControl(IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag);
-
-/**
- * @brief Set clock divider value for SDC peripheral
- * @param pSDC : Pointer to SDC register block
- * @param div : clock divider
- * @return Nothing
- * @note While the SD card interface is in identification mode, the SD_CLK frequency must be less
- * than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
- * when relative card addresses are assigned to all cards.
- * SD_CLK frequency = MCLK / [2x(ClkDiv+1)].
- */
-void IP_SDC_SetClockDiv(IP_SDC_001_T *pSDC, uint8_t div);
-
-/**
- * @brief Set or Reset clock control of SDC peripheral
- * @param pSDC : Pointer to SDC register block
- * @param ctrlType : Clock Control type
- * @param NewState : New State to set
- * @return Nothing
- */
-void IP_SDC_ClockControl(IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType,
- FunctionalState NewState);
-
-/**
- * @brief Set SDC Command Information
- * @param pSDC : Pointer to SDC register block
- * @param Cmd : Command value
- * @param Arg : Argument for the command
- * @return Nothing
- */
-void IP_SDC_SetCommand(IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg);
-
-/**
- * @brief Reset SDC Command Information
- * @param pSDC : Pointer to SDC register block
- * @return Nothing
- */
-void IP_SDC_ResetCommand(IP_SDC_001_T *pSDC);
-
-/**
- * @brief Get SDC Response
- * @param pSDC : Pointer to SDC register block
- * @param pResp : Pointer to buffer storing response data
- * @return Nothing
- */
-void IP_SDC_GetResp(IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp);
-
-/**
- * @brief Set SDC Data Timeout Period
- * @param pSDC : Pointer to SDC register block
- * @param timeout : Data timeout value in card bus clock periods
- * @return Nothing
- */
-STATIC INLINE void IP_SDC_SetDataTimer(IP_SDC_001_T *pSDC, uint32_t timeout)
-{
- pSDC->DATATIMER = timeout;
-}
-
-/**
- * @brief Set SDC Data Transfer Information
- * @param pSDC : Pointer to SDC register block
- * @param pTransfer : Pointer to Data Transfer structure
- * @return Nothing
- */
-void IP_SDC_SetDataTransfer(IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer);
-
-/**
- * @brief Write Data to FIFO
- * @param pSDC : Pointer to SDC register block
- * @param pSrc : Pointer to data buffer
- * @param bFirstHalf : true (write to the first half of FIFO) false (write to the second half of FIFO)
- * @return Nothing
- */
-void IP_SDC_WriteFIFO(IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
-
-/**
- * @brief Write Data to FIFO
- * @param pSDC : Pointer to SDC register block
- * @param pDst : The buffer hold the data read
- * @param bFirstHalf : true (read the first half of FIFO) false (read the second half of FIFO)
- * @return Nothing
- */
-void IP_SDC_ReadFIFO(IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf);
-
-/**
- * @brief Get status of SDC Peripheral
- * @param pSDC : Pointer to SDC register block
- * @return Status (Or-ed bit value of SDC_STATUS_*)
- */
-STATIC INLINE uint32_t IP_SDC_GetStatus(IP_SDC_001_T *pSDC)
-{
- return pSDC->STATUS;
-}
-
-/**
- * @brief Clear status of SDC Peripheral
- * @param pSDC : Pointer to SDC register block
- * @param flag : Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)
- * @return None
- */
-STATIC INLINE void IP_SDC_ClearStatus(IP_SDC_001_T *pSDC, uint32_t flag)
-{
- pSDC->CLEAR = flag;
-}
-
-/**
- * @brief Set interrupt mask for SDC Peripheral
- * @param pSDC : Pointer to SDC register block
- * @param mask : Interrupt mask (Or-ed bit value of SDC_MASK0_*)
- * @return None
- */
-STATIC INLINE void IP_SDC_SetIntMask(IP_SDC_001_T *pSDC, uint32_t mask)
-{
- pSDC->MASK0 = mask;
-}
-
-/**
- * @brief Initialize the SDC card controller
- * @param pSDC : Pointer to SDC register block
- * @return None
- */
-void IP_SDC_Init(IP_SDC_001_T *pSDC);
-
-/**
- * @brief Deinitialise the SDC peripheral
- * @param pSDC : Pointer to SDC register block
- * @return None
- */
-STATIC INLINE void IP_SDC_DeInit(IP_SDC_001_T *pSDC)
-{
- IP_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdmmc_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdmmc_001.h
deleted file mode 100644
index 653eb503d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sdmmc_001.h
+++ /dev/null
@@ -1,439 +0,0 @@
-/*
- * @brief SD/SDIO (MCI) registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SDMMC_001_H_
-#define __SDMMC_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SDMMC_001 IP: SDMMC register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SD/MMC & SDIO register block structure
- */
-typedef struct { /*!< SDMMC Structure */
- __IO uint32_t CTRL; /*!< Control Register */
- __IO uint32_t PWREN; /*!< Power Enable Register */
- __IO uint32_t CLKDIV; /*!< Clock Divider Register */
- __IO uint32_t CLKSRC; /*!< SD Clock Source Register */
- __IO uint32_t CLKENA; /*!< Clock Enable Register */
- __IO uint32_t TMOUT; /*!< Timeout Register */
- __IO uint32_t CTYPE; /*!< Card Type Register */
- __IO uint32_t BLKSIZ; /*!< Block Size Register */
- __IO uint32_t BYTCNT; /*!< Byte Count Register */
- __IO uint32_t INTMASK; /*!< Interrupt Mask Register */
- __IO uint32_t CMDARG; /*!< Command Argument Register */
- __IO uint32_t CMD; /*!< Command Register */
- __I uint32_t RESP0; /*!< Response Register 0 */
- __I uint32_t RESP1; /*!< Response Register 1 */
- __I uint32_t RESP2; /*!< Response Register 2 */
- __I uint32_t RESP3; /*!< Response Register 3 */
- __I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */
- __IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */
- __I uint32_t STATUS; /*!< Status Register */
- __IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */
- __I uint32_t CDETECT; /*!< Card Detect Register */
- __I uint32_t WRTPRT; /*!< Write Protect Register */
- __IO uint32_t GPIO; /*!< General Purpose Input/Output Register */
- __I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */
- __I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */
- __IO uint32_t DEBNCE; /*!< Debounce Count Register */
- __IO uint32_t USRID; /*!< User ID Register */
- __I uint32_t VERID; /*!< Version ID Register */
- __I uint32_t RESERVED0;
- __IO uint32_t UHS_REG; /*!< UHS-1 Register */
- __IO uint32_t RST_N; /*!< Hardware Reset */
- __I uint32_t RESERVED1;
- __IO uint32_t BMOD; /*!< Bus Mode Register */
- __O uint32_t PLDMND; /*!< Poll Demand Register */
- __IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */
- __IO uint32_t IDSTS; /*!< Internal DMAC Status Register */
- __IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */
- __I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */
- __I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */
-} IP_SDMMC_001_T;
-
-/** @brief SDIO DMA descriptor control (des0) register defines
- */
-#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */
-#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */
-#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */
-#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */
-#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */
-#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */
-#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */
-
-/** @brief SDIO DMA descriptor size (des1) register defines
- */
-#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
-#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
-#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
-
-/** @brief SDIO control register defines
- */
-#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */
-#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */
-#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */
-#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */
-#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */
-#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */
-#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */
-#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */
-#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */
-#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */
-#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */
-#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */
-
-/** @brief SDIO Power Enable register defines
- */
-#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */
-
-/** @brief SDIO Clock divider register defines
- */
-#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */
-
-/** @brief SDIO Clock source register defines
- */
-#define MCI_CLKSRC_CLKDIV0 0
-#define MCI_CLKSRC_CLKDIV1 1
-#define MCI_CLKSRC_CLKDIV2 2
-#define MCI_CLKSRC_CLKDIV3 3
-#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */
-
-/** @brief SDIO Clock Enable register defines
- */
-#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */
-#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */
-
-/** @brief SDIO time-out register defines
- */
-#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */
-#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
-#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
-#define MCI_TMOUT_RESP_MSK 0xFF
-
-/** @brief SDIO card-type register defines
- */
-#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */
-#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */
-
-/** @brief SDIO Interrupt status & mask register defines
- */
-#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */
-#define MCI_INT_EBE (1 << 15) /*!< End-bit error */
-#define MCI_INT_ACD (1 << 14) /*!< Auto command done */
-#define MCI_INT_SBE (1 << 13) /*!< Start bit error */
-#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */
-#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */
-#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */
-#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */
-#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */
-#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */
-#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */
-#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */
-#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */
-#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */
-#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */
-#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */
-#define MCI_INT_CD (1 << 0) /*!< Card detect */
-
-/** @brief SDIO Command register defines
- */
-#define MCI_CMD_START (1UL << 31) /*!< Start command */
-#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */
-#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */
-#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */
-#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */
-#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */
-#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */
-#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */
-#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */
-#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */
-#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */
-#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */
-#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */
-#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */
-#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */
-#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */
-#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */
-#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */
-#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */
-#define MCI_CMD_INDX(n) ((n) & 0x1F)
-
-/** @brief SDIO status register definess
- */
-#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
-
-/** @brief SDIO FIFO threshold defines
- */
-#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
-#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
-#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
-#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
-#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
-#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
-#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
-#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
-#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
-#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
-
-/** @brief Bus mode register defines
- */
-#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */
-#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */
-#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */
-#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */
-#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */
-#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */
-#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */
-#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */
-#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */
-#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */
-#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */
-#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */
-
-/** @brief Commonly used definitions
- */
-#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */
-
-/** Function prototype for SD interface IRQ callback */
-typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
-
-/** Function prototype for SD detect and write protect status check */
-typedef int32_t (*PSCHECK_FUNC_T)(void);
-
-/** Function prototype for SD slot power enable or slot reset */
-typedef void (*PS_POWER_FUNC_T)(int32_t enable);
-
-/** @brief SDIO chained DMA descriptor
- */
-typedef struct {
- volatile uint32_t des0; /*!< Control and status */
- volatile uint32_t des1; /*!< Buffer size(s) */
- volatile uint32_t des2; /*!< Buffer address pointer 1 */
- volatile uint32_t des3; /*!< Buffer address pointer 2 */
-} pSDMMC_DMA_T;
-
-/** @brief SDIO device type
- */
-typedef struct _sdif_device {
- /* MCI_IRQ_CB_FUNC_T irq_cb; */
- pSDMMC_DMA_T mci_dma_dd[1 + (0x100000 / MCI_DMADES1_MAXTR)];
- /* uint32_t sdio_clk_rate; */
- /* uint32_t sdif_slot_clk_rate; */
- /* int32_t clock_enabled; */
-} sdif_device;
-
-/**
- * @brief Initializes the MCI card controller
- * @param pSDMMC Pointer to IP_SDMMC_001_T structure
- * @return None
- */
-void IP_SDMMC_Init(IP_SDMMC_001_T *pSDMMC);
-
-/**
- * @brief Close the MCI
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return None
- */
-void IP_SDMMC_DeInit(IP_SDMMC_001_T *pSDMMC);
-
-/**
- * @brief Set block size for transfer
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param bytes : block size in bytes
- * @return None
- */
-void IP_SDMMC_SetBlkSize(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);
-
-/**
- * @brief Reset card in slot
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param reset : Sets SD_RST to passed state
- * @return None
- * @note Reset card in slot, must manually de-assert reset after assertion
- * (Uses SD_RST pin, set per reset parameter state)
- */
-void IP_SDMMC_Reset(IP_SDMMC_001_T *pSDMMC, int32_t reset);
-
-/**
- * @brief Enable slot power
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return None
- * @note Uses SD_POW pin, set to high.
- */
-STATIC INLINE void IP_SDMMC_PowerOn(IP_SDMMC_001_T *pSDMMC)
-{
- pSDMMC->PWREN = 1;
-}
-
-/**
- * @brief Disable slot power
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return None
- * @note Uses SD_POW pin, set to low.
- */
-STATIC INLINE void IP_SDMMC_PowerOff(IP_SDMMC_001_T *pSDMMC)
-{
- pSDMMC->PWREN = 0;
-}
-
-/**
- * @brief Detect if write protect is enabled
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return Returns 1 if card is write protected, otherwise 0
- * @note Detect if write protect is enabled
- * (uses SD_WP pin, returns 1 if card is write protected)
- */
-STATIC INLINE int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_T *pSDMMC)
-{
- return (pSDMMC->WRTPRT & 1);
-}
-
-/**
- * @brief Detect if an SD card is inserted
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return Returns 0 if a card is detected, otherwise 1
- * @note Detect if an SD card is inserted
- * (uses SD_CD pin, returns 0 on card detect)
- */
-STATIC INLINE int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_T *pSDMMC)
-{
- return (pSDMMC->CDETECT & 1);
-}
-
-/**
- * @brief Function to send command to Card interface unit (CIU)
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param cmd : Command with all flags set
- * @param arg : Argument for the command
- * @return TRUE on times-out, otherwise FALSE
- */
-int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_T *pSDMMC, uint32_t cmd, uint32_t arg);
-
-/**
- * @brief Read the response from the last command
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param resp : Pointer to response array to fill
- * @return None
- */
-void IP_SDMMC_GetResponse(IP_SDMMC_001_T *pSDMMC, uint32_t *resp);
-
-/**
- * @brief Sets the SD bus clock speed
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param clk_rate : Input clock rate into the IP block
- * @param speed : Desired clock speed to the card
- * @return None
- */
-void IP_SDMMC_SetClock(IP_SDMMC_001_T *pSDMMC, uint32_t clk_rate, uint32_t speed);
-
-/**
- * @brief Function to set card type
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param ctype : card type
- * @return None
- */
-void IP_SDMMC_SetCardType(IP_SDMMC_001_T *pSDMMC, uint32_t ctype);
-
-/**
- * @brief Function to clear interrupt & FIFOs
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return None
- */
-void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_T *pSDMMC);
-
-/**
- * @brief Returns the raw SD interface interrupt status
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @return Raw interrupt status of Or'ed values MCI_INT_*
- */
-uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_T *pSDMMC);
-
-/**
- * @brief Sets the raw SD interface interrupt status
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param iVal : Raw interrupts to set, Or'ed values MCI_INT_*
- * @return None
- */
-void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);
-
-/**
- * @brief Sets the SD interface interrupt mask
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param iVal : Interrupts to enable, Or'ed values MCI_INT_*
- * @return None
- */
-void IP_SDMMC_SetIntMask(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);
-
-/**
- * @brief Setup DMA descriptors
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param psdif_dev : SD interface device
- * @param addr : Address of buffer (source or destination)
- * @param size : size of buffer in bytes (64K max)
- * @return None
- */
-void IP_SDMMC_DmaSetup(IP_SDMMC_001_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);
-
-/**
- * @brief Set block size and byte count for transfer
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param blk_size: block size and byte count in bytes
- * @return None
- */
-void IP_SDMMC_SetBlkSizeByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t blk_size);
-
-/**
- * @brief Set byte count for transfer
- * @param pSDMMC : Pointer to IP_SDMMC_001_T structure
- * @param bytes : block size and byte count in bytes
- * @return None
- */
-void IP_SDMMC_SetByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SDMMC_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sgpio_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sgpio_001.h
deleted file mode 100644
index aefdeb3a7..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/sgpio_001.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * @brief Serial GPIO registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SGPIO_001_H_
-#define __SGPIO_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SGPIO_001 IP: SGPIO register block and driver
- * @ingroup IP_Drivers
- * Serial GPIO
- * @{
- */
-
-/**
- * @brief Serial GPIO register block structure
- */
-typedef struct { /*!< SGPIO Structure */
- __IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */
- __IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */
- __IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */
- __IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
- __IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
- __IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
- __IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */
- __IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */
- __IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */
- __IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */
- __IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */
- __IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */
- __I uint32_t GPIO_INREG; /*!< GPIO input status register */
- __IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */
- __IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */
- __IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */
- __IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */
- __I uint32_t RESERVED0[823];
- __O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */
- __O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */
- __I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */
- __I uint32_t STATUS_0; /*!< Shift clock interrupt status */
- __O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */
- __O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */
- __I uint32_t RESERVED1[2];
- __O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */
- __O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */
- __I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */
- __I uint32_t STATUS_1; /*!< Capture clock interrupt status */
- __O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */
- __O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */
- __I uint32_t RESERVED2[2];
- __O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */
- __O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */
- __I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */
- __I uint32_t STATUS_2; /*!< Pattern match interrupt status */
- __O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */
- __O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */
- __I uint32_t RESERVED3[2];
- __O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */
- __O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */
- __I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */
- __I uint32_t STATUS_3; /*!< Input bit match interrupt status */
- __O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */
- __O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */
-} IP_SGPIO_001_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SGPIO_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/spi_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/spi_001.h
deleted file mode 100644
index 127af15a4..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/spi_001.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * @brief SPI registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SPI_001_H_
-#define __SPI_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SPI_001 IP: SPI register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SPI register block structure
- */
-typedef struct { /*!< SPI Structure */
- __IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */
- __I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */
- __IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
- __IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
-} IP_SPI_001_T;
-
-/*
- * Macro defines for SPI Control register
- */
-/* SPI CFG Register BitMask */
-#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
-/** Enable of controlling the number of bits per transfer */
-#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
-/** Mask of field of bit controlling */
-#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
-/** Set the number of bits per a transfer */
-#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
-/** SPI Clock Phase Select*/
-#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
-#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
-/** SPI Clock Polarity Select*/
-#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
-#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
-/** SPI Slave Mode Select */
-#define SPI_CR_SLAVE_EN ((uint32_t) 0)
-/** SPI Master Mode Select */
-#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
-/** SPI MSB First mode enable */
-#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
-/** SPI LSB First mode enable */
-#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
-/** SPI interrupt enable */
-#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
-
-/*
- * Macro defines for SPI Status register
- */
-/** SPI STAT Register BitMask */
-#define SPI_SR_BITMASK ((uint32_t) 0xF8)
-/** Slave abort Flag */
-#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
-/* Mode fault Flag */
-#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
-/** Read overrun flag*/
-#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
-/** Write collision flag. */
-#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
-/** SPI transfer complete flag. */
-#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
-/** SPI error flag */
-#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
-/*
- * Macro defines for SPI Test Control Register register
- */
-/*Enable SPI Test Mode */
-#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
-
-/*
- * Macro defines for SPI Interrupt register
- */
-/** SPI interrupt flag */
-#define SPI_INT_SPIF ((uint32_t) (1 << 0))
-
-/**
- * Macro defines for SPI Data register
- */
-/** Receiver Data */
-#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
-
-/** @brief SPI Mode*/
-typedef enum IP_SPI_MODE {
- SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
- SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
-} IP_SPI_MODE_T;
-
-/** @brief SPI Clock Mode*/
-typedef enum IP_SPI_CLOCK_MODE {
- SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */
- SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */
- SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */
- SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */
- SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */
- SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */
- SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */
- SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */
-} IP_SPI_CLOCK_MODE_T;
-
-/** @brief SPI Data Order Mode*/
-typedef enum IP_SPI_DATA_ORDER {
- SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
- SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
-} IP_SPI_DATA_ORDER_T;
-
-/*
- * @brief Number of bits per frame
- */
-typedef enum IP_SPI_BITS {
- SPI_BITS_8 = SPI_CR_BITS(8), /**< 8 bits/frame */
- SPI_BITS_9 = SPI_CR_BITS(9), /**< 9 bits/frame */
- SPI_BITS_10 = SPI_CR_BITS(10), /**< 10 bits/frame */
- SPI_BITS_11 = SPI_CR_BITS(11), /**< 11 bits/frame */
- SPI_BITS_12 = SPI_CR_BITS(12), /**< 12 bits/frame */
- SPI_BITS_13 = SPI_CR_BITS(13), /**< 13 bits/frame */
- SPI_BITS_14 = SPI_CR_BITS(14), /**< 14 bits/frame */
- SPI_BITS_15 = SPI_CR_BITS(15), /**< 15 bits/frame */
- SPI_BITS_16 = SPI_CR_BITS(16), /**< 16 bits/frame */
-} IP_SPI_BITS_T;
-
-/**
- * @brief Get the current status of SPI controller
- * @param pSPI : The base of SPI peripheral on the chip
- * @return SPI Status (Or-ed bit value of SPI_SR_*)
- * @note See user manual about how status bits are cleared.
- */
-STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_001_T *pSPI)
-{
- return pSPI->SR;
-}
-
-/**
- * @brief Enable the interrupt for the SPI
- * @param pSPI : The base of SPI peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void IP_SPI_IntEnable(IP_SPI_001_T *pSPI)
-{
- pSPI->CR |= SPI_CR_INT_EN;
-}
-
-/**
- * @brief Disable the interrupt for the SPI
- * @param pSPI : The base of SPI peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void IP_SPI_IntDisable(IP_SPI_001_T *pSPI)
-{
- pSPI->CR &= ~SPI_CR_INT_EN;
-}
-
-/**
- * @brief Get the interrupt status
- * @param pSPI : The base of SPI peripheral on the chip
- * @return SPI interrupt Status (Or-ed bit value of SPI_INT_*)
- */
-STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_001_T *pSPI)
-{
- return pSPI->INT;
-}
-
-/**
- * @brief Clear the interrupt status
- * @param pSPI : The base of SPI peripheral on the chip
- * @param mask : SPI interrupt mask (Or-ed bit value of SPI_INT_*)
- * @return Nothing
- */
-STATIC INLINE void IP_SPI_ClearIntStatus(IP_SPI_001_T *pSPI, uint32_t mask)
-{
- pSPI->INT = mask;
-}
-
-/**
- * @brief Send SPI 16-bit data
- * @param pSPI : The base of SPI peripheral on the chip
- * @param data : Transmit Data
- * @return Nothing
- */
-STATIC INLINE void IP_SPI_SendFrame(IP_SPI_001_T *pSPI, uint16_t data)
-{
- pSPI->DR = SPI_DR_DATA(data);
-}
-
-/**
- * @brief Get received SPI data
- * @param pSPI : The base of SPI peripheral on the chip
- * @return receive data
- */
-STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_001_T *pSPI)
-{
- return SPI_DR_DATA(pSPI->DR);
-}
-
-/**
- * @brief Set up output clocks per bit for SPI bus
- * @param pSPI : The base of SPI peripheral on the chip
- * @param counter : the number of SPI peripheral clock cycles that make up an SPI clock
- * @return Nothing
- * @note The counter must be an even number greater than or equal to 8.
- * The SPI SCK rate = PCLK_SPI / counter.
- */
-STATIC INLINE void IP_SPI_SetClockCounter(IP_SPI_001_T *pSPI, uint32_t counter)
-{
- pSPI->CCR = counter;
-}
-
-/**
- * @brief Set up the SPI frame format
- * @param pSPI : The base of SPI peripheral on the chip
- * @param bits : The number of bits transferred in each frame.
- * @param clockMode : Select Clock polarity and Clock phase, should be :
- * - SPI_CLOCK_CPHA0_CPOL0
- * - SPI_CLOCK_CPHA0_CPOL1
- * - SPI_CLOCK_CPHA1_CPOL0
- * - SPI_CLOCK_CPHA1_CPOL1
- * or SPI_CLOCK_MODE*
- * @param order : Data order (MSB first/LSB first).
- * @return Nothing
- * @note Note: The clockFormat is only used in SPI mode
- */
-STATIC INLINE void IP_SPI_SetFormat(IP_SPI_001_T *pSPI, IP_SPI_BITS_T bits,
- IP_SPI_CLOCK_MODE_T clockMode, IP_SPI_DATA_ORDER_T order)
-{
- pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | bits | clockMode | order;
-}
-
-/**
- * @brief Get the number of bits transferred in each frame
- * @param pSPI : The base of SPI peripheral on the chip
- * @return the number of bits transferred in each frame
- */
-STATIC INLINE IP_SPI_BITS_T IP_SPI_GetDataSize(IP_SPI_001_T *pSPI)
-{
- return (pSPI->CR & SPI_CR_BIT_EN) ? ((IP_SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
-}
-
-/**
- * @brief Get the current CPHA & CPOL setting
- * @param pSPI : The base of SPI peripheral on the chip
- * @return CPHA & CPOL setting
- */
-STATIC INLINE IP_SPI_CLOCK_MODE_T IP_SPI_GetClockMode(IP_SPI_001_T *pSPI)
-{
- return (IP_SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
-}
-
-/**
- * @brief Set the SPI working as master or slave mode
- * @param pSPI : The base of SPI peripheral on the chip
- * @param mode : Operating mode
- * @return Nothing
- */
-STATIC INLINE void IP_SPI_SetMode(IP_SPI_001_T *pSPI, IP_SPI_MODE_T mode)
-{
- pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
-}
-
-/**
- * @brief Set the SPI working as master or slave mode
- * @param pSPI : The base of SPI peripheral on the chip
- * @return Operating mode
- */
-STATIC INLINE IP_SPI_MODE_T IP_SPI_GetMode(IP_SPI_001_T *pSPI)
-{
- return (IP_SPI_MODE_T) (pSPI->CR & (1 << 5));
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SPI_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ssp_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ssp_001.h
deleted file mode 100644
index 6873229f2..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/ssp_001.h
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * @brief SSP Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __SSP_001_H_
-#define __SSP_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_SSP_001 IP: SSP register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief SSP register block structure
- */
-typedef struct { /*!< SSPn Structure */
- __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /*!< Status Register */
- __IO uint32_t CPSR; /*!< Clock Prescale Register */
- __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /*!< Raw Interrupt Status Register */
- __I uint32_t MIS; /*!< Masked Interrupt Status Register */
- __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
-#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
- !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
- __IO uint32_t DMACR; /*!< SSPn DMA control register */
-#endif
-} IP_SSP_001_T;
-
-/**
- * Macro defines for CR0 register
- */
-
-/** SSP data size select, must be 4 bits to 16 bits */
-#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
-/** SSP control 0 Motorola SPI mode */
-#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
-/** SSP control 0 TI synchronous serial mode */
-#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
-/** SSP control 0 National Micro-wire mode */
-#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
-/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
- bus clock high between frames, (0) = low */
-#define SSP_CR0_CPOL_LO ((uint32_t) (0))
-#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
-/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
- on the second clock transition of the frame, (0) = first */
-#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
-#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
-/** SSP serial clock rate value load macro, divider rate is
- PERIPH_CLK / (cpsr * (SCR + 1)) */
-#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
-/** SSP CR0 bit mask */
-#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
-/** SSP CR0 bit mask */
-#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
-/** SSP serial clock rate value load macro, divider rate is
- PERIPH_CLK / (cpsr * (SCR + 1)) */
-#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
-
-/**
- * Macro defines for CR1 register
- */
-
-/** SSP control 1 loopback mode enable bit */
-#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
-/** SSP control 1 enable bit */
-#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
-/** SSP control 1 slave enable */
-#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
-#define SSP_CR1_MASTER_EN ((uint32_t) (0))
-/** SSP control 1 slave out disable bit, disables transmit line in slave
- mode */
-#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
-/** SSP CR1 bit mask */
-#define SSP_CR1_BITMASK ((uint32_t) (0x0F))
-
-/** SSP CPSR bit mask */
-#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
-/**
- * Macro defines for DR register
- */
-
-/** SSP data bit mask */
-#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
-
-/**
- * Macro defines for SR register
- */
-
-/** SSP SR bit mask */
-#define SSP_SR_BITMASK ((uint32_t) (0x1F))
-
-/** ICR bit mask */
-#define SSP_ICR_BITMASK ((uint32_t) (0x03))
-
-/**
- * @brief SSP Type of Status
- */
-typedef enum IP_SSP_STATUS {
- SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
- SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
- SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
- SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
- SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
-} IP_SSP_STATUS_T;
-
-/**
- * @brief SSP Type of Interrupt Mask
- */
-typedef enum IP_SSP_INTMASK {
- SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */
- SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
- SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
- SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
- SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
-} IP_SSP_INTMASK_T;
-
-/**
- * @brief SSP Type of Mask Interrupt Status
- */
-typedef enum IP_SSP_MASKINTSTATUS {
- SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */
- SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */
- SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
- SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
- SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
-} IP_SSP_MASKINTSTATUS_T;
-
-/**
- * @brief SSP Type of Raw Interrupt Status
- */
-typedef enum IP_SSP_RAWINTSTATUS {
- SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */
- SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */
- SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
- SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
- SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
-} IP_SSP_RAWINTSTATUS_T;
-
-typedef enum IP_SSP_INTCLEAR {
- SSP_RORIC = 0x0,
- SSP_RTIC = 0x1,
- SSP_INT_CLEAR_BITMASK = 0x3,
-} IP_SSP_INTCLEAR_T;
-
-typedef enum IP_SSP_DMA {
- SSP_DMA_RX = (1u), /**< DMA RX Enable */
- SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */
- SSP_DMA_BITMASK = ((uint32_t)(0x3)),
-} IP_SSP_DMA_T;
-
-/**
- * @brief Disable SSP operation
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- * @note The SSP controller is disabled
- */
-STATIC INLINE void IP_SSP_DeInit(IP_SSP_001_T *pSSP)
-{
- pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
-}
-
-/**
- * @brief Enable SSP operation
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_Enable(IP_SSP_001_T *pSSP)
-{
- pSSP->CR1 |= SSP_CR1_SSP_EN;
-}
-
-/**
- * @brief Disable SSP operation
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_Disable(IP_SSP_001_T *pSSP)
-{
- pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
-}
-
-/**
- * @brief Enable loopback mode
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- * @note Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-STATIC INLINE void IP_SSP_EnableLoopBack(IP_SSP_001_T *pSSP)
-{
- pSSP->CR1 |= SSP_CR1_LBM_EN;
-}
-
-/**
- * @brief Disable loopback mode
- * @param pSSP : The base of SSP peripheral on the chip
- * @return Nothing
- * @note Serial input is taken from the serial output (MOSI or MISO) rather
- * than the serial input pin
- */
-STATIC INLINE void IP_SSP_DisableLoopBack(IP_SSP_001_T *pSSP)
-{
- pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
-}
-
-/**
- * @brief Get the current status of SSP controller
- * @param pSSP : The base of SSP peripheral on the chip
- * @param Stat : Type of status, should be :
- * - SSP_STAT_TFE
- * - SSP_STAT_TNF
- * - SSP_STAT_RNE
- * - SSP_STAT_RFF
- * - SSP_STAT_BSY
- * @return SSP controller status, SET or RESET
- */
-STATIC INLINE FlagStatus IP_SSP_GetStatus(IP_SSP_001_T *pSSP, IP_SSP_STATUS_T Stat)
-{
- return (pSSP->SR & Stat) ? SET : RESET;
-}
-
-/**
- * @brief Get the masked interrupt status
- * @param pSSP : The base of SSP peripheral on the chip
- * @return SSP Masked Interrupt Status Register value
- * @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
- */
-STATIC INLINE uint32_t IP_SSP_GetIntStatus(IP_SSP_001_T *pSSP)
-{
- return pSSP->MIS;
-}
-
-/**
- * @brief Get the raw interrupt status
- * @param pSSP : The base of SSP peripheral on the chip
- * @param RawInt : Interrupt condition to be get status, shoud be :
- * - SSP_RORRIS
- * - SSP_RTRIS
- * - SSP_RXRIS
- * - SSP_TXRIS
- * @return Raw interrupt status corresponding to interrupt condition , SET or RESET
- * @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
- */
-STATIC INLINE IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_T *pSSP, IP_SSP_RAWINTSTATUS_T RawInt)
-{
- return (pSSP->RIS & RawInt) ? SET : RESET;
-}
-
-/**
- * @brief Get the number of bits transferred in each frame
- * @param pSSP : The base of SSP peripheral on the chip
- * @return the number of bits transferred in each frame minus one
- * @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
- */
-STATIC INLINE uint8_t IP_SSP_GetDataSize(IP_SSP_001_T *pSSP)
-{
- return SSP_CR0_DSS(pSSP->CR0);
-}
-
-/**
- * @brief Clear the corresponding interrupt condition(s) in the SSP controller
- * @param pSSP : The base of SSP peripheral on the chip
- * @param IntClear: Type of cleared interrupt, should be :
- * - SSP_RORIC
- * - SSP_RTIC
- * @return Nothing
- * @note Software can clear one or more interrupt condition(s) in the SSP controller
- */
-STATIC INLINE void IP_SSP_ClearIntPending(IP_SSP_001_T *pSSP, IP_SSP_INTCLEAR_T IntClear)
-{
- pSSP->ICR = IntClear;
-}
-
-/**
- * @brief Enable interrupt for the SSP
- * @param pSSP : The base of SSP peripheral on the chip
- * @param IntType : Type of interrupt condition to be enable/disable, should be :
- * - SSP_RORIM
- * - SSP_RTIM
- * - SSP_RXIM
- * - SSP_TXIM
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_Int_Enable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
-{
- pSSP->IMSC |= IntType;
-}
-
-/**
- * @brief Disable interrupt for the SSP
- * @param pSSP : The base of SSP peripheral on the chip
- * @param IntType : Type of interrupt condition to be enable/disable, should be :
- * - SSP_RORIM
- * - SSP_RTIM
- * - SSP_RXIM
- * - SSP_TXIM
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_Int_Disable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)
-{
- pSSP->IMSC &= (~IntType);
-}
-
-/**
- * @brief Get received SSP data
- * @param pSSP : The base of SSP peripheral on the chip
- * @return SSP 16-bit data received
- */
-STATIC INLINE uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_T *pSSP)
-{
- return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
-}
-
-/**
- * @brief Send SSP 16-bit data
- * @param pSSP : The base of SSP peripheral on the chip
- * @param tx_data : SSP 16-bit data to be transmited
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_SendFrame(IP_SSP_001_T *pSSP, uint16_t tx_data)
-{
- pSSP->DR = SSP_DR_BITMASK(tx_data);
-}
-
-/**
- * @brief Set up output clocks per bit for SSP bus
- * @param pSSP : The base of SSP peripheral on the chip
- * @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one
- * @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK
- * @return Nothing
- * @note The bit frequency is PCLK / (prescale x[clk_rate+1])
- */
-void IP_SSP_Set_ClockRate(IP_SSP_001_T *pSSP, uint32_t clk_rate, uint32_t prescale);
-
-/**
- * @brief Set up the SSP frame format
- * @param pSSP : The base of SSP peripheral on the chip
- * @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
- * @param frameFormat : Frame format, should be :
- * - SSP_FRAMEFORMAT_SPI
- * - SSP_FRAME_FORMAT_TI
- * - SSP_FRAMEFORMAT_MICROWIRE
- * @param clockMode : Select Clock polarity and Clock phase, should be :
- * - SSP_CLOCK_CPHA0_CPOL0
- * - SSP_CLOCK_CPHA0_CPOL1
- * - SSP_CLOCK_CPHA1_CPOL0
- * - SSP_CLOCK_CPHA1_CPOL1
- * @return Nothing
- * @note Note: The clockFormat is only used in SPI mode
- */
-STATIC INLINE void IP_SSP_SetFormat(IP_SSP_001_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
-{
- pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
-}
-
-/**
- * @brief Set the SSP working as master or slave mode
- * @param pSSP : The base of SSP peripheral on the chip
- * @param mode : Operating mode, should be
- * - SSP_MODE_MASTER
- * - SSP_MODE_SLAVE
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_Set_Mode(IP_SSP_001_T *pSSP, uint32_t mode)
-{
- pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
-}
-
-#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
- !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
-/**
- * @brief Enable DMA for SSP
- * @param pSSP : The base of SSP peripheral on the chip
- * @param flag : DMA flag for transmit/receive SSP, should be
- * - SSP_DMA_RX
- * - SSP_DMA_TX
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_DMA_Enable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
-{
- pSSP->DMACR |= flag;
-}
-
-/**
- * @brief Disable DMA for SSP
- * @param pSSP : The base of SSP peripheral on the chip
- * @param flag : DMA flag for transmit/receive SSP, should be
- * - SSP_DMA_RX
- * - SSP_DMA_TX
- * @return Nothing
- */
-STATIC INLINE void IP_SSP_DMA_Disable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)
-{
- pSSP->DMACR &= ~flag;
-}
-
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SSP_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/timer_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/timer_001.h
deleted file mode 100644
index 70c85aca1..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/timer_001.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * @brief 32-bit Timer/PWM registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __TIMER_001_H_
-#define __TIMER_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_TIMER_001 IP: Timer register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief 32-bit Standard timer register block structure
- */
-typedef struct { /*!< TIMERn Structure */
- __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
- __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11AXX) || \
- defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
- __IO uint32_t PWMC;
-#endif
-} IP_TIMER_001_T;
-
-/** Macro to clear interrupt pending */
-#define TIMER_IR_CLR(n) _BIT(n)
-
-/** Macro for getting a timer match interrupt bit */
-#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
-/** Macro for getting a capture event interrupt bit */
-#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
-
-/** Timer/counter enable bit */
-#define TIMER_ENABLE ((uint32_t) (1 << 0))
-/** Timer/counter reset bit */
-#define TIMER_RESET ((uint32_t) (1 << 1))
-
-/** Bit location for interrupt on MRx match, n = 0 to 3 */
-#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
-/** Bit location for reset on MRx match, n = 0 to 3 */
-#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
-/** Bit location for stop on MRx match, n = 0 to 3 */
-#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
-
-/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
-#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
-/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
-#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
-/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
-#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
-
-/**
- * @brief Determine if a match interrupt is pending
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match interrupt number to check
- * @return false if the interrupt is not pending, otherwise true
- * @note Determine if the match interrupt for the passed timer and match
- * counter is pending.
- */
-STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- return (bool) ((pTimer->IR & TIMER_MATCH_INT(matchnum)) != 0);
-}
-
-/**
- * @brief Determine if a capture interrupt is pending
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture interrupt number to check
- * @return false if the interrupt is not pending, otherwise true
- * @note Determine if the capture interrupt for the passed capture pin is
- * pending.
- */
-STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- return (bool) ((pTimer->IR & TIMER_CAP_INT(capnum)) != 0);
-}
-
-/**
- * @brief Clears a (pending) match interrupt
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match interrupt number to clear
- * @return Nothing
- * @note Clears a pending timer match interrupt.
- */
-STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->IR = TIMER_IR_CLR(matchnum);
-}
-
-/**
- * @brief Clears a (pending) capture interrupt
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture interrupt number to clear
- * @return Nothing
- * @note Clears a pending timer capture interrupt.
- */
-STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->IR = (0x10 << capnum);
-}
-
-/**
- * @brief Enables the timer (starts count)
- * @param pTimer : Pointer to timer IP register address
- * @return Nothing
- * @note Enables the timer to start counting.
- */
-STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_T *pTimer)
-{
- pTimer->TCR |= TIMER_ENABLE;
-}
-
-/**
- * @brief Disables the timer (stops count)
- * @param pTimer : Pointer to timer IP register address
- * @return Nothing
- * @note Disables the timer to stop counting.
- */
-STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_T *pTimer)
-{
- pTimer->TCR &= ~TIMER_ENABLE;
-}
-
-/**
- * @brief Returns the current timer count
- * @param pTimer : Pointer to timer IP register address
- * @return Current timer terminal count value
- * @note Returns the current timer terminal count.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_T *pTimer)
-{
- return pTimer->TC;
-}
-
-/**
- * @brief Returns the current prescale count
- * @param pTimer : Pointer to timer IP register address
- * @return Current timer prescale count value
- * @note Returns the current prescale count.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_T *pTimer)
-{
- return pTimer->PC;
-}
-
-/**
- * @brief Sets the prescaler value
- * @param pTimer : Pointer to timer IP register address
- * @param prescale : Prescale value to set the prescale register to
- * @return Nothing
- * @note Sets the prescale count value.
- */
-STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_T *pTimer, uint32_t prescale)
-{
- pTimer->PR = prescale;
-}
-
-/**
- * @brief Sets a timer match value
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer to set match count for
- * @param matchval : Match value for the selected match count
- * @return Nothing
- * @note Sets ones of the timer match values.
- */
-STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_T *pTimer, int8_t matchnum, uint32_t matchval)
-{
- pTimer->MR[matchnum] = matchval;
-}
-
-/**
- * @brief Reads a capture register
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture register to read
- * @return The selected capture register value
- * @note Returns the selected capture register value.
- */
-STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- return pTimer->CR[capnum];
-}
-
-/**
- * @brief Resets the timer terminal and prescale counts to 0
- * @param pTimer : Pointer to timer IP register address
- * @return Nothing
- */
-void IP_TIMER_Reset(IP_TIMER_001_T *pTimer);
-
-/**
- * @brief Enables a match interrupt that fires when the terminal count
- * matches the match counter value.
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR |= TIMER_INT_ON_MATCH(matchnum);
-}
-
-/**
- * @brief Disables a match interrupt for a match counter.
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
-}
-
-/**
- * @brief For the specific match counter, enables reset of the terminal count register when a match occurs
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR |= TIMER_RESET_ON_MATCH(matchnum);
-}
-
-/**
- * @brief For the specific match counter, disables reset of the terminal count register when a match occurs
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
-}
-
-/**
- * @brief Enable a match timer to stop the terminal count when a
- * match count equals the terminal count.
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR |= TIMER_STOP_ON_MATCH(matchnum);
-}
-
-/**
- * @brief Disable stop on match for a match timer. Disables a match timer
- * to stop the terminal count when a match count equals the terminal count.
- * @param pTimer : Pointer to timer IP register address
- * @param matchnum : Match timer, 0 to 3
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)
-{
- pTimer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
-}
-
-/**
- * @brief Enables capture on on rising edge of selected CAP signal for the
- * selected capture register, enables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a rising edge.
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR |= TIMER_CAP_RISING(capnum);
-}
-
-/**
- * @brief Disables capture on on rising edge of selected CAP signal. For the
- * selected capture register, disables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a rising edge.
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR &= ~TIMER_CAP_RISING(capnum);
-}
-
-/**
- * @brief Enables capture on on falling edge of selected CAP signal. For the
- * selected capture register, enables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a falling edge.
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR |= TIMER_CAP_FALLING(capnum);
-}
-
-/**
- * @brief Disables capture on on falling edge of selected CAP signal. For the
- * selected capture register, disables the selected CAPn.capnum signal to load
- * the capture register with the terminal coount on a falling edge.
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR &= ~TIMER_CAP_FALLING(capnum);
-}
-
-/**
- * @brief Enables interrupt on capture of selected CAP signal. For the
- * selected capture register, an interrupt will be generated when the enabled
- * rising or falling edge on CAPn.capnum is detected.
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR |= TIMER_INT_ON_CAP(capnum);
-}
-
-/**
- * @brief Disables interrupt on capture of selected CAP signal
- * @param pTimer : Pointer to timer IP register address
- * @param capnum : Capture signal/register to use
- * @return Nothing
- */
-STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_T *pTimer, int8_t capnum)
-{
- pTimer->CCR &= ~TIMER_INT_ON_CAP(capnum);
-}
-
-/**
- * @brief Standard timer initial match pin state and change state
- */
-typedef enum IP_TIMER_PIN_MATCH_STATE {
- TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */
- TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */
- TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */
- TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */
-} IP_TIMER_PIN_MATCH_STATE_T;
-
-/**
- * @brief Sets external match control (MATn.matchnum) pin control
- * @param pTimer : Pointer to timer IP register address
- * @param initial_state : Initial state of the pin, high(1) or low(0)
- * @param matchState : Selects the match state for the pin
- * @param matchnum : MATn.matchnum signal to use
- * @return Nothing
- * @note For the pin selected with matchnum, sets the function of the pin that occurs on
- * a terminal count match for the match count.
- */
-void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_T *pTimer, int8_t initial_state,
- IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
-
-/**
- * @brief Standard timer clock and edge for count source
- */
-typedef enum IP_TIMER_CAP_SRC_STATE {
- TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */
- TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */
- TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */
- TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */
-} IP_TIMER_CAP_SRC_STATE_T;
-
-/**
- * @brief Sets timer count source and edge with the selected passed from CapSrc
- * @param pTimer : Pointer to timer IP register address
- * @param capSrc : timer clock source and edge
- * @param capnum : CAPn.capnum pin to use (if used)
- * @return Nothing
- * @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
- */
-void IP_TIMER_SetCountClockSrc(IP_TIMER_001_T *pTimer,
- IP_TIMER_CAP_SRC_STATE_T capSrc, int8_t capnum);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __TIMER_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_001.h
deleted file mode 100644
index 592042105..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_001.h
+++ /dev/null
@@ -1,708 +0,0 @@
-/*
- * @brief UART/USART Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USART_001_H_
-#define __USART_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USART_001 IP: USART register block and driver
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief USART register block structure
- */
-typedef struct { /*!< USARTn Structure */
-
- union {
- __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
- __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
- };
-
- union {
- __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
- __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- };
-
- union {
- __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
- __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
-
- __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
- __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
- __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
- __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
- __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
- __I uint32_t RESERVED1[1];
- __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
- __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
- union {
- __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
- __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
- };
-
-#if !defined CHIP_LPC11XX
- __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
-#endif
-} IP_USART_001_T;
-
-#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) /*!< UART time-out definitions in case of using Read/Write function with Blocking Flag mode */
-
-#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/**
- * @brief Macro defines for UARTn Receiver Buffer Register
- */
-#define UART_RBR_MASKBIT ((uint8_t) 0xFF) /*!< UART Received Buffer mask bit (8 bits) */
-
-/**
- * @brief Macro defines for UARTn Transmit Holding Register
- */
-#define UART_THR_MASKBIT ((uint8_t) 0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
-
-/**
- * @brief Macro defines for UARTn Divisor Latch LSB register
- */
-#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading least significant halfs of divisors */
-#define UART_DLL_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch LSB bit mask */
-
-/**
- * @brief Macro defines for UARTn Divisor Latch MSB register
- */
-#define UART_DLM_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch MSB bit mask */
-#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading most significant halfs of divisors */
-
-/**
- * @brief Macro defines for UART interrupt enable register
- */
-#define UART_IER_RBRINT_EN ((uint32_t) (1 << 0)) /*!< RBR Interrupt enable*/
-#define UART_IER_THREINT_EN ((uint32_t) (1 << 1)) /*!< THR Interrupt enable*/
-#define UART_IER_RLSINT_EN ((uint32_t) (1 << 2)) /*!< RX line status interrupt enable*/
-#define UART_IER_MSINT_EN ((uint32_t) (1 << 3)) /*!< Modem status interrupt enable */
-#define UART_IER_CTSINT_EN ((uint32_t) (1 << 7)) /*!< CTS1 signal transition interrupt enable */
-#define UART_IER_ABEOINT_EN ((uint32_t) (1 << 8)) /*!< Enables the end of auto-baud interrupt */
-#define UART_IER_ABTOINT_EN ((uint32_t) (1 << 9)) /*!< Enables the auto-baud time-out interrupt */
-#define UART_IER_BITMASK ((uint32_t) (0x307)) /*!< UART interrupt enable register bit mask */
-#define UART1_IER_BITMASK ((uint32_t) (0x38F)) /*!< UART1 interrupt enable register bit mask */
-
-/**
- * @brief Macro defines for UART interrupt identification register
- */
-#define UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0)) /*!> 8) & 0x0F)) /*!< Reflects the current level of the UART transmitter FIFO */
-#define UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F)) /*!< UART FIFO Level Register bit mask */
-
-/**
- * @brief Macro defines for Ring Buffer
- */
-#define UART_RING_BUFSIZE 256 /*!< buffer size definition */
-#define __BUF_MASK (UART_RING_BUFSIZE - 1) /*!< Buf mask */
-#define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK)) /*!< Check buf is full or not */
-#define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK)) /*!< Check buf will be full in next receiving or not */
-#define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK)) /*!< Check buf is empty */
-#define __BUF_RESET(bufidx) (bufidx = 0) /*!< Reset buf */
-#define __BUF_INCR(bufidx) (bufidx = (bufidx + 1) & __BUF_MASK) /*!< Increase buf */
-
-/**
- * @brief UART Ring buffer structure
- */
-typedef struct {
- __IO uint32_t tx_head; /*!< UART Tx ring buffer head index */
- __IO uint32_t tx_tail; /*!< UART Tx ring buffer tail index */
- __IO uint32_t rx_head; /*!< UART Rx ring buffer head index */
- __IO uint32_t rx_tail; /*!< UART Rx ring buffer tail index */
- __IO uint8_t tx[UART_RING_BUFSIZE]; /*!< UART Tx data ring buffer */
- __IO uint8_t rx[UART_RING_BUFSIZE]; /*!< UART Rx data ring buffer */
-} UART_RingBuffer_T;
-
-/**
- * @brief UART Line Status Type definition
- */
-typedef enum IP_UART_LS {
- UART_LINESTAT_RDR = UART_LSR_RDR, /*!< Line status register: Receive data ready*/
- UART_LINESTAT_OE = UART_LSR_OE, /*!< Line status register: Overrun error*/
- UART_LINESTAT_PE = UART_LSR_PE, /*!< Line status register: Parity error*/
- UART_LINESTAT_FE = UART_LSR_FE, /*!< Line status register: Framing error*/
- UART_LINESTAT_BI = UART_LSR_BI, /*!< Line status register: Break interrupt*/
- UART_LINESTAT_THRE = UART_LSR_THRE, /*!< Line status register: Transmit holding register empty*/
- UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!< Line status register: Transmitter empty*/
- UART_LINESTAT_RXFE = UART_LSR_RXFE /*!< Error in RX FIFO*/
-} IP_UART_LS_T;
-
-/**
- * @brief UART Full modem - Signal states definition
- */
-typedef enum IP_UART_SIGNAL_STATE {
- INACTIVE = 0, /*!< In-active state */
- ACTIVE = !INACTIVE /*!< Active state */
-} IP_UART_SIGNAL_STATE_T;
-
-/**
- * @brief UART modem status type definition
- */
-typedef enum IP_UART_MODEM_STAT {
- UART_MODEM_STAT_DELTA_CTS = UART_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
- UART_MODEM_STAT_DELTA_DSR = UART_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
- UART_MODEM_STAT_LO2HI_RI = UART_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
- UART_MODEM_STAT_DELTA_DCD = UART_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
- UART_MODEM_STAT_CTS = UART_MSR_CTS, /*!< Clear To Send State */
- UART_MODEM_STAT_DSR = UART_MSR_DSR, /*!< Data Set Ready State */
- UART_MODEM_STAT_RI = UART_MSR_RI, /*!< Ring Indicator State */
- UART_MODEM_STAT_DCD = UART_MSR_DCD /*!< Data Carrier Detect State */
-} IP_UART_MODEM_STAT_T;
-
-/**
- * @brief Modem output pin type definition
- */
-typedef enum IP_UART_MODEM_PIN {
- UART_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
- UART_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
-} IP_UART_MODEM_PIN_T;
-
-/**
- * @brief UART Modem mode type definition
- */
-typedef enum IP_UART_MODEM_MODE {
- UART_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
- UART_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
- UART_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
-} IP_UART_MODEM_MODE_T;
-
-/**
- * @brief UART Interrupt Type definitions
- */
-typedef enum IP_UART_INT {
- UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
- UART_INTCFG_THRE, /*!< THR Interrupt enable*/
- UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
- UART_INTCFG_MS, /*!< Modem status interrupt enable */
- UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable */
- UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
- UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
-} IP_UART_INT_T;
-
-/**
- * @brief UART Parity type definitions
- */
-typedef enum IP_UART_PARITY {
- UART_PARITY_NONE = 0, /*!< No parity */
- UART_PARITY_ODD = (4 << 3), /*!< Odd parity */
- UART_PARITY_EVEN = (5 << 3), /*!< Even parity */
- UART_PARITY_SP_1 = (6 << 3), /*!< Forced "1" stick parity */
- UART_PARITY_SP_0 = (7 << 3) /*!< Forced "0" stick parity */
-} IP_UART_PARITY_T;
-
-/**
- * @brief FIFO Level type definitions
- */
-typedef enum IP_UART_FITO_LEVEL {
- UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
- UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
- UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
- UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
-} IP_UART_FITO_LEVEL_T;
-
-/**
- * @brief UART Stop bit type definitions
- */
-typedef enum IP_UART_STOPBIT {
- UART_STOPBIT_1 = 0, /*!< UART One Stop Bit Select */
- UART_STOPBIT_2 = (1 << 2) /*!< UART Two Stop Bits Select */
-} IP_UART_STOPBIT_T;
-
-/**
- * @brief UART Databit type definitions
- */
-typedef enum IP_UART_DATABIT {
- UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
- UART_DATABIT_6, /*!< UART 6 bit data mode */
- UART_DATABIT_7, /*!< UART 7 bit data mode */
- UART_DATABIT_8 /*!< UART 8 bit data mode */
-} IP_UART_DATABIT_T;
-
-/**
- * @brief UART ID
- */
-typedef enum IP_UART_ID {
- UART_0 = 0,
- UART_1,
- UART_2,
- UART_3,
- UART_4,
-} IP_UART_ID_T;
-
-/**
- * @brief UART Interrupt Status
- */
-typedef enum IP_UART_INT_STATUS {
- UART_INTSTS_ERROR = 1 << 0, /*!< UART Interrupt Error*/
- UART_INTSTS_RTS = 1 << 1, /*!< UART Interrupt status: Ready to Send*/
- UART_INTSTS_RTR = 1 << 2, /*!< UART Interrupt status: Ready to Receive*/
- UART_INTSTS_ABEO = UART_IIR_ABEO_INT, /*!< UART End of auto-baud interrupt */
- UART_INTSTS_ABTO = UART_IIR_ABTO_INT /*!< UART Auto-baud time-out interrupt */
-} IP_UART_INT_STATUS_T;
-
-/**
- * @brief UART Auto-baudrate mode type definition
- */
-typedef enum IP_UART_AB_MODE {
- UART_AUTOBAUD_MODE0 = 0, /*!< UART Auto baudrate Mode 0 */
- UART_AUTOBAUD_MODE1, /*!< UART Auto baudrate Mode 1 */
-} IP_UART_AB_MODE_T;
-
-/**
- * @brief Auto Baudrate mode configuration type definition
- */
-typedef struct {
- IP_UART_AB_MODE_T ABMode; /*!< Autobaudrate mode */
- FunctionalState AutoRestart; /*!< Auto Restart state */
-} UART_AB_CFG_T;
-
-/**
- * @brief UART FIFO Configuration Structure definition
- */
-typedef struct {
- FunctionalState FIFO_ResetRxBuf; /*!< Reset Rx FIFO command state , should be:
- - ENABLE: Reset Rx FIFO in UART
- - DISABLE: Do not reset Rx FIFO in UART
- */
- FunctionalState FIFO_ResetTxBuf; /*!< Reset Tx FIFO command state , should be:
- - ENABLE: Reset Tx FIFO in UART
- - DISABLE: Do not reset Tx FIFO in UART
- */
- FunctionalState FIFO_DMAMode; /*!< DMA mode, should be:
- - ENABLE: Enable DMA mode in UART
- - DISABLE: Disable DMA mode in UART
- */
- IP_UART_FITO_LEVEL_T FIFO_Level; /*!< Rx FIFO trigger level, should be:
- - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
- */
-} UART_FIFO_CFG_T;
-
-/**
- * @brief Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct.
- * @param pUART : Pointer to selected UARTx peripheral
- * @param UARTPort : UART ID type
- * @return Nothing
- */
-void IP_UART_Init(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
-
-/**
- * @brief De-initializes the UARTx peripheral registers to their default reset values.
- * @param pUART : Pointer to selected UARTx peripheral
- * @param UARTPort : UART ID type
- * @return Nothing
- */
-void IP_UART_DeInit(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);
-
-/**
- * @brief Determines best dividers to get a target clock rate
- * @param pUART : Pointer to selected UARTx peripheral
- * @param baudrate : Desired UART baud rate.
- * @param uClk : Current Uart Block Clock.
- * @return Error status, could be SUCCESS or ERROR
- */
-Status IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);
-
-/**
- * @brief Configure data width, parity mode and stop bits
- * @param pUART : Pointer to selected UARTx peripheral
- * @param Databits : UART Data width, should be:
- * UART_DATABIT_5: UART 5 bit data mode
- * UART_DATABIT_6: UART 6 bit data mode
- * UART_DATABIT_7: UART 7 bit data mode
- * UART_DATABIT_8: UART 8 bit data mode
- * @param Parity : UART Parity mode, should be:
- * UART_PARITY_NONE: No parity
- * UART_PARITY_ODD: Odd parity
- * UART_PARITY_EVEN: Even parity
- * UART_PARITY_SP_1: Forced "1" stick parity
- * UART_PARITY_SP_0: Forced "0" stick parity
- * @param Stopbits : Number of stop bits, should be:
- * UART_STOPBIT_1: One Stop Bit Select
- * UART_STOPBIT_2: Two Stop Bits Select
- * @return Nothing
- */
-void IP_UART_ConfigData(IP_USART_001_T *pUART,
- IP_UART_DATABIT_T Databits,
- IP_UART_PARITY_T Parity,
- IP_UART_STOPBIT_T Stopbits);
-
-/* UART Send/Receive functions -------------------------------------------------*/
-/**
- * @brief Transmit a single data through UART peripheral
- * @param pUART : Pointer to selected UARTx peripheral
- * @param data : Data to transmit (must be 8-bit long)
- * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)
- */
-Status IP_UART_SendByte(IP_USART_001_T *pUART, uint8_t data);
-
-/**
- * @brief Receive a single data from UART peripheral
- * @param pUART : Pointer to selected UARTx peripheral
- * @param *Data : Pointer to Data to receive (must be 8-bit long)
- * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)
- */
-Status IP_UART_ReceiveByte(IP_USART_001_T *pUART, uint8_t *Data);
-
-/**
- * @brief Send a block of data via UART peripheral
- * @param pUART : Pointer to selected UARTx peripheral
- * @param txbuf : Pointer to Transmit buffer
- * @param buflen : Length of Transmit buffer
- * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING
- * @return Number of bytes sent
- *
- * Note: when using UART in BLOCKING mode, a time-out condition is used
- * via defined symbol UART_BLOCKING_TIMEOUT.
- */
-uint32_t IP_UART_Send(IP_USART_001_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
-
-/**
- * @brief Receive a block of data via UART peripheral
- * @param pUART : Pointer to selected UARTx peripheral
- * @param rxbuf : Pointer to Received buffer
- * @param buflen : Length of Received buffer
- * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING
- * @return Number of bytes received
- * @note
- * Note: when using UART in BLOCKING mode, a time-out condition is used
- * via defined symbol UART_BLOCKING_TIMEOUT.
- */
-uint32_t IP_UART_Receive(IP_USART_001_T *pUART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);
-
-/* UART operate functions -------------------------------------------------------*/
-/**
- * @brief Enable or disable specified UART interrupt.
- * @param pUART : Pointer to selected UARTx peripheral
- * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following:
- * - UART_INTCFG_RBR : RBR Interrupt enable
- * - UART_INTCFG_THRE : THR Interrupt enable
- * - UART_INTCFG_RLS : RX line status interrupt enable
- * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
- * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
- * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
- * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
- * @param NewState : New state of specified UART interrupt type, should be:
- * - ENALBE : Enable this UART interrupt type
- * - DISALBE : Disable this UART interrupt type
- * @return Nothing
- */
-void IP_UART_IntConfig(IP_USART_001_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState);
-
-/**
- * @brief Get Source Interrupt
- * @param pUART : Pointer to selected UARTx peripheral
- * @return Return the value of IIR register
- */
-uint32_t IP_UART_IntGetStatus(IP_USART_001_T *pUART);
-
-/**
- * @brief Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0
- * @param pUART : Pointer to selected UARTx peripheral
- * @return Nothing
- */
-void IP_UART_ForceBreak(IP_USART_001_T *pUART);
-
-/**
- * @brief Get current value of Line Status register in UART peripheral.
- * @param pUART : Pointer to selected UARTx peripheral
- * @return Current value of Line Status register in UART peripheral
- * @note
- * The return value of this function must be ANDed with each member in UART_LS_T
- * enumeration to determine current flag status corresponding to each Line status type. Because
- * some flags in Line Status register will be cleared after reading, the next reading Line
- * Status register could not be correct. So this function used to read Line status register
- * in one time only, then the return value used to check all flags.
- */
-uint8_t IP_UART_GetLineStatus(IP_USART_001_T *pUART);
-
-/**
- * @brief Check whether if UART is busy or not
- * @param pUART : Pointer to selected UARTx peripheral
- * @return RESET if UART is not busy, otherwise return SET.
- */
-FlagStatus IP_UART_CheckBusy(IP_USART_001_T *pUART);
-
-/**
- * @brief Enable/Disable transmission on UART TxD pin
- * @param pUART : Pointer to selected UARTx peripheral
- * @param UARTPort : UART ID type
- * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE
- * @return Nothing
- */
-void IP_UART_TxCmd(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort, FunctionalState NewState);
-
-/* UART FIFO functions ----------------------------------------------------------*/
-/**
- * @brief Configure FIFO function on selected UART peripheral
- * @param pUART : Pointer to selected UARTx peripheral
- * @param FIFOCfg : Pointer to a UART_FIFO_CFG_T Structure that contains specified information about FIFO configuration
- * @return Nothing
- */
-void IP_UART_FIFOConfig(IP_USART_001_T *pUART, UART_FIFO_CFG_T *FIFOCfg);
-
-/**
- * @brief Fills each UART_FIFOInitStruct member with its default value:
- * - FIFO_DMAMode = DISABLE
- * - FIFO_Level = UART_FIFO_TRGLEV0
- * - FIFO_ResetRxBuf = ENABLE
- * - FIFO_ResetTxBuf = ENABLE
- * - FIFO_State = ENABLE
- * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_T structure which will be initialized.
- * @return Nothing
- */
-void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_T *UART_FIFOInitStruct);
-
-/**
- * @brief Start/Stop Auto Baudrate activity
- * @param pUART : Pointer to selected UARTx peripheral
- * @param ABConfigStruct : A pointer to UART_AB_CFG_T structure that
- * contains specified information about UAR auto baud configuration
- * @param NewState : New State of Auto baudrate activity, should be ENABLE or DISABLE
- * @return Nothing
- * @note Auto-baudrate mode enable bit will be cleared once this mode completed.
- */
-void IP_UART_ABCmd(IP_USART_001_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState);
-
-/**
- * @brief Clear Autobaud Interrupt
- * @param pUART : Pointer to selected UARTx peripheral
- * @param ABIntType : type of auto-baud interrupt, should be:
- * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
- * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
- * @return Nothing
- */
-void IP_UART_ABClearIntPending(IP_USART_001_T *pUART, IP_UART_INT_STATUS_T ABIntType);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USART_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_004.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_004.h
deleted file mode 100644
index faa112e34..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usart_004.h
+++ /dev/null
@@ -1,647 +0,0 @@
-/*
- * @brief UART/USART Registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USART_004_H_
-#define __USART_004_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USART_004 IP: USART register block and driver (004)
- * @ingroup IP_Drivers
- * @{
- */
-
-/**
- * @brief USART register block structure
- */
-typedef struct { /*!< USARTn Structure */
-
- union {
- __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
- __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
- };
-
- union {
- __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
- __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- };
-
- union {
- __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
- __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
-
- __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
- __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
- __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
- __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
-
- __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
- __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
- __I uint32_t RESERVED1[1];
- __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
-
- __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
-
- union {
- __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
- __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
- };
-
- __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
-} IP_USART_001_T;
-
-#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */
-
-/**
- * @brief Basic UART initialization
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- * @note This function performs very basic UART initialization
- */
-void IP_UART_Init(IP_USART_001_T *pUART);
-
-/**
- * @brief UART de-initialization
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_UART_DeInit(IP_USART_001_T *pUART) {}
-
-/**
- * @brief Transmit a single byte through the UART peripheral
- * @param pUART : Pointer to selected UART peripheral
- * @param data : Byte to transmit
- * @return Nothing
- * @note This function attempts to place a byte into the UART transmit
- * FIFO or transmit hold register regard regardless of UART state.
- */
-STATIC INLINE void IP_UART_SendByte(IP_USART_001_T *pUART, const uint8_t data)
-{
- pUART->THR = (uint32_t) data;
-}
-
-/**
- * @brief Get a single data from UART peripheral
- * @param pUART : Pointer to selected UART peripheral
- * @return A single byte of data read
- * @note This function reads a byte from the UART receive FIFO or
- * receive hold register regard regardless of UART state.
- */
-STATIC INLINE uint8_t IP_UART_ReadByte(IP_USART_001_T *pUART)
-{
- return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
-}
-
-/**
- * @brief Macro defines for UART interrupt enable register
- */
-#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable*/
-#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable*/
-#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable*/
-#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable */
-#define UART_IER_CTSINT (1 << 7) /*!< CTS1 signal transition interrupt enable */
-#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */
-#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */
-#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask */
-#define UART1_IER_BITMASK (0x38F) /*!< UART1 interrupt enable register bit mask */
-
-/**
- * @brief Enable UART interrupts
- * @param pUART : Pointer to selected UART peripheral
- * @param intMask : Or'ed Interrupts to enable in the Interrupt Enable Register (IER)
- * @return Nothing
- * @note Use an Or'ed value of UART_IER_* definitions with this call
- * to enable specific UART interrupts. The Divisor Latch Access Bit
- * (DLAB) in LCR must be cleared in order to access the IER register.
- * This function doesn't alter the DLAB state.
- */
-STATIC INLINE void IP_UART_IntEnable(IP_USART_001_T *pUART, uint32_t intMask)
-{
- pUART->IER |= intMask;
-}
-
-/**
- * @brief Disable UART interrupts
- * @param pUART : Pointer to selected UART peripheral
- * @param intMask : Or'ed Interrupts to disable in the Interrupt Enable Register (IER)
- * @return Nothing
- * @note Use an Or'ed value of UART_IER_* definitions with this call
- * to disable specific UART interrupts. The Divisor Latch Access Bit
- * (DLAB) in LCR must be cleared in order to access the IER register.
- * This function doesn't alter the DLAB state.
- */
-STATIC INLINE void IP_UART_IntDisable(IP_USART_001_T *pUART, uint32_t intMask)
-{
- pUART->IER &= ~intMask;
-}
-
-/**
- * @brief Macro defines for UART interrupt identification register
- */
-#define UART_IIR_INTSTAT_PEND (1 << 0) /*!IIR;
-}
-
-/**
- * @brief Macro defines for UART FIFO control register
- */
-#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */
-#define UART_FCR_RX_RS (1 << 1) /*!< UART FIFO RX reset */
-#define UART_FCR_TX_RS (1 << 2) /*!< UART FIFO TX reset */
-#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection */
-#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */
-#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */
-#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */
-#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */
-#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */
-#define UART_TX_FIFO_SIZE (16)
-
-/**
- * @brief Setup the UART FIFOs
- * @param pUART : Pointer to selected UART peripheral
- * @param fcr : FIFO control register setup OR'ed flags
- * @return Nothing
- * @note Use an Or'ed value of UART_FCR_* definitions with this call
- * to select specific options.
- */
-STATIC INLINE void IP_UART_SetupFIFOS(IP_USART_001_T *pUART, uint32_t fcr)
-{
- pUART->FCR = fcr;
-}
-
-/**
- * @brief Macro defines for UART line control register
- */
-#define UART_LCR_WLEN5 (0) /*!< UART 5 bit data mode */
-#define UART_LCR_WLEN6 (1 << 0) /*!< UART 6 bit data mode */
-#define UART_LCR_WLEN7 (2 << 0) /*!< UART 7 bit data mode */
-#define UART_LCR_WLEN8 (3 << 0) /*!< UART 8 bit data mode */
-#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART One Stop Bit Select */
-#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART Two Stop Bits Select */
-#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */
-#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */
-#define UART_LCR_PARITY_ODD (0) /*!< UART Odd Parity Select */
-#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Even Parity Select */
-#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART force 1 stick parity */
-#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART force 0 stick parity */
-#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Transmission Break enable */
-#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */
-#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */
-
-/**
- * @brief Setup the UART operation mode in the Line Control Register (LCR)
- * @param pUART : Pointer to selected UART peripheral
- * @param lcr : OR'ed flags
- * @return Nothing
- * @note Sets up the UART transmit mode (data bits, stop bits, parity,
- * and break). Use an Or'ed value of UART_LCR_* definitions with this
- * call to select specific options. Unless the UART_LCR_DLAB_EN
- * option is passed in lcd, DLAB will be cleared and divisor access
- * will be disabled.
- */
-STATIC INLINE void IP_UART_SetMode(IP_USART_001_T *pUART, uint32_t lcr)
-{
- pUART->LCR = lcr;
-}
-
-/**
- * @brief Enable access to Divisor Latches
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_UART_EnableDivisorAccess(IP_USART_001_T *pUART)
-{
- pUART->LCR |= UART_LCR_DLAB_EN;
-}
-
-/**
- * @brief Disable access to Divisor Latches
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_UART_DisableDivisorAccess(IP_USART_001_T *pUART)
-{
- pUART->LCR &= ~UART_LCR_DLAB_EN;
-}
-
-#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB (DLL) bit mask */
-#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB (DLM) bit mask */
-
-/**
- * @brief Set LSB and MSB divisor latch registers
- * @param pUART : Pointer to selected UART peripheral
- * @param dll : Divisor Latch LSB value
- * @param dlm : Divisor Latch MSB value
- * @return Nothing
- * @note The Divisor Latch Access Bit (DLAB) in LCR must be set in
- * order to access the USART Divisor Latches. This function
- * doesn't alter the DLAB state.
- */
-STATIC INLINE void IP_UART_SetDivisorLatches(IP_USART_001_T *pUART, uint8_t dll, uint8_t dlm)
-{
- pUART->DLL = (uint32_t) dll;
- pUART->DLM = (uint32_t) dlm;
-}
-
-/**
- * @brief Macro defines for UART Modem control register
- */
-#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */
-#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */
-#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */
-#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */
-#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */
-#define UART_MCR_BITMASK (0x0F3) /*!< UART1 bit mask value */
-
-/**
- * @brief Return modem control register/status
- * @param pUART : Pointer to selected UART peripheral
- * @return Modem control register (status)
- * @note Mask bits of the returned status value with UART_MCR_*
- * definitions for specific statuses.
- */
-STATIC INLINE uint32_t IP_UART_ReadModemControl(IP_USART_001_T *pUART)
-{
- return pUART->MCR;
-}
-
-/**
- * @brief Set modem control register/status
- * @param pUART : Pointer to selected UART peripheral
- * @param mcr : Modem control register flags to set
- * @return Nothing
- * @note Use an Or'ed value of UART_MCR_* definitions with this
- * call to set specific options.
- */
-STATIC INLINE void IP_UART_SetModemControl(IP_USART_001_T *pUART, uint32_t mcr)
-{
- pUART->MCR |= mcr;
-}
-
-/**
- * @brief Clear modem control register/status
- * @param pUART : Pointer to selected UART peripheral
- * @param mcr : Modem control register flags to clear
- * @return Nothing
- * @note Use an Or'ed value of UART_MCR_* definitions with this
- * call to clear specific options.
- */
-STATIC INLINE void IP_UART_ClearModemControl(IP_USART_001_T *pUART, uint32_t mcr)
-{
- pUART->MCR &= ~mcr;
-}
-
-/**
- * @brief Macro defines for UART line status register
- */
-#define UART_LSR_RDR (1 << 0) /*!< Line status register: Receive data ready */
-#define UART_LSR_OE (1 << 1) /*!< Line status register: Overrun error */
-#define UART_LSR_PE (1 << 2) /*!< Line status register: Parity error */
-#define UART_LSR_FE (1 << 3) /*!< Line status register: Framing error */
-#define UART_LSR_BI (1 << 4) /*!< Line status register: Break interrupt */
-#define UART_LSR_THRE (1 << 5) /*!< Line status register: Transmit holding register empty */
-#define UART_LSR_TEMT (1 << 6) /*!< Line status register: Transmitter empty */
-#define UART_LSR_RXFE (1 << 7) /*!< Error in RX FIFO */
-#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */
-
-/**
- * @brief Return Line Status register/status (LSR)
- * @param pUART : Pointer to selected UART peripheral
- * @return Line Status register (status)
- * @note Mask bits of the returned status value with UART_LSR_*
- * definitions for specific statuses.
- */
-STATIC INLINE uint32_t IP_UART_ReadLineStatus(IP_USART_001_T *pUART)
-{
- return pUART->LSR;
-}
-
-/**
- * @brief Macro defines for UART Modem status register
- */
-#define UART_MSR_DELTA_CTS (1 << 0) /*!< Set upon state change of input CTS */
-#define UART_MSR_DELTA_DSR (1 << 1) /*!< Set upon state change of input DSR */
-#define UART_MSR_LO2HI_RI (1 << 2) /*!< Set upon low to high transition of input RI */
-#define UART_MSR_DELTA_DCD (1 << 3) /*!< Set upon state change of input DCD */
-#define UART_MSR_CTS (1 << 4) /*!< Clear To Send State */
-#define UART_MSR_DSR (1 << 5) /*!< Data Set Ready State */
-#define UART_MSR_RI (1 << 6) /*!< Ring Indicator State */
-#define UART_MSR_DCD (1 << 7) /*!< Data Carrier Detect State */
-#define UART_MSR_BITMASK (0xFF) /*!< MSR register bit-mask value */
-
-/**
- * @brief Return Modem Status register/status (MSR)
- * @param pUART : Pointer to selected UART peripheral
- * @return Modem Status register (status)
- * @note Mask bits of the returned status value with UART_MSR_*
- * definitions for specific statuses.
- */
-STATIC INLINE uint32_t IP_UART_ReadModemStatus(IP_USART_001_T *pUART)
-{
- return pUART->MSR;
-}
-
-/**
- * @brief Write a byte to the scratchpad register
- * @param pUART : Pointer to selected UART peripheral
- * @param data : Byte value to write
- * @return Nothing
- */
-STATIC INLINE void IP_UART_SetScratch(IP_USART_001_T *pUART, uint8_t data)
-{
- pUART->SCR = (uint32_t) data;
-}
-
-/**
- * @brief Returns current byte value in the scratchpad register
- * @param pUART : Pointer to selected UART peripheral
- * @return Byte value read from scratchpad register
- */
-STATIC INLINE uint8_t IP_UART_ReadScratch(IP_USART_001_T *pUART)
-{
- return (uint8_t) (pUART->SCR & 0xFF);
-}
-
-/**
- * @brief Macro defines for UART Auto baudrate control register
- */
-#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */
-#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */
-#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */
-#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */
-#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */
-#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */
-
-/**
- * @brief Set autobaud register options
- * @param pUART : Pointer to selected UART peripheral
- * @param acr : Or'ed values to set for ACR register
- * @return Nothing
- * @note Use an Or'ed value of UART_ACR_* definitions with this
- * call to set specific options.
- */
-STATIC INLINE void IP_UART_SetAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
-{
- pUART->ACR |= acr;
-}
-
-/**
- * @brief Clear autobaud register options
- * @param pUART : Pointer to selected UART peripheral
- * @param acr : Or'ed values to clear for ACR register
- * @return Nothing
- * @note Use an Or'ed value of UART_ACR_* definitions with this
- * call to clear specific options.
- */
-STATIC INLINE void IP_UART_ClearAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)
-{
- pUART->ACR &= ~acr;
-}
-
-/**
- * @brief Enable transmission on UART TxD pin
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_UART_TXEnable(IP_USART_001_T *pUART)
-{
- pUART->TER1 = (1 << 7);
-}
-
-/**
- * @brief Disable transmission on UART TxD pin
- * @param pUART : Pointer to selected UART peripheral
- * @return Nothing
- */
-STATIC INLINE void IP_UART_TXDisable(IP_USART_001_T *pUART)
-{
- pUART->TER1 = 0;
-}
-
-/**
- * @brief Macro defines for UART1 RS485 Control register
- */
-#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
-#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */
-#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */
-#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
- used for direction control */
-#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */
-#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction
- control signal on the RTS (or DTR) pin. The direction control pin
- will be driven to logic "1" when the transmitter has data to be sent */
-#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */
-
-/**
- * @brief Set RS485 control register options
- * @param pUART : Pointer to selected UART peripheral
- * @param ctrl : Or'ed values to set for RS485 control register
- * @return Nothing
- * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
- * call to set specific options.
- */
-STATIC INLINE void IP_UART_SetRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
-{
- pUART->RS485CTRL |= ctrl;
-}
-
-/**
- * @brief Clear RS485 control register options
- * @param pUART : Pointer to selected UART peripheral
- * @param ctrl : Or'ed values to clear for RS485 control register
- * @return Nothing
- * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
- * call to clear specific options.
- */
-STATIC INLINE void IP_UART_ClearRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)
-{
- pUART->RS485CTRL &= ~ctrl;
-}
-
-/**
- * @brief Set RS485 address match value
- * @param pUART : Pointer to selected UART peripheral
- * @param addr : Address match value for RS-485/EIA-485 mode
- * @return Nothing
- */
-STATIC INLINE void IP_UART_SetRS485Addr(IP_USART_001_T *pUART, uint8_t addr)
-{
- pUART->RS485ADRMATCH = (uint32_t) addr;
-}
-
-/**
- * @brief Read RS485 address match value
- * @param pUART : Pointer to selected UART peripheral
- * @return Address match value for RS-485/EIA-485 mode
- */
-STATIC INLINE uint8_t IP_UART_GetRS485Addr(IP_USART_001_T *pUART)
-{
- return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
-}
-
-/**
- * @brief Set RS485 direction control (RTS or DTR) delay value
- * @param pUART : Pointer to selected UART peripheral
- * @param dly : direction control (RTS or DTR) delay value
- * @return Nothing
- * @note This delay time is in periods of the baud clock. Any delay
- * time from 0 to 255 bit times may be programmed.
- */
-STATIC INLINE void IP_UART_SetRS485Delay(IP_USART_001_T *pUART, uint8_t dly)
-{
- pUART->RS485DLY = (uint32_t) dly;
-}
-
-/**
- * @brief Read RS485 direction control (RTS or DTR) delay value
- * @param pUART : Pointer to selected UART peripheral
- * @return direction control (RTS or DTR) delay value
- * @note This delay time is in periods of the baud clock. Any delay
- * time from 0 to 255 bit times may be programmed.
- */
-STATIC INLINE uint8_t IP_UART_GetRS485Delay(IP_USART_001_T *pUART)
-{
- return (uint8_t) (pUART->RS485DLY & 0xFF);
-}
-
-/**
- * @brief Determines and sets best dividers to get a target bit rate
- * @param pUART : Pointer to selected UART peripheral
- * @param baudrate : Target baud rate (baud rate = bit rate)
- * @param uClk : Clock rate into UART peripheral
- * @return The actual baud rate, or 0 if no rate can be found
- * @note Once you've computed your baud rate, you can remove this function
- * to make your image smaller.
- */
-uint32_t IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);
-
-#if 0 // FIXME
-// FIXME
-// FDR handled at chip layer
-// OSR not ready
-// TER1 not ready
-// HDEN handled at chip layer
-// SCICTRL handled at chip layer
-// TER2 handled at chip layer
-
-/**
- * @brief Macro defines for UART IrDA control register
- */
-#define UART_ICR_IRDAEN ((uint32_t) (1 << 0)) /*!< IrDA mode enable */
-#define UART_ICR_IRDAINV ((uint32_t) (1 << 1)) /*!< IrDA serial input inverted */
-#define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2)) /*!< IrDA fixed pulse width mode */
-#define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3)) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
-#define UART_ICR_BITMASK ((uint32_t) (0x3F)) /*!< UART IRDA bit mask */
-
-/**
- * @brief Macro defines for UART half duplex register
- */
-#define UART_HDEN_HDEN ((uint32_t) (1 << 0)) /*!< enable half-duplex mode*/
-
-/**
- * @brief Macro defines for UART smart card interface control register
- */
-#define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0)) /*!< enable asynchronous half-duplex smart card interface*/
-#define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1)) /*!< NACK response is inhibited*/
-#define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2)) /*!< ISO7816-3 protocol T1 is selected*/
-#define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5)) /*!< number of retransmission*/
-#define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< Extra guard time*/
-
-/**
- * @brief Macro defines for UART Fractional divider register
- */
-#define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F)) /*!< Baud-rate generation pre-scaler divisor */
-#define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0)) /*!< Baud-rate pre-scaler multiplier value */
-#define UART_FDR_BITMASK ((uint32_t) (0xFF)) /*!< UART Fractional Divider register bit mask */
-
-/**
- * @brief Macro defines for UART Tx Enable register
- */
-#define UART_TER1_TXEN ((uint8_t) (1 << 7)) /*!< Transmit enable bit */
-#define UART_TER1_BITMASK ((uint8_t) (0x80)) /*!< UART Transmit Enable Register bit mask */
-#define UART_TER2_TXEN ((uint8_t) (1 << 0)) /*!< Transmit enable bit */
-#define UART_TER2_BITMASK ((uint8_t) (0x01)) /*!< UART Transmit Enable Register bit mask */
-
-/**
- * @brief Macro defines for UART synchronous control register
- */
-#define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0)) /*!< enable synchronous mode*/
-#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1)) /*!< synchronous master mode*/
-#define UART_SYNCCTRL_FES ((uint32_t) (1 << 2)) /*!< sample on falling edge*/
-#define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3)) /*!< to be defined*/
-#define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4)) /*!< continuous running clock enable (master mode only)*/
-#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5)) /*!< do not send start/stop bit*/
-#define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6)) /*!< stop continuous clock*/
-
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USART_004_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usb_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usb_001.h
deleted file mode 100644
index a402ffb9f..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usb_001.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * @brief USB registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USB_001_H_
-#define __USB_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USB_001 IP: USB Device, Host, & OTG register block and driver
- * @ingroup IP_Drivers
- * USB Device, Host, & OTG
- * Note:
- * @{
- */
-
-/**
- * @brief USB register block structure
- */
-typedef struct
-{
- __I uint32_t Revision; /* USB Host Registers */
- __IO uint32_t Control;
- __IO uint32_t CommandStatus;
- __IO uint32_t InterruptStatus;
- __IO uint32_t InterruptEnable;
- __IO uint32_t InterruptDisable;
- __IO uint32_t HCCA;
- __I uint32_t PeriodCurrentED;
- __IO uint32_t ControlHeadED;
- __IO uint32_t ControlCurrentED;
- __IO uint32_t BulkHeadED;
- __IO uint32_t BulkCurrentED;
- __I uint32_t DoneHead;
- __IO uint32_t FmInterval;
- __I uint32_t FmRemaining;
- __I uint32_t FmNumber;
- __IO uint32_t PeriodicStart;
- __IO uint32_t LSTreshold;
- __IO uint32_t RhDescriptorA;
- __IO uint32_t RhDescriptorB;
- __IO uint32_t RhStatus;
- __IO uint32_t RhPortStatus1;
- __IO uint32_t RhPortStatus2;
- uint32_t RESERVED0[40];
- __I uint32_t Module_ID;
-
- __I uint32_t IntSt; /* USB On-The-Go Registers */
- __IO uint32_t IntEn;
- __O uint32_t IntSet;
- __O uint32_t IntClr;
- __IO uint32_t StCtrl;
- __IO uint32_t Tmr;
- uint32_t RESERVED1[58];
-
- __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
- __IO uint32_t DevIntEn;
- __O uint32_t DevIntClr;
- __O uint32_t DevIntSet;
-
- __O uint32_t CmdCode; /* USB Device SIE Command Registers */
- __I uint32_t CmdData;
-
- __I uint32_t RxData; /* USB Device Transfer Registers */
- __O uint32_t TxData;
- __I uint32_t RxPLen;
- __O uint32_t TxPLen;
- __IO uint32_t Ctrl;
- __O uint32_t DevIntPri;
-
- __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
- __IO uint32_t EpIntEn;
- __O uint32_t EpIntClr;
- __O uint32_t EpIntSet;
- __O uint32_t EpIntPri;
-
- __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
- __O uint32_t EpInd;
- __IO uint32_t MaxPSize;
-
- __I uint32_t DMARSt; /* USB Device DMA Registers */
- __O uint32_t DMARClr;
- __O uint32_t DMARSet;
- uint32_t RESERVED2[9];
- __IO uint32_t UDCAH;
- __I uint32_t EpDMASt;
- __O uint32_t EpDMAEn;
- __O uint32_t EpDMADis;
- __I uint32_t DMAIntSt;
- __IO uint32_t DMAIntEn;
- uint32_t RESERVED3[2];
- __I uint32_t EoTIntSt;
- __O uint32_t EoTIntClr;
- __O uint32_t EoTIntSet;
- __I uint32_t NDDRIntSt;
- __O uint32_t NDDRIntClr;
- __O uint32_t NDDRIntSet;
- __I uint32_t SysErrIntSt;
- __O uint32_t SysErrIntClr;
- __O uint32_t SysErrIntSet;
- uint32_t RESERVED4[15];
-
- union {
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */
- __O uint32_t I2C_TX;
- };
- __IO uint32_t I2C_STS;
- __IO uint32_t I2C_CTL;
- __IO uint32_t I2C_CLKHI;
- __O uint32_t I2C_CLKLO;
- uint32_t RESERVED5[824];
-
- union {
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
- __IO uint32_t OTGClkCtrl;
- };
- union {
- __I uint32_t USBClkSt;
- __I uint32_t OTGClkSt;
- };
-} IP_USB_001_T;
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_001_H_ */
-
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usbhs_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usbhs_001.h
deleted file mode 100644
index d8283995b..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/usbhs_001.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * @brief High-Speed USB registers and control functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __USBHS_001_H_
-#define __USBHS_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_USBHS_001 IP: USBHS Device, Host, & OTG register block and driver
- * @ingroup IP_Drivers
- * USB High-Speed Device, Host, & OTG
- * Note: On the LPC18xx and LPC43xx, only USB0 supports OTG
- * @{
- */
-
-/**
- * @brief USB High-Speed register block structure
- */
-typedef struct { /*!< USB Structure */
- __I uint32_t RESERVED0[64];
- __I uint32_t CAPLENGTH; /*!< Capability register length */
- __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */
- __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */
- __I uint32_t RESERVED1[5];
- __I uint32_t DCIVERSION; /*!< Device interface version number */
- __I uint32_t RESERVED2[7];
- union {
- __IO uint32_t USBCMD_H; /*!< USB command (host mode) */
- __IO uint32_t USBCMD_D; /*!< USB command (device mode) */
- };
-
- union {
- __IO uint32_t USBSTS_H; /*!< USB status (host mode) */
- __IO uint32_t USBSTS_D; /*!< USB status (device mode) */
- };
-
- union {
- __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */
- __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */
- };
-
- union {
- __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */
- __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */
- };
-
- __I uint32_t RESERVED3;
- union {
- __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */
- __IO uint32_t DEVICEADDR; /*!< USB device address */
- };
-
- union {
- __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */
- __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */
- };
-
- __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */
- __IO uint32_t BURSTSIZE; /*!< Programmable burst size */
- __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */
- __I uint32_t RESERVED4[2];
- __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */
- __IO uint32_t BINTERVAL; /*!< Length of virtual frame */
- __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */
- __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */
- __I uint32_t RESERVED5;
- union {
- __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */
- __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */
- };
-
- __I uint32_t RESERVED6[7];
- __IO uint32_t OTGSC; /*!< OTG status and control */
- union {
- __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */
- __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */
- };
-
- __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */
- __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */
- __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */
- __I uint32_t ENDPTSTAT; /*!< Endpoint status */
- __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */
- __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */
-} IP_USBHS_001_T;
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBHS_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wkt_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wkt_001.h
deleted file mode 100644
index b6408489d..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wkt_001.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * @brief Self Wakeup Timer (WKT) registers and functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __WKT_001_H_
-#define __WKT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_WKT_001 IP: Self Wakeup Timer (WKT) register block and driver
- * @ingroup IP_Drivers
- * Self Wakeup Timer
- * @{
- */
-
-/**
- * @brief Self wake-up timer register block structure
- */
-typedef struct {
- __IO uint32_t CTRL; /*!< Offset: 0x000 Alarm/Wakeup Timer Control register */
- uint32_t Reserved[2];
- __IO uint32_t COUNT; /*!< Offset: 0x000C Alarm/Wakeup Timer Counter register */
-} IP_WKT_001_T;
-
-/**
- * WKT Control register bit fields & masks
- */
-#define WKT_CTRL_CLKSEL ((uint32_t) (1 << 0)) /*!< Select the self wake-up timer clock source */
-#define WKT_CTRL_ALARMFLAG ((uint32_t) (1 << 1)) /*!< Wake-up or alarm timer flag */
-#define WKT_CTRL_CLEARCTR ((uint32_t) (1 << 2)) /*!< Clears the self wake-up timer */
-
-/**
- * WKT Clock source values enum
- */
-typedef enum IP_WKT_CLKSRC {
- IP_WKT_CLKSRC_DIVIRC = 0, /*!< Divided IRC clock - runs at 750kHz */
- IP_WKT_CLKSRC_10KHZ = 1 /*!< Low power clock - runs at 10kHz */
-} IP_WKT_CLKSRC_T;
-
-/**
- * @brief Clear WKT interrupt status
- * @param pWKT : Pointer to WKT register block
- * @return Nothing
- */
-STATIC INLINE void IP_WKT_ClearIntStatus(IP_WKT_001_T *pWKT)
-{
- if ( pWKT->CTRL & WKT_CTRL_ALARMFLAG ) {
- pWKT->CTRL |= WKT_CTRL_ALARMFLAG;
- }
-}
-
-/**
- * @brief Clear and stop WKT counter
- * @param pWKT : Pointer to WKT register block
- * @return Nothing
- */
-STATIC INLINE void IP_WKT_Stop(IP_WKT_001_T *pWKT)
-{
- pWKT->CTRL |= WKT_CTRL_CLEARCTR;
-}
-
-/**
- * @brief Set the WKT clock source
- * @param pWKT : Pointer to WKT register block
- * @param clkSrc : WKT Clock source(WKT_CLKSRC_10KHZ or WKT_CLKSRC_DIVIRC)
- * @return Nothing
- */
-STATIC INLINE void IP_WKT_SetClockSource(IP_WKT_001_T *pWKT, IP_WKT_CLKSRC_T clkSrc)
-{
- if (clkSrc == IP_WKT_CLKSRC_10KHZ) {
- pWKT->CTRL |= WKT_CTRL_CLKSEL; /* using Low Power clock 10kHz */
- }
- else {
- pWKT->CTRL &= ~WKT_CTRL_CLKSEL; /* using Divided IRC clock 750kHz */
- }
-}
-
-/**
- * @brief Set the WKT counter value & start the counter
- * @param pWKT : Pointer to WKT register block
- * @param cntVal : WKT Counter value
- * @return Nothing
- */
-STATIC INLINE void IP_WKT_Start(IP_WKT_001_T *pWKT, uint32_t cntVal)
-{
- pWKT->COUNT = cntVal;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WKT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wwdt_001.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wwdt_001.h
deleted file mode 100644
index cc32739f0..000000000
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/LPCOpen/lpc_core/lpc_ip/wwdt_001.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * @brief Windowed Watchdog Timer Registers and functions
- *
- * @note
- * Copyright(C) NXP Semiconductors, 2012
- * All rights reserved.
- *
- * @par
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * LPC products. This software is supplied "AS IS" without any warranties of
- * any kind, and NXP Semiconductors and its licensor disclaim any and
- * all warranties, express or implied, including all implied warranties of
- * merchantability, fitness for a particular purpose and non-infringement of
- * intellectual property rights. NXP Semiconductors assumes no responsibility
- * or liability for the use of the software, conveys no license or rights under any
- * patent, copyright, mask work right, or any other intellectual property rights in
- * or to any products. NXP Semiconductors reserves the right to make changes
- * in the software without notification. NXP Semiconductors also makes no
- * representation or warranty that such application will be suitable for the
- * specified use without further testing or modification.
- *
- * @par
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors' and its
- * licensor's relevant copyrights in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
- */
-
-#ifndef __WWDT_001_H_
-#define __WWDT_001_H_
-
-#include "sys_config.h"
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup IP_WWDT_001 IP: WWDT register block and driver
- * @ingroup IP_Drivers
- * Windowed Watchdog
- * @{
- */
-#if !defined(CHIP_LPC175X_6X) && !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC1343)
-#define WATCHDOG_WINDOW_SUPPORT
-#endif
-
-#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC175X_6X) \
- || defined(CHIP_LPC1347)
-#define WATCHDOG_CLKSEL_SUPPORT
-#endif
-
-/**
- * @brief Windowed Watchdog register block structure
- */
-typedef struct { /*!< WWDT Structure */
- __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
- __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */
- __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
- __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
-#ifdef WATCHDOG_CLKSEL_SUPPORT
- __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
-#else
- __I uint32_t RESERVED0;
-#endif
-#ifdef WATCHDOG_WINDOW_SUPPORT
- __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
- __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */
-#endif
-} IP_WWDT_001_T;
-
-/**
- * @brief Watchdog Mode register definitions
- */
-/** Watchdog Mode Bitmask */
-#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F)
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0))
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1))
-/** WWDT time out flag bit */
-#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2))
-/** WDT Time Out flag bit */
-#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3))
-#if !defined(CHIP_LPC175X_6X)
-/** WWDT Protect flag bit */
-#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4))
-#endif
-#if defined(WATCHDOG_CLKSEL_SUPPORT)
-/**
- * @brief Watchdog Timer Clock Source Selection register definitions
- */
-/** Clock source select bitmask */
-#define WWDT_CLKSEL_BITMASK ((uint32_t) 0x10000003)
-/** Clock source select */
-#define WWDT_CLKSEL_SOURCE(n) ((uint32_t) (n & 0x03))
-/** Lock the clock source selection */
-#define WWDT_CLKSEL_LOCK ((uint32_t) (1 << 31))
-#endif /* defined(WATCHDOG_CLKSEL_SUPPORT) */
-
-/**
- * @brief Initialize the Watchdog Timer
- * @param pWWDT : pointer to WWDT register block
- * @return None
- */
-void IP_WWDT_Init(IP_WWDT_001_T *pWWDT);
-
-/**
- * @brief De-initialize the Watchdog Timer
- * @param pWWDT : pointer to WWDT register block
- * @return None
- */
-STATIC INLINE void IP_WWDT_DeInit(IP_WWDT_001_T *pWWDT)
-{}
-
-/**
- * @brief Set WDT timeout constant value used for feed
- * @param pWWDT : pointer to WWDT register block
- * @param timeout : WDT timeout in ticks
- * @return none
- */
-STATIC INLINE void IP_WWDT_SetTimeOut(IP_WWDT_001_T *pWWDT, uint32_t timeout)
-{
- pWWDT->TC = timeout;
-}
-
-#if defined(WATCHDOG_CLKSEL_SUPPORT)
-/**
- * @brief Clock selection for Watchdog Timer
- * @param pWWDT : pointer to WWDT register block
- * @param src : Clock source selection (Or-ed value of WWDT_CLKSEL_*)
- * @return none
- */
-STATIC INLINE void IP_WWDT_SelClockSource(IP_WWDT_001_T *pWWDT, uint32_t src)
-{
- pWWDT->CLKSEL = src & WWDT_CLKSEL_BITMASK;
-}
-
-#endif /*WATCHDOG_CLKSEL_SUPPORT*/
-
-/**
- * @brief Feed watchdog timer
- * @param pWWDT : pointer to WWDT register block
- * @return None
- * @note If this function isn't called, a watchdog timer warning will occur.
- * After the warning, a timeout will occur if a feed has happened.
- */
-STATIC INLINE void IP_WWDT_Feed(IP_WWDT_001_T *pWWDT)
-{
- pWWDT->FEED = 0xAA;
- pWWDT->FEED = 0x55;
-}
-
-#if defined(WATCHDOG_WINDOW_SUPPORT)
-/**
- * @brief Set WWDT warning interrupt
- * @param pWWDT : pointer to WWDT register block
- * @param timeout : WDT warning in ticks, between 0 and 1023
- * @return None
- * @note This is the number of ticks after the watchdog interrupt that the
- * warning interrupt will be generated.
- */
-STATIC INLINE void IP_WWDT_SetWarning(IP_WWDT_001_T *pWWDT, uint32_t timeout)
-{
- pWWDT->WARNINT = timeout;
-}
-
-/**
- * @brief Set WWDT window time
- * @param pWWDT : pointer to WWDT register block
- * @param timeout : WDT timeout in ticks
- * @return none
- * @note The watchdog timer must be fed between the timeout from the IP_WWDT_SetTimeOut()
- * function and this function, with this function defining the last tick before the
- * watchdog window interrupt occurs.
- */
-STATIC INLINE void IP_WWDT_SetWindow(IP_WWDT_001_T *pWWDT, uint32_t timeout)
-{
- pWWDT->WINDOW = timeout;
-}
-
-#endif /* defined(WATCHDOG_WINDOW_SUPPORT) */
-
-/**
- * @brief Enable watchdog timer options
- * @param pWWDT : pointer to WWDT register block
- * @param options : An or'ed set of options of values
- * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return None
- * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
- * are set (or unset) with no other options.
- */
-STATIC INLINE void IP_WWDT_SetOption(IP_WWDT_001_T *pWWDT, uint32_t options)
-{
- pWWDT->MOD |= options;
-}
-
-/**
- * @brief Disable/clear watchdog timer options
- * @param pWWDT : pointer to WWDT register block
- * @param options : An or'ed set of options of values
- * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
- * @return None
- * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
- * WWDT_WDMOD_WDTOF).
- */
-STATIC INLINE void IP_WWDT_UnsetOption(IP_WWDT_001_T *pWWDT, uint32_t options)
-{
- pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
-}
-
-/**
- * @brief Enable WWDT activity
- * @param pWWDT : pointer to WWDT register block
- * @return None
- */
-STATIC INLINE void IP_WWDT_Start(IP_WWDT_001_T *pWWDT)
-{
- IP_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
- IP_WWDT_Feed(pWWDT);
-}
-
-/**
- * @brief Read WWDT status flag
- * @param pWWDT : pointer to WWDT register block
- * @return Watchdog status, an Or'ed value of WWDT_WDMOD_*
- */
-STATIC INLINE uint32_t IP_WWDT_GetStatus(IP_WWDT_001_T *pWWDT)
-{
- return pWWDT->MOD;
-}
-
-/**
- * @brief Clear WWDT interrupt status flags
- * @param pWWDT : pointer to WWDT register block
- * @param status : Or'ed value of status flag(s) that you want to clear, should be:
- * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
- * - WWDT_WDMOD_WDINT: Clear watchdog warning flag
- * @return None
- */
-void IP_WWDT_ClearStatusFlag(IP_WWDT_001_T *pWWDT, uint32_t status);
-
-/**
- * @brief Get the current value of WDT
- * @return current value of WDT
- */
-STATIC INLINE uint32_t IP_WWDT_GetCurrentCount(IP_WWDT_001_T *pWWDT)
-{
- return pWWDT->TV;
-}
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __WWDT_001_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c
new file mode 100644
index 000000000..b30c36225
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/cdcuser.c
@@ -0,0 +1,264 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: cdcuser.c
+ * Purpose: USB Communication Device Class User module
+ * Version: V1.10
+ *----------------------------------------------------------------------------
+* This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "usbhw.h"
+#include "usbcfg.h"
+#include "usbcore.h"
+#include "cdc.h"
+#include "cdcuser.h"
+
+#ifdef __ICCARM__
+#pragma data_alignment=4
+#define __align(x)
+#elif defined ( __GNUC__ )
+#define __align(x) __attribute__((aligned(x)))
+#endif
+
+unsigned char __align(4) BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet
+
+#ifdef __ICCARM__
+#undef __align(x)
+#endif
+
+/*----------------------------------------------------------------------------
+ We need a buffer for incomming data on USB port because USB receives
+ much faster than UART transmits
+ *---------------------------------------------------------------------------*/
+/* Buffer masks */
+#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2)
+ // large enough for file transfer
+#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)
+
+/* Buffer read / write macros */
+#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0)
+#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn))
+#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++])
+#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx)
+#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1)
+#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx))
+
+
+// CDC output buffer
+typedef struct __CDC_BUF_T {
+ unsigned char data[CDC_BUF_SIZE];
+ unsigned int wrIdx;
+ unsigned int rdIdx;
+} CDC_BUF_T;
+
+CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data
+
+/*----------------------------------------------------------------------------
+ read data from CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_RdOutBuf (char *buffer, const int *length) {
+ int bytesToRead, bytesRead;
+
+ /* Read *length bytes, block if *bytes are not avaialable */
+ bytesToRead = *length;
+ bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);
+ bytesRead = bytesToRead;
+
+ // ... add code to check for underrun
+
+ while (bytesToRead--) {
+ *buffer++ = CDC_BUF_RD(CDC_OutBuf);
+ }
+ return (bytesRead);
+}
+
+/*----------------------------------------------------------------------------
+ write data to CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_WrOutBuf (const char *buffer, int length) {
+ int bytesWritten;
+
+ // ... add code to check for overwrite
+
+ for( bytesWritten = 0; bytesWritten < length; bytesWritten++ ) {
+ CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer
+ }
+
+ return (bytesWritten);
+}
+
+/*----------------------------------------------------------------------------
+ check if character(s) are available at CDC_OutBuf
+ *---------------------------------------------------------------------------*/
+int CDC_OutBufAvailChar (int *availChar) {
+
+ *availChar = CDC_BUF_COUNT(CDC_OutBuf);
+
+ return (0);
+}
+/* end Buffer handling */
+
+
+
+/*----------------------------------------------------------------------------
+ CDC SendEncapsulatedCommand Request Callback
+ Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SendEncapsulatedCommand (void) {
+
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetEncapsulatedResponse Request Callback
+ Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetEncapsulatedResponse (void) {
+
+ /* ... add code to handle request */
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetCommFeature Request Callback
+ Called automatically on CDC Set_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ ( void ) wFeatureSelector;
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetCommFeature Request Callback
+ Called automatically on CDC Get_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ ( void ) wFeatureSelector;
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC ClearCommFeature Request Callback
+ Called automatically on CDC CLEAR_COMM_FATURE Request
+ Parameters: FeatureSelector
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) {
+
+ /* ... add code to handle request */
+ ( void ) wFeatureSelector;
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetLineCoding Request Callback
+ Called automatically on CDC SET_LINE_CODING Request
+ Parameters: none (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetLineCoding (void) {
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC GetLineCoding Request Callback
+ Called automatically on CDC GET_LINE_CODING Request
+ Parameters: None (global SetupPacket and EP0Buf)
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_GetLineCoding (void) {
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SetControlLineState Request Callback
+ Called automatically on CDC SET_CONTROL_LINE_STATE Request
+ Parameters: ControlSignalBitmap
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) {
+
+ /* ... add code to handle request */
+ ( void ) wControlSignalBitmap;
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC SendBreak Request Callback
+ Called automatically on CDC Set_COMM_FATURE Request
+ Parameters: 0xFFFF start of Break
+ 0x0000 stop of Break
+ 0x#### Duration of Break
+ Return Value: TRUE - Success, FALSE - Error
+ *---------------------------------------------------------------------------*/
+uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) {
+
+ /* ... add code to handle request */
+ ( void ) wDurationOfBreak;
+ return (TRUE);
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC_BulkIn call on DataIn Request
+ Parameters: none
+ Return Value: none
+ *---------------------------------------------------------------------------*/
+void CDC_BulkIn(void) {
+}
+
+
+/*----------------------------------------------------------------------------
+ CDC_BulkOut call on DataOut Request
+ Parameters: none
+ Return Value: none
+ *---------------------------------------------------------------------------*/
+void CDC_BulkOut(void) {
+ int numBytesRead;
+
+ // get data from USB into intermediate buffer
+ numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]);
+
+ // ... add code to check for overwrite
+
+ // store data in a buffer to transmit it over serial interface
+ CDC_WrOutBuf ((char *)&BulkBufOut[0], numBytesRead);
+ vCDCNewDataNotify();
+}
+
+void CDC_BulkOutNak(void){
+
+ USB_ReadReqEP(CDC_DEP_OUT, &BulkBufOut[0], 64);
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h
new file mode 100644
index 000000000..7bb2abf35
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdc.h
@@ -0,0 +1,283 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: CDC.h
+ * Purpose: USB Communication Device Class Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __CDC_H
+#define __CDC_H
+#include "lpc_types.h"
+
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+/*----------------------------------------------------------------------------
+ * Definitions based on usbcdc11.pdf (www.usb.org)
+ *---------------------------------------------------------------------------*/
+// Communication device class specification version 1.10
+#define CDC_V1_10 0x0110
+
+// Communication interface class code
+// (usbcdc11.pdf, 4.2, Table 15)
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
+
+// Communication interface class subclass codes
+// (usbcdc11.pdf, 4.3, Table 16)
+#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02
+#define CDC_TELEPHONE_CONTROL_MODEL 0x03
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04
+#define CDC_CAPI_CONTROL_MODEL 0x05
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06
+#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07
+
+// Communication interface class control protocol codes
+// (usbcdc11.pdf, 4.4, Table 17)
+#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01
+
+// Data interface class code
+// (usbcdc11.pdf, 4.5, Table 18)
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+// Data interface class protocol codes
+// (usbcdc11.pdf, 4.7, Table 19)
+#define CDC_PROTOCOL_ISDN_BRI 0x30
+#define CDC_PROTOCOL_HDLC 0x31
+#define CDC_PROTOCOL_TRANSPARENT 0x32
+#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50
+#define CDC_PROTOCOL_Q921_DATA_LINK 0x51
+#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52
+#define CDC_PROTOCOL_V42 0x90
+#define CDC_PROTOCOL_EURO_ISDN 0x91
+#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92
+#define CDC_PROTOCOL_CAPI 0x93
+#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD
+#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE
+
+// Type values for bDescriptorType field of functional descriptors
+// (usbcdc11.pdf, 5.2.3, Table 24)
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT 0x25
+
+// Type values for bDescriptorSubtype field of functional descriptors
+// (usbcdc11.pdf, 5.2.3, Table 25)
+#define CDC_HEADER 0x00
+#define CDC_CALL_MANAGEMENT 0x01
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
+#define CDC_DIRECT_LINE_MANAGEMENT 0x03
+#define CDC_TELEPHONE_RINGER 0x04
+#define CDC_REPORTING_CAPABILITIES 0x05
+#define CDC_UNION 0x06
+#define CDC_COUNTRY_SELECTION 0x07
+#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08
+#define CDC_USB_TERMINAL 0x09
+#define CDC_NETWORK_CHANNEL 0x0A
+#define CDC_PROTOCOL_UNIT 0x0B
+#define CDC_EXTENSION_UNIT 0x0C
+#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D
+#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E
+#define CDC_ETHERNET_NETWORKING 0x0F
+#define CDC_ATM_NETWORKING 0x10
+
+// CDC class-specific request codes
+// (usbcdc11.pdf, 6.2, Table 46)
+// see Table 45 for info about the specific requests.
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
+#define CDC_SET_COMM_FEATURE 0x02
+#define CDC_GET_COMM_FEATURE 0x03
+#define CDC_CLEAR_COMM_FEATURE 0x04
+#define CDC_SET_AUX_LINE_STATE 0x10
+#define CDC_SET_HOOK_STATE 0x11
+#define CDC_PULSE_SETUP 0x12
+#define CDC_SEND_PULSE 0x13
+#define CDC_SET_PULSE_TIME 0x14
+#define CDC_RING_AUX_JACK 0x15
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+#define CDC_SEND_BREAK 0x23
+#define CDC_SET_RINGER_PARMS 0x30
+#define CDC_GET_RINGER_PARMS 0x31
+#define CDC_SET_OPERATION_PARMS 0x32
+#define CDC_GET_OPERATION_PARMS 0x33
+#define CDC_SET_LINE_PARMS 0x34
+#define CDC_GET_LINE_PARMS 0x35
+#define CDC_DIAL_DIGITS 0x36
+#define CDC_SET_UNIT_PARAMETER 0x37
+#define CDC_GET_UNIT_PARAMETER 0x38
+#define CDC_CLEAR_UNIT_PARAMETER 0x39
+#define CDC_GET_PROFILE 0x3A
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define CDC_SET_ETHERNET_PMP_FILTER 0x41
+#define CDC_GET_ETHERNET_PMP_FILTER 0x42
+#define CDC_SET_ETHERNET_PACKET_FILTER 0x43
+#define CDC_GET_ETHERNET_STATISTIC 0x44
+#define CDC_SET_ATM_DATA_FORMAT 0x50
+#define CDC_GET_ATM_DEVICE_STATISTICS 0x51
+#define CDC_SET_ATM_DEFAULT_VC 0x52
+#define CDC_GET_ATM_VC_STATISTICS 0x53
+
+// Communication feature selector codes
+// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47)
+#define CDC_ABSTRACT_STATE 0x01
+#define CDC_COUNTRY_SETTING 0x02
+
+// Feature Status returned for ABSTRACT_STATE Selector
+// (usbcdc11.pdf, 6.2.3, Table 48)
+#define CDC_IDLE_SETTING (1 << 0)
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
+
+
+// Control signal bitmap values for the SetControlLineState request
+// (usbcdc11.pdf, 6.2.14, Table 51)
+#define CDC_DTE_PRESENT (1 << 0)
+#define CDC_ACTIVATE_CARRIER (1 << 1)
+
+// CDC class-specific notification codes
+// (usbcdc11.pdf, 6.3, Table 68)
+// see Table 67 for Info about class-specific notifications
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
+#define CDC_RESPONSE_AVAILABLE 0x01
+#define CDC_AUX_JACK_HOOK_STATE 0x08
+#define CDC_RING_DETECT 0x09
+#define CDC_NOTIFICATION_SERIAL_STATE 0x20
+#define CDC_CALL_STATE_CHANGE 0x28
+#define CDC_LINE_STATE_CHANGE 0x29
+#define CDC_CONNECTION_SPEED_CHANGE 0x2A
+
+// UART state bitmap values (Serial state notification).
+// (usbcdc11.pdf, 6.3.5, Table 69)
+#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred
+#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred
+#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred
+#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection
+#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection
+#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier
+#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier
+
+
+/*----------------------------------------------------------------------------
+ * Structures based on usbcdc11.pdf (www.usb.org)
+ *---------------------------------------------------------------------------*/
+
+// Header functional descriptor
+// (usbcdc11.pdf, 5.2.3.1)
+// This header must precede any list of class-specific descriptors.
+
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_HEADER_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_HEADER_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_HEADER_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // Header functional descriptor subtype
+ uint16_t bcdCDC; // USB CDC specification release version
+} CDC_HEADER_DESCRIPTOR;
+
+//Call management functional descriptor
+// (usbcdc11.pdf, 5.2.3.2)
+// Describes the processing of calls for the communication class interface.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_CALL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // call management functional descriptor subtype
+ uint8_t bmCapabilities; // capabilities that this configuration supports
+ uint8_t bDataInterface; // interface number of the data class interface used for call management (optional)
+} CDC_CALL_MANAGEMENT_DESCRIPTOR;
+
+// Abstract control management functional descriptor
+// (usbcdc11.pdf, 5.2.3.3)
+// Describes the command supported by the communication interface class with the Abstract Control Model subclass code.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype
+ uint8_t bmCapabilities; // capabilities supported by this configuration
+} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;
+
+// Union functional descriptors
+// (usbcdc11.pdf, 5.2.3.8)
+// Describes the relationship between a group of interfaces that can be considered to form a functional unit.
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_UNION_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_UNION_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_UNION_DESCRIPTOR {
+#endif
+ uint8_t bFunctionLength; // size of this descriptor in bytes
+ uint8_t bDescriptorType; // CS_INTERFACE descriptor type
+ uint8_t bDescriptorSubtype; // union functional descriptor subtype
+ uint8_t bMasterInterface; // interface number designated as master
+} CDC_UNION_DESCRIPTOR;
+
+// Union functional descriptors with one slave interface
+// (usbcdc11.pdf, 5.2.3.8)
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_UNION_1SLAVE_DESCRIPTOR{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR {
+#endif
+ CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor
+ uint8_t bSlaveInterfaces[1]; // Slave interface 0
+} CDC_UNION_1SLAVE_DESCRIPTOR;
+
+// Line coding structure
+// Format of the data returned when a GetLineCoding request is received
+// (usbcdc11.pdf, 6.2.13)
+#if defined ( __CC_ARM )
+typedef __packed struct _CDC_LINE_CODING{
+#elif defined ( __GNUC__ )
+typedef struct __packed _CDC_LINE_CODING{
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _CDC_LINE_CODING {
+#endif
+ uint32_t dwDTERate; // Data terminal rate in bits per second
+ uint8_t bCharFormat; // Number of stop bits
+ uint8_t bParityType; // Parity bit type
+ uint8_t bDataBits; // Number of data bits
+} CDC_LINE_CODING;
+
+// Notification header
+// Data sent on the notification endpoint must follow this header.
+// see USB_SETUP_PACKET in file usb.h
+typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;
+
+#endif /* __CDC_H */
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h
new file mode 100644
index 000000000..f624e7b4a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/cdcuser.h
@@ -0,0 +1,68 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: cdcuser.h
+ * Purpose: USB Communication Device Class User module Definitions
+ * Version: V1.10
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __CDCUSER_H__
+#define __CDCUSER_H__
+
+/* CDC buffer handling */
+extern int CDC_RdOutBuf (char *buffer, const int *length);
+extern int CDC_WrOutBuf (const char *buffer, int length);
+extern int CDC_OutBufAvailChar (int *availChar);
+extern void CDC_WaitNewData ( void );
+
+
+/* CDC Data In/Out Endpoint Address */
+#define CDC_DEP_IN 0x82
+#define CDC_DEP_OUT 0x02
+
+/* CDC Communication In Endpoint Address */
+#define CDC_CEP_IN 0x81
+
+/* CDC Requests Callback Functions */
+extern uint32_t CDC_SendEncapsulatedCommand (void);
+extern uint32_t CDC_GetEncapsulatedResponse (void);
+extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector);
+extern uint32_t CDC_GetLineCoding (void);
+extern uint32_t CDC_SetLineCoding (void);
+extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap);
+extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak);
+
+/* CDC Bulk Callback Functions */
+extern void CDC_BulkIn (void);
+extern void CDC_BulkOut (void);
+extern void CDC_BulkOutNak (void);
+
+/* CDC Notification Callback Function */
+extern void CDC_NotificationIn (void);
+
+/* CDC Initializtion Function */
+extern void CDC_Init (char portNum);
+
+/* CDC prepare the SERAIAL_STATE */
+extern unsigned short CDC_GetSerialState (void);
+
+/* CDC New data Notification Function */
+extern void vCDCNewDataNotify();
+
+/* flow control */
+extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty
+
+#endif /* __CDCUSER_H__ */
+
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h
new file mode 100644
index 000000000..cbfc0a2dc
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/lpc43xx_libcfg.h
@@ -0,0 +1,146 @@
+/**********************************************************************
+* $Id$ lpc43xx_libcfg.h 2011-06-02
+*//**
+* @file lpc43xx_libcfg.h
+* @brief Library configuration file
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef lpc43xx_LIBCFG_H_
+#define lpc43xx_LIBCFG_H_
+
+#include "lpc_types.h"
+
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+ the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* GPIO ------------------------------- */
+#define _GPIO
+
+/* EXTI ------------------------------- */
+//#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+#define _UART3
+
+/* SPI ------------------------------- */
+//#define _SPI
+
+/* SSP ------------------------------- */
+//#define _SSP
+//#define _SSP0
+//#define _SSP1
+
+/* SYSTICK --------------------------- */
+//#define _SYSTICK
+
+/* I2C ------------------------------- */
+//#define _I2C
+//#define _I2C0
+//#define _I2C1
+//#define _I2C2
+
+/* TIMER ------------------------------- */
+//#define _TIM
+
+/* WDT ------------------------------- */
+//#define _WDT
+
+
+/* GPDMA ------------------------------- */
+//#define _GPDMA
+
+
+/* DAC ------------------------------- */
+//#define _DAC
+
+/* DAC ------------------------------- */
+//#define _ADC
+
+
+/* PWM ------------------------------- */
+//#define _PWM
+//#define _PWM1
+
+/* RTC ------------------------------- */
+//#define _RTC
+
+/* I2S ------------------------------- */
+//#define _I2S
+
+/* USB device ------------------------------- */
+#define _USBDEV
+//#define _USB_DMA
+
+/* QEI ------------------------------- */
+//#define _QEI
+
+/* MCPWM ------------------------------- */
+//#define _MCPWM
+
+/* CAN--------------------------------*/
+//#define _CAN
+
+/* RIT ------------------------------- */
+//#define _RIT
+
+/* EMAC ------------------------------ */
+//#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief The CHECK_PARAM macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* @param[in] expr - If expr is false, it calls check_failed() function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* - If expr is true, it returns no value.
+* @return None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+
+
+/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+
+#endif /* lpc43xx_LIBCFG_H_ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h
new file mode 100644
index 000000000..629a7a036
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usb.h
@@ -0,0 +1,422 @@
+/**********************************************************************
+* $Id$ usb.h 2011-06-02
+*//**
+* @file usb.h
+* @brief USB Definitions
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __USB_H__
+#define __USB_H__
+
+#include "usbcfg.h"
+
+#ifdef USE_USB0
+#define LPC_USB LPC_USB0 // Use USB0
+#else
+#define LPC_USB LPC_USB1 // Use USB1
+#endif
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+
+#if defined ( __CC_ARM )
+typedef __packed union {
+#elif defined ( __GNUC__ )
+typedef union __packed {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef union {
+#endif
+ uint16_t W;
+#if defined ( __CC_ARM )
+ __packed struct {
+#elif defined ( __GNUC__ )
+ struct __packed {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+ struct {
+#endif
+ uint8_t L;
+ uint8_t H;
+ } WB;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+} WORD_BYTE;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+
+/* bmRequestType.Dir */
+#define REQUEST_HOST_TO_DEVICE 0
+#define REQUEST_DEVICE_TO_HOST 1
+
+/* bmRequestType.Type */
+#define REQUEST_STANDARD 0
+#define REQUEST_CLASS 1
+#define REQUEST_VENDOR 2
+#define REQUEST_RESERVED 3
+
+/* bmRequestType.Recipient */
+#define REQUEST_TO_DEVICE 0
+#define REQUEST_TO_INTERFACE 1
+#define REQUEST_TO_ENDPOINT 2
+#define REQUEST_TO_OTHER 3
+
+/* bmRequestType Definition */
+#if defined ( __CC_ARM )
+typedef __packed union _REQUEST_TYPE {
+#elif defined ( __GNUC__ )
+typedef union __packed _REQUEST_TYPE {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef union _REQUEST_TYPE {
+#endif
+#if defined ( __CC_ARM )
+ __packed struct _BM {
+#elif defined ( __GNUC__ )
+ struct __packed _BM {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+ struct _BM {
+#endif
+ uint8_t Recipient : 5;
+ uint8_t Type : 2;
+ uint8_t Dir : 1;
+ } BM;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+ uint8_t B;
+} REQUEST_TYPE;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Request Codes */
+#define USB_REQUEST_GET_STATUS 0
+#define USB_REQUEST_CLEAR_FEATURE 1
+#define USB_REQUEST_SET_FEATURE 3
+#define USB_REQUEST_SET_ADDRESS 5
+#define USB_REQUEST_GET_DESCRIPTOR 6
+#define USB_REQUEST_SET_DESCRIPTOR 7
+#define USB_REQUEST_GET_CONFIGURATION 8
+#define USB_REQUEST_SET_CONFIGURATION 9
+#define USB_REQUEST_GET_INTERFACE 10
+#define USB_REQUEST_SET_INTERFACE 11
+#define USB_REQUEST_SYNC_FRAME 12
+
+/* USB GET_STATUS Bit Values */
+#define USB_GETSTATUS_SELF_POWERED 0x01
+#define USB_GETSTATUS_REMOTE_WAKEUP 0x02
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01
+
+/* USB Standard Feature selectors */
+#define USB_FEATURE_ENDPOINT_STALL 0
+#define USB_FEATURE_REMOTE_WAKEUP 1
+#define USB_FEATURE_TEST_MODE 2
+
+/* USB Default Control Pipe Setup Packet */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_SETUP_PACKET {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_SETUP_PACKET {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_SETUP_PACKET {
+#endif
+ REQUEST_TYPE bmRequestType;
+ uint8_t bRequest;
+ WORD_BYTE wValue;
+ WORD_BYTE wIndex;
+ uint16_t wLength;
+} USB_SETUP_PACKET;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+
+/* USB Descriptor Types */
+#define USB_DEVICE_DESCRIPTOR_TYPE 1
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
+#define USB_STRING_DESCRIPTOR_TYPE 3
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
+#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6
+#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7
+#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8
+#define USB_OTG_DESCRIPTOR_TYPE 9
+#define USB_DEBUG_DESCRIPTOR_TYPE 10
+#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11
+
+/* USB Device Classes */
+#define USB_DEVICE_CLASS_RESERVED 0x00
+#define USB_DEVICE_CLASS_AUDIO 0x01
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
+#define USB_DEVICE_CLASS_MONITOR 0x04
+#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05
+#define USB_DEVICE_CLASS_POWER 0x06
+#define USB_DEVICE_CLASS_PRINTER 0x07
+#define USB_DEVICE_CLASS_STORAGE 0x08
+#define USB_DEVICE_CLASS_HUB 0x09
+#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
+
+/* bmAttributes in Configuration Descriptor */
+#define USB_CONFIG_POWERED_MASK 0x40
+#define USB_CONFIG_BUS_POWERED 0x80
+#define USB_CONFIG_SELF_POWERED 0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+/* bMaxPower in Configuration Descriptor */
+#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
+
+/* bEndpointAddress in Endpoint Descriptor */
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)
+
+/* bmAttributes in Endpoint Descriptor */
+#define USB_ENDPOINT_TYPE_MASK 0x03
+#define USB_ENDPOINT_TYPE_CONTROL 0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
+#define USB_ENDPOINT_TYPE_BULK 0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
+#define USB_ENDPOINT_SYNC_MASK 0x0C
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
+#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
+#define USB_ENDPOINT_USAGE_MASK 0x30
+#define USB_ENDPOINT_USAGE_DATA 0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
+#define USB_ENDPOINT_USAGE_RESERVED 0x30
+
+/* USB Standard Device Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_DEVICE_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_DEVICE_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_DEVICE_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} USB_DEVICE_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB 2.0 Device Qualifier Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize0;
+ uint8_t bNumConfigurations;
+ uint8_t bReserved;
+} USB_DEVICE_QUALIFIER_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Configuration Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_CONFIGURATION_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_CONFIGURATION_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} USB_CONFIGURATION_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Interface Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_INTERFACE_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_INTERFACE_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_INTERFACE_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} USB_INTERFACE_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Standard Endpoint Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_ENDPOINT_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_ENDPOINT_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_ENDPOINT_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint16_t wMaxPacketSize;
+ uint8_t bInterval;
+} USB_ENDPOINT_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB String Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_STRING_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_STRING_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_STRING_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bString/*[]*/;
+} USB_STRING_DESCRIPTOR;
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+/* USB Common Descriptor */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_COMMON_DESCRIPTOR {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_COMMON_DESCRIPTOR {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_COMMON_DESCRIPTOR {
+#endif
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+} USB_COMMON_DESCRIPTOR;
+
+/* USB Other Speed Configuration */
+#if defined ( __CC_ARM )
+typedef __packed struct _USB_OTHER_SPEED_CONFIGURATION {
+#elif defined ( __GNUC__ )
+typedef struct __packed _USB_OTHER_SPEED_CONFIGURATION {
+#elif defined ( __IAR_SYSTEMS_ICC__ )
+#pragma pack(1)
+typedef struct _USB_OTHER_SPEED_CONFIGURATION {
+#endif
+
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t IConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} USB_OTHER_SPEED_CONFIGURATION;
+
+
+/* USB Endpoint Callback Events */
+#define USB_EVT_SETUP 1 /* Setup Packet */
+#define USB_EVT_OUT 2 /* OUT Packet */
+#define USB_EVT_IN 3 /* IN Packet */
+#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */
+#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */
+#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */
+#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */
+#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */
+#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */
+#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */
+#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */
+#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */
+#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */
+
+/* call back structure */
+typedef struct _USB_INIT_
+{
+ uint32_t ep0_maxp;
+ /* USB Device Events Callback Functions */
+ void (* USB_Power_Event)(uint32_t power);
+ void (* USB_Reset_Event)(void);
+ void (* USB_Suspend_Event)(void);
+ void (* USB_Resume_Event)(void);
+ void (* USB_WakeUp_Event)(void);
+ void (* USB_SOF_Event)(void);
+ void (* USB_Error_Event)(uint32_t error);
+ /* USB Core Events Callback Functions */
+ void (* USB_Configure_Event)(void);
+ void (* USB_Interface_Event)(void);
+ void (* USB_Feature_Event)(void);
+ /* USB Endpoint Events Callback Pointers */
+ void (* USB_P_EP[4])(uint32_t event);
+} LPC_USBDRV_INIT_T;
+
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma pack()
+#endif
+
+#endif /* __USB_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h
new file mode 100644
index 000000000..a47472e64
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcfg.h
@@ -0,0 +1,135 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcfg.h
+ * Purpose: USB Custom Configuration
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added vendor specific support
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+
+#ifndef __USBCFG_H__
+#define __USBCFG_H__
+
+
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
+
+
+/*
+// USB Configuration
+// USB Power
+// Default Power Setting
+// <0=> Bus-powered
+// <1=> Self-powered
+// Max Number of Interfaces <1-256>
+// Max Number of Endpoints <1-32>
+// Max Endpoint 0 Packet Size
+// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
+//
+*/
+
+#define USB_POWER 1
+#define USB_IF_NUM 1
+#define USB_EP_NUM 4
+#define USB_MAX_PACKET0 64
+
+
+/*
+// USB Event Handlers
+// Device Events
+// Power Event
+// Reset Event
+// Suspend Event
+// Resume Event
+// Remote Wakeup Event
+// Start of Frame Event
+// Error Event
+//
+// Endpoint Events
+// Endpoint 0 Event
+// Endpoint 1 Event
+// Endpoint 2 Event
+// Endpoint 3 Event
+// Endpoint 4 Event
+//
+// USB Core Events
+// Set Configuration Event
+// Set Interface Event
+// Set/Clear Feature Event
+//
+//
+*/
+
+#define USB_POWER_EVENT 0
+#define USB_RESET_EVENT 1
+#define USB_SUSPEND_EVENT 1
+#define USB_RESUME_EVENT 1
+#define USB_WAKEUP_EVENT 0
+#define USB_SOF_EVENT 0
+#define USB_ERROR_EVENT 0
+#define USB_EP_EVENT 0x0007
+#define USB_CONFIGURE_EVENT 1
+#define USB_INTERFACE_EVENT 0
+#define USB_FEATURE_EVENT 0
+
+
+/*
+// USB Class Support
+// enables USB Class specific Requests
+// Human Interface Device (HID)
+// Interface Number <0-255>
+//
+// Mass Storage
+// Interface Number <0-255>
+//
+// Audio Device
+// Control Interface Number <0-255>
+// Streaming Interface 1 Number <0-255>
+// Streaming Interface 2 Number <0-255>
+//
+// Communication Device
+// Control Interface Number <0-255>
+// Bulk Interface Number <0-255>
+// Max Communication Device Buffer Size
+// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
+//
+//
+*/
+
+#define USB_CLASS 1
+#define USB_HID 0
+#define USB_HID_IF_NUM 0
+#define USB_MSC 0
+#define USB_MSC_IF_NUM 0
+#define USB_AUDIO 0
+#define USB_ADC_CIF_NUM 0
+#define USB_ADC_SIF1_NUM 1
+#define USB_ADC_SIF2_NUM 2
+#define USB_CDC 1
+#define USB_CDC_CIF_NUM 0
+#define USB_CDC_DIF_NUM 1
+#define USB_CDC_BUFSIZE 64
+
+/*
+// USB Vendor Support
+// enables USB Vendor specific Requests
+//
+*/
+#define USB_VENDOR 0
+
+#define USE_USB0
+
+
+#endif /* __USBCFG_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h
new file mode 100644
index 000000000..b9d0a9198
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbcore.h
@@ -0,0 +1,51 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcore.h
+ * Purpose: USB Core Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBCORE_H__
+#define __USBCORE_H__
+
+
+/* USB Endpoint Data Structure */
+typedef struct _USB_EP_DATA {
+ uint8_t *pData;
+ uint16_t Count;
+} USB_EP_DATA;
+
+/* USB Core Global Variables */
+extern uint16_t USB_DeviceStatus;
+extern uint8_t USB_DeviceAddress;
+extern uint8_t USB_Configuration;
+extern uint32_t USB_EndPointMask;
+extern uint32_t USB_EndPointHalt;
+extern uint32_t USB_EndPointStall;
+extern uint8_t USB_AltSetting[USB_IF_NUM];
+
+/* USB Endpoint 0 Buffer */
+extern uint8_t EP0Buf[USB_MAX_PACKET0];
+
+/* USB Endpoint 0 Data Info */
+extern USB_EP_DATA EP0Data;
+
+/* USB Setup Packet */
+extern USB_SETUP_PACKET SetupPacket;
+
+/* USB Core Functions */
+extern void USB_ResetCore (void);
+
+
+#endif /* __USBCORE_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h
new file mode 100644
index 000000000..6f00e0fb2
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbdesc.h
@@ -0,0 +1,41 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbdesc.h
+ * Purpose: USB Descriptors Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBDESC_H__
+#define __USBDESC_H__
+
+
+#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF)
+
+#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
+#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
+#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
+#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
+#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))
+#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))
+
+extern const uint8_t USB_DeviceDescriptor[];
+extern const uint8_t USB_FSConfigDescriptor[];
+extern const uint8_t USB_HSConfigDescriptor[];
+extern const uint8_t USB_StringDescriptor[];
+extern const uint8_t USB_DeviceQualifier[];
+extern const uint8_t USB_FSOtherSpeedConfiguration[];
+extern const uint8_t USB_HSOtherSpeedConfiguration[];
+
+
+#endif /* __USBDESC_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h
new file mode 100644
index 000000000..e946a4a78
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbhw.h
@@ -0,0 +1,156 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbhw.h
+ * Purpose: USB Hardware Layer Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added USB_ClearEPBuf
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+
+#ifndef __USBHW_H__
+#define __USBHW_H__
+#include "usb.h"
+/* dTD Transfer Description */
+typedef volatile struct
+{
+ volatile uint32_t next_dTD;
+ volatile uint32_t total_bytes ;
+ volatile uint32_t buffer0;
+ volatile uint32_t buffer1;
+ volatile uint32_t buffer2;
+ volatile uint32_t buffer3;
+ volatile uint32_t buffer4;
+ volatile uint32_t reserved;
+} DTD_T;
+
+/* dQH Queue Head */
+typedef volatile struct
+{
+ volatile uint32_t cap;
+ volatile uint32_t curr_dTD;
+ volatile uint32_t next_dTD;
+ volatile uint32_t total_bytes;
+ volatile uint32_t buffer0;
+ volatile uint32_t buffer1;
+ volatile uint32_t buffer2;
+ volatile uint32_t buffer3;
+ volatile uint32_t buffer4;
+ volatile uint32_t reserved;
+ volatile uint32_t setup[2];
+ volatile uint32_t gap[4];
+} DQH_T;
+
+/* bit defines for USBCMD register */
+#define USBCMD_RS (1<<0)
+#define USBCMD_RST (1<<1)
+#define USBCMD_ATDTW (1<<12)
+#define USBCMD_SUTW (1<<13)
+
+/* bit defines for USBSTS register */
+#define USBSTS_UI (1<<0)
+#define USBSTS_UEI (1<<1)
+#define USBSTS_PCI (1<<2)
+#define USBSTS_URI (1<<6)
+#define USBSTS_SRI (1<<7)
+#define USBSTS_SLI (1<<8)
+#define USBSTS_NAKI (1<<16)
+
+/* bit defines for DEVICEADDR register */
+#define USBDEV_ADDR_AD (1<<24)
+#define USBDEV_ADDR(n) (((n) & 0x7F)<<25)
+
+/* bit defines for PRTSC1 register */
+#define USBPRTS_CCS (1<<0)
+#define USBPRTS_PE (1<<2)
+#define USBPRTS_FPR (1<<6)
+#define USBPRTS_SUSP (1<<7)
+#define USBPRTS_PR (1<<8)
+#define USBPRTS_HSP (1<<9)
+#define USBPRTS_PLPSCD (1<<23)
+#define USBPRTS_PFSC (1<<24)
+
+/* bit defines for USBMODE register */
+#define USBMODE_CM_IDLE (0x0<<0)
+#define USBMODE_CM_DEV (0x2<<0)
+#define USBMODE_CM_HOST (0x3<<0)
+#define USBMODE_SLOM (1<<3)
+#define USBMODE_SDIS (1<<4)
+
+/* bit defines for EP registers*/
+#define USB_EP_BITPOS(n) (((n) & 0x80)? (0x10 | ((n) & 0x7)) : ((n) & 0x7))
+
+/* bit defines EPcontrol registers*/
+#define EPCTRL_RXS (1<<0)
+#define EPCTRL_RX_TYPE(n) (((n) & 0x3)<<2)
+#define EPCTRL_RX_CTL (0<<2)
+#define EPCTRL_RX_ISO (1<<2)
+#define EPCTRL_RX_BLK (2<<2)
+#define EPCTRL_RXI (1<<5)
+#define EPCTRL_RXR (1<<6)
+#define EPCTRL_RXE (1<<7)
+#define EPCTRL_TXS (1<<16)
+#define EPCTRL_TX_TYPE(n) (((n) & 0x3)<<18)
+#define EPCTRL_TX_CTL (0<<18)
+#define EPCTRL_TX_ISO (1<<18)
+#define EPCTRL_TX_BLK (2<<18)
+#define EPCTRL_TX_INT (3<<18)
+#define EPCTRL_TXI (1<<21)
+#define EPCTRL_TXR (1<<22)
+#define EPCTRL_TXE (1<<23)
+
+/* dQH field and bit defines */
+/* Temp fixed on max, should be taken out of table */
+#define QH_MAX_CTRL_PAYLOAD 0x03ff
+#define QH_MAX_PKT_LEN_POS 16
+#define QH_MAXP(n) (((n) & 0x3FF)<<16)
+#define QH_IOS (1<<15)
+#define QH_ZLT (1<<29)
+
+/* dTD field and bit defines */
+#define TD_NEXT_TERMINATE (1<<0)
+#define TD_IOC (1<<15)
+
+/* Total physical enpoints*/
+#define EP_NUM_MAX 8
+
+
+/* USB Hardware Functions */
+extern void USB_Init (LPC_USBDRV_INIT_T* cbs);
+extern void USB_Connect (uint32_t con);
+extern void USB_Reset (void);
+extern void USB_Suspend (void);
+extern void USB_Resume (void);
+extern void USB_WakeUp (void);
+extern void USB_WakeUpCfg (uint32_t cfg);
+extern void USB_SetAddress (uint32_t adr);
+extern void USB_Configure (uint32_t cfg);
+extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD);
+extern void USB_DirCtrlEP (uint32_t dir);
+extern void USB_EnableEP (uint32_t EPNum);
+extern void USB_DisableEP (uint32_t EPNum);
+extern void USB_ResetEP (uint32_t EPNum);
+extern void USB_SetStallEP (uint32_t EPNum);
+extern void USB_ClrStallEP (uint32_t EPNum);
+extern void USB_ClearEPBuf (uint32_t EPNum);
+extern uint32_t USB_SetTestMode(uint8_t mode);
+extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData);
+extern uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len);
+extern uint32_t USB_ReadSetupPkt(uint32_t, uint32_t *);
+extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt);
+extern uint32_t USB_GetFrame (void);
+//extern void USB_ISR(void) __irq;
+
+#endif /* __USBHW_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h
new file mode 100644
index 000000000..5f1479989
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/include/usbuser.h
@@ -0,0 +1,49 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbuser.h
+ * Purpose: USB Custom User Definitions
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#ifndef __USBUSER_H__
+#define __USBUSER_H__
+
+
+/* USB Device Events Callback Functions */
+extern void USB_Power_Event (uint32_t power);
+extern void USB_Reset_Event (void);
+extern void USB_Suspend_Event (void);
+extern void USB_Resume_Event (void);
+extern void USB_WakeUp_Event (void);
+extern void USB_SOF_Event (void);
+extern void USB_Error_Event (uint32_t error);
+
+/* USB Endpoint Events Callback Pointers */
+extern void (* const USB_P_EP[USB_EP_NUM])(uint32_t event);
+
+/* USB Endpoint Events Callback Functions */
+extern void USB_EndPoint0 (uint32_t event);
+extern void USB_EndPoint1 (uint32_t event);
+extern void USB_EndPoint2 (uint32_t event);
+extern void USB_EndPoint3 (uint32_t event);
+extern void USB_EndPoint4 (uint32_t event);
+extern void USB_EndPoint5 (uint32_t event);
+
+/* USB Core Events Callback Functions */
+extern void USB_Configure_Event (void);
+extern void USB_Interface_Event (void);
+extern void USB_Feature_Event (void);
+
+
+#endif /* __USBUSER_H__ */
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf
new file mode 100644
index 000000000..5778adbf7
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom-win7.inf
@@ -0,0 +1,60 @@
+;
+; Keil - An ARM Company Comunication Device Class driver installation file
+; (C)2007 Copyright
+;
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%Keil%
+LayoutFile=layout.inf
+DriverVer=01/06/07
+
+[Manufacturer]
+%Keil%=DeviceList,NT,NTamd64
+
+[DestinationDirs]
+DefaultDestDir=12
+
+[SourceDisksFiles]
+
+[SourceDisksNames]
+
+[DeviceList.NT]
+%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002
+[DeviceList.NTamd64]
+%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002
+
+;------------------------------------------------------------------------------
+; Windows Sections
+;------------------------------------------------------------------------------
+
+[LPC18xxUSB.NT]
+Include=mdmcpq.inf
+CopyFiles=FakeModemCopyFileSection
+AddReg=LPC18xxUSB.NT.AddReg
+
+[LPC18xxUSB.NT.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[LPC18xxUSB.NT.Services]
+AddService=usbser, 0x00000002, DriverService.NT
+
+[DriverService.NT]
+DisplayName=%DESCRIPTION%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\usbser.sys
+LoadOrderGroup = Base
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+
+[Strings]
+NXP="NXP - Founded by Philips"
+DESCRIPTION="LPC18xx USB VCom Port"
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf
new file mode 100644
index 000000000..715179f16
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/inf/lpc18xx-vcom.inf
@@ -0,0 +1,65 @@
+;
+; Keil - An ARM Company Comunication Device Class driver installation file
+; (C)2007 Copyright
+;
+
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%Keil%
+;LayoutFile=layout.inf
+DriverVer=01/06/07
+
+[Manufacturer]
+%Keil%=DeviceList
+
+[DestinationDirs]
+DefaultDestDir=12
+
+[SourceDisksFiles]
+
+[SourceDisksNames]
+
+[DeviceList]
+%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002
+
+;------------------------------------------------------------------------------
+; Windows 2000/XP Sections
+;------------------------------------------------------------------------------
+
+[LPC18xxUSB.nt]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles
+AddReg=LPC18xxUSB.nt.AddReg
+
+[DriverCopyFiles]
+usbser.sys,,,0x20
+
+[LPC18xxUSB.nt.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[LPC18xxUSB.nt.Services]
+include=mdmcpq.inf
+AddService=usbser, 0x00000002, DriverService
+
+
+[LPC18xxUSB.nt.HW]
+include=mdmcpq.inf
+
+[DriverService]
+DisplayName=%DESCRIPTION%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\usbser.sys
+
+;------------------------------------------------------------------------------
+; String Definitions
+;------------------------------------------------------------------------------
+
+[Strings]
+NXP="NXP - Founded by Philips"
+DESCRIPTION="LPC18xx USB VCom Port"
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c
new file mode 100644
index 000000000..554390aa7
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbcore.c
@@ -0,0 +1,1130 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbcore.c
+ * Purpose: USB Core Module
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Added vendor specific requests
+ * Changed string descriptor handling
+ * Reworked Endpoint0
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+#include "lpc18xx.H"
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "usbcfg.h"
+#include "usbhw.h"
+#include "usbcore.h"
+#include "usbdesc.h"
+#include "usbuser.h"
+
+#if (USB_CLASS)
+
+#if (USB_AUDIO)
+#include "audio.h"
+#include "adcuser.h"
+#endif
+
+#if (USB_HID)
+#include "hid.h"
+#include "hiduser.h"
+#endif
+
+#if (USB_MSC)
+#include "msc.h"
+#include "mscuser.h"
+extern MSC_CSW CSW;
+#endif
+
+#if (USB_CDC)
+#include "cdc.h"
+#include "cdcuser.h"
+#endif
+
+#endif
+
+#if (USB_VENDOR)
+#include "vendor.h"
+#endif
+
+#ifdef __CC_ARM
+#pragma diag_suppress 111,177,1441
+#endif
+
+#if defined ( __GNUC__ )
+#define __packed __attribute__((__packed__))
+#endif
+
+uint16_t USB_DeviceStatus;
+uint8_t USB_DeviceAddress;
+uint8_t USB_Configuration;
+uint32_t USB_EndPointMask;
+uint32_t USB_EndPointHalt;
+uint32_t USB_EndPointStall; /* EP must stay stalled */
+uint8_t USB_NumInterfaces;
+uint8_t USB_AltSetting[USB_IF_NUM];
+
+USB_EP_DATA EP0Data;
+
+#pragma pack(4)
+uint8_t EP0Buf[USB_MAX_PACKET0];
+USB_SETUP_PACKET SetupPacket;
+
+extern volatile uint32_t DevStatusFS2HS;
+
+/*
+ * Reset USB Core
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_ResetCore (void) {
+
+ USB_DeviceStatus = USB_POWER;
+ USB_DeviceAddress = 0;
+ USB_Configuration = 0;
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall = 0x00000000;
+}
+
+
+/*
+ * USB Request - Setup Stage
+ * Parameters: None (global SetupPacket)
+ * Return Value: None
+ */
+
+void USB_SetupStage (void) {
+ USB_ReadSetupPkt(0x00, (uint32_t *)&SetupPacket);
+}
+
+
+/*
+ * USB Request - Data In Stage
+ * Parameters: None (global EP0Data)
+ * Return Value: None
+ */
+
+void USB_DataInStage (void) {
+ uint32_t cnt;
+
+ if (EP0Data.Count > USB_MAX_PACKET0) {
+ cnt = USB_MAX_PACKET0;
+ } else {
+ cnt = EP0Data.Count;
+ }
+ cnt = USB_WriteEP(0x80, EP0Data.pData, cnt);
+ EP0Data.pData += cnt;
+ EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Request - Data Out Stage
+ * Parameters: None (global EP0Data)
+ * Return Value: None
+ */
+
+void USB_DataOutStage (void) {
+ uint32_t cnt;
+
+ cnt = USB_ReadEP(0x00, EP0Data.pData);
+ EP0Data.pData += cnt;
+ EP0Data.Count -= cnt;
+}
+
+
+/*
+ * USB Request - Status In Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_StatusInStage (void) {
+ USB_WriteEP(0x80, NULL, 0);
+}
+
+
+/*
+ * USB Request - Status Out Stage
+ * Parameters: None
+ * Return Value: None
+ */
+
+void USB_StatusOutStage (void) {
+ USB_ReadEP(0x00, EP0Buf);
+}
+
+
+/*
+ * Get Status USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqGetStatus (void) {
+ uint32_t n, m;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ EP0Data.pData = (uint8_t *)&USB_DeviceStatus;
+ break;
+ case REQUEST_TO_INTERFACE:
+ if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
+ *((__packed uint16_t *)EP0Buf) = 0;
+ EP0Data.pData = EP0Buf;
+ } else {
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_ENDPOINT:
+ n = SetupPacket.wIndex.WB.L & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) {
+ *((__packed uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;
+ EP0Data.pData = EP0Buf;
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set/Clear Feature USB Request
+ * Parameters: sc: 0 - Clear, 1 - Set
+ * (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqSetClrFeature (uint32_t sc) {
+ uint32_t n, m;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) {
+ if (sc) {
+ USB_WakeUpCfg(TRUE);
+ USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP;
+ } else {
+ USB_WakeUpCfg(FALSE);
+ USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP;
+ }
+ } else if (SetupPacket.wValue.W == USB_FEATURE_TEST_MODE) {
+ return USB_SetTestMode(SetupPacket.wIndex.WB.H);
+ } else {
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_INTERFACE:
+ return (FALSE);
+ case REQUEST_TO_ENDPOINT:
+ n = SetupPacket.wIndex.WB.L & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) {
+ if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) {
+ if (sc) {
+ USB_SetStallEP(n);
+ USB_EndPointHalt |= m;
+ } else {
+ if ((USB_EndPointStall & m) != 0) {
+ return (TRUE);
+ }
+ USB_ClrStallEP(n);
+#if (USB_MSC)
+ if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) {
+ /* Compliance Test: rewrite CSW after unstall */
+ if (CSW.dSignature == MSC_CSW_Signature) {
+ USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW));
+ }
+ }
+#endif
+ USB_EndPointHalt &= ~m;
+ }
+ } else {
+ return (FALSE);
+ }
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Address USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqSetAddress (void) {
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L;
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Get Descriptor USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqGetDescriptor (void) {
+ uint8_t *pD;
+ uint32_t len, n;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ switch (SetupPacket.wValue.WB.H) {
+ case USB_DEVICE_DESCRIPTOR_TYPE:
+ EP0Data.pData = (uint8_t *)USB_DeviceDescriptor;
+ len = USB_DEVICE_DESC_SIZE;
+ break;
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if ( DevStatusFS2HS == FALSE ) {
+ pD = (uint8_t *)USB_FSConfigDescriptor;
+ } else {
+ pD = (uint8_t *)USB_HSConfigDescriptor;
+ }
+ for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ }
+ }
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {
+ return (FALSE);
+ }
+ EP0Data.pData = pD;
+ len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ break;
+ case USB_STRING_DESCRIPTOR_TYPE:
+ pD = (uint8_t *)USB_StringDescriptor;
+ for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) {
+ pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength;
+ }
+ }
+ if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) {
+ return (FALSE);
+ }
+ EP0Data.pData = pD;
+ len = ((USB_STRING_DESCRIPTOR *)pD)->bLength;
+ break;
+ case USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE:
+ /* USB Chapter 9. page 9.6.2 */
+ if ( DevStatusFS2HS == FALSE ) {
+ return (FALSE);
+ }
+ else
+ {
+ EP0Data.pData = (uint8_t *)USB_DeviceQualifier;
+ len = USB_DEVICE_QUALI_SIZE;
+ }
+ break;
+ case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE:
+ if ( DevStatusFS2HS == TRUE ) {
+ pD = (uint8_t *)USB_FSOtherSpeedConfiguration;
+ } else {
+ pD = (uint8_t *)USB_HSOtherSpeedConfiguration;
+ }
+
+ for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
+ if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength != 0) {
+ pD += ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength;
+ }
+ }
+ if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength == 0) {
+ return (FALSE);
+ }
+ EP0Data.pData = pD;
+ len = ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength;
+ break;
+ default:
+ return (FALSE);
+ }
+ break;
+ case REQUEST_TO_INTERFACE:
+ switch (SetupPacket.wValue.WB.H) {
+#if USB_HID
+ case HID_HID_DESCRIPTOR_TYPE:
+ if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
+ return (FALSE); /* Only Single HID Interface is supported */
+ }
+ if ( DevStatusFS2HS == FALSE ) {
+ EP0Data.pData = (uint8_t *)USB_FSConfigDescriptor + HID_DESC_OFFSET;
+ } else {
+ EP0Data.pData = (uint8_t *)USB_HSConfigDescriptor + HID_DESC_OFFSET;
+ }
+ len = HID_DESC_SIZE;
+ break;
+ case HID_REPORT_DESCRIPTOR_TYPE:
+ if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
+ return (FALSE); /* Only Single HID Interface is supported */
+ }
+ EP0Data.pData = (uint8_t *)HID_ReportDescriptor;
+ len = HID_ReportDescSize;
+ break;
+ case HID_PHYSICAL_DESCRIPTOR_TYPE:
+ return (FALSE); /* HID Physical Descriptor is not supported */
+#endif
+ default:
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+
+ if (EP0Data.Count > len) {
+ EP0Data.Count = len;
+ }
+
+ return (TRUE);
+}
+
+
+/*
+ * Get Configuration USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqGetConfiguration (void) {
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ EP0Data.pData = &USB_Configuration;
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Configuration USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqSetConfiguration (void) {
+ USB_COMMON_DESCRIPTOR *pD;
+ uint32_t alt = 0;
+ uint32_t n, m;
+ uint32_t new_addr;
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+
+ if (SetupPacket.wValue.WB.L) {
+ if ( DevStatusFS2HS == FALSE ) {
+ pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor;
+ } else {
+ pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor;
+ }
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) {
+ USB_Configuration = SetupPacket.wValue.WB.L;
+ USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces;
+ for (n = 0; n < USB_IF_NUM; n++) {
+ USB_AltSetting[n] = 0;
+ }
+ for (n = 1; n < USB_EP_NUM; n++) {
+ if (USB_EndPointMask & (1 << n)) {
+ USB_DisableEP(n);
+ }
+ if (USB_EndPointMask & ((1 << 16) << n)) {
+ USB_DisableEP(n | 0x80);
+ }
+ }
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall= 0x00000000;
+ USB_Configure(TRUE);
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) {
+ USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED;
+ } else {
+ USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED;
+ }
+ } else {
+ new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ pD = (USB_COMMON_DESCRIPTOR*)new_addr;
+ continue;
+ }
+ break;
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ break;
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (alt == 0) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ USB_EndPointMask |= m;
+ USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
+ USB_EnableEP(n);
+ USB_ResetEP(n);
+ }
+ break;
+ }
+ new_addr = (uint32_t)pD + pD->bLength;
+ pD = (USB_COMMON_DESCRIPTOR*)new_addr;
+ }
+ }
+ else {
+ USB_Configuration = 0;
+ for (n = 1; n < USB_EP_NUM; n++) {
+ if (USB_EndPointMask & (1 << n)) {
+ USB_DisableEP(n);
+ }
+ if (USB_EndPointMask & ((1 << 16) << n)) {
+ USB_DisableEP(n | 0x80);
+ }
+ }
+ USB_EndPointMask = 0x00010001;
+ USB_EndPointHalt = 0x00000000;
+ USB_EndPointStall = 0x00000000;
+ USB_Configure(FALSE);
+ }
+
+ if (USB_Configuration != SetupPacket.wValue.WB.L) {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Get Interface USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqGetInterface (void) {
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
+ EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L;
+ } else {
+ return (FALSE);
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+ return (TRUE);
+}
+
+
+/*
+ * Set Interface USB Request
+ * Parameters: None (global SetupPacket)
+ * Return Value: TRUE - Success, FALSE - Error
+ */
+
+INLINE uint32_t USB_ReqSetInterface (void) {
+ USB_COMMON_DESCRIPTOR *pD;
+ uint32_t ifn = 0, alt = 0, old = 0, msk = 0;
+ uint32_t n, m;
+ uint32_t set, new_addr;
+
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_INTERFACE:
+ if (USB_Configuration == 0) return (FALSE);
+ set = FALSE;
+ if ( DevStatusFS2HS == FALSE ) {
+ pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor;
+ } else {
+ pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor;
+ }
+ while (pD->bLength) {
+ switch (pD->bDescriptorType) {
+ case USB_CONFIGURATION_DESCRIPTOR_TYPE:
+ if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) {
+ new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
+ pD = (USB_COMMON_DESCRIPTOR*)new_addr;
+ continue;
+ }
+ break;
+ case USB_INTERFACE_DESCRIPTOR_TYPE:
+ ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber;
+ alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
+ msk = 0;
+ if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) {
+ set = TRUE;
+ old = USB_AltSetting[ifn];
+ USB_AltSetting[ifn] = (uint8_t)alt;
+ }
+ break;
+ case USB_ENDPOINT_DESCRIPTOR_TYPE:
+ if (ifn == SetupPacket.wIndex.WB.L) {
+ n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
+ m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
+ if (alt == SetupPacket.wValue.WB.L) {
+ USB_EndPointMask |= m;
+ USB_EndPointHalt &= ~m;
+ USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
+ USB_EnableEP(n);
+ USB_ResetEP(n);
+ msk |= m;
+ }
+ else if ((alt == old) && ((msk & m) == 0)) {
+ USB_EndPointMask &= ~m;
+ USB_EndPointHalt &= ~m;
+ USB_DisableEP(n);
+ }
+ }
+ break;
+ }
+ new_addr = (uint32_t)pD + pD->bLength;
+ pD = (USB_COMMON_DESCRIPTOR*)new_addr;
+ }
+ break;
+ default:
+ return (FALSE);
+ }
+
+ return (set);
+}
+
+
+/*
+ * USB Endpoint 0 Event Callback
+ * Parameters: event
+ * Return Value: none
+ */
+
+void USB_EndPoint0 (uint32_t event) {
+
+ switch (event) {
+ case USB_EVT_SETUP:
+ USB_SetupStage();
+ USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir);
+ EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */
+ switch (SetupPacket.bmRequestType.BM.Type) {
+
+ case REQUEST_STANDARD:
+ switch (SetupPacket.bRequest) {
+ case USB_REQUEST_GET_STATUS:
+ if (!USB_ReqGetStatus()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_CLEAR_FEATURE:
+ if (!USB_ReqSetClrFeature(0)) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_FEATURE_EVENT
+ USB_Feature_Event();
+#endif
+ break;
+
+ case USB_REQUEST_SET_FEATURE:
+ if (!USB_ReqSetClrFeature(1)) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_FEATURE_EVENT
+ USB_Feature_Event();
+#endif
+ break;
+
+ case USB_REQUEST_SET_ADDRESS:
+ if (!USB_ReqSetAddress()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+ break;
+
+ case USB_REQUEST_GET_DESCRIPTOR:
+ if (!USB_ReqGetDescriptor()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_DESCRIPTOR:
+/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */
+ EP0Data.Count = 0;
+ break;
+
+ case USB_REQUEST_GET_CONFIGURATION:
+ if (!USB_ReqGetConfiguration()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_CONFIGURATION:
+ if (!USB_ReqSetConfiguration()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_CONFIGURE_EVENT
+ USB_Configure_Event();
+#endif
+ break;
+
+ case USB_REQUEST_GET_INTERFACE:
+ if (!USB_ReqGetInterface()) {
+ goto stall_i;
+ }
+ USB_DataInStage();
+ break;
+
+ case USB_REQUEST_SET_INTERFACE:
+ if (!USB_ReqSetInterface()) {
+ goto stall_i;
+ }
+ USB_StatusInStage();
+#if USB_INTERFACE_EVENT
+ USB_Interface_Event();
+#endif
+ break;
+
+ default:
+ goto stall_i;
+ }
+ break; /* end case REQUEST_STANDARD */
+
+#if USB_CLASS
+ case REQUEST_CLASS:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ goto stall_i; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+#if USB_HID
+ if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case HID_REQUEST_GET_REPORT:
+ if (HID_GetReport()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_REPORT:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ case HID_REQUEST_GET_IDLE:
+ if (HID_GetIdle()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_IDLE:
+ if (HID_SetIdle()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_GET_PROTOCOL:
+ if (HID_GetProtocol()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case HID_REQUEST_SET_PROTOCOL:
+ if (HID_SetProtocol()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_HID */
+#if USB_MSC
+ if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case MSC_REQUEST_RESET:
+ if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */
+ (SetupPacket.wLength == 0)) {
+ if (MSC_Reset()) {
+ USB_StatusInStage();
+ goto setup_class_ok;
+ }
+ }
+ break;
+ case MSC_REQUEST_GET_MAX_LUN:
+ if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */
+ (SetupPacket.wLength == 1)) {
+ if (MSC_GetMaxLUN()) {
+ EP0Data.pData = EP0Buf;
+ USB_DataInStage();
+ goto setup_class_ok;
+ }
+ }
+ break;
+ }
+ }
+#endif /* USB_MSC */
+#if USB_AUDIO
+ if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+ if (ADC_IF_GetRequest()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ }
+ }
+#endif /* USB_AUDIO */
+#if USB_CDC
+ if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_ENCAPSULATED_RESPONSE:
+ if (CDC_GetEncapsulatedResponse()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_COMM_FEATURE:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_COMM_FEATURE:
+ if (CDC_GetCommFeature(SetupPacket.wValue.W)) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_CLEAR_COMM_FEATURE:
+ if (CDC_ClearCommFeature(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_LINE_CODING:
+ EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
+ goto setup_class_ok;
+ case CDC_GET_LINE_CODING:
+ if (CDC_GetLineCoding()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SET_CONTROL_LINE_STATE:
+ if (CDC_SetControlLineState(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ case CDC_SEND_BREAK:
+ if (CDC_SendBreak(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto setup_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_CDC */
+ goto stall_i; /* not supported */
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+#if USB_AUDIO
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+ if (ADC_EP_GetRequest()) {
+ EP0Data.pData = EP0Buf; /* point to data to be sent */
+ USB_DataInStage(); /* send requested data */
+ goto setup_class_ok;
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ EP0Data.pData = EP0Buf; /* data to be received */
+ goto setup_class_ok;
+ }
+#endif /* USB_AUDIO */
+ goto stall_i;
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall_i;
+ }
+setup_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+#endif /* USB_CLASS */
+
+#if USB_VENDOR
+ case REQUEST_VENDOR:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ if (!USB_ReqVendorDev(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if (!USB_ReqVendorIF(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_ENDPOINT:
+ if (!USB_ReqVendorEP(TRUE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ default:
+ goto stall_i;
+ }
+
+ if (SetupPacket.wLength) {
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
+ USB_DataInStage();
+ }
+ } else {
+ USB_StatusInStage();
+ }
+
+ break; /* end case REQUEST_VENDOR */
+#endif /* USB_VENDOR */
+
+ default:
+stall_i: USB_SetStallEP(0x80);
+ EP0Data.Count = 0;
+ break;
+ }
+ break; /* end case USB_EVT_SETUP */
+
+ case USB_EVT_OUT_NAK:
+ if (SetupPacket.bmRequestType.BM.Dir == 0)
+ {
+ USB_ReadReqEP(0x00, EP0Data.pData, EP0Data.Count);
+ }
+ else
+ {
+ /* might be zero length pkt */
+ USB_ReadReqEP(0x00, EP0Data.pData, 0);
+ }
+ break;
+ case USB_EVT_OUT:
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) {
+ if (EP0Data.Count) { /* still data to receive ? */
+ USB_DataOutStage(); /* receive data */
+ if (EP0Data.Count == 0) { /* data complete ? */
+ switch (SetupPacket.bmRequestType.BM.Type) {
+
+ case REQUEST_STANDARD:
+ goto stall_i; /* not supported */
+
+#if (USB_CLASS)
+ case REQUEST_CLASS:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+ case REQUEST_TO_DEVICE:
+ goto stall_i; /* not supported */
+
+ case REQUEST_TO_INTERFACE:
+#if USB_HID
+ if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
+ switch (SetupPacket.bRequest) {
+ case HID_REQUEST_SET_REPORT:
+ if (HID_SetReport()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_HID */
+#if USB_AUDIO
+ if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
+ (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ if (ADC_IF_SetRequest()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_AUDIO */
+#if USB_CDC
+ if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
+ (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
+ switch (SetupPacket.bRequest) {
+ case CDC_SEND_ENCAPSULATED_COMMAND:
+ if (CDC_SendEncapsulatedCommand()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ case CDC_SET_COMM_FEATURE:
+ if (CDC_SetCommFeature(SetupPacket.wValue.W)) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ case CDC_SET_LINE_CODING:
+ if (CDC_SetLineCoding()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+ }
+#endif /* USB_CDC */
+ goto stall_i;
+ /* end case REQUEST_TO_INTERFACE */
+
+ case REQUEST_TO_ENDPOINT:
+#if USB_AUDIO
+ switch (SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+// case AUDIO_REQUEST_SET_MIN:
+// case AUDIO_REQUEST_SET_MAX:
+// case AUDIO_REQUEST_SET_RES:
+ if (ADC_EP_SetRequest()) {
+ USB_StatusInStage(); /* send Acknowledge */
+ goto out_class_ok;
+ }
+ break;
+ }
+#endif /* USB_AUDIO */
+ goto stall_i;
+ /* end case REQUEST_TO_ENDPOINT */
+
+ default:
+ goto stall_i;
+ }
+out_class_ok: /* request finished successfully */
+ break; /* end case REQUEST_CLASS */
+#endif /* USB_CLASS */
+
+#if USB_VENDOR
+ case REQUEST_VENDOR:
+ switch (SetupPacket.bmRequestType.BM.Recipient) {
+
+ case REQUEST_TO_DEVICE:
+ if (!USB_ReqVendorDev(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_INTERFACE:
+ if (!USB_ReqVendorIF(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ case REQUEST_TO_ENDPOINT:
+ if (!USB_ReqVendorEP(FALSE)) {
+ goto stall_i; /* not supported */
+ }
+ break;
+
+ default:
+ goto stall_i;
+ }
+
+ USB_StatusInStage();
+
+ break; /* end case REQUEST_VENDOR */
+#endif /* USB_VENDOR */
+
+ default:
+ goto stall_i;
+ }
+ }
+ }
+ } else {
+ USB_StatusOutStage(); /* receive Acknowledge */
+ }
+ break; /* end case USB_EVT_OUT */
+
+ case USB_EVT_IN :
+ if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
+ USB_DataInStage(); /* send data */
+ } else {
+ if (USB_DeviceAddress & 0x80) {
+ USB_DeviceAddress &= 0x7F;
+ USB_SetAddress(USB_DeviceAddress);
+ }
+ }
+ break; /* end case USB_EVT_IN */
+
+ case USB_EVT_OUT_STALL:
+ USB_ClrStallEP(0x00);
+ break;
+
+ case USB_EVT_IN_STALL:
+ USB_ClrStallEP(0x80);
+ break;
+
+ }
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c
new file mode 100644
index 000000000..270b838ca
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbdesc.c
@@ -0,0 +1,479 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbdesc.c
+ * Purpose: USB Descriptors
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC microcontroller devices only. Nothing else
+ * gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------
+ * History:
+ * V1.20 Changed string descriptor handling
+ * V1.00 Initial Version
+ *----------------------------------------------------------------------------*/
+#include "lpc18xx.H"
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "cdc.h"
+#include "usbcfg.h"
+#include "usbdesc.h"
+
+
+/* USB Standard Device Descriptor */
+const uint8_t USB_DeviceDescriptor[] = {
+ USB_DEVICE_DESC_SIZE, /* bLength */
+ USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0200), /* 2.0 */ /* bcdUSB */
+ USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USB_MAX_PACKET0, /* bMaxPacketSize0 */
+ WBVAL(0x1FC9), /* idVendor */
+ WBVAL(0x2002), /* idProduct */
+ WBVAL(0x0100), /* 1.00 */ /* bcdDevice */
+ 0x01, /* iManufacturer */
+ 0x02, /* iProduct */
+ 0x03, /* iSerialNumber */
+ 0x01 /* bNumConfigurations: one possible configuration*/
+};
+
+/* USB FSConfiguration Descriptor */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t USB_FSConfigDescriptor[] = {
+/* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(( /* wTotalLength */
+ 1*USB_CONFIGUARTION_DESC_SIZE +
+ 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
+ 0x0013 + /* CDC functions */
+ 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
+ 1*USB_INTERFACE_DESC_SIZE + /* data interface */
+ 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
+ )),
+ 0x02, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
+ 0x00, /* iConfiguration: no string to describe this configuration */
+ USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
+/*USB_CONFIG_REMOTE_WAKEUP*/,
+ USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
+/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: Alternate setting */
+ 0x01, /* bNumEndpoints: One endpoint used */
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/*Header Functional Descriptor*/
+ 0x05, /* bLength: Endpoint Descriptor size */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
+/*Call Management Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
+ 0x01, /* bmCapabilities: device handles call management */
+ 0x01, /* bDataInterface: CDC data IF ID */
+/*Abstract Control Management Functional Descriptor*/
+ 0x04, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
+ 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
+/*Union Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */
+ USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
+ USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
+/*Endpoint 1 Descriptor*/ /* event notification (optional) */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(1), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(0x0010), /* wMaxPacketSize */
+ 0x02, /* 2ms */ /* bInterval */
+/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: no alternate setting */
+ 0x02, /* bNumEndpoints: two endpoints used */
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
+ 0x00, /* bInterfaceSubClass: no subclass available */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/* Endpoint, EP2 Bulk Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_OUT(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Endpoint, EP2 Bulk In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Terminator */
+ 0 /* bLength */
+ /* bLength */
+};
+
+/* USB HSConfiguration Descriptor */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t USB_HSConfigDescriptor[] = {
+/* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(( /* wTotalLength */
+ 1*USB_CONFIGUARTION_DESC_SIZE +
+ 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
+ 0x0013 + /* CDC functions */
+ 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
+ 1*USB_INTERFACE_DESC_SIZE + /* data interface */
+ 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
+ )),
+ 0x02, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
+ 0x00, /* iConfiguration: no string to describe this configuration */
+ USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
+/*USB_CONFIG_REMOTE_WAKEUP*/,
+ USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
+/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: Alternate setting */
+ 0x01, /* bNumEndpoints: One endpoint used */
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/*Header Functional Descriptor*/
+ 0x05, /* bLength: Endpoint Descriptor size */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
+/*Call Management Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
+ 0x01, /* bmCapabilities: device handles call management */
+ 0x01, /* bDataInterface: CDC data IF ID */
+/*Abstract Control Management Functional Descriptor*/
+ 0x04, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
+ 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
+/*Union Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */
+ USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
+ USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
+/*Endpoint 1 Descriptor*/ /* event notification (optional) */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(1), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(0x0010), /* wMaxPacketSize */
+ 0x02, /* 2ms */ /* bInterval */
+/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: no alternate setting */
+ 0x02, /* bNumEndpoints: two endpoints used */
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
+ 0x00, /* bInterfaceSubClass: no subclass available */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/* Endpoint, EP2 Bulk Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_OUT(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Endpoint, EP2 Bulk In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Terminator */
+ 0 /* bLength */
+ /* bLength */
+};
+
+/* USB String Descriptor (optional) */
+const uint8_t USB_StringDescriptor[] = {
+/* Index 0x00: LANGID Codes */
+ 0x04, /* bLength */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0409), /* US English */ /* wLANGID */
+/* Index 0x01: Manufacturer */
+ (16*2 + 2), /* bLength (13 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'N',0,
+ 'G',0,
+ 'X',0,
+ ' ',0,
+ 'T',0,
+ 'E',0,
+ 'C',0,
+ 'H',0,
+ 'N',0,
+ 'O',0,
+ 'L',0,
+ 'O',0,
+ 'G',0,
+ 'I',0,
+ 'E',0,
+ 'S',0,
+/* Index 0x02: Product */
+ (17*2 + 2), /* bLength ( 17 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'N',0,
+ 'G',0,
+ 'X',0,
+ ' ',0,
+ 'L',0,
+ 'P',0,
+ 'C',0,
+ '1',0,
+ '8',0,
+ 'x',0,
+ 'x',0,
+ ' ',0,
+ 'V',0,
+ 'C',0,
+ 'O',0,
+ 'M',0,
+ ' ',0,
+/* Index 0x03: Serial Number */
+ (12*2 + 2), /* bLength (12 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'D',0,
+ 'E',0,
+ 'M',0,
+ 'O',0,
+ '0',0,
+ '0',0,
+ '0',0,
+ '0',0,
+ '0',0,
+ '0',0,
+ '0',0,
+ '0',0,
+/* Index 0x04: Interface 0, Alternate Setting 0 */
+ ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'V',0,
+ 'C',0,
+ 'O',0,
+ 'M',0,
+};
+
+/* USB Device Qualifier */
+const uint8_t USB_DeviceQualifier[] = {
+ USB_DEVICE_QUALI_SIZE, /* bLength */
+ USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0200), /* 2.00 */ /* bcdUSB */
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USB_MAX_PACKET0, /* bMaxPacketSize0 */
+ 0x01, /* bNumOtherSpeedConfigurations */
+ 0x00 /* bReserved */
+};
+
+/* USB Configuration Descriptor */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t USB_FSOtherSpeedConfiguration[] = {
+/* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(( /* wTotalLength */
+ 1*USB_CONFIGUARTION_DESC_SIZE +
+ 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
+ 0x0013 + /* CDC functions */
+ 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
+ 1*USB_INTERFACE_DESC_SIZE + /* data interface */
+ 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
+ )),
+ 0x02, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
+ 0x00, /* iConfiguration: no string to describe this configuration */
+ USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
+/*USB_CONFIG_REMOTE_WAKEUP*/,
+ USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
+/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: Alternate setting */
+ 0x01, /* bNumEndpoints: One endpoint used */
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/*Header Functional Descriptor*/
+ 0x05, /* bLength: Endpoint Descriptor size */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
+/*Call Management Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
+ 0x01, /* bmCapabilities: device handles call management */
+ 0x01, /* bDataInterface: CDC data IF ID */
+/*Abstract Control Management Functional Descriptor*/
+ 0x04, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
+ 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
+/*Union Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */
+ USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
+ USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
+/*Endpoint 1 Descriptor*/ /* event notification (optional) */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(1), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(0x0010), /* wMaxPacketSize */
+ 0x02, /* 2ms */ /* bInterval */
+/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: no alternate setting */
+ 0x02, /* bNumEndpoints: two endpoints used */
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
+ 0x00, /* bInterfaceSubClass: no subclass available */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/* Endpoint, EP2 Bulk Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_OUT(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Endpoint, EP2 Bulk In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Terminator */
+ 0 /* bLength */
+};
+
+/* USB Configuration Descriptor */
+/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t USB_HSOtherSpeedConfiguration[] = {
+/* Configuration 1 */
+ USB_CONFIGUARTION_DESC_SIZE, /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(( /* wTotalLength */
+ 1*USB_CONFIGUARTION_DESC_SIZE +
+ 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
+ 0x0013 + /* CDC functions */
+ 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
+ 1*USB_INTERFACE_DESC_SIZE + /* data interface */
+ 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
+ )),
+ 0x02, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
+ 0x00, /* iConfiguration: no string to describe this configuration */
+ USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
+/*USB_CONFIG_REMOTE_WAKEUP*/,
+ USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
+/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: Alternate setting */
+ 0x01, /* bNumEndpoints: One endpoint used */
+ CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
+ CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/*Header Functional Descriptor*/
+ 0x05, /* bLength: Endpoint Descriptor size */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
+ WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
+/*Call Management Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
+ 0x01, /* bmCapabilities: device handles call management */
+ 0x01, /* bDataInterface: CDC data IF ID */
+/*Abstract Control Management Functional Descriptor*/
+ 0x04, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
+ 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
+/*Union Functional Descriptor*/
+ 0x05, /* bFunctionLength */
+ CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
+ CDC_UNION, /* bDescriptorSubtype: Union func desc */
+ USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
+ USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
+/*Endpoint 1 Descriptor*/ /* event notification (optional) */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(1), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(0x0010), /* wMaxPacketSize */
+ 0x02, /* 2ms */ /* bInterval */
+/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
+ 0x00, /* bAlternateSetting: no alternate setting */
+ 0x02, /* bNumEndpoints: two endpoints used */
+ CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
+ 0x00, /* bInterfaceSubClass: no subclass available */
+ 0x00, /* bInterfaceProtocol: no protocol used */
+ 0x5E, /* iInterface: */
+/* Endpoint, EP2 Bulk Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_OUT(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Endpoint, EP2 Bulk In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ USB_ENDPOINT_IN(2), /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
+ WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
+ 0x00, /* bInterval: ignore for Bulk transfer */
+/* Terminator */
+ 0 /* bLength */
+};
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c
new file mode 100644
index 000000000..a49596f8e
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbhw.c
@@ -0,0 +1,803 @@
+/**********************************************************************
+* $Id$ usbhw.c 2011-06-02
+*//**
+* @file usbhw.c
+* @brief USB Hardware Layer Module for NXP's lpc43xx MCU
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+#include
+#include "lpc18xx.H" /* lpc43xx definitions */
+#include "lpc_types.h"
+#include "usb.h"
+#include "usbhw.h"
+#include "usbcfg.h"
+#include "usbcore.h"
+#include "lpc18xx_scu.h"
+#include "lpc18xx_cgu.h"
+#include "FreeRTOS.h"
+#ifdef __CC_ARM
+#pragma diag_suppress 1441
+#endif
+
+#ifdef __ICCARM__
+#pragma data_alignment=2048
+DQH_T ep_QH[EP_NUM_MAX];
+#pragma data_alignment=32
+DTD_T ep_TD[EP_NUM_MAX];
+#pragma data_alignment=4
+#elif defined ( __GNUC__ )
+#define __align(x) __attribute__((aligned(x)))
+DQH_T ep_QH[EP_NUM_MAX] __attribute__((aligned(2048)));
+DTD_T ep_TD[EP_NUM_MAX] __attribute__((aligned(32)));
+#else
+DQH_T __align(2048) ep_QH[EP_NUM_MAX];
+DTD_T __align(32) ep_TD[EP_NUM_MAX];
+#endif
+
+
+static uint32_t ep_read_len[4];
+volatile uint32_t DevStatusFS2HS = FALSE;
+LPC_USBDRV_INIT_T g_drv;
+
+/*
+ * Get Endpoint Physical Address
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: Endpoint Physical Address
+ */
+
+uint32_t EPAdr (uint32_t EPNum) {
+ uint32_t val;
+
+ val = (EPNum & 0x0F) << 1;
+ if (EPNum & 0x80) {
+ val += 1;
+ }
+ return (val);
+}
+
+/*
+ * USB Initialize Function
+ * Called by the User to initialize USB
+ * Return Value: None
+ */
+
+void USB_Init (LPC_USBDRV_INIT_T* cbs)
+{
+ memcpy(&g_drv, cbs, sizeof(LPC_USBDRV_INIT_T));
+ /*maxp for EP0 should be atleast 8 */
+ if( g_drv.ep0_maxp == 0)
+ g_drv.ep0_maxp = 64;
+
+#ifdef USE_USB0
+ scu_pinmux(0x8,1,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_1 1: usb0 usb0_ind1 2: nc 3: gpio4 gpio4_1
+ scu_pinmux(0x8,2,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_0 1: usb0 usb0_ind0 2: nc 3: gpio4 gpio4_2
+#endif
+#ifdef USE_USB0
+ CGU_SetPLL0();
+ CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);
+ CGU_EntityConnect(CGU_CLKSRC_PLL0, CGU_BASE_USB0);
+#else
+ CGU_SetPLL1(5);
+ CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
+ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1);
+ /* enable USB phy */
+ LPC_CREG->CREG0 &= ~(1 << 5);
+ /* enable USB1_DP and USB1_DN on chip FS phy */
+ LPC_SCU->SFSUSB = 0x12;
+ /* enable USB1_VBUS */
+ scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);
+
+#endif
+ /* Turn on the phy */
+#ifdef USE_USB0
+ LPC_CREG->CREG0 &= ~(1<<5);
+#endif
+ /* reset the controller */
+ LPC_USB->USBCMD_D = USBCMD_RST;
+ /* wait for reset to complete */
+ while (LPC_USB->USBCMD_D & USBCMD_RST);
+
+ /* Program the controller to be the USB device controller */
+ LPC_USB->USBMODE_D = USBMODE_CM_DEV
+ | USBMODE_SDIS
+ | USBMODE_SLOM ;
+
+ /* set OTG transcever in proper state, device is present
+ on the port(CCS=1), port enable/disable status change(PES=1). */
+#ifdef USE_USB0
+ LPC_USB->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+#else
+ /* force full speed */
+ LPC_USB->PORTSC1_D |= (1<<24);
+#endif
+
+#ifdef USE_USB0
+ NVIC_EnableIRQ(USB0_IRQn); // enable USB0 interrrupts
+ NVIC_SetPriority(USB0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+#else
+ NVIC_EnableIRQ(USB1_IRQn); // enable USB1 interrrupts
+ NVIC_SetPriority(USB0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+ USB_Reset();
+ USB_SetAddress(0);
+ return;
+}
+
+/*
+ * USB Connect Function
+ * Called by the User to Connect/Disconnect USB
+ * Parameters: con: Connect/Disconnect
+ * Return Value: None
+ */
+void USB_Connect (uint32_t con) {
+ if (con)
+ LPC_USB->USBCMD_D |= USBCMD_RS;
+ else
+ LPC_USB->USBCMD_D &= ~USBCMD_RS;
+}
+
+
+/*
+ * USB Reset Function
+ * Called automatically on USB Reset
+ * Return Value: None
+ */
+
+void USB_Reset (void)
+{
+ uint32_t i;
+
+ DevStatusFS2HS = FALSE;
+ /* disable all EPs */
+ LPC_USB->ENDPTCTRL0 &= ~(EPCTRL_RXE | EPCTRL_TXE);
+ LPC_USB->ENDPTCTRL2 &= ~(EPCTRL_RXE | EPCTRL_TXE);
+ LPC_USB->ENDPTCTRL3 &= ~(EPCTRL_RXE | EPCTRL_TXE);
+
+ /* Clear all pending interrupts */
+ LPC_USB->ENDPTNAK = 0xFFFFFFFF;
+ LPC_USB->ENDPTNAKEN = 0;
+ LPC_USB->USBSTS_D = 0xFFFFFFFF;
+ LPC_USB->ENDPTSETUPSTAT = LPC_USB->ENDPTSETUPSTAT;
+ LPC_USB->ENDPTCOMPLETE = LPC_USB->ENDPTCOMPLETE;
+ while (LPC_USB->ENDPTPRIME) /* Wait until all bits are 0 */
+ {
+ }
+ LPC_USB->ENDPTFLUSH = 0xFFFFFFFF;
+ while (LPC_USB->ENDPTFLUSH); /* Wait until all bits are 0 */
+
+
+ /* Set the interrupt Threshold control interval to 0 */
+ LPC_USB->USBCMD_D &= ~0x00FF0000;
+
+ /* Zero out the Endpoint queue heads */
+ memset((void*)ep_QH, 0, EP_NUM_MAX * sizeof(DQH_T));
+ /* Zero out the device transfer descriptors */
+ memset((void*)ep_TD, 0, EP_NUM_MAX * sizeof(DTD_T));
+ memset((void*)ep_read_len, 0, sizeof(ep_read_len));
+ /* Configure the Endpoint List Address */
+ /* make sure it in on 64 byte boundary !!! */
+ /* init list address */
+ LPC_USB->ENDPOINTLISTADDR = (uint32_t)ep_QH;
+ /* Initialize device queue heads for non ISO endpoint only */
+ for (i = 0; i < EP_NUM_MAX; i++)
+ {
+ ep_QH[i].next_dTD = (uint32_t)&ep_TD[i];
+ }
+ /* Enable interrupts */
+ LPC_USB->USBINTR_D = USBSTS_UI
+ | USBSTS_UEI
+ | USBSTS_PCI
+ | USBSTS_URI
+ | USBSTS_SLI
+ | USBSTS_NAKI;
+// LPC_USB->usbintr |= (0x1<<7); /* Test SOF */
+ /* enable ep0 IN and ep0 OUT */
+ ep_QH[0].cap = QH_MAXP(g_drv.ep0_maxp)
+ | QH_IOS
+ | QH_ZLT;
+ ep_QH[1].cap = QH_MAXP(g_drv.ep0_maxp)
+ | QH_IOS
+ | QH_ZLT;
+ /* enable EP0 */
+ LPC_USB->ENDPTCTRL0 = EPCTRL_RXE | EPCTRL_RXR | EPCTRL_TXE | EPCTRL_TXR;
+ return;
+
+}
+
+
+/*
+ * USB Suspend Function
+ * Called automatically on USB Suspend
+ * Return Value: None
+ */
+
+void USB_Suspend (void) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Resume Function
+ * Called automatically on USB Resume
+ * Return Value: None
+ */
+
+void USB_Resume (void) {
+ /* Performed by Hardware */
+}
+
+
+/*
+ * USB Remote Wakeup Function
+ * Called automatically on USB Remote Wakeup
+ * Return Value: None
+ */
+
+void USB_WakeUp (void) {
+
+ //if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP)
+ {
+ /* Set FPR bit in PORTSCX reg p63 */
+ LPC_USB->PORTSC1_D |= USBPRTS_FPR ;
+ }
+}
+
+
+/*
+ * USB Remote Wakeup Configuration Function
+ * Parameters: cfg: Enable/Disable
+ * Return Value: None
+ */
+
+void USB_WakeUpCfg (uint32_t cfg) {
+ ( void ) cfg;
+ /* Not needed */
+}
+
+
+/*
+ * USB Set Address Function
+ * Parameters: adr: USB Address
+ * Return Value: None
+ */
+
+void USB_SetAddress (uint32_t adr) {
+ LPC_USB->DEVICEADDR = USBDEV_ADDR(adr);
+ LPC_USB->DEVICEADDR |= USBDEV_ADDR_AD;
+}
+
+/*
+* USB set test mode Function
+* Parameters: mode: test mode
+* Return Value: TRUE if supported else FALSE
+*/
+
+uint32_t USB_SetTestMode(uint8_t mode)
+{
+ uint32_t portsc;
+
+ if ((mode > 0) && (mode < 8))
+ {
+ portsc = LPC_USB->PORTSC1_D & ~(0xF << 16);
+
+ LPC_USB->PORTSC1_D = portsc | (mode << 16);
+ return TRUE;
+ }
+ return (FALSE);
+}
+
+/*
+ * USB Configure Function
+ * Parameters: cfg: Configure/Deconfigure
+ * Return Value: None
+ */
+
+void USB_Configure (uint32_t cfg) {
+ ( void ) cfg;
+}
+
+
+/*
+ * Configure USB Endpoint according to Descriptor
+ * Parameters: pEPD: Pointer to Endpoint Descriptor
+ * Return Value: None
+ */
+
+void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) {
+ uint32_t num, lep;
+ uint32_t ep_cfg;
+ uint8_t bmAttributes;
+
+ lep = pEPD->bEndpointAddress & 0x7F;
+ num = EPAdr(pEPD->bEndpointAddress);
+
+ ep_cfg = ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep];
+ /* mask the attributes we are not-intersetd in */
+ bmAttributes = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
+ /* set EP type */
+ if (bmAttributes != USB_ENDPOINT_TYPE_ISOCHRONOUS)
+ {
+ /* init EP capabilities */
+ ep_QH[num].cap = QH_MAXP(pEPD->wMaxPacketSize)
+ | QH_IOS | QH_ZLT ;
+ /* The next DTD pointer is INVALID */
+ ep_TD[num].next_dTD = 0x01 ;
+ }
+ else
+ {
+ /* init EP capabilities */
+ ep_QH[num].cap = QH_MAXP(0x400) | QH_ZLT;
+ }
+ /* setup EP control register */
+ if (pEPD->bEndpointAddress & 0x80)
+ {
+ ep_cfg &= ~0xFFFF0000;
+ ep_cfg |= EPCTRL_TX_TYPE(bmAttributes)
+ | EPCTRL_TXR;
+ }
+ else
+ {
+ ep_cfg &= ~0xFFFF;
+ ep_cfg |= EPCTRL_RX_TYPE(bmAttributes)
+ | EPCTRL_RXR;
+ }
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] = ep_cfg;
+ return;
+}
+
+/*
+ * Set Direction for USB Control Endpoint
+ * Parameters: dir: Out (dir == 0), In (dir <> 0)
+ * Return Value: None
+ */
+
+void USB_DirCtrlEP (uint32_t dir) {
+ /* Not needed */
+ ( void ) dir;
+}
+
+
+/*
+ * Enable USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_EnableEP (uint32_t EPNum) {
+ uint32_t lep, bitpos;
+
+ lep = EPNum & 0x0F;
+
+ if (EPNum & 0x80)
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXE;
+ }
+ else
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXE;
+ /* enable NAK interrupt */
+ bitpos = USB_EP_BITPOS(EPNum);
+ LPC_USB->ENDPTNAKEN |= (1<ENDPTCTRL0))[lep] &= ~EPCTRL_TXE;
+ }
+ else
+ {
+ /* disable NAK interrupt */
+ bitpos = USB_EP_BITPOS(EPNum);
+ LPC_USB->ENDPTNAKEN &= ~(1<ENDPTCTRL0))[lep] &= ~EPCTRL_RXE;
+ }
+}
+
+/*
+ * Reset USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_ResetEP (uint32_t EPNum) {
+ uint32_t bit_pos = USB_EP_BITPOS(EPNum);
+ uint32_t lep = EPNum & 0x0F;
+
+ /* flush EP buffers */
+ LPC_USB->ENDPTFLUSH = (1<ENDPTFLUSH & (1<ENDPTCTRL0))[lep] |= EPCTRL_TXR;
+ }
+ else
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR;
+ }
+}
+
+/*
+ * Set Stall for USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_SetStallEP (uint32_t EPNum) {
+ uint32_t lep;
+
+ lep = EPNum & 0x0F;
+ if (EPNum & 0x80)
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXS;
+ }
+ else
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXS;
+ }
+}
+
+/*
+ * Clear Stall for USB Endpoint
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Return Value: None
+ */
+
+void USB_ClrStallEP (uint32_t EPNum) {
+ uint32_t lep;
+
+ lep = EPNum & 0x0F;
+ if (EPNum & 0x80)
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_TXS;
+ /* reset data toggle */
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXR;
+ }
+ else
+ {
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_RXS;
+ /* reset data toggle */
+ ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR;
+ }
+}
+
+/*
+ * Process DTD
+ * Parameters: EPNum: Endpoint Number
+ * EPNum.0..3: Address
+ * EPNum.7: Dir
+ * Buffer pointer
+ * Transfer buffer size
+ * Return Value: None
+ */
+void USB_ProgDTD(uint32_t Edpt, uint32_t ptrBuff, uint32_t TsfSize)
+{
+ DTD_T* pDTD;
+
+ pDTD = (DTD_T*)&ep_TD[ Edpt ];
+
+ /* Zero out the device transfer descriptors */
+ memset((void*)pDTD, 0, sizeof(DTD_T));
+ /* The next DTD pointer is INVALID */
+ pDTD->next_dTD = 0x01 ;
+
+ /* Length */
+ pDTD->total_bytes = ((TsfSize & 0x7fff) << 16);
+ pDTD->total_bytes |= TD_IOC ;
+ pDTD->total_bytes |= 0x80 ;
+
+ pDTD->buffer0 = ptrBuff;
+ pDTD->buffer1 = (ptrBuff + 0x1000) & 0xfffff000;
+ pDTD->buffer2 = (ptrBuff + 0x2000) & 0xfffff000;
+ pDTD->buffer3 = (ptrBuff + 0x3000) & 0xfffff000;
+ pDTD->buffer4 = (ptrBuff + 0x4000) & 0xfffff000;
+
+ ep_QH[Edpt].next_dTD = (uint32_t)(&ep_TD[ Edpt ]);
+ ep_QH[Edpt].total_bytes &= (~0xC0) ;
+}
+
+/*
+* Read USB Endpoint Data
+* Parameters: EPNum: Endpoint Number
+* EPNum.0..3: Address
+* EPNum.7: Dir
+* pData: Pointer to Data Buffer
+* Return Value: Number of bytes read
+*/
+uint32_t USB_ReadSetupPkt(uint32_t EPNum, uint32_t *pData)
+{
+ uint32_t setup_int, cnt = 0;
+ uint32_t num = EPAdr(EPNum);
+
+ setup_int = LPC_USB->ENDPTSETUPSTAT ;
+ /* Clear the setup interrupt */
+ LPC_USB->ENDPTSETUPSTAT = setup_int;
+
+ /* ********************************** */
+ /* Check if we have received a setup */
+ /* ********************************** */
+ if (setup_int & (1<<0)) /* Check only for bit 0 */
+ /* No setup are admitted on other endpoints than 0 */
+ {
+ do
+ {
+ /* Setup in a setup - must considere only the second setup */
+ /*- Set the tripwire */
+ LPC_USB->USBCMD_D |= USBCMD_SUTW ;
+
+ /* Transfer Set-up data to the gtmudsCore_Request buffer */
+ pData[0] = ep_QH[num].setup[0];
+ pData[1] = ep_QH[num].setup[1];
+ cnt = 8;
+
+ }
+ while (!(LPC_USB->USBCMD_D & USBCMD_SUTW)) ;
+
+ /* setup in a setup - Clear the tripwire */
+ LPC_USB->USBCMD_D &= (~USBCMD_SUTW);
+ }
+ while ((setup_int = LPC_USB->ENDPTSETUPSTAT) != 0)
+ {
+ /* Clear the setup interrupt */
+ LPC_USB->ENDPTSETUPSTAT = setup_int;
+ }
+ return cnt;
+}
+
+/*
+* Enque read request
+* Parameters: EPNum: Endpoint Number
+* EPNum.0..3: Address
+* EPNum.7: Dir
+* pData: Pointer to Data Buffer
+* Return Value: Number of bytes read
+*/
+
+uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len)
+{
+ uint32_t num = EPAdr(EPNum);
+ uint32_t n = USB_EP_BITPOS(EPNum);
+
+ USB_ProgDTD(num, (uint32_t)pData, len);
+ ep_read_len[EPNum & 0x0F] = len;
+ /* prime the endpoint for read */
+ LPC_USB->ENDPTPRIME |= (1<total_bytes >> 16) & 0x7FFF;
+ cnt = ep_read_len[EPNum & 0x0F] - cnt;
+ return (cnt);
+}
+
+/*
+* Write USB Endpoint Data
+* Parameters: EPNum: Endpoint Number
+* EPNum.0..3: Address
+* EPNum.7: Dir
+* pData: Pointer to Data Buffer
+* cnt: Number of bytes to write
+* Return Value: Number of bytes written
+*/
+uint32_t USB_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
+{
+ uint32_t x = 0, n = USB_EP_BITPOS(EPNum);
+
+ USB_ProgDTD(EPAdr(EPNum), (uint32_t)pData, cnt);
+ /* prime the endpoint for transmit */
+ LPC_USB->ENDPTPRIME |= (1<ENDPTPRIME & (1<USBSTS_D; /* Device Interrupt Status */
+ LPC_USB->USBSTS_D = disr;
+
+// printf("USB interrupt: 0x%08x\n",disr);
+
+// LPC_UART1->THR = 'U';
+// LPC_UART1->THR = 'S';
+// LPC_UART1->THR = 'B';
+// LPC_UART1->THR = '\n';
+
+
+ /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
+ if (disr & USBSTS_URI) /* Reset */
+ {
+// LPC_UART1->THR = 'R';
+// LPC_UART1->THR = '\n';
+ USB_Reset();
+ if (g_drv.USB_Reset_Event)
+ g_drv.USB_Reset_Event();
+ return;
+ //goto isr_end;
+ }
+
+ if (disr & USBSTS_SLI) /* Suspend */
+ {
+// LPC_UART1->THR = 'U';
+// LPC_UART1->THR = '\n';
+ if (g_drv.USB_Suspend_Event)
+ g_drv.USB_Suspend_Event();
+ }
+
+ if (disr & USBSTS_PCI) /* Resume */
+ {
+// LPC_UART1->THR = 'P';
+// LPC_UART1->THR = '\n';
+ /* check if device isoperating in HS mode or full speed */
+ if (LPC_USB->PORTSC1_D & (1<<9))
+ DevStatusFS2HS = TRUE;
+
+ if (g_drv.USB_Resume_Event)
+ g_drv.USB_Resume_Event();
+ }
+
+ /* handle setup status interrupts */
+ val = LPC_USB->ENDPTSETUPSTAT;
+ /* Only EP0 will have setup packets so call EP0 handler */
+ if (val)
+ {
+// LPC_UART1->THR = 'S';
+// LPC_UART1->THR = '\n';
+ /* Clear the endpoint complete CTRL OUT & IN when */
+ /* a Setup is received */
+ LPC_USB->ENDPTCOMPLETE = 0x00010001;
+ /* enable NAK inetrrupts */
+ LPC_USB->ENDPTNAKEN |= 0x00010001;
+ if (g_drv.USB_P_EP[0]){
+// LPC_UART1->THR = 's';
+// LPC_UART1->THR = '\n';
+ g_drv.USB_P_EP[0](USB_EVT_SETUP);
+ }
+ }
+
+ /* handle completion interrupts */
+ val = LPC_USB->ENDPTCOMPLETE;
+ if (val)
+ {
+// LPC_UART1->THR = 'C';
+// LPC_UART1->THR = '\n';
+
+ LPC_USB->ENDPTNAK = val;
+ for (n = 0; n < EP_NUM_MAX / 2; n++)
+ {
+ if (val & (1<ENDPTCOMPLETE = (1<ENDPTCOMPLETE = (1<<(n + 16));
+ }
+ }
+ }
+
+ if (disr & USBSTS_NAKI)
+ {
+// LPC_UART1->THR = 'N';
+// LPC_UART1->THR = '\n';
+ val = LPC_USB->ENDPTNAK;
+ val &= LPC_USB->ENDPTNAKEN;
+ /* handle NAK interrupts */
+ if (val)
+ {
+ for (n = 0; n < EP_NUM_MAX / 2; n++)
+ {
+ if (val & (1<ENDPTNAK = val;
+ }
+ }
+
+ /* Start of Frame Interrupt */
+ if (disr & USBSTS_SRI)
+ {
+// LPC_UART1->THR = 'F';
+// LPC_UART1->THR = '\n';
+ if (g_drv.USB_SOF_Event)
+ g_drv.USB_SOF_Event();
+ }
+
+ /* Error Interrupt */
+ if (disr & USBSTS_UEI)
+ {
+// LPC_UART1->THR = 'E';
+// LPC_UART1->THR = '\n';
+ if (g_drv.USB_Error_Event)
+ g_drv.USB_Error_Event(disr);
+ }
+
+// LPC_UART1->THR = 'r';
+// LPC_UART1->THR = '\n';
+//isr_end:
+// LPC_VIC->VectAddr = 0; /* Acknowledge Interrupt */
+ return;
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c
new file mode 100644
index 000000000..b0226ac2a
--- /dev/null
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/USB_CDC/usbuser.c
@@ -0,0 +1,221 @@
+/*----------------------------------------------------------------------------
+ * U S B - K e r n e l
+ *----------------------------------------------------------------------------
+ * Name: usbuser.c
+ * Purpose: USB Custom User Module
+ * Version: V1.20
+ *----------------------------------------------------------------------------
+ * This software is supplied "AS IS" without any warranties, express,
+ * implied or statutory, including but not limited to the implied
+ * warranties of fitness for purpose, satisfactory quality and
+ * noninfringement. Keil extends you a royalty-free right to reproduce
+ * and distribute executable files created using this software for use
+ * on NXP Semiconductors LPC family microcontroller devices only. Nothing
+ * else gives you the right to use this software.
+ *
+ * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include "lpc18xx.H"
+#include "lpc_types.h"
+
+#include "usb.h"
+#include "usbcfg.h"
+#include "usbhw.h"
+#include "usbcore.h"
+#include "usbuser.h"
+#include "cdcuser.h"
+
+
+
+/*
+ * USB Power Event Callback
+ * Called automatically on USB Power Event
+ * Parameter: power: On(TRUE)/Off(FALSE)
+ */
+
+#if USB_POWER_EVENT
+void USB_Power_Event (uint32_t power) {
+}
+#endif
+
+
+/*
+ * USB Reset Event Callback
+ * Called automatically on USB Reset Event
+ */
+
+#if USB_RESET_EVENT
+void USB_Reset_Event (void) {
+ USB_ResetCore();
+}
+#endif
+
+
+/*
+ * USB Suspend Event Callback
+ * Called automatically on USB Suspend Event
+ */
+
+#if USB_SUSPEND_EVENT
+void USB_Suspend_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Resume Event Callback
+ * Called automatically on USB Resume Event
+ */
+
+#if USB_RESUME_EVENT
+void USB_Resume_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Remote Wakeup Event Callback
+ * Called automatically on USB Remote Wakeup Event
+ */
+
+#if USB_WAKEUP_EVENT
+void USB_WakeUp_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Start of Frame Event Callback
+ * Called automatically on USB Start of Frame Event
+ */
+
+#if USB_SOF_EVENT
+void USB_SOF_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Error Event Callback
+ * Called automatically on USB Error Event
+ * Parameter: error: Error Code
+ */
+
+#if USB_ERROR_EVENT
+void USB_Error_Event (uint32_t error) {
+}
+#endif
+
+
+/*
+ * USB Set Configuration Event Callback
+ * Called automatically on USB Set Configuration Request
+ */
+
+#if USB_CONFIGURE_EVENT
+void USB_Configure_Event (void) {
+
+ if (USB_Configuration) { /* Check if USB is configured */
+ /* add your code here */
+ }
+}
+#endif
+
+
+/*
+ * USB Set Interface Event Callback
+ * Called automatically on USB Set Interface Request
+ */
+
+#if USB_INTERFACE_EVENT
+void USB_Interface_Event (void) {
+}
+#endif
+
+
+/*
+ * USB Set/Clear Feature Event Callback
+ * Called automatically on USB Set/Clear Feature Request
+ */
+
+#if USB_FEATURE_EVENT
+void USB_Feature_Event (void) {
+}
+#endif
+
+
+#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL)
+
+/* USB Endpoint Events Callback Pointers */
+void (* const USB_P_EP[USB_EP_NUM]) (uint32_t event) = {
+ P_EP(0),
+ P_EP(1),
+ P_EP(2),
+ P_EP(3),
+};
+
+
+/*
+ * USB Endpoint 1 Event Callback
+ * Called automatically on USB Endpoint 1 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint1 (uint32_t event) {
+ ( void ) event;
+}
+
+
+/*
+ * USB Endpoint 2 Event Callback
+ * Called automatically on USB Endpoint 2 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint2 (uint32_t event) {
+ switch (event) {
+ case USB_EVT_OUT_NAK:
+ CDC_BulkOutNak();
+ break;
+ case USB_EVT_OUT:
+ CDC_BulkOut (); /* data received from Host */
+ break;
+ case USB_EVT_IN:
+ CDC_BulkIn (); /* data expected from Host */
+ break;
+ }
+}
+
+
+/*
+ * USB Endpoint 3 Event Callback
+ * Called automatically on USB Endpoint 3 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint3 (uint32_t event) {
+ ( void ) event;
+}
+
+
+/*
+ * USB Endpoint 4 Event Callback
+ * Called automatically on USB Endpoint 4 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint4 (uint32_t event) {
+ ( void ) event;
+}
+
+
+/*
+ * USB Endpoint 5 Event Callback
+ * Called automatically on USB Endpoint 5 Event
+ * Parameter: event
+ */
+
+void USB_EndPoint5 (uint32_t event) {
+ ( void ) event;
+}
diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c
index 54c2add54..6007ff01c 100644
--- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c
+++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/main.c
@@ -90,8 +90,7 @@
#include "CDCCommandConsole.h"
/* Library includes. */
-#include "cmsis.h"
-#include "Board_API.h"
+#include "LPC18xx.h"
/* The size of the stack and the priority used by the two echo client tasks. */
#define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )
@@ -100,12 +99,12 @@
/* The size of the stack and the priority used by the USB CDC command console
task. */
#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )
-#define mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ( 4U )
/*
- * Register commands that can be used with FreeRTOS+CLI. The commands are
- * defined in CLI-commands.c.
- */
+* Register commands that can be used with FreeRTOS+CLI. The commands are
+* defined in CLI-commands.c.
+*/
extern void vRegisterCLICommands( void );
/*
@@ -142,9 +141,6 @@ const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_
int main( void )
{
- /* Hardware setup. */
- Board_Init();
-
/* The examples assume that all priority bits are assigned as preemption
priority bits. */
NVIC_SetPriorityGrouping( 0UL );