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Merge branch 'main' into fix-cmake-spaces

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Rahul Kar 2025-03-28 09:16:30 +05:30 committed by GitHub
parent 2338737f30 0030d609a4
commit 34c854dd9e
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26 changed files with 5022 additions and 5092 deletions
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4
.github/.cSpellWords.txt vendored
View file

@ -786,6 +786,7 @@ SHPR
SHTIM
SIFIVE
sinclude
slli
SODR
SOFTIRQ
SPCK
@ -937,6 +938,7 @@ USRIO
utest
utilises
utilising
vcsr
VDDCORE
vect
Vect
@ -947,6 +949,7 @@ visualisation
vldmdbeq
vldmia
vldmiaeq
vlenb
VMSRNE
vpop
VPOPNE
@ -954,6 +957,7 @@ vpush
VPUSHNE
VRPM
Vrtc
vsetvl
vstmdbeq
vstmiaeq
VTOR

10
portable/ARMv8M/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM23/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM23_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM33/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM33_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM35P/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM35P_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM55/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM55_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM85/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/GCC/ARM_CM85_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

2
portable/GCC/RISC-V/port.c
View file

@ -90,7 +90,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
uint64_t ullNextTime = 0ULL;
const uint64_t * pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
/* Holds the critical nesting value - deliberately non-zero at start up to

9
portable/GCC/RISC-V/portASM.S
View file

@ -192,6 +192,7 @@ definitions. */
* x5
* portTASK_RETURN_ADDRESS
* [FPU registers (when enabled/available) go here]
* [VPU registers (when enabled/available) go here]
* [chip specific registers go here]
* mstatus
* pxCode
@ -233,6 +234,14 @@ chip_specific_stack_frame: /* First add any chip specific registers
or t0, t0, t1
#endif
#if( configENABLE_VPU == 1 )
/* Mark the VPU as clean in the mstatus value. */
li t1, ~MSTATUS_VS_MASK
and t0, t0, t1
li t1, MSTATUS_VS_CLEAN
or t0, t0, t1
#endif
addi a0, a0, -portWORD_SIZE
store_x t0, 0(a0) /* mstatus onto the stack. */

269
portable/GCC/RISC-V/portContext.h
View file

@ -33,6 +33,10 @@
#define configENABLE_FPU 0
#endif
#ifndef configENABLE_VPU
#define configENABLE_VPU 0
#endif
#if __riscv_xlen == 64
#define portWORD_SIZE 8
#define store_x sd
@ -87,9 +91,29 @@
#define portFPU_REG_SIZE ( __riscv_flen / 8 )
#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
#else
#error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU
#error configENABLE_FPU must not be set to 1 if the hardware does not have FPU
#endif
#endif
#if ( configENABLE_VPU == 1 )
/* Bit [10:9] in the mstatus encode the status of VPU state which is one of
* the following values:
* 1. Value: 0, Meaning: Off.
* 2. Value: 1, Meaning: Initial.
* 3. Value: 2, Meaning: Clean.
* 4. Value: 3, Meaning: Dirty.
*/
#define MSTATUS_VS_MASK 0x600
#define MSTATUS_VS_INITIAL 0x200
#define MSTATUS_VS_CLEAN 0x400
#define MSTATUS_VS_DIRTY 0x600
#define MSTATUS_VS_OFFSET 9
#ifndef __riscv_vector
#error configENABLE_VPU must not be set to 1 if the hardware does not have VPU
#endif
#endif
/*-----------------------------------------------------------*/
@ -103,83 +127,149 @@
.macro portcontexSAVE_FPU_CONTEXT
addi sp, sp, -( portFPU_CONTEXT_SIZE )
/* Store the FPU registers. */
store_f f0, 2 * portFPU_REG_SIZE( sp )
store_f f1, 3 * portFPU_REG_SIZE( sp )
store_f f2, 4 * portFPU_REG_SIZE( sp )
store_f f3, 5 * portFPU_REG_SIZE( sp )
store_f f4, 6 * portFPU_REG_SIZE( sp )
store_f f5, 7 * portFPU_REG_SIZE( sp )
store_f f6, 8 * portFPU_REG_SIZE( sp )
store_f f7, 9 * portFPU_REG_SIZE( sp )
store_f f8, 10 * portFPU_REG_SIZE( sp )
store_f f9, 11 * portFPU_REG_SIZE( sp )
store_f f10, 12 * portFPU_REG_SIZE( sp )
store_f f11, 13 * portFPU_REG_SIZE( sp )
store_f f12, 14 * portFPU_REG_SIZE( sp )
store_f f13, 15 * portFPU_REG_SIZE( sp )
store_f f14, 16 * portFPU_REG_SIZE( sp )
store_f f15, 17 * portFPU_REG_SIZE( sp )
store_f f16, 18 * portFPU_REG_SIZE( sp )
store_f f17, 19 * portFPU_REG_SIZE( sp )
store_f f18, 20 * portFPU_REG_SIZE( sp )
store_f f19, 21 * portFPU_REG_SIZE( sp )
store_f f20, 22 * portFPU_REG_SIZE( sp )
store_f f21, 23 * portFPU_REG_SIZE( sp )
store_f f22, 24 * portFPU_REG_SIZE( sp )
store_f f23, 25 * portFPU_REG_SIZE( sp )
store_f f24, 26 * portFPU_REG_SIZE( sp )
store_f f25, 27 * portFPU_REG_SIZE( sp )
store_f f26, 28 * portFPU_REG_SIZE( sp )
store_f f27, 29 * portFPU_REG_SIZE( sp )
store_f f28, 30 * portFPU_REG_SIZE( sp )
store_f f29, 31 * portFPU_REG_SIZE( sp )
store_f f30, 32 * portFPU_REG_SIZE( sp )
store_f f31, 33 * portFPU_REG_SIZE( sp )
store_f f0, portFPU_REG_OFFSET( 0 )( sp )
store_f f1, portFPU_REG_OFFSET( 1 )( sp )
store_f f2, portFPU_REG_OFFSET( 2 )( sp )
store_f f3, portFPU_REG_OFFSET( 3 )( sp )
store_f f4, portFPU_REG_OFFSET( 4 )( sp )
store_f f5, portFPU_REG_OFFSET( 5 )( sp )
store_f f6, portFPU_REG_OFFSET( 6 )( sp )
store_f f7, portFPU_REG_OFFSET( 7 )( sp )
store_f f8, portFPU_REG_OFFSET( 8 )( sp )
store_f f9, portFPU_REG_OFFSET( 9 )( sp )
store_f f10, portFPU_REG_OFFSET( 10 )( sp )
store_f f11, portFPU_REG_OFFSET( 11 )( sp )
store_f f12, portFPU_REG_OFFSET( 12 )( sp )
store_f f13, portFPU_REG_OFFSET( 13 )( sp )
store_f f14, portFPU_REG_OFFSET( 14 )( sp )
store_f f15, portFPU_REG_OFFSET( 15 )( sp )
store_f f16, portFPU_REG_OFFSET( 16 )( sp )
store_f f17, portFPU_REG_OFFSET( 17 )( sp )
store_f f18, portFPU_REG_OFFSET( 18 )( sp )
store_f f19, portFPU_REG_OFFSET( 19 )( sp )
store_f f20, portFPU_REG_OFFSET( 20 )( sp )
store_f f21, portFPU_REG_OFFSET( 21 )( sp )
store_f f22, portFPU_REG_OFFSET( 22 )( sp )
store_f f23, portFPU_REG_OFFSET( 23 )( sp )
store_f f24, portFPU_REG_OFFSET( 24 )( sp )
store_f f25, portFPU_REG_OFFSET( 25 )( sp )
store_f f26, portFPU_REG_OFFSET( 26 )( sp )
store_f f27, portFPU_REG_OFFSET( 27 )( sp )
store_f f28, portFPU_REG_OFFSET( 28 )( sp )
store_f f29, portFPU_REG_OFFSET( 29 )( sp )
store_f f30, portFPU_REG_OFFSET( 30 )( sp )
store_f f31, portFPU_REG_OFFSET( 31 )( sp )
csrr t0, fcsr
store_x t0, 34 * portFPU_REG_SIZE( sp )
store_x t0, portFPU_REG_OFFSET( 32 )( sp )
.endm
/*-----------------------------------------------------------*/
.macro portcontextRESTORE_FPU_CONTEXT
/* Restore the FPU registers. */
load_f f0, 2 * portFPU_REG_SIZE( sp )
load_f f1, 3 * portFPU_REG_SIZE( sp )
load_f f2, 4 * portFPU_REG_SIZE( sp )
load_f f3, 5 * portFPU_REG_SIZE( sp )
load_f f4, 6 * portFPU_REG_SIZE( sp )
load_f f5, 7 * portFPU_REG_SIZE( sp )
load_f f6, 8 * portFPU_REG_SIZE( sp )
load_f f7, 9 * portFPU_REG_SIZE( sp )
load_f f8, 10 * portFPU_REG_SIZE( sp )
load_f f9, 11 * portFPU_REG_SIZE( sp )
load_f f10, 12 * portFPU_REG_SIZE( sp )
load_f f11, 13 * portFPU_REG_SIZE( sp )
load_f f12, 14 * portFPU_REG_SIZE( sp )
load_f f13, 15 * portFPU_REG_SIZE( sp )
load_f f14, 16 * portFPU_REG_SIZE( sp )
load_f f15, 17 * portFPU_REG_SIZE( sp )
load_f f16, 18 * portFPU_REG_SIZE( sp )
load_f f17, 19 * portFPU_REG_SIZE( sp )
load_f f18, 20 * portFPU_REG_SIZE( sp )
load_f f19, 21 * portFPU_REG_SIZE( sp )
load_f f20, 22 * portFPU_REG_SIZE( sp )
load_f f21, 23 * portFPU_REG_SIZE( sp )
load_f f22, 24 * portFPU_REG_SIZE( sp )
load_f f23, 25 * portFPU_REG_SIZE( sp )
load_f f24, 26 * portFPU_REG_SIZE( sp )
load_f f25, 27 * portFPU_REG_SIZE( sp )
load_f f26, 28 * portFPU_REG_SIZE( sp )
load_f f27, 29 * portFPU_REG_SIZE( sp )
load_f f28, 30 * portFPU_REG_SIZE( sp )
load_f f29, 31 * portFPU_REG_SIZE( sp )
load_f f30, 32 * portFPU_REG_SIZE( sp )
load_f f31, 33 * portFPU_REG_SIZE( sp )
load_x t0, 34 * portFPU_REG_SIZE( sp )
load_f f0, portFPU_REG_OFFSET( 0 )( sp )
load_f f1, portFPU_REG_OFFSET( 1 )( sp )
load_f f2, portFPU_REG_OFFSET( 2 )( sp )
load_f f3, portFPU_REG_OFFSET( 3 )( sp )
load_f f4, portFPU_REG_OFFSET( 4 )( sp )
load_f f5, portFPU_REG_OFFSET( 5 )( sp )
load_f f6, portFPU_REG_OFFSET( 6 )( sp )
load_f f7, portFPU_REG_OFFSET( 7 )( sp )
load_f f8, portFPU_REG_OFFSET( 8 )( sp )
load_f f9, portFPU_REG_OFFSET( 9 )( sp )
load_f f10, portFPU_REG_OFFSET( 10 )( sp )
load_f f11, portFPU_REG_OFFSET( 11 )( sp )
load_f f12, portFPU_REG_OFFSET( 12 )( sp )
load_f f13, portFPU_REG_OFFSET( 13 )( sp )
load_f f14, portFPU_REG_OFFSET( 14 )( sp )
load_f f15, portFPU_REG_OFFSET( 15 )( sp )
load_f f16, portFPU_REG_OFFSET( 16 )( sp )
load_f f17, portFPU_REG_OFFSET( 17 )( sp )
load_f f18, portFPU_REG_OFFSET( 18 )( sp )
load_f f19, portFPU_REG_OFFSET( 19 )( sp )
load_f f20, portFPU_REG_OFFSET( 20 )( sp )
load_f f21, portFPU_REG_OFFSET( 21 )( sp )
load_f f22, portFPU_REG_OFFSET( 22 )( sp )
load_f f23, portFPU_REG_OFFSET( 23 )( sp )
load_f f24, portFPU_REG_OFFSET( 24 )( sp )
load_f f25, portFPU_REG_OFFSET( 25 )( sp )
load_f f26, portFPU_REG_OFFSET( 26 )( sp )
load_f f27, portFPU_REG_OFFSET( 27 )( sp )
load_f f28, portFPU_REG_OFFSET( 28 )( sp )
load_f f29, portFPU_REG_OFFSET( 29 )( sp )
load_f f30, portFPU_REG_OFFSET( 30 )( sp )
load_f f31, portFPU_REG_OFFSET( 31 )( sp )
load_x t0, portFPU_REG_OFFSET( 32 )( sp )
csrw fcsr, t0
addi sp, sp, ( portFPU_CONTEXT_SIZE )
.endm
/*-----------------------------------------------------------*/
.macro portcontexSAVE_VPU_CONTEXT
/* Un-reserve the space reserved for mstatus and epc. */
add sp, sp, ( 2 * portWORD_SIZE )
csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
neg t0, t0
/* Store the vector registers in group of 8. */
add sp, sp, t0
vs8r.v v0, (sp) /* Store v0-v7. */
add sp, sp, t0
vs8r.v v8, (sp) /* Store v8-v15. */
add sp, sp, t0
vs8r.v v16, (sp) /* Store v16-v23. */
add sp, sp, t0
vs8r.v v24, (sp) /* Store v24-v31. */
/* Store the VPU CSRs. */
addi sp, sp, -( 4 * portWORD_SIZE )
csrr t0, vstart
store_x t0, 0 * portWORD_SIZE( sp )
csrr t0, vcsr
store_x t0, 1 * portWORD_SIZE( sp )
csrr t0, vl
store_x t0, 2 * portWORD_SIZE( sp )
csrr t0, vtype
store_x t0, 3 * portWORD_SIZE( sp )
/* Re-reserve the space for mstatus and epc. */
add sp, sp, -( 2 * portWORD_SIZE )
.endm
/*-----------------------------------------------------------*/
.macro portcontextRESTORE_VPU_CONTEXT
/* Un-reserve the space reserved for mstatus and epc. */
add sp, sp, ( 2 * portWORD_SIZE )
/* Restore the VPU CSRs. */
load_x t0, 0 * portWORD_SIZE( sp )
csrw vstart, t0
load_x t0, 1 * portWORD_SIZE( sp )
csrw vcsr, t0
load_x t0, 2 * portWORD_SIZE( sp )
load_x t1, 3 * portWORD_SIZE( sp )
vsetvl x0, t0, t1 /* vlen and vtype can only be updated by using vset*vl* instructions. */
addi sp, sp, ( 4 * portWORD_SIZE )
csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */
slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */
/* Restore the vector registers. */
vl8r.v v24, (sp)
add sp, sp, t0
vl8r.v v16, (sp)
add sp, sp, t0
vl8r.v v8, (sp)
add sp, sp, t0
vl8r.v v0, (sp)
add sp, sp, t0
/* Re-reserve the space for mstatus and epc. */
add sp, sp, -( 2 * portWORD_SIZE )
.endm
/*-----------------------------------------------------------*/
.macro portcontextSAVE_CONTEXT_INTERNAL
addi sp, sp, -portCONTEXT_SIZE
store_x x1, 2 * portWORD_SIZE( sp )
@ -227,6 +317,17 @@ store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the criti
1:
#endif
#if( configENABLE_VPU == 1 )
csrr t0, mstatus
srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3
addi t2, x0, 3
bne t1, t2, 2f /* If VPU status is not dirty, do not save FPU registers. */
portcontexSAVE_VPU_CONTEXT
2:
#endif
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
csrr t0, mstatus
@ -237,14 +338,29 @@ store_x t0, 1 * portWORD_SIZE( sp )
srl t1, t0, MSTATUS_FS_OFFSET
andi t1, t1, 3
addi t2, x0, 3
bne t1, t2, 2f
bne t1, t2, 3f
li t1, ~MSTATUS_FS_MASK
and t0, t0, t1
li t1, MSTATUS_FS_CLEAN
or t0, t0, t1
csrw mstatus, t0
2:
3:
#endif
#if( configENABLE_VPU == 1 )
/* Mark the VPU as clean, if it was dirty and we saved VPU registers. */
srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3
addi t2, x0, 3
bne t1, t2, 4f
li t1, ~MSTATUS_VS_MASK
and t0, t0, t1
li t1, MSTATUS_VS_CLEAN
or t0, t0, t1
csrw mstatus, t0
4:
#endif
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
@ -287,15 +403,26 @@ csrw mstatus, t0
/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
portasmRESTORE_ADDITIONAL_REGISTERS
#if( configENABLE_VPU == 1 )
csrr t0, mstatus
srl t1, t0, MSTATUS_VS_OFFSET
andi t1, t1, 3
addi t2, x0, 3
bne t1, t2, 5f /* If VPU status is not dirty, do not restore VPU registers. */
portcontextRESTORE_VPU_CONTEXT
5:
#endif /* ifdef portasmSTORE_VPU_CONTEXT */
#if( configENABLE_FPU == 1 )
csrr t0, mstatus
srl t1, t0, MSTATUS_FS_OFFSET
andi t1, t1, 3
addi t2, x0, 3
bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */
bne t1, t2, 6f /* If FPU status is not dirty, do not restore FPU registers. */
portcontextRESTORE_FPU_CONTEXT
3:
6:
#endif /* ifdef portasmSTORE_FPU_CONTEXT */
load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */

10
portable/IAR/ARM_CM23/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM23_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM33/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM33_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM35P/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM35P_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM55/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM55_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM85/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

10
portable/IAR/ARM_CM85_NTZ/non_secure/port.c
View file

@ -241,9 +241,6 @@ typedef void ( * portISR_t )( void );
/* Enable MPU. */
#define portMPU_ENABLE_BIT ( 1UL << 0UL )
/* Expected value of the portMPU_TYPE register. */
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
/* Extract first address of the MPU region as encoded in the
* RBAR (Region Base Address Register) value. */
#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \
@ -925,12 +922,6 @@ static void prvTaskExitError( void )
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check that the MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{
/* MAIR0 - Index 0. */
portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
/* MAIR0 - Index 1. */
@ -983,7 +974,6 @@ static void prvTaskExitError( void )
* regions have privileged access. */
portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
}
}
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/

2
portable/IAR/RISC-V/port.c
View file

@ -98,7 +98,7 @@ void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
uint64_t ullNextTime = 0ULL;
const uint64_t * pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
/* Holds the critical nesting value - deliberately non-zero at start up to