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Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently.

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This commit is contained in:
Richard Barry 2019-10-22 02:03:15 +00:00
parent ef31243396
commit 343fbe795f
7 changed files with 16 additions and 29 deletions
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10
FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
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@ -38,7 +38,7 @@
* main_full.c.
*/
.align( 8 )
.align( 4 )
vRegTest1Implementation:
/* Fill the core registers with known values. */
@ -145,15 +145,14 @@ reg1_loop:
reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop
.align( 16 )
.align( 4 )
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
/*-----------------------------------------------------------*/
.align( 8 )
.align( 4 )
vRegTest2Implementation:
/* Fill the core registers with known values. */
@ -257,10 +256,9 @@ Reg2_loop:
reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop
.align( 16 )
.align( 4 )
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter