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RISC-V: refine fpu reg context offset

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The index 0 and 1 are general register which should depends on
_XLEN_.

Signed-off-by: wangfei_chen <wangfei_chen@realsil.com.cn>
This commit is contained in:
wangfei_chen 2025-03-13 14:00:36 +08:00
parent bb47bc02f2
commit 32d189d46b
1 changed files with 2 additions and 2 deletions
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4
portable/GCC/RISC-V/portContext.h
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@ -103,7 +103,7 @@
.macro portcontexSAVE_FPU_CONTEXT
addi sp, sp, -( portFPU_CONTEXT_SIZE )
/* Store the FPU registers. */
store_f f0, 2 * portFPU_REG_SIZE( sp )
store_f f0, 2 * portWORD_SIZE( sp )
store_f f1, 3 * portFPU_REG_SIZE( sp )
store_f f2, 4 * portFPU_REG_SIZE( sp )
store_f f3, 5 * portFPU_REG_SIZE( sp )
@ -142,7 +142,7 @@ store_x t0, 34 * portFPU_REG_SIZE( sp )
.macro portcontextRESTORE_FPU_CONTEXT
/* Restore the FPU registers. */
load_f f0, 2 * portFPU_REG_SIZE( sp )
load_f f0, 2 * portWORD_SIZE( sp )
load_f f1, 3 * portFPU_REG_SIZE( sp )
load_f f2, 4 * portFPU_REG_SIZE( sp )
load_f f3, 5 * portFPU_REG_SIZE( sp )