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Update some more standard demos for use on 64-bit architectures.

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Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
This commit is contained in:
Richard Barry 2016-05-06 12:40:27 +00:00
parent 0cb71ee9ce
commit 324127837c
269 changed files with 193989 additions and 181 deletions
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2
FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
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@ -357,7 +357,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
value. */
// configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
/* Restore the clobbered interrupt priority register to its original
value. */

4
FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
View file

@ -91,10 +91,6 @@
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.global vPortInstallFreeRTOSVectorTable
.macro portSAVE_CONTEXT

2
FreeRTOS/Source/portable/MemMang/heap_4.c
View file

@ -297,7 +297,7 @@ void *pvReturn = NULL;
}
#endif
configASSERT( ( ( ( uint32_t ) pvReturn ) & portBYTE_ALIGNMENT_MASK ) == 0 );
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
return pvReturn;
}
/*-----------------------------------------------------------*/