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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Add ehb instructions back into PIC32 port layer (upon advice).
Add configCLEAR_TICK_TIMER_INTERRUPT into PIC32 port layer to allow the timer configuration to be changed without any edits to the port layer being required. Add prvTaskExitError() into the PIC32 port layer to trap tasks that attempt to exit from their implementing function. Provide the ability to trap interrupt stack overflows in the PIC32 port. Radically improve the timing in the Win32 simulator port layer.
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5 changed files with 218 additions and 80 deletions
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@ -1,5 +1,5 @@
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/*
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FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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@ -116,29 +116,27 @@ vPortStartFirstTask:
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/*******************************************************************/
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.set noreorder
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.set noreorder
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.set noat
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.ent vPortYieldISR
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.ent vPortYieldISR
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vPortYieldISR:
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/* Make room for the context. First save the current status so it can be
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manipulated, and the cause and EPC registers so thier original values are
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so we can use them during this interrupt. Any
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nesting interrupts should maintain the values of these registers
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across the ISR. */
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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maintain the values of these registers across the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Interrupts above the kernel priority are going to be re-enabled. */
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srl k0, k0, 0xa
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ins k1, k0, 10, 6
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/* Prepare to re-enabled interrupt above the kernel priority. */
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ins k1, zero, 10, 6
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ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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@ -159,16 +157,16 @@ vPortYieldISR:
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after interrupts are enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. */
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sw ra, 120(s5)
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sw ra, 120(s5)
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sw s8, 116(s5)
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sw t9, 112(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t6, 100(s5)
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sw t5, 96(s5)
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sw t4, 92(s5)
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@ -185,7 +183,7 @@ vPortYieldISR:
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sw s7, 48(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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/* s5 and s6 has already been saved. */
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sw s4, 36(s5)
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sw s4, 36(s5)
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sw s3, 32(s5)
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sw s2, 28(s5)
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sw s1, 24(s5)
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@ -209,18 +207,21 @@ vPortYieldISR:
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is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
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raise the IPL value and never lower it. */
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di
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ehb
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mfc0 s7, _CP0_STATUS
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ins s7, $0, 10, 6
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ins s7, zero, 10, 6
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ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
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/* This mtc0 re-enables interrupts, but only above
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configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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mtc0 s6, _CP0_STATUS
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ehb
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/* Clear the software interrupt in the core. */
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mfc0 s6, _CP0_CAUSE
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ins s6, zero, 8, 1
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mtc0 s6, _CP0_CAUSE
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ehb
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/* Clear the interrupt in the interrupt controller. */
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la s6, IFS0CLR
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/* Clear the interrupt mask again. The saved status value is still in s7. */
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mtc0 s7, _CP0_STATUS
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ehb
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/* Restore the stack pointer from the TCB. */
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la s0, pxCurrentTCB
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/* Protect access to the k registers, and others. */
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di
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ehb
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/* Set nesting back to zero. As the lowest priority interrupt this
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interrupt cannot have nested. */
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@ -290,10 +293,11 @@ vPortYieldISR:
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lw k0, portEPC_STACK_LOCATION(sp)
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/* Remove stack frame. */
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addiu sp, sp, portCONTEXT_SIZE
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k1, _CP0_STATUS
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mtc0 k0, _CP0_EPC
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ehb
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eret
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nop
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