mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-10-14 16:57:41 -04:00
Expand RV32E demo support, prevent 'ebreak' looping (#883)
* Expand RV32E demo support, prevent 'ebreak' looping The RegTest tests are modified in the Qemu and HiFive demos to support RV32E and its limited set of registers. 'ebreak' call looping is removed in RegTest. This produces a lot of noise when debugging. * Correct whitespace * Remove 'ebreak' instruction calls The ebreak instruction sets and exception which leads to jumping around the binary. This can make debugging difficult. * Fix whitespace formatting
This commit is contained in:
Kody Stribrny
GitHub
parent
fe9322ca23
commit
2f3e5235aa
10 changed files with 931 additions and 938 deletions
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@ -187,9 +187,7 @@ reg1_loop:
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jal reg1_loop
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reg1_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg1_error_loop
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.align( 4 )
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@ -334,12 +332,8 @@ Reg2_loop:
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jal Reg2_loop
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reg2_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg2_error_loop
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.align( 4 )
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ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
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@ -51,7 +51,7 @@ vRegTest1Implementation:
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li x12, 0xc
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li x13, 0xd
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li x14, 0xe
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li x15, 0xf
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#ifndef __riscv_32e
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li x16, 0x10
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li x17, 0x11
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li x18, 0x12
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@ -67,73 +67,77 @@ vRegTest1Implementation:
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li x28, 0x1c
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li x29, 0x1d
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li x30, 0x1e
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li x31, 0x1f
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#endif
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reg1_loop:
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/* Check each register still contains the expected known value.
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vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
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vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
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uses x5 as the temporary. */
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li x31, 0x5
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bne x31, x5, reg1_error_loop
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li x31, 0x6
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bne x31, x6, reg1_error_loop
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li x31, 0x7
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bne x31, x7, reg1_error_loop
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li x31, 0x8
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bne x31, x8, reg1_error_loop
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li x31, 0x9
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bne x31, x9, reg1_error_loop
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li x31, 0xa
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bne x31, x10, reg1_error_loop
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li x31, 0xb
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bne x31, x11, reg1_error_loop
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li x31, 0xc
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bne x31, x12, reg1_error_loop
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li x31, 0xd
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bne x31, x13, reg1_error_loop
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li x31, 0xe
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bne x31, x14, reg1_error_loop
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li x31, 0xf
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bne x31, x15, reg1_error_loop
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li x31, 0x10
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bne x31, x16, reg1_error_loop
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li x31, 0x11
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bne x31, x17, reg1_error_loop
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li x31, 0x12
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bne x31, x18, reg1_error_loop
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li x31, 0x13
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bne x31, x19, reg1_error_loop
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li x31, 0x14
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bne x31, x20, reg1_error_loop
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li x31, 0x15
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bne x31, x21, reg1_error_loop
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li x31, 0x16
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bne x31, x22, reg1_error_loop
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li x31, 0x17
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bne x31, x23, reg1_error_loop
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li x31, 0x18
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bne x31, x24, reg1_error_loop
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li x31, 0x19
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bne x31, x25, reg1_error_loop
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li x31, 0x1a
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bne x31, x26, reg1_error_loop
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li x31, 0x1b
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bne x31, x27, reg1_error_loop
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li x31, 0x1c
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bne x31, x28, reg1_error_loop
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li x31, 0x1d
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bne x31, x29, reg1_error_loop
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li x31, 0x1e
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bne x31, x30, reg1_error_loop
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li x15, 0x5
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bne x15, x5, reg1_error_loop
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li x15, 0x6
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bne x15, x6, reg1_error_loop
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li x15, 0x7
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bne x15, x7, reg1_error_loop
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li x15, 0x8
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bne x15, x8, reg1_error_loop
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li x15, 0x9
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bne x15, x9, reg1_error_loop
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li x15, 0xa
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bne x15, x10, reg1_error_loop
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li x15, 0xb
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bne x15, x11, reg1_error_loop
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li x15, 0xc
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bne x15, x12, reg1_error_loop
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li x15, 0xd
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bne x15, x13, reg1_error_loop
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li x15, 0xe
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bne x15, x14, reg1_error_loop
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#ifndef __riscv_32e
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li x15, 0x10
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bne x15, x16, reg1_error_loop
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li x15, 0x11
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bne x15, x17, reg1_error_loop
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li x15, 0x12
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bne x15, x18, reg1_error_loop
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li x15, 0x13
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bne x15, x19, reg1_error_loop
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li x15, 0x14
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bne x15, x20, reg1_error_loop
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li x15, 0x15
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bne x15, x21, reg1_error_loop
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li x15, 0x16
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bne x15, x22, reg1_error_loop
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li x15, 0x17
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bne x15, x23, reg1_error_loop
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li x15, 0x18
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bne x15, x24, reg1_error_loop
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li x15, 0x19
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bne x15, x25, reg1_error_loop
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li x15, 0x1a
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bne x15, x26, reg1_error_loop
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li x15, 0x1b
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bne x15, x27, reg1_error_loop
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li x15, 0x1c
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bne x15, x28, reg1_error_loop
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li x15, 0x1d
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bne x15, x29, reg1_error_loop
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li x15, 0x1e
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bne x15, x30, reg1_error_loop
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li x15, 0x1f
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bne x15, x31, reg1_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x31, ulRegTest1LoopCounterConst
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lw x30, 0(x31)
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addi x30, x30, 1
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sw x30, 0(x31)
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lw x15, ulRegTest1LoopCounterConst
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lw x14, 0(x15)
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addi x14, x14, 1
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sw x14, 0(x15)
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/* Restore clobbered register reading for next loop. */
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li x30, 0x1e
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li x14, 0xe
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/* Yield to increase code coverage. */
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ecall
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@ -142,9 +146,7 @@ reg1_loop:
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jal reg1_loop
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reg1_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg1_error_loop
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.align( 4 )
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@ -166,6 +168,7 @@ vRegTest2Implementation:
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li x13, 0xd1
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li x14, 0xe1
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li x15, 0xf1
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#ifndef __riscv_32e
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li x16, 0x20
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li x17, 0x21
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li x18, 0x22
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@ -182,6 +185,7 @@ vRegTest2Implementation:
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li x29, 0x2d
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li x30, 0x2e
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li x31, 0x2f
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#endif
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Reg2_loop:
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@ -208,6 +212,7 @@ Reg2_loop:
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bne x5, x14, reg2_error_loop
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li x5, 0xf1
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bne x5, x15, reg2_error_loop
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#ifndef __riscv_32e
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li x5, 0x20
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bne x5, x16, reg2_error_loop
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li x5, 0x21
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@ -240,6 +245,7 @@ Reg2_loop:
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bne x5, x30, reg2_error_loop
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li x5, 0x2f
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bne x5, x31, reg2_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x5, ulRegTest2LoopCounterConst
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@ -254,12 +260,8 @@ Reg2_loop:
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jal Reg2_loop
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reg2_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg2_error_loop
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.align( 4 )
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ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
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@ -52,6 +52,7 @@ vRegTest1Implementation:
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li x13, 0xd
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li x14, 0xe
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li x15, 0xf
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#ifndef __riscv_32e
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li x16, 0x10
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li x17, 0x11
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li x18, 0x12
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@ -67,73 +68,77 @@ vRegTest1Implementation:
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li x28, 0x1c
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li x29, 0x1d
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li x30, 0x1e
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li x31, 0x1f
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#endif
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reg1_loop:
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/* Check each register still contains the expected known value.
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vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
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vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
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uses x5 as the temporary. */
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li x31, 0x5
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bne x31, x5, reg1_error_loop
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li x31, 0x6
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bne x31, x6, reg1_error_loop
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li x31, 0x7
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bne x31, x7, reg1_error_loop
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li x31, 0x8
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bne x31, x8, reg1_error_loop
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li x31, 0x9
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bne x31, x9, reg1_error_loop
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li x31, 0xa
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bne x31, x10, reg1_error_loop
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li x31, 0xb
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bne x31, x11, reg1_error_loop
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li x31, 0xc
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bne x31, x12, reg1_error_loop
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li x31, 0xd
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bne x31, x13, reg1_error_loop
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li x31, 0xe
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bne x31, x14, reg1_error_loop
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li x31, 0xf
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bne x31, x15, reg1_error_loop
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li x31, 0x10
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bne x31, x16, reg1_error_loop
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li x31, 0x11
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bne x31, x17, reg1_error_loop
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li x31, 0x12
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bne x31, x18, reg1_error_loop
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li x31, 0x13
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bne x31, x19, reg1_error_loop
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li x31, 0x14
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bne x31, x20, reg1_error_loop
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li x31, 0x15
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bne x31, x21, reg1_error_loop
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li x31, 0x16
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bne x31, x22, reg1_error_loop
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li x31, 0x17
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bne x31, x23, reg1_error_loop
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li x31, 0x18
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bne x31, x24, reg1_error_loop
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li x31, 0x19
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bne x31, x25, reg1_error_loop
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li x31, 0x1a
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bne x31, x26, reg1_error_loop
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li x31, 0x1b
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bne x31, x27, reg1_error_loop
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li x31, 0x1c
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bne x31, x28, reg1_error_loop
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li x31, 0x1d
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bne x31, x29, reg1_error_loop
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li x31, 0x1e
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bne x31, x30, reg1_error_loop
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li x15, 0x5
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bne x15, x5, reg1_error_loop
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li x15, 0x6
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bne x15, x6, reg1_error_loop
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li x15, 0x7
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bne x15, x7, reg1_error_loop
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li x15, 0x8
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bne x15, x8, reg1_error_loop
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li x15, 0x9
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bne x15, x9, reg1_error_loop
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li x15, 0xa
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bne x15, x10, reg1_error_loop
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li x15, 0xb
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bne x15, x11, reg1_error_loop
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li x15, 0xc
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bne x15, x12, reg1_error_loop
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li x15, 0xd
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bne x15, x13, reg1_error_loop
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li x15, 0xe
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bne x15, x14, reg1_error_loop
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#ifndef __riscv_32e
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li x15, 0x10
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bne x15, x16, reg1_error_loop
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li x15, 0x11
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bne x15, x17, reg1_error_loop
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li x15, 0x12
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bne x15, x18, reg1_error_loop
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li x15, 0x13
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bne x15, x19, reg1_error_loop
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li x15, 0x14
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bne x15, x20, reg1_error_loop
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li x15, 0x15
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bne x15, x21, reg1_error_loop
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li x15, 0x16
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bne x15, x22, reg1_error_loop
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li x15, 0x17
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bne x15, x23, reg1_error_loop
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li x15, 0x18
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bne x15, x24, reg1_error_loop
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li x15, 0x19
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bne x15, x25, reg1_error_loop
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li x15, 0x1a
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bne x15, x26, reg1_error_loop
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li x15, 0x1b
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bne x15, x27, reg1_error_loop
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li x15, 0x1c
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bne x15, x28, reg1_error_loop
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li x15, 0x1d
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bne x15, x29, reg1_error_loop
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li x15, 0x1e
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bne x15, x30, reg1_error_loop
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li x15, 0x1f
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bne x15, x31, reg1_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x31, ulRegTest1LoopCounterConst
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lw x30, 0(x31)
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addi x30, x30, 1
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sw x30, 0(x31)
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lw x15, ulRegTest1LoopCounterConst
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lw x14, 0(x15)
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addi x14, x14, 1
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sw x14, 0(x15)
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/* Restore clobbered register reading for next loop. */
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li x30, 0x1e
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li x14, 0xe
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/* Yield to increase code coverage. */
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ecall
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@ -142,9 +147,7 @@ reg1_loop:
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jal reg1_loop
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reg1_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg1_error_loop
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.align( 4 )
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@ -166,6 +169,7 @@ vRegTest2Implementation:
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li x13, 0xd1
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li x14, 0xe1
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li x15, 0xf1
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#ifdef __riscv_32e
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li x16, 0x20
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li x17, 0x21
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li x18, 0x22
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@ -182,6 +186,7 @@ vRegTest2Implementation:
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li x29, 0x2d
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li x30, 0x2e
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li x31, 0x2f
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#endif
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Reg2_loop:
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@ -208,6 +213,7 @@ Reg2_loop:
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bne x5, x14, reg2_error_loop
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li x5, 0xf1
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bne x5, x15, reg2_error_loop
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#ifndef __riscv_32e
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li x5, 0x20
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bne x5, x16, reg2_error_loop
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li x5, 0x21
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@ -240,6 +246,7 @@ Reg2_loop:
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bne x5, x30, reg2_error_loop
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li x5, 0x2f
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bne x5, x31, reg2_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x5, ulRegTest2LoopCounterConst
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@ -254,9 +261,7 @@ Reg2_loop:
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jal Reg2_loop
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reg2_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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/* Busy loop which holds the task. */
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jal reg2_error_loop
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.align( 4 )
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@ -94,7 +94,7 @@
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/* Normal assert() semantics without relying on the provision of an assert.h
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* header file. */
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#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Map to the platform write function. */
|
||||
extern void vSendString( const char * const pcString );
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ vRegTest1Implementation:
|
|||
li x12, 0xc
|
||||
li x13, 0xd
|
||||
li x14, 0xe
|
||||
li x15, 0xf
|
||||
#ifndef __riscv_32e
|
||||
li x16, 0x10
|
||||
li x17, 0x11
|
||||
li x18, 0x12
|
||||
|
|
@ -70,73 +70,77 @@ vRegTest1Implementation:
|
|||
li x28, 0x1c
|
||||
li x29, 0x1d
|
||||
li x30, 0x1e
|
||||
li x31, 0x1f
|
||||
#endif
|
||||
|
||||
reg1_loop:
|
||||
|
||||
/* Check each register still contains the expected known value.
|
||||
* vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
|
||||
* vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
|
||||
* uses x5 as the temporary. */
|
||||
li x31, 0x5
|
||||
bne x31, x5, reg1_error_loop
|
||||
li x31, 0x6
|
||||
bne x31, x6, reg1_error_loop
|
||||
li x31, 0x7
|
||||
bne x31, x7, reg1_error_loop
|
||||
li x31, 0x8
|
||||
bne x31, x8, reg1_error_loop
|
||||
li x31, 0x9
|
||||
bne x31, x9, reg1_error_loop
|
||||
li x31, 0xa
|
||||
bne x31, x10, reg1_error_loop
|
||||
li x31, 0xb
|
||||
bne x31, x11, reg1_error_loop
|
||||
li x31, 0xc
|
||||
bne x31, x12, reg1_error_loop
|
||||
li x31, 0xd
|
||||
bne x31, x13, reg1_error_loop
|
||||
li x31, 0xe
|
||||
bne x31, x14, reg1_error_loop
|
||||
li x31, 0xf
|
||||
bne x31, x15, reg1_error_loop
|
||||
li x31, 0x10
|
||||
bne x31, x16, reg1_error_loop
|
||||
li x31, 0x11
|
||||
bne x31, x17, reg1_error_loop
|
||||
li x31, 0x12
|
||||
bne x31, x18, reg1_error_loop
|
||||
li x31, 0x13
|
||||
bne x31, x19, reg1_error_loop
|
||||
li x31, 0x14
|
||||
bne x31, x20, reg1_error_loop
|
||||
li x31, 0x15
|
||||
bne x31, x21, reg1_error_loop
|
||||
li x31, 0x16
|
||||
bne x31, x22, reg1_error_loop
|
||||
li x31, 0x17
|
||||
bne x31, x23, reg1_error_loop
|
||||
li x31, 0x18
|
||||
bne x31, x24, reg1_error_loop
|
||||
li x31, 0x19
|
||||
bne x31, x25, reg1_error_loop
|
||||
li x31, 0x1a
|
||||
bne x31, x26, reg1_error_loop
|
||||
li x31, 0x1b
|
||||
bne x31, x27, reg1_error_loop
|
||||
li x31, 0x1c
|
||||
bne x31, x28, reg1_error_loop
|
||||
li x31, 0x1d
|
||||
bne x31, x29, reg1_error_loop
|
||||
li x31, 0x1e
|
||||
bne x31, x30, reg1_error_loop
|
||||
li x15, 0x5
|
||||
bne x15, x5, reg1_error_loop
|
||||
li x15, 0x6
|
||||
bne x15, x6, reg1_error_loop
|
||||
li x15, 0x7
|
||||
bne x15, x7, reg1_error_loop
|
||||
li x15, 0x8
|
||||
bne x15, x8, reg1_error_loop
|
||||
li x15, 0x9
|
||||
bne x15, x9, reg1_error_loop
|
||||
li x15, 0xa
|
||||
bne x15, x10, reg1_error_loop
|
||||
li x15, 0xb
|
||||
bne x15, x11, reg1_error_loop
|
||||
li x15, 0xc
|
||||
bne x15, x12, reg1_error_loop
|
||||
li x15, 0xd
|
||||
bne x15, x13, reg1_error_loop
|
||||
li x15, 0xe
|
||||
bne x15, x14, reg1_error_loop
|
||||
#ifndef __riscv_32e
|
||||
li x15, 0x10
|
||||
bne x15, x16, reg1_error_loop
|
||||
li x15, 0x11
|
||||
bne x15, x17, reg1_error_loop
|
||||
li x15, 0x12
|
||||
bne x15, x18, reg1_error_loop
|
||||
li x15, 0x13
|
||||
bne x15, x19, reg1_error_loop
|
||||
li x15, 0x14
|
||||
bne x15, x20, reg1_error_loop
|
||||
li x15, 0x15
|
||||
bne x15, x21, reg1_error_loop
|
||||
li x15, 0x16
|
||||
bne x15, x22, reg1_error_loop
|
||||
li x15, 0x17
|
||||
bne x15, x23, reg1_error_loop
|
||||
li x15, 0x18
|
||||
bne x15, x24, reg1_error_loop
|
||||
li x15, 0x19
|
||||
bne x15, x25, reg1_error_loop
|
||||
li x15, 0x1a
|
||||
bne x15, x26, reg1_error_loop
|
||||
li x15, 0x1b
|
||||
bne x15, x27, reg1_error_loop
|
||||
li x15, 0x1c
|
||||
bne x15, x28, reg1_error_loop
|
||||
li x15, 0x1d
|
||||
bne x15, x29, reg1_error_loop
|
||||
li x15, 0x1e
|
||||
bne x15, x30, reg1_error_loop
|
||||
li x15, 0x1f
|
||||
bne x15, x31, reg1_error_loop
|
||||
#endif
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
lw x31, pulRegTest1LoopCounter
|
||||
lw x30, 0(x31)
|
||||
addi x30, x30, 1
|
||||
sw x30, 0(x31)
|
||||
lw x15, pulRegTest1LoopCounter
|
||||
lw x14, 0(x15)
|
||||
addi x14, x14, 1
|
||||
sw x14, 0(x15)
|
||||
|
||||
/* Restore clobbered register reading for next loop. */
|
||||
li x30, 0x1e
|
||||
li x14, 0xe
|
||||
|
||||
/* Yield to increase code coverage. */
|
||||
ecall
|
||||
|
|
@ -145,9 +149,7 @@ reg1_loop:
|
|||
jal reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
* counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg1_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -166,6 +168,7 @@ vRegTest2Implementation:
|
|||
li x13, 0xd1
|
||||
li x14, 0xe1
|
||||
li x15, 0xf1
|
||||
#ifndef __riscv_32e
|
||||
li x16, 0x20
|
||||
li x17, 0x21
|
||||
li x18, 0x22
|
||||
|
|
@ -182,12 +185,13 @@ vRegTest2Implementation:
|
|||
li x29, 0x2d
|
||||
li x30, 0x2e
|
||||
li x31, 0x2f
|
||||
#endif
|
||||
|
||||
Reg2_loop:
|
||||
|
||||
/* Check each register still contains the expected known value.
|
||||
* vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
|
||||
* uses x31 as the temporary. */
|
||||
* uses x15 as the temporary. */
|
||||
li x5, 0x61
|
||||
bne x5, x6, reg2_error_loop
|
||||
li x5, 0x71
|
||||
|
|
@ -208,6 +212,7 @@ Reg2_loop:
|
|||
bne x5, x14, reg2_error_loop
|
||||
li x5, 0xf1
|
||||
bne x5, x15, reg2_error_loop
|
||||
#ifndef __riscv_32e
|
||||
li x5, 0x20
|
||||
bne x5, x16, reg2_error_loop
|
||||
li x5, 0x21
|
||||
|
|
@ -240,6 +245,7 @@ Reg2_loop:
|
|||
bne x5, x30, reg2_error_loop
|
||||
li x5, 0x2f
|
||||
bne x5, x31, reg2_error_loop
|
||||
#endif
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
lw x5, pulRegTest2LoopCounter
|
||||
|
|
@ -254,9 +260,7 @@ Reg2_loop:
|
|||
jal Reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
* counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg2_error_loop
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -242,7 +242,6 @@ void vApplicationMallocFailedHook( void )
|
|||
* to query the size of free heap space that remains (although it does not
|
||||
* provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
__asm volatile( "ebreak" );
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -270,7 +269,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
|
|||
* configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
* function is called if a stack overflow is detected. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
__asm volatile( "ebreak" );
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -142,9 +142,7 @@ reg1_loop:
|
|||
jal reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
* counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg1_error_loop
|
||||
|
||||
.align( 4 )
|
||||
|
|
@ -254,9 +252,7 @@ Reg2_loop:
|
|||
jal Reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
* counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg2_error_loop
|
||||
|
||||
.align( 4 )
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ to exclude the API function. */
|
|||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* Defined in main.c and used in main_blinky.c and main_full.c. */
|
||||
void vSendString( const char * const pcString );
|
||||
|
|
|
|||
|
|
@ -142,9 +142,7 @@ reg1_loop:
|
|||
jal reg1_loop
|
||||
|
||||
reg1_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg1_error_loop
|
||||
|
||||
.align( 4 )
|
||||
|
|
@ -254,9 +252,7 @@ Reg2_loop:
|
|||
jal Reg2_loop
|
||||
|
||||
reg2_error_loop:
|
||||
/* Jump here if a register contains an uxpected value. This stops the loop
|
||||
counter being incremented so the check task knows an error was found. */
|
||||
ebreak
|
||||
/* Busy loop which holds the task. */
|
||||
jal reg2_error_loop
|
||||
|
||||
.align( 4 )
|
||||
|
|
|
|||
|
|
@ -137,7 +137,6 @@ void vApplicationMallocFailedHook( void )
|
|||
to query the size of free heap space that remains (although it does not
|
||||
provide information on how the remaining heap might be fragmented). */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
__asm volatile( "ebreak" );
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -165,7 +164,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
|
|||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
taskDISABLE_INTERRUPTS();
|
||||
__asm volatile( "ebreak" );
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue