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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Expand RV32E demo support, prevent 'ebreak' looping (#883)
* Expand RV32E demo support, prevent 'ebreak' looping The RegTest tests are modified in the Qemu and HiFive demos to support RV32E and its limited set of registers. 'ebreak' call looping is removed in RegTest. This produces a lot of noise when debugging. * Correct whitespace * Remove 'ebreak' instruction calls The ebreak instruction sets and exception which leads to jumping around the binary. This can make debugging difficult. * Fix whitespace formatting
This commit is contained in:
Kody Stribrny
GitHub
parent
fe9322ca23
commit
2f3e5235aa
10 changed files with 931 additions and 938 deletions
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@ -24,11 +24,11 @@
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*
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*/
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.extern ulRegTest1LoopCounter
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.extern ulRegTest2LoopCounter
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.extern ulRegTest1LoopCounter
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.extern ulRegTest2LoopCounter
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.global vRegTest1Implementation
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.global vRegTest2Implementation
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.global vRegTest1Implementation
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.global vRegTest2Implementation
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/*-----------------------------------------------------------*/
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@ -40,112 +40,114 @@
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.align( 4 )
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vRegTest1Implementation:
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/* Fill the core registers with known values. */
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li x5, 0x5
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li x6, 0x6
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li x7, 0x7
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li x8, 0x8
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li x9, 0x9
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li x10, 0xa
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li x11, 0xb
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li x12, 0xc
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li x13, 0xd
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li x14, 0xe
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li x15, 0xf
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li x16, 0x10
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li x17, 0x11
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li x18, 0x12
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li x19, 0x13
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li x20, 0x14
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li x21, 0x15
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li x22, 0x16
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li x23, 0x17
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li x24, 0x18
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li x25, 0x19
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li x26, 0x1a
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li x27, 0x1b
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li x28, 0x1c
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li x29, 0x1d
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li x30, 0x1e
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/* Fill the core registers with known values. */
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li x5, 0x5
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li x6, 0x6
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li x7, 0x7
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li x8, 0x8
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li x9, 0x9
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li x10, 0xa
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li x11, 0xb
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li x12, 0xc
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li x13, 0xd
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li x14, 0xe
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#ifndef __riscv_32e
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li x16, 0x10
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li x17, 0x11
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li x18, 0x12
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li x19, 0x13
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li x20, 0x14
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li x21, 0x15
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li x22, 0x16
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li x23, 0x17
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li x24, 0x18
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li x25, 0x19
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li x26, 0x1a
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li x27, 0x1b
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li x28, 0x1c
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li x29, 0x1d
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li x30, 0x1e
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li x31, 0x1f
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#endif
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reg1_loop:
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/* Check each register still contains the expected known value.
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vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
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uses x5 as the temporary. */
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li x31, 0x5
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bne x31, x5, reg1_error_loop
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li x31, 0x6
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bne x31, x6, reg1_error_loop
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li x31, 0x7
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bne x31, x7, reg1_error_loop
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li x31, 0x8
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bne x31, x8, reg1_error_loop
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li x31, 0x9
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bne x31, x9, reg1_error_loop
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li x31, 0xa
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bne x31, x10, reg1_error_loop
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li x31, 0xb
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bne x31, x11, reg1_error_loop
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li x31, 0xc
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bne x31, x12, reg1_error_loop
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li x31, 0xd
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bne x31, x13, reg1_error_loop
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li x31, 0xe
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bne x31, x14, reg1_error_loop
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li x31, 0xf
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bne x31, x15, reg1_error_loop
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li x31, 0x10
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bne x31, x16, reg1_error_loop
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li x31, 0x11
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bne x31, x17, reg1_error_loop
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li x31, 0x12
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bne x31, x18, reg1_error_loop
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li x31, 0x13
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bne x31, x19, reg1_error_loop
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li x31, 0x14
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bne x31, x20, reg1_error_loop
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li x31, 0x15
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bne x31, x21, reg1_error_loop
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li x31, 0x16
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bne x31, x22, reg1_error_loop
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li x31, 0x17
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bne x31, x23, reg1_error_loop
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li x31, 0x18
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bne x31, x24, reg1_error_loop
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li x31, 0x19
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bne x31, x25, reg1_error_loop
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li x31, 0x1a
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bne x31, x26, reg1_error_loop
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li x31, 0x1b
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bne x31, x27, reg1_error_loop
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li x31, 0x1c
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bne x31, x28, reg1_error_loop
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li x31, 0x1d
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bne x31, x29, reg1_error_loop
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li x31, 0x1e
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bne x31, x30, reg1_error_loop
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/* Check each register still contains the expected known value.
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vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
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uses x5 as the temporary. */
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li x15, 0x5
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bne x15, x5, reg1_error_loop
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li x15, 0x6
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bne x15, x6, reg1_error_loop
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li x15, 0x7
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bne x15, x7, reg1_error_loop
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li x15, 0x8
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bne x15, x8, reg1_error_loop
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li x15, 0x9
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bne x15, x9, reg1_error_loop
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li x15, 0xa
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bne x15, x10, reg1_error_loop
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li x15, 0xb
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bne x15, x11, reg1_error_loop
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li x15, 0xc
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bne x15, x12, reg1_error_loop
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li x15, 0xd
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bne x15, x13, reg1_error_loop
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li x15, 0xe
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bne x15, x14, reg1_error_loop
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#ifndef __riscv_32e
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li x15, 0x10
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bne x15, x16, reg1_error_loop
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li x15, 0x11
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bne x15, x17, reg1_error_loop
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li x15, 0x12
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bne x15, x18, reg1_error_loop
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li x15, 0x13
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bne x15, x19, reg1_error_loop
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li x15, 0x14
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bne x15, x20, reg1_error_loop
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li x15, 0x15
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bne x15, x21, reg1_error_loop
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li x15, 0x16
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bne x15, x22, reg1_error_loop
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li x15, 0x17
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bne x15, x23, reg1_error_loop
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li x15, 0x18
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bne x15, x24, reg1_error_loop
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li x15, 0x19
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bne x15, x25, reg1_error_loop
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li x15, 0x1a
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bne x15, x26, reg1_error_loop
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li x15, 0x1b
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bne x15, x27, reg1_error_loop
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li x15, 0x1c
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bne x15, x28, reg1_error_loop
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li x15, 0x1d
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bne x15, x29, reg1_error_loop
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li x15, 0x1e
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bne x15, x30, reg1_error_loop
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li x15, 0x1f
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bne x15, x31, reg1_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x31, ulRegTest1LoopCounterConst
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lw x30, 0(x31)
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addi x30, x30, 1
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sw x30, 0(x31)
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/* Everything passed, increment the loop counter. */
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lw x15, ulRegTest1LoopCounterConst
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lw x14, 0(x15)
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addi x14, x14, 1
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sw x14, 0(x15)
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/* Restore clobbered register reading for next loop. */
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li x30, 0x1e
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/* Restore clobbered register reading for next loop. */
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li x14, 0xe
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/* Yield to increase code coverage. */
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ecall
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/* Yield to increase code coverage. */
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ecall
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/* Start again. */
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jal reg1_loop
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/* Start again. */
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jal reg1_loop
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reg1_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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jal reg1_error_loop
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/* Busy loop which holds the task. */
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jal reg1_error_loop
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.align( 4 )
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ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
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@ -155,111 +157,111 @@ ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
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.align( 4 )
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vRegTest2Implementation:
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/* Fill the core registers with known values. */
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li x6, 0x61
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li x7, 0x71
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li x8, 0x81
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li x9, 0x91
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li x10, 0xa1
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li x11, 0xb1
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li x12, 0xc1
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li x13, 0xd1
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li x14, 0xe1
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li x15, 0xf1
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li x16, 0x20
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li x17, 0x21
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li x18, 0x22
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li x19, 0x23
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li x20, 0x24
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li x21, 0x25
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li x22, 0x26
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li x23, 0x27
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li x24, 0x28
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li x25, 0x29
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li x26, 0x2a
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li x27, 0x2b
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li x28, 0x2c
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li x29, 0x2d
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li x30, 0x2e
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li x31, 0x2f
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/* Fill the core registers with known values. */
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li x6, 0x61
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li x7, 0x71
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li x8, 0x81
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li x9, 0x91
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li x10, 0xa1
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li x11, 0xb1
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li x12, 0xc1
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li x13, 0xd1
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li x14, 0xe1
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li x15, 0xf1
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#ifndef __riscv_32e
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li x16, 0x20
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li x17, 0x21
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li x18, 0x22
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li x19, 0x23
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li x20, 0x24
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li x21, 0x25
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li x22, 0x26
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li x23, 0x27
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li x24, 0x28
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li x25, 0x29
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li x26, 0x2a
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li x27, 0x2b
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li x28, 0x2c
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li x29, 0x2d
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li x30, 0x2e
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li x31, 0x2f
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#endif
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Reg2_loop:
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/* Check each register still contains the expected known value.
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vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
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uses x31 as the temporary. */
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li x5, 0x61
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bne x5, x6, reg2_error_loop
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li x5, 0x71
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bne x5, x7, reg2_error_loop
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li x5, 0x81
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bne x5, x8, reg2_error_loop
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li x5, 0x91
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bne x5, x9, reg2_error_loop
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li x5, 0xa1
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bne x5, x10, reg2_error_loop
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li x5, 0xb1
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bne x5, x11, reg2_error_loop
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li x5, 0xc1
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bne x5, x12, reg2_error_loop
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li x5, 0xd1
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bne x5, x13, reg2_error_loop
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li x5, 0xe1
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bne x5, x14, reg2_error_loop
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li x5, 0xf1
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bne x5, x15, reg2_error_loop
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li x5, 0x20
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bne x5, x16, reg2_error_loop
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li x5, 0x21
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bne x5, x17, reg2_error_loop
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li x5, 0x22
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bne x5, x18, reg2_error_loop
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li x5, 0x23
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bne x5, x19, reg2_error_loop
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li x5, 0x24
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bne x5, x20, reg2_error_loop
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li x5, 0x25
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bne x5, x21, reg2_error_loop
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li x5, 0x26
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bne x5, x22, reg2_error_loop
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li x5, 0x27
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bne x5, x23, reg2_error_loop
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li x5, 0x28
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bne x5, x24, reg2_error_loop
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li x5, 0x29
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bne x5, x25, reg2_error_loop
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li x5, 0x2a
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bne x5, x26, reg2_error_loop
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li x5, 0x2b
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bne x5, x27, reg2_error_loop
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li x5, 0x2c
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bne x5, x28, reg2_error_loop
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li x5, 0x2d
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bne x5, x29, reg2_error_loop
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li x5, 0x2e
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bne x5, x30, reg2_error_loop
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li x5, 0x2f
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bne x5, x31, reg2_error_loop
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/* Check each register still contains the expected known value.
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vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
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uses x31 as the temporary. */
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li x5, 0x61
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bne x5, x6, reg2_error_loop
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li x5, 0x71
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bne x5, x7, reg2_error_loop
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li x5, 0x81
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bne x5, x8, reg2_error_loop
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li x5, 0x91
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bne x5, x9, reg2_error_loop
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li x5, 0xa1
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bne x5, x10, reg2_error_loop
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li x5, 0xb1
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bne x5, x11, reg2_error_loop
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li x5, 0xc1
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bne x5, x12, reg2_error_loop
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li x5, 0xd1
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bne x5, x13, reg2_error_loop
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li x5, 0xe1
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bne x5, x14, reg2_error_loop
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li x5, 0xf1
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bne x5, x15, reg2_error_loop
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#ifndef __riscv_32e
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li x5, 0x20
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bne x5, x16, reg2_error_loop
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li x5, 0x21
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bne x5, x17, reg2_error_loop
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li x5, 0x22
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bne x5, x18, reg2_error_loop
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li x5, 0x23
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bne x5, x19, reg2_error_loop
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li x5, 0x24
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bne x5, x20, reg2_error_loop
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li x5, 0x25
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bne x5, x21, reg2_error_loop
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li x5, 0x26
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bne x5, x22, reg2_error_loop
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li x5, 0x27
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bne x5, x23, reg2_error_loop
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li x5, 0x28
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bne x5, x24, reg2_error_loop
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li x5, 0x29
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bne x5, x25, reg2_error_loop
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li x5, 0x2a
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bne x5, x26, reg2_error_loop
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li x5, 0x2b
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bne x5, x27, reg2_error_loop
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li x5, 0x2c
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bne x5, x28, reg2_error_loop
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li x5, 0x2d
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bne x5, x29, reg2_error_loop
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li x5, 0x2e
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bne x5, x30, reg2_error_loop
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li x5, 0x2f
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bne x5, x31, reg2_error_loop
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#endif
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/* Everything passed, increment the loop counter. */
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lw x5, ulRegTest2LoopCounterConst
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lw x6, 0(x5)
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addi x6, x6, 1
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sw x6, 0(x5)
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/* Everything passed, increment the loop counter. */
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lw x5, ulRegTest2LoopCounterConst
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lw x6, 0(x5)
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addi x6, x6, 1
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sw x6, 0(x5)
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/* Restore clobbered register reading for next loop. */
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li x6, 0x61
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/* Restore clobbered register reading for next loop. */
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li x6, 0x61
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/* Start again. */
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jal Reg2_loop
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/* Start again. */
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jal Reg2_loop
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reg2_error_loop:
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/* Jump here if a register contains an uxpected value. This stops the loop
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counter being incremented so the check task knows an error was found. */
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ebreak
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jal reg2_error_loop
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/* Busy loop which holds the task. */
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jal reg2_error_loop
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.align( 4 )
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ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
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