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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Merge ef308b3f7c into 92bfb86ce3
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zhoumingshun
GitHub
commit
2e267cc2b3
2 changed files with 200 additions and 63 deletions
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@ -338,13 +338,16 @@ freertos_risc_v_interrupt_handler:
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/*-----------------------------------------------------------*/
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.section .text.freertos_risc_v_mtimer_interrupt_handler
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.align 2
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freertos_risc_v_mtimer_interrupt_handler:
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portcontextSAVE_INTERRUPT_CONTEXT
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portcontextSAVE_TIMER_CALLER_CONTEXT
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portUPDATE_MTIMER_COMPARE_REGISTER
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call xTaskIncrementTick
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beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
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bnez a0, mtimer_context_switch
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portcontextRESTORE_TIMER_CALLER_CONTEXT
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mtimer_context_switch:
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portcontextSAVE_DEFERRED_TASK_STATE
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call vTaskSwitchContext
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exit_without_context_switch:
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portcontextRESTORE_CONTEXT
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/*-----------------------------------------------------------*/
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@ -64,6 +64,10 @@
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#define portCRITICAL_NESTING_OFFSET 30
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#endif
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/* Keep the ISR stack aligned to the RISC-V ABI while reserving metadata used
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* by the machine-timer fast path. */
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#define portISR_STACK_METADATA_SIZE 16
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#if ( configENABLE_FPU == 1 )
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/* Bit [14:13] in the mstatus encode the status of FPU state which is one of
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* the following values:
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@ -270,38 +274,48 @@ add sp, sp, -( 2 * portWORD_SIZE )
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_CALLER_REGISTERS frame
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store_x x1, 2 * portWORD_SIZE( \frame )
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store_x x5, 3 * portWORD_SIZE( \frame )
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store_x x6, 4 * portWORD_SIZE( \frame )
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store_x x7, 5 * portWORD_SIZE( \frame )
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store_x x10, 8 * portWORD_SIZE( \frame )
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store_x x11, 9 * portWORD_SIZE( \frame )
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store_x x12, 10 * portWORD_SIZE( \frame )
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store_x x13, 11 * portWORD_SIZE( \frame )
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store_x x14, 12 * portWORD_SIZE( \frame )
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store_x x15, 13 * portWORD_SIZE( \frame )
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#ifndef __riscv_32e
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store_x x16, 14 * portWORD_SIZE( \frame )
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store_x x17, 15 * portWORD_SIZE( \frame )
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store_x x28, 26 * portWORD_SIZE( \frame )
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store_x x29, 27 * portWORD_SIZE( \frame )
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store_x x30, 28 * portWORD_SIZE( \frame )
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store_x x31, 29 * portWORD_SIZE( \frame )
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#endif /* ifndef __riscv_32e */
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.endm
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.macro portcontextSAVE_CALLEE_REGISTERS frame
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store_x x8, 6 * portWORD_SIZE( \frame )
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store_x x9, 7 * portWORD_SIZE( \frame )
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#ifndef __riscv_32e
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store_x x18, 16 * portWORD_SIZE( \frame )
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store_x x19, 17 * portWORD_SIZE( \frame )
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store_x x20, 18 * portWORD_SIZE( \frame )
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store_x x21, 19 * portWORD_SIZE( \frame )
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store_x x22, 20 * portWORD_SIZE( \frame )
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store_x x23, 21 * portWORD_SIZE( \frame )
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store_x x24, 22 * portWORD_SIZE( \frame )
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store_x x25, 23 * portWORD_SIZE( \frame )
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store_x x26, 24 * portWORD_SIZE( \frame )
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store_x x27, 25 * portWORD_SIZE( \frame )
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#endif /* ifndef __riscv_32e */
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.endm
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.macro portcontextSAVE_CONTEXT_INTERNAL
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 2 * portWORD_SIZE( sp )
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store_x x5, 3 * portWORD_SIZE( sp )
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store_x x6, 4 * portWORD_SIZE( sp )
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store_x x7, 5 * portWORD_SIZE( sp )
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store_x x8, 6 * portWORD_SIZE( sp )
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store_x x9, 7 * portWORD_SIZE( sp )
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store_x x10, 8 * portWORD_SIZE( sp )
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store_x x11, 9 * portWORD_SIZE( sp )
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store_x x12, 10 * portWORD_SIZE( sp )
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store_x x13, 11 * portWORD_SIZE( sp )
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store_x x14, 12 * portWORD_SIZE( sp )
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store_x x15, 13 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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store_x x16, 14 * portWORD_SIZE( sp )
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store_x x17, 15 * portWORD_SIZE( sp )
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store_x x18, 16 * portWORD_SIZE( sp )
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store_x x19, 17 * portWORD_SIZE( sp )
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store_x x20, 18 * portWORD_SIZE( sp )
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store_x x21, 19 * portWORD_SIZE( sp )
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store_x x22, 20 * portWORD_SIZE( sp )
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store_x x23, 21 * portWORD_SIZE( sp )
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store_x x24, 22 * portWORD_SIZE( sp )
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store_x x25, 23 * portWORD_SIZE( sp )
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store_x x26, 24 * portWORD_SIZE( sp )
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store_x x27, 25 * portWORD_SIZE( sp )
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store_x x28, 26 * portWORD_SIZE( sp )
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store_x x29, 27 * portWORD_SIZE( sp )
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store_x x30, 28 * portWORD_SIZE( sp )
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store_x x31, 29 * portWORD_SIZE( sp )
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#endif /* ifndef __riscv_32e */
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portcontextSAVE_CALLER_REGISTERS sp
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portcontextSAVE_CALLEE_REGISTERS sp
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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@ -369,6 +383,116 @@ store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_TIMER_CALLER_CONTEXT
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addi sp, sp, -portCONTEXT_SIZE
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portcontextSAVE_CALLER_REGISTERS sp
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/* Keep the fixed integer frame base available after variable-length optional
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* contexts have been saved by recording it in per-hart ISR stack metadata. */
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load_x t0, xISRStackTop
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addi t0, t0, -portISR_STACK_METADATA_SIZE
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store_x sp, 0( t0 )
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#if( configENABLE_FPU == 1 )
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csrr t0, mstatus
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srl t1, t0, MSTATUS_FS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 7f
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portcontexSAVE_FPU_CONTEXT
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7:
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#endif
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#if( configENABLE_VPU == 1 )
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csrr t0, mstatus
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srl t1, t0, MSTATUS_VS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 8f
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portcontexSAVE_VPU_CONTEXT
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8:
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#endif
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csrr t0, mstatus
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store_x t0, 1 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS
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#if( configENABLE_FPU == 1 )
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srl t1, t0, MSTATUS_FS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 9f
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li t1, ~MSTATUS_FS_MASK
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and t0, t0, t1
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li t1, MSTATUS_FS_CLEAN
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or t0, t0, t1
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csrw mstatus, t0
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9:
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#endif
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#if( configENABLE_VPU == 1 )
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srl t1, t0, MSTATUS_VS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 10f
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li t1, ~MSTATUS_VS_MASK
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and t0, t0, t1
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li t1, MSTATUS_VS_CLEAN
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or t0, t0, t1
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csrw mstatus, t0
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10:
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#endif
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csrr t0, mepc
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store_x t0, 0 * portWORD_SIZE( sp )
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load_x t0, pxCurrentTCB
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store_x sp, 0( t0 )
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load_x sp, xISRStackTop
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addi sp, sp, -portISR_STACK_METADATA_SIZE
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.endm
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.macro portcontextSAVE_DEFERRED_TASK_STATE
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load_x t1, 0( sp )
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portcontextSAVE_CALLEE_REGISTERS t1
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load_x t0, xCriticalNesting
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( t1 )
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.endm
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.macro portcontextRESTORE_TIMER_CALLER_CONTEXT
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load_x t1, pxCurrentTCB
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load_x sp, 0( t1 )
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load_x t0, 0 * portWORD_SIZE( sp )
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csrw mepc, t0
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portasmRESTORE_ADDITIONAL_REGISTERS
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load_x t3, 1 * portWORD_SIZE( sp )
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csrw mstatus, t3
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#if( configENABLE_VPU == 1 )
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srl t1, t3, MSTATUS_VS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 11f
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portcontextRESTORE_VPU_CONTEXT
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11:
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#endif
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#if( configENABLE_FPU == 1 )
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srl t1, t3, MSTATUS_FS_OFFSET
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andi t1, t1, 3
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addi t2, x0, 3
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bne t1, t2, 12f
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portcontextRESTORE_FPU_CONTEXT
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12:
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#endif
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portcontextRESTORE_CALLER_REGISTERS sp
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextSAVE_EXCEPTION_CONTEXT
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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@ -388,6 +512,44 @@ load_x sp, xISRStackTop /* Switch to ISR stack. */
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.endm
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/*-----------------------------------------------------------*/
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.macro portcontextRESTORE_CALLER_REGISTERS frame
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load_x x1, 2 * portWORD_SIZE( \frame )
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load_x x5, 3 * portWORD_SIZE( \frame )
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load_x x6, 4 * portWORD_SIZE( \frame )
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load_x x7, 5 * portWORD_SIZE( \frame )
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load_x x10, 8 * portWORD_SIZE( \frame )
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load_x x11, 9 * portWORD_SIZE( \frame )
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load_x x12, 10 * portWORD_SIZE( \frame )
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load_x x13, 11 * portWORD_SIZE( \frame )
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load_x x14, 12 * portWORD_SIZE( \frame )
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load_x x15, 13 * portWORD_SIZE( \frame )
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#ifndef __riscv_32e
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load_x x16, 14 * portWORD_SIZE( \frame )
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load_x x17, 15 * portWORD_SIZE( \frame )
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load_x x28, 26 * portWORD_SIZE( \frame )
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load_x x29, 27 * portWORD_SIZE( \frame )
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load_x x30, 28 * portWORD_SIZE( \frame )
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load_x x31, 29 * portWORD_SIZE( \frame )
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#endif
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.endm
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.macro portcontextRESTORE_CALLEE_REGISTERS frame
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load_x x8, 6 * portWORD_SIZE( \frame )
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load_x x9, 7 * portWORD_SIZE( \frame )
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#ifndef __riscv_32e
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load_x x18, 16 * portWORD_SIZE( \frame )
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load_x x19, 17 * portWORD_SIZE( \frame )
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load_x x20, 18 * portWORD_SIZE( \frame )
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load_x x21, 19 * portWORD_SIZE( \frame )
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load_x x22, 20 * portWORD_SIZE( \frame )
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load_x x23, 21 * portWORD_SIZE( \frame )
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load_x x24, 22 * portWORD_SIZE( \frame )
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load_x x25, 23 * portWORD_SIZE( \frame )
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load_x x26, 24 * portWORD_SIZE( \frame )
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load_x x27, 25 * portWORD_SIZE( \frame )
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#endif
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.endm
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.macro portcontextRESTORE_CONTEXT
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */
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@ -429,36 +591,8 @@ load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCritical
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */
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load_x x1, 2 * portWORD_SIZE( sp )
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load_x x5, 3 * portWORD_SIZE( sp )
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load_x x6, 4 * portWORD_SIZE( sp )
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load_x x7, 5 * portWORD_SIZE( sp )
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load_x x8, 6 * portWORD_SIZE( sp )
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load_x x9, 7 * portWORD_SIZE( sp )
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load_x x10, 8 * portWORD_SIZE( sp )
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load_x x11, 9 * portWORD_SIZE( sp )
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load_x x12, 10 * portWORD_SIZE( sp )
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load_x x13, 11 * portWORD_SIZE( sp )
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load_x x14, 12 * portWORD_SIZE( sp )
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load_x x15, 13 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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load_x x16, 14 * portWORD_SIZE( sp )
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load_x x17, 15 * portWORD_SIZE( sp )
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load_x x18, 16 * portWORD_SIZE( sp )
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load_x x19, 17 * portWORD_SIZE( sp )
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load_x x20, 18 * portWORD_SIZE( sp )
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load_x x21, 19 * portWORD_SIZE( sp )
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load_x x22, 20 * portWORD_SIZE( sp )
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load_x x23, 21 * portWORD_SIZE( sp )
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load_x x24, 22 * portWORD_SIZE( sp )
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load_x x25, 23 * portWORD_SIZE( sp )
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load_x x26, 24 * portWORD_SIZE( sp )
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load_x x27, 25 * portWORD_SIZE( sp )
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load_x x28, 26 * portWORD_SIZE( sp )
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load_x x29, 27 * portWORD_SIZE( sp )
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load_x x30, 28 * portWORD_SIZE( sp )
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load_x x31, 29 * portWORD_SIZE( sp )
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#endif /* ifndef __riscv_32e */
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portcontextRESTORE_CALLEE_REGISTERS sp
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portcontextRESTORE_CALLER_REGISTERS sp
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addi sp, sp, portCONTEXT_SIZE
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mret
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