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Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)

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* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Paul Bartell 2022-06-29 22:05:26 -07:00 • committed by GitHub
parent 8e89acfc98
commit 2dfdfc4ba4
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GPG key ID: 4AEE18F83AFDEB23
8 changed files with 122 additions and 24 deletions
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13
portable/RVDS/ARM_CM4_MPU/portmacro.h
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@ -70,6 +70,7 @@ typedef unsigned long UBaseType_t;
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@ -334,9 +335,15 @@ static portFORCE_INLINE void vPortRaiseBASEPRI( void )
/* Set BASEPRI to the max syscall priority to effect a critical
* section. */
/* *INDENT-OFF* */
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i
#endif
msr basepri, ulNewBASEPRI
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i
#endif
/* *INDENT-ON* */
}
}
@ -366,9 +373,15 @@ static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
* section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i
#endif
msr basepri, ulNewBASEPRI
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i
#endif
/* *INDENT-ON* */
}