len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-20 01:58:32 -04:00
Code Issues Projects Releases Packages Wiki Activity

Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)

Browse source 
* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Paul Bartell 2022-06-29 22:05:26 -07:00 • committed by GitHub
parent 8e89acfc98
commit 2dfdfc4ba4
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
8 changed files with 122 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

24
portable/RVDS/ARM_CM4_MPU/port.c
View file

@ -59,6 +59,12 @@
#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
* that a work around is active for errata 837070. */
#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
/* Constants required to access and manipulate the MPU. */
#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
@ -400,6 +406,18 @@ BaseType_t xPortStartScheduler( void )
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
/* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
* and r0p1 cores. */
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
#else
/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
* FreeRTOSConfig.h. */
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
#endif
#if ( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@ -591,9 +609,15 @@ __asm void xPortPendSVHandler( void )
stmdb sp !, { r0, r3 }
mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
msr basepri, r0
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0

13
portable/RVDS/ARM_CM4_MPU/portmacro.h
View file

@ -70,6 +70,7 @@ typedef unsigned long UBaseType_t;
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/
/* MPU specific constants. */
@ -334,9 +335,15 @@ static portFORCE_INLINE void vPortRaiseBASEPRI( void )
/* Set BASEPRI to the max syscall priority to effect a critical
* section. */
/* *INDENT-OFF* */
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i
#endif
msr basepri, ulNewBASEPRI
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i
#endif
/* *INDENT-ON* */
}
}
@ -366,9 +373,15 @@ static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
* section. */
/* *INDENT-OFF* */
mrs ulReturn, basepri
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i
#endif
msr basepri, ulNewBASEPRI
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i
#endif
/* *INDENT-ON* */
}